JP4495555B2 - DC offset removing method and receiving apparatus using the same - Google Patents

Description

  The present invention relates to a DC offset elimination method such as a wireless communication terminal device that performs digital communication such as a mobile phone and a wired communication terminal device, and a reception device using the same, and more particularly to a TDMA communication system such as GSM, US-TDMA, and PDC. In addition, the present invention relates to a receiving apparatus used in a CDMA communication system such as IS95, W-CDMA, and UMTS.

  In recent years, with the development of wireless communication terminals such as mobile phones, direct conversion is becoming the mainstream as one of means for realizing miniaturization and price reduction.

  Direct conversion is a method for converting a high-frequency signal into a baseband signal without intermediate frequency conversion, and is advantageous for low power consumption and miniaturization, such as eliminating the need for an intermediate frequency filter.

  However, in direct conversion, since a desired frequency is converted into a baseband band including a DC component, a DC offset voltage is relatively large as compared with a conventional heterodyne system. Further, direct conversion has a drawback that the DC offset voltage fluctuates due to the effects of self-mixing and interference power from the outside. This is a cause of degradation of demodulation performance and degradation of interference wave suppression characteristics for the baseband unit.

  As a general method for removing the DC offset voltage, there is AC coupling by inserting a capacitor before the A / D converter. FIG. 14 is a block diagram showing a configuration of a conventional receiving apparatus using a method of removing a DC offset voltage by AC coupling.

  As shown in FIG. 14, the receiving apparatus 10 includes an antenna 11, an RF receiving unit 20, and an analog baseband unit 30.

  The RF receiver 20 includes bandpass filters (BPF) 21 and 24, a low noise amplifier (LNA) 22, a frequency converter 23, an orthogonal mixer 25, low pass filters (LPF) 26a and 26b, a variable gain amplifier (PGA) 27a, 27b.

  The analog baseband unit 30 includes capacitors 31a and 31b, low-pass filters (LPF) 32a and 32b, amplifiers 33a and 33b, and A / D converters 34a and 34b.

  In FIG. 14, the radio wave (reception signal) received by the antenna 11 is input to the RF receiving unit 20. In the RF receiver 20, the received signal is converted into a baseband signal via a bandpass filter 21, a low noise amplifier 22, a frequency converter 23, a bandpass filter 24, and an orthogonal mixer 25, and the lowpass filter 26a, 26b and the variable gain amplifiers 27a and 27b, and then sent to the analog baseband unit 30.

  In the analog baseband unit 30, after the DC voltage is first removed by the capacitors 31a and 31b, the digital I and Q signals are obtained by the A / D converters 34a and 34b via the low pass filters 32a and 32b and the amplifiers 33a and 33b. Get.

In addition, as a receiver using another DC offset voltage removal method for direct conversion, the DC offset voltage detected after A / D conversion is D / A converted, and the DC offset voltage is A / D converted from the mixer. There is known a method that cancels feedback by the time before the device (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 10-13482

  However, the receiver using the conventional method of removing the DC offset voltage by AC coupling has two main problems.

  The first problem is the voltage median fluctuation at the signal point Y with respect to the voltage fluctuation at the signal point X shown in FIG. FIG. 15A is a diagram showing voltage fluctuations in the received signal at the signal point X shown in FIG. FIG. 15B is a diagram showing the voltage median fluctuation occurring at the signal point Y shown in FIG.

  That is, in this receiving apparatus, as shown in FIG. 15A, the capacitance of the capacitors 31a and 31b and the low-pass filter 32a at the signal point Y in FIG. 14 due to the voltage fluctuation v in the received signal at the signal point X in FIG. , 32b, the median voltage in the section A shown in FIG.

  The second problem is a preheating time problem. FIG. 16A shows a received signal at signal point X shown in FIG. FIG. 16B is a diagram showing the preheating time at the signal point Y shown in FIG.

  That is, the reception signal is transmitted in bursts in the TDMA type receiver. Therefore, in order to reduce power consumption, the TDMA receiver generally energizes the RF receiver 20 and the analog baseband unit 30 only during the burst reception process in section B shown in FIG. In other sections C and D, a process of not energizing is performed.

  However, in the receiving apparatus that performs such processing, in order to stabilize the voltage operation points at the signal point X and the signal point Y in FIG. 14, the charging time of the capacitors 31a and 31b is required. Therefore, in this receiving apparatus, it is necessary to secure a section (preheat time) E in which the RF receiving unit 20 and the analog baseband unit 30 are energized in advance before the section B shown in FIG. is there. For this reason, this receiving device has a drawback of increasing power consumption when applied to a communication device such as a mobile phone on the premise of battery driving.

  On the other hand, in the receiving apparatus described in Patent Document 1, a D / A converter and a circuit element for analog calculation for canceling the DC offset voltage are newly required. In addition, in this receiving apparatus, since a loop delay associated with A / D conversion and D / A conversion occurs in principle, there remains a problem that a response cannot be made to a relatively steep DC voltage fluctuation in which the loop delay cannot be ignored. .

  The present invention has been made in view of such a point, and provides a receiving apparatus that can remove a steady DC offset voltage during reception and a DC offset voltage that is superimposed and fluctuated on the received baseband signal. Objective.

  In order to solve such a problem, the receiving apparatus of the present invention includes a memory means for storing baseband received I and Q data converted into digital values, and DC offset profile estimation based on the received I and Q data. A partial average calculating means for calculating a partial average value for selecting one of the DC offset profile candidates of a pattern prepared in advance based on the partial average value calculated by the partial average calculating means DC offset estimation means, DC offset voltage calculation means for calculating a DC offset voltage for each section based on the DC offset profile selected by the DC profile selection means, DC offset estimation means, and the reception I, Q Calculated from the data by the DC offset voltage calculation means. A configuration having a, a subtracter for removing said DC offset voltage component.

  According to the present invention, it is possible to ideally remove the DC offset component by estimating the DC profile of the DC offset component superimposed on the received baseband signal by digital signal processing and removing it by calculation. An increase in error rate can be minimized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the component and equivalent part which have the same structure or function, and the description is not repeated.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of a receiving apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the receiving apparatus 100 according to the first embodiment includes an antenna 110, an RF receiving unit 120, an analog baseband unit 130, DC offset removing means 140a and 140b, a demodulation processing unit 150, a receiving memory 160a. , 160b.

  In FIG. 1, the antenna 110 inputs the received reception signal to the RF receiving unit 120. The RF receiver 120 converts the received signal received into a baseband signal and sends it to the analog baseband unit 130. The analog baseband unit 130 performs band limitation and A / D conversion on the input baseband signal, and then outputs it as digital I and Q signals. The reception memories 160a and 160b accumulate the digital I and Q signals in predetermined TDMA burst units and send them to the DC offset estimating means 141a and 141b and the subtractors 142a and 142b of the DC offset removing means 140a and 140b. Note that the reception memories 160a and 160b can be shared with a memory that is generally used in the process of storing reception data for the reception window after A / D conversion. As a result, the storage memory can be shared, so that the amount of memory used can be reduced.

  The DC offset removing means 140a and 140b remove the DC offset component from the digital I and Q signals input from the analog baseband unit 130, and demodulate the digital I and Q signals after removing the DC offset component. Send to.

  The demodulation processing unit 150 is configured by an equalizer or the like, and demodulates the transmission sequence using the digital I and Q signals from which the DC offset components have been removed by the DC offset removal means 140a and 140b.

  The DC offset removing means 140a and 140b are composed of DC offset estimating means 141a and 141b and subtractors 142a and 142b. The DC offset estimation means 141a and 141b are configured by partial average calculation means 1411a and 1411b, DC profile selection means 1412a and 1412b, and DC offset voltage calculation means 1413a and 1413b.

  In receiving apparatus 100 according to the first embodiment, the processing in DC offset estimating means 141a and 141b is performed in four stages.

  In the first stage processing, the partial average calculation means 1411a and 1411b use partial average values M (j, 1), M (j, 2), M (j, 3), M (j , 4) is calculated.

In this first stage of processing, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1... In each partial estimation section shown in FIG. t1), R _{I, Q} (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) Then, an average value is calculated using these as partial estimation intervals. These partial average values M (j, 1), M (j, 2), M (j, 3), and M (j, 4) are obtained by the following equation 1.

  In the second stage process, the DC profile selection means 1412a and 1412b have partial average values M (j, 1), M (j, 2), M (j, 3), which are the results of the first stage process. Based on M (j, 4), one likely DC offset profile is selected from the DC offset profile candidates for DC offset profile estimation of DC_1 to DC_8 shown in FIG.

That is, in the DC profile selection means 1412a and 1412b, as shown in the following equation 2, partial average values M (j, 1), M (j, 2), M (j, 3), M (j, 4) The absolute value of the difference between adjacent neighbors is obtained and compared with the threshold value th1.

  In Equation 2, if the partial average values M (j, 1), M (j, 2), M (j, 3), and M (j, 4) are equal to or greater than the threshold value th1 If it is smaller than the threshold value th1, the partial estimation section is regarded as the same DC offset voltage. For example, if | M (j, 1) −M (j, 2) | ≧ th1 and | M (j, 3) −M (j, 4) | ≧ th1, then DC_5 is selected, and neither For example, DC_8 is selected.

  In the third stage processing, the DC offset voltage calculation means 1413a and 1413b calculate the DC offset voltage of each section based on the DC offset profile selected by the DC profile selection means 1412a and 1412b.

This calculation formula is as shown in Formula 3. Here, the symbol index t regarded as a variation point in the DC offset profile is regarded as a boundary, and an average value between the boundaries is calculated. In Equation 3, Av (j, a..b) represents an operation for calculating the average amplitude of the symbol series R _{I, Q} (j, t) from the burst index j and the symbol indexes a to b.

In the fourth stage process, as shown in Expression 4, the DC offset voltage component based on the estimated DC offset voltage Rdc (j, t) is removed by the subtractors 142a and 142b.

Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index after the completion of the fourth step is input to the demodulation processing unit 150.

  Note that the processing of the DC offset estimating means 141a and 141b is performed independently for I and Q.

Further, in this example, the example in which the baseband sequence R _{I, Q} (j, t) is divided into four equal parts in the first stage processing has been described, but the number of divisions is not limited to four.

  Furthermore, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

(Embodiment 2)
Next, the receiving apparatus according to Embodiment 2 of the present invention will be described. FIG. 4 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the second embodiment. As shown in FIG. 4, this receiving apparatus 400 is different from receiving apparatus 100 according to Embodiment 1 in the configuration of DC offset estimating means 141a and 141b.

  That is, the DC offset estimating means 141a and 141b in the receiving apparatus 400 are provided with Max value searching means 1414a and 1414b and DC profile selecting means 1415a and 1415b instead of the DC profile selecting means 1412a and 1412b of the receiving apparatus 100. It has been.

  In receiving apparatus 400 according to the second embodiment, the processing in DC offset estimating means 141a and 141b is performed in five stages.

  The first-stage process is the same as the first-stage process performed by DC offset estimating means 141a and 141b in receiving apparatus 100 according to Embodiment 1. That is, in the first stage processing of this example, the partial average calculation means 1411a and 1411b use partial average values M (j, 1), M (j, 2), M (j, 3) for DC offset profile estimation. ), M (j, 4) is calculated.

In this first stage of processing, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1... In each partial estimation section shown in FIG. t1), R _{I, Q} (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) Then, an average value is calculated using these as partial estimation intervals.

In the second stage processing, the maximum value searching means 1414a, 1414b searches for the maximum value of the absolute value of the difference among the partial average values M (j, 1) to M (j, 4) obtained by the equation 1. To do. Then, the maximum value Mmax (j, 1..4) searched by the following equation 5 is sent to the third stage process.

  In the third stage processing, the DC profile selection means 1415a, 1415b compares the partial average maximum value Mmax (j, 1..4), which is the result of the second stage processing, with the threshold th2. One plausible DC offset profile is selected from the DC offset profile candidates DC_1 to DC_8 shown in FIG.

Here, if the following expression 6 is satisfied, it is processed as a variation due to the offset voltage, and if not satisfied, the processing unit section is regarded as the same DC offset voltage. For example, when Mmax (j, 1..4) = | M (j, 2) −M (j, 3) | ≧ th2 holds, DC_2 is selected, and when it does not hold, DC_8 is selected. It becomes.

  In the fourth stage of processing, the DC offset voltage calculation means 1413a and 1413b calculate the DC offset voltage of each section based on the selected DC offset profile. This calculation is as shown in Equation 3 above. However, possible DC offset profile candidates are DC_1 to DC_3, DC_8.

That is, the symbol index t regarded as a variation point in the DC offset profile is regarded as a boundary, and an average value between the boundaries is calculated. In Equation 3, Av (j, a..b) represents an operation for calculating the average amplitude of the symbol series R _{I, Q} (j, t) from the burst index j and the symbol indexes a to b.

In the fifth stage processing, as shown in the equation 4, the DC offset voltage components based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b are subtracted by the subtractors 142a, 142b. Remove with. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index is input to the demodulation processing unit 150 from the result of Equation 4.

  Note that the processing of the DC offset estimating means 141a and 141b is performed independently for I and Q.

  In this example, the number of divisions is assumed to be 4, but it can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

  Further, in the Max value search means 1414a and 1414b, the maximum value of the partial average value is sent to the DC profile selection means 1415a and 1415b, but a method of selecting a DC profile from the maximum value based on two or more search results. Is also possible.

(Embodiment 3)
Next, the receiving apparatus according to Embodiment 3 of the present invention will be described. FIG. 6 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the third embodiment. As shown in FIG. 6, this receiving apparatus 600 is different from receiving apparatus 100 according to Embodiment 1 in the configuration of DC offset estimating means 141a and 141b.

  That is, the DC offset estimating means 141a and 141b in the receiving apparatus 600 has a configuration in which the DC offset voltage calculating means 1413a and 1413b of the receiving apparatus 100 are replaced with DC offset voltage calculating means 1416a and 1416b.

  In receiving apparatus 600 according to Embodiment 3, the processing in DC offset estimating means 141a and 141b is performed in four stages.

  The first-stage process is the same as the first-stage process performed by DC offset estimating means 141a and 141b in receiving apparatus 100 according to Embodiment 1. That is, in the first stage processing of this example, the partial average calculation means 1411a and 1411b use the partial average values M (j, 1), M (j, 2), M (j, 3), M (j, 4) is calculated.

In this first stage of processing, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1... In each partial estimation section shown in FIG. t1), R _{I, Q} (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) Then, an average value is calculated using these as partial estimation intervals.

  In the second stage processing, the DC profile selection means 1412a and 1412b use partial average values M (j, 1), M (j, 2), M (j, 3), which are the results of the first stage processing. Based on M (j, 4), one likely DC offset profile is selected from the DC offset profile candidates DC_1 to DC_8 shown in FIG.

  In the DC profile selection means 1412a and 1412b, the absolute value of the difference between the adjacent partial average values is obtained and the threshold value th1 is compared with that of the partial average value, as in the case of Equation 2. The illustration of this comparison is the same as that of the receiving apparatus 100 according to Embodiment 1, and thus will be omitted. In Formula 2, if none of the three formulas is satisfied, DC_8 is selected.

  In the third stage processing, the DC offset voltage calculation means 1416a and 1416b calculate the DC offset voltage of each section based on the DC offset profile selected by the DC profile selection means 1412a and 1412b.

  Here, if the results of the DC profile selection means 1412a and 1412b are DC_1 to DC_7, the calculation selects the first to seventh formulas of the formula 3. However, when the selection result by the DC profile selection means 1412a and 1412b is DC_8, the DC offset profile in the continuous L−1 processing unit sections up to immediately before is DC_8, and the current DC_8 and the past When the absolute value of the difference from the average value of DC_8 in the L-1 processing unit sections is equal to or less than the threshold th3, the average of the DC offset voltages in the past L-1 processing unit sections as shown in FIG. The moving average is performed in the conversion interval. Then, the average value of the L unit processing sections including the present is set as the DC offset voltage value in the current process (corresponding to the process of DC_8 in Expression 7).

  As another operation, if DC_8 is selected as a result of selection by the DC profile selection means 1412a and 1412b, the processing unit interval L is incremented with 1 as an initial value and increases to a predetermined maximum value Lmax. Alternatively, as a result of selection by the DC profile selection means 1412a and 1412b, the value of the processing unit section L is initialized to 1 in cases other than DC_8.

That is, the symbol index t regarded as a variation point in the DC offset profile is regarded as a boundary, and an average value between the boundaries of the processing unit interval L is calculated. In the following expression 7, Av (j, a..b) represents an operation for calculating the average amplitude of the symbol series R _{I, Q} (j, t) from the burst index j and the symbol indexes a to b. Also, {c, d} indicates that the average values c and d in the burst of the current processing unit interval are different values depending on the burst index.

In the fourth stage process, as shown in the equation 4, the DC offset based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b by the subtractors 142a, 142b. Remove the voltage component. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index obtained from Equation 4 is input to the demodulation processing unit 150.

  Note that the processing of the DC offset estimating means 141a and 141b is performed independently for I and Q.

  In this example, it is assumed that the number of divisions is 4. However, the number of divisions can be determined regardless of this.

  Furthermore, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

(Embodiment 4)
Next, a receiving apparatus according to Embodiment 4 of the present invention will be described. FIG. 7 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the fourth embodiment. As shown in FIG. 7, this receiving apparatus 700 is different from receiving apparatus 400 according to Embodiment 2 in the configuration of DC offset estimating means 141a and 141b.

  That is, the DC offset estimating means 141a and 141b in the receiving apparatus 700 is replaced with the DC offset of the receiving apparatus 600 according to the third embodiment instead of the DC offset voltage calculating means 1413a and 1413b of the receiving apparatus 400 according to the second embodiment. The voltage calculation means 1416a and 1416b are used.

  In receiving apparatus 700 according to Embodiment 4, the processing in DC offset estimating means 141a and 141b is performed in five stages.

  The first-stage process is the same as the first-stage process performed by DC offset estimating means 141a and 141b in receiving apparatus 100 according to Embodiment 1. That is, in the first stage processing of this example, the partial average calculation means 1411a and 1411b use the partial average values M (j, 1), M (j, 2), M (j, 3), M (j, 4) is calculated.

In this first stage of processing, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1... In each partial estimation section shown in FIG. t1), R _{I, Q} (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) Then, an average value is calculated using these as partial estimation intervals.

  The second-stage process is the same as the second-stage process in DC offset estimating means 141a and 141b in receiving apparatus 400 according to Embodiment 2. That is, in the second stage process, the maximum value of the absolute value of the difference among the partial average values M (j, 1) to M (j, 4) obtained by the above equation 1 in the Max value search means 1414a and 1414b. Search for a value. Then, the maximum value Mmax (j, 1..4) searched by the equation 5 is sent to the third stage process.

  In the third stage processing, the DC profile selection means 1415a, 1415b compares the partial average maximum value Mmax (j, 1..4), which is the result of the second stage processing, with the threshold th2. One plausible DC offset profile is selected from the DC offset profile candidates DC_1 to DC_8 shown in FIG.

  Here, if Equation 6 is satisfied, it is processed as a variation due to the offset voltage, and if not satisfied, the processing unit section is regarded as the same DC offset voltage. For example, when Mmax (j, 1..4) = | M (j, 2) −M (j, 3) | ≧ th2 holds, DC_2 is selected, and when it does not hold, DC_8 is selected. It becomes.

The process in the fourth stage is the same as the process in DC offset voltage calculation means 1416a and 1416b of receiving apparatus 600 according to Embodiment 3. That is, in the fourth stage process, the DC offset voltage of each section is calculated based on the DC offset profile selected in the third stage process. The calculation here is the same as that in Equation 7, but the possible candidates are DC_1 to DC_3, DC_8, and therefore, the following Equation 8 is obtained.

  Here, if the results of the DC profile selection means 1415a and 1415b are DC_1 to DC_3, the calculation selects the first to third formulas of the formula 8. However, when the selection result is DC_8, the DC offset profile in the continuous L-1 processing unit sections up to immediately before the past is also DC_8, and the current DC_8 and the past L-1 processing unit sections When the absolute value of the difference between the average values of DC_8 is equal to or less than the threshold th3, the moving average is performed in the DC offset voltage averaging section of the past L-1 processing unit sections as shown in FIG. Then, the average value of the L unit processing sections including the present is set as the DC offset voltage value in the current process (corresponding to the expression DC_8 in Expression 8). Here, if DC_8 is selected as a result of searching by the Max value searching means 1414a and 1414b, the processing unit section L is incremented with 1 as an initial value and increases to a predetermined maximum value Lmax. Alternatively, in a case other than DC_8, the value of the processing unit section L is initialized to 1.

  That is, here, the burst index j regarded as a variation point in the DC offset profile is regarded as a boundary, and the average value between the boundaries of the processing unit interval L is calculated.

In the fifth stage processing, as shown in the equation 4, the DC offset based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b by the subtractors 142a, 142b. Remove the voltage component. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index is input to the demodulation processing unit 150 from the result of Equation 4.

  The processing in the DC offset estimation means 141a and 141b is performed independently for I and Q.

  In this example, it is assumed that the number of divisions is 4. However, the number of divisions can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

  In the Max value search means 1414a and 1414b, the maximum value of the partial average value is sent to the DC profile selection means 1415a and 1415b. However, there is also a method of selecting a profile from the maximum value based on two or more search results. Conceivable.

  Further, the threshold value th2 can be considered different from that of the receiving apparatus 400 according to the second embodiment.

(Embodiment 5)
Next, the receiving apparatus according to Embodiment 5 of the present invention will be described. FIG. 8 is a block diagram showing the configuration of the DC offset removal means of the receiving apparatus according to the fifth embodiment. As shown in FIG. 8, this receiving apparatus 800 differs from receiving apparatus 100 according to Embodiment 1 in the configuration of DC offset estimating means 141a and 141b.

  That is, DC offset estimating means 141a and 141b in receiving apparatus 800 have a configuration in which DC profile selecting means 1412a and 1412b in receiving apparatus 100 are replaced with DC profile selecting means 1417a and 1417b.

  Further, the DC profile selection units 1417a and 1417b in the receiving apparatus 800 receive the reception likelihood F from the demodulation processing unit 150, for example, in a burst period or a decoder frame period. In this case, the reception likelihood F may be an SNR estimation value for each burst, a bit error rate estimation value for each burst, an RSSI value for each burst, a training sequence power value for each burst, or a value based on these values. it can.

  In receiving apparatus 800 according to Embodiment 5, the processing in DC offset estimating means 141a and 141b is performed in four stages.

In the first stage processing, the partial average values M (j, 1), M (j, 2), M (j, 3), M (j, 4) in the partial average calculation means 1411a and 1411b described above are used. Perform the calculation. Here, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1..t1), R _{I of} each partial estimation section shown in FIG. _{, Q} (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) An average value is calculated as an estimation interval.

  In the second stage process, the DC profile selection means 1417a and 1417b use partial average values M (j, 1), M (j, 2), M (j, 3), which are the results of the first stage process. Based on M (j, 4), one likely DC offset profile is selected from the DC offset profile candidates DC_1 to DC_8 shown in FIG. That is, the DC profile selection means 1417a and 1417b obtain the absolute value of the difference between adjacent partial average values and compare them with the threshold value th4.

Here, the threshold value th4 is a function of the reception likelihood F. Table 1 shows the relationship between the threshold value and the reception likelihood.

  In Table 1, F1> F2> F3, and F1 indicates the best reception state. The magnitude relation of the threshold value th4 is 0 <TH4_L <TH4_M <TH4_H. This is because when the likelihood of reception F is small, the ratio of the amplitude of the noise component occupying the I and Q received signals becomes high, and a partial average error is likely to occur. Therefore, it is necessary to increase the threshold th4. Because there is.

As a result, the following equation 9 is calculated.

  In this equation 9, if the threshold value is equal to or greater than th4, it is processed as a variation due to the DC offset voltage, and if it is smaller than th4, the partial estimation section is regarded as the same DC offset voltage. For example, if | M (j, 1) −M (j, 2) | ≧ th4 and | M (j, 3) −M (j, 4) | ≧ th4 hold, DC_5 is selected, and none of these must be satisfied. For example, DC_8 is selected.

  The third-stage process is the same as the third-stage process in DC offset estimating means 141a, 141b in receiving apparatus 100 according to Embodiment 1. That is, in the third stage process, the DC offset voltage of each section is calculated based on the DC offset profile selected in the second stage process. This calculation is as shown in Equation 3 described above.

In the fourth step, as shown in the above equation 4, the subtractor 142a removes the DC offset voltage component based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b. 142b. Thereafter, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index is input to the demodulation processing unit 150.

  Note that the processing of the DC offset estimating means 141a and 141b is performed independently for I and Q.

  In this example, it is assumed that the number of divisions is 4. However, the number of divisions can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

  In this example, three thresholds th4 are set, but this number is not limited to three.

  The threshold value th4 may be given as a function instead of the form shown in Table 1.

(Embodiment 6)
Next, the receiving apparatus according to Embodiment 6 of the present invention will be described. FIG. 9 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the sixth embodiment. As shown in FIG. 9, this receiving apparatus 900 is different from receiving apparatus 400 according to Embodiment 2 in the configuration of DC offset estimating means 141a and 141b.

  That is, DC offset estimating means 141a, 141b in receiving apparatus 900 has a configuration in which DC profile selecting means 1418a, 1418b are used instead of DC profile selecting means 1415a, 1415b in receiving apparatus 400 according to Embodiment 2. is doing.

  Further, the DC profile selection means 1418a and 1418b in the receiving apparatus 900 receive the reception likelihood F from the demodulation processing unit 150.

  In receiving apparatus 900 according to Embodiment 6, the processing in DC offset estimating means 141a and 141b is performed in five stages.

The first stage process is the same as the first stage process in receiving apparatus 100 according to Embodiment 1. That is, in this first stage processing, the partial average calculation means 1411a and 1411b use the partial average values M (j, 1), M (j, 2), M (j, 3), M shown in the above-described equation 1. Calculate (j, 4). Here, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1..t1), R _I, Partial estimation of _Q (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) The average value is calculated as the interval.

  The process in the second stage is the same as the process in the second stage in receiving apparatus 400 according to Embodiment 2. That is, in the second stage processing, the maximum value of the absolute value of the difference among the partial average values M (j, 1) to M (j, 4) obtained by the above equation 1 in the Max value search means 1414a and 1414b. Explore. And | M (j, 1) −M (j, 2) |, | M (j, 2) −M (j, 3) |, | M (j, 3) −M (j, 4) | The maximum value is sent to the third stage process as Mmax (j, 1..4).

  In the third stage processing, the DC profile selection means 1418a, 1418b compares the partial average maximum value Mmax (j, 1..4), which is the result of the second stage processing, with the threshold th4. One likely DC offset profile is selected from the DC offset profile candidates DC_1 to DC_3 and DC_8 shown in FIG. Here, threshold value th4 is a threshold value considering reception likelihood F described in reception apparatus 800 according to Embodiment 5.

As a result, the following equation 10 is calculated.

  If this expression 10 is satisfied, it is processed as a variation due to the offset voltage, and if not satisfied, the processing unit section is regarded as the same DC offset voltage. For example, when Mmax (j, 1..4) = | M (j, 2) −M (j, 3) | ≧ th4 is satisfied, DC_2 is selected, and when it is not satisfied, DC_8 is selected. It becomes.

  In the fourth stage process, the DC offset voltage calculation means 1413a and 1413b calculate the DC offset voltage of each section based on the DC offset profile selected in the third stage process. This calculation is as shown in Equation 3 above. However, possible DC offset profile candidates are DC_1 to DC_3, DC_8.

In the fifth stage processing, as shown in the equation 4, the DC offset voltage component based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b is subtracted by the subtractor 142a, Removed at 142b. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index is input to the demodulation processing unit 150 from the result of Equation 4.

  Note that the processing of the DC offset estimating means 141a and 141b is performed independently for I and Q.

  In this example, the number of divisions is assumed to be 4, but the number of divisions can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

  Further, in the Max value search means 1414a and 1414b, the maximum value of the partial average value is sent to the DC profile selection means 1418a and 1418b, but a method of selecting a DC profile from the maximum value based on two or more search results. Is also possible.

(Embodiment 7)
Next, the receiving apparatus according to Embodiment 7 of the present invention will be described. FIG. 10 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the seventh embodiment. As shown in FIG. 10, this receiving apparatus 1000 differs from receiving apparatus 800 according to Embodiment 5 in the configuration of DC offset estimating means 141a and 141b.

  That is, the DC offset estimation means 141a and 141b in the receiving apparatus 1000 includes the DC profile selection means 1417a and 1417b and the DC offset voltage calculation means 1413a and 1413b in the receiving apparatus 800, the DC profile selection means 1419a and 1419b, and the DC offset voltage. The calculation unit 1416a and 1416b are replaced.

  In receiving apparatus 1000 according to the seventh embodiment, the processes in DC offset estimating means 141a and 141b are performed in four stages.

The first stage process is the same as the first stage process in receiving apparatus 100 according to Embodiment 1. That is, in this first stage process, the partial average calculation means 1411a and 1411b use the partial average values M (j, 1), M (j, 2), M (j, 3), M ( j, 4) is calculated. That is, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1..t1), R _{I, Q of} each partial estimation section shown in FIG. (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) The average value is calculated as the interval.

  In the second stage processing, the DC profile selection means 1419a and 1419b use partial average values M (j, 1), M (j, 2), M (j, 3), which are the results of the first stage processing. Based on M (j, 4), one likely DC offset profile is selected from the DC offset profile candidates DC_1 to DC_8 shown in FIG.

  In the DC profile selection means 1419a and 1419b, the absolute value of the difference between the adjacent partial average values is obtained and the threshold value th4 is compared with the partial average value, as in the case of the equation 2. Threshold value th4 is as described in receiving apparatus 800 according to Embodiment 5, and is a value according to Table 1 based on reception likelihood F. If none of the expressions 2 holds, DC_8 is selected.

  In the third stage process, the DC offset voltage of each section based on the selected DC offset profile is expressed as shown in Equation 7 as in the DC offset voltage calculation means 1416a and 1416b of the receiving apparatus 600 according to Embodiment 3. Perform the calculation. If the results of the DC profile selection means 1419a and 1419b are DC_1 to DC_7, the calculation is equal to the above equation 3. However, when DC_8 is sent here, if the DC offset profile in the L consecutive processing unit intervals up to the past is DC_8, the DC offset voltage averaging interval in the L processing unit intervals Extend the past to the moving average.

  If DC_8 is selected as a result of DC profile selection means 1419a and 1419b before the calculation of Equation 7, the processing unit interval L is incremented with 1 as an initial value and increases to a predetermined maximum value Lmax. . Alternatively, here, in the case of DC_1 to DC_7, the value of the processing unit section L is initialized to 1.

In the fourth stage process, as shown in Equation 4, the DC offset voltage component based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b is subtracted by the subtractors 142a, 142b. Remove with. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index obtained from Equation 4 is input to the demodulation processing unit 150.

  Note that the processing in the DC offset estimation means 141a and 141b of this example is performed independently for I and Q.

  In this example, it is assumed that the number of divisions is 4. However, the number of divisions can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

(Embodiment 8)
Next, a receiving apparatus according to Embodiment 8 of the present invention will be described. FIG. 11 is a block diagram showing a configuration of DC offset removing means of the receiving apparatus according to the eighth embodiment. As shown in FIG. 11, this receiving apparatus 1100 differs from receiving apparatus 900 according to Embodiment 6 in the configuration of DC offset estimating means 141a and 141b.

  That is, the DC offset estimating means 141a and 141b in the receiving apparatus 1100 includes the DC profile selecting means 1418a and 1418b and the DC offset voltage calculating means 1413a and 1413b in the receiving apparatus 900, and the DC profile selecting means 1420a and 1420b and the DC offset voltage. The calculation unit 1416a and 1416b are replaced.

  In receiving apparatus 1100 according to the eighth embodiment, the processes in DC offset estimating means 141a and 141b are performed in five stages.

The first stage process is the same as the first stage process in receiving apparatus 100 according to Embodiment 1. That is, in this first stage processing, the partial average calculation means 1411a and 1411b use the partial average values M (j, 1), M (j, 2), M (j, 3), M shown in the above-described equation 1. Calculate (j, 4). That is, the baseband sequence R _{I, Q} (j, t) is divided into four equal parts, and the sample sequences R _{I, Q} (j, 1..t1), R _{I, Q of} each partial estimation section shown in FIG. (j, t1 + 1..t2), R _{I, Q} (j, t2 + 1..t3), R _{I, Q} (j, t3 + 1..N) The average value is calculated as the interval.

  In the second stage of processing, the maximum value of the absolute value of the difference is searched for among the partial average values M (j, 1) to M (j, 4) obtained by the expression 1 by the Max value searching means 1414a and 1414b. To do. Then, the maximum value Mmax (j, 1..4) searched by the equation 5 is sent to the third stage process.

  In the third stage process, the DC profile selection means 1420a, 1420b compares the partial average maximum value Mmax (j, 1..4), which is the result of the second stage process, with the threshold value th4. One likely DC offset profile of DC offset profile candidates DC_1 to DC_8 shown in FIG. 3 is selected.

  Here, if the above expression 6 is satisfied by applying the threshold value th4, it is processed as a variation due to the DC offset voltage, and if not satisfied, the processing unit section is regarded as the same DC offset voltage. Threshold value th4 is as described in receiving apparatus 800 according to Embodiment 5, and is a value according to Table 1 based on reception likelihood F. For example, when Mmax (j, 1..4) = | M (j, 2) −M (j, 3) | ≧ th4 is satisfied, DC_2 is selected, and when it is not satisfied, DC_8 is selected. It becomes.

  The process of the fourth stage is the same as the process of DC offset voltage calculation means 1416a and 1416b of receiving apparatus 1000 according to Embodiment 7. That is, here, the DC offset voltage of each section is calculated based on the selected DC offset profile. This calculation is the same as that in Equation 7, but the possible DC offset profile candidates are DC_1 to DC_3, DC_8, and thus Equation 8 is obtained. Here, the processing unit interval L is determined before the execution of Expression 8. If DC_8 is selected as a result of the Max value search means 1414a and 1414b, the processing unit section L is incremented with 1 as an initial value and increases to a predetermined maximum value Lmax. Alternatively, in the case of DC_1 to DC_3, the value of the processing unit section L is initialized to 1.

  That is, here, the burst index j regarded as a variation point in the DC offset profile is regarded as a boundary, and the average value between the boundaries of the processing unit interval L is calculated.

In the fifth stage process, as shown in the equation 4, the DC offset voltage components based on the DC offset voltage Rdc (j, t) estimated by the DC offset estimating means 141a, 141b are subtracted by the subtractors 142a, 142b. Remove with. Then, the subtraction result R ′ _{I, Q} (j, 1..N) for each symbol index is input to the demodulation processing unit 150 from the result of Equation 4.

  Note that the processing of the DC offset estimation means 141a and 141b in this example is performed independently for I and Q.

  In this example, it is assumed that the number of divisions is 4. However, the number of divisions can be determined regardless of this.

  Further, the symbol indexes t1, t2, t3, and t4 in this example can be arbitrarily determined as long as the condition 1 <t1 <t2 <t3 <t4 <N is satisfied.

  In the Max value search means 1414a and 1414b, the maximum value of the partial average value is sent to the DC profile selection means 1420a and 1420b, but a method of selecting a DC profile from the maximum value based on two or more search results. Is also possible.

  Further, the threshold th4 can be considered different from that of the receiving apparatus 100 according to the first embodiment.

  In this example, a TDMA burst is assumed as an adjacent section, and a processing unit section for each burst is set. However, a continuous reception signal format such as CDMA is also applicable.

  Although this example has been described on the assumption of TDMA wireless communication, it can be applied to a method that does not perform amplitude modulation, such as an FSK or PSK modulation method. The present invention can also be applied to wired transmission, and the transmission medium is not limited to wireless.

  As described above, in the receiving apparatus according to each embodiment, steady DC offset voltage during reception, that is, DC offset voltage fluctuation caused by gain control such as AGC, DC offset voltage due to analog processing of the baseband front end In addition, characteristic DC offset voltage in direct conversion, that is, DC offset voltage fluctuation due to the effect of self-mixing and interference power captured by the antenna can be removed.

  In addition, in the receiving apparatus according to each embodiment, since the calculation and removal of the DC offset voltage are all performed by the arithmetic processing based on the digital I and Q after A / D conversion, no analog element is required, and the characteristics are Stable and cost reduction can be achieved.

  In addition, in the receiving apparatus according to each embodiment, steep DC offset voltage fluctuations up to the time resolution of digital I and Q can be removed.

  As described above, in the receiving apparatus according to each embodiment, the DC offset component superimposed on the received baseband signal is estimated by digital signal processing, and is removed by calculation. Since it can be eliminated, the reduction in the received bit error rate can be minimized.

  Furthermore, in the receiving apparatus according to each embodiment, there is an advantage that there is almost no increase in circuit scale and power consumption is small as compared with the removal in the analog unit.

  FIG. 13 is a diagram illustrating a state in which a DC offset voltage fluctuation occurs due to reception AGC. In general, when the input level of the antenna decreases, the AGC gain increases due to the action of the AGC, and thus the DC offset voltage also increases.

  Since the DC offset caused by the change in AGC gain is considered to take a constant value in the processing unit of the received burst, the profile of DC_8 in FIG. 3 or FIG. 5 is selected. In addition, it is possible to remove the DC offset voltage that fluctuates in the burst period.

  However, when using direct conversion, it is necessary to estimate a plausible profile from all the candidates in FIG. 3 or FIG. 5 in consideration of the possibility that the DC offset voltage fluctuates due to interference power during reception. This DC offset voltage profile can be estimated by determining the presence or absence of fluctuations based on the difference between adjacent partial estimation sections.

  In the description of the first to eighth embodiments, adjacent TDMA bursts are assumed. However, if the difference between adjacent processing unit sections is equal to or less than the threshold th3, one estimation section is provided as shown in FIG. Therefore, even when applied to a continuous reception transmission method such as CDMA, the estimation accuracy can be improved in the same manner.

  Further, when the noise power at the time of reception becomes relatively large, the dispersion value of the amplitudes of the reception I and Q gradually increases. Therefore, the partial average value M (j, The errors of 1), M (j, 2)... Increase, and the probability of selecting an incorrect DC offset increases.

  Therefore, when the reception likelihood information is small, the estimation error of the DC offset profile can be reduced by increasing the threshold value to suppress the influence of erroneous determination due to the influence of noise. As the likelihood information, an RSSI value, an SNR estimated value, a burst BER estimated value, a training sequence power obtained by a channel estimator, and the like can be used.

  In addition, the partial average calculation unit, the DC profile selection unit, the DC offset voltage calculation unit, the Max value search unit, etc., which are elements constituting the DC offset removal unit 140a, b described in any of the first to eighth embodiments, are used. Of course, it can be realized not only by hardware, but also by software processing by a DSP or CPU if the algorithm is the same.

  The receiver according to the present invention can ideally remove the DC offset component by estimating the DC profile of the DC offset component superimposed on the received baseband signal by digital signal processing and removing it by calculation. It is useful as a receiving device such as a wireless communication terminal and a wired communication terminal for digital communication such as a mobile phone.

FIG. 2 is a block diagram showing a schematic configuration of a receiving apparatus according to Embodiment 1 of the present invention. The figure which shows the partial average process for DC offset profile estimation in the receiver which concerns on Embodiment 1 of this invention The figure which shows the profile candidate for DC offset profile estimation in the receiver which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the DC offset removal means of the receiver which concerns on Embodiment 2 of this invention. The figure which shows the profile candidate for DC offset profile estimation in the receiver which concerns on Embodiment 2 of this invention. The block diagram which shows the structure of the DC offset removal means of the receiver which concerns on Embodiment 3 of this invention. FIG. 7 is a block diagram showing a configuration of DC offset removing means of a receiving apparatus according to Embodiment 4 of the present invention. FIG. 9 is a block diagram showing a configuration of DC offset removing means of a receiving apparatus according to Embodiment 5 of the present invention. The block diagram which shows the structure of the DC offset removal means of the receiver which concerns on Embodiment 6 of this invention. FIG. 9 is a block diagram showing a configuration of DC offset removing means of a receiving apparatus according to Embodiment 7 of the present invention. The block diagram which shows the structure of the DC offset removal means of the receiver which concerns on Embodiment 8 of this invention. The figure which shows the profile candidate for DC offset profile estimation The figure which shows a mode that DC offset voltage fluctuation | variation arises by receiving AGC. A block diagram showing a configuration of a conventional receiver using a method of removing a DC offset voltage by AC coupling (A) is a figure which shows the voltage fluctuation in the received signal in the signal point X shown in FIG. 14, (b) is a figure which shows the voltage median fluctuation which arises in the signal point Y shown in FIG. (A) is a figure which shows the received signal in the signal point X shown in FIG. 14, (b) is a figure which shows the preheating time in the signal point Y shown in FIG.

Explanation of symbols

100, 400, 600, 700, 800. 900, 1000, 1100 Receiver 110 Antenna 120 RF receiver 130 Analog baseband unit 140a, 140b DC offset removal means 141a, 141b DC offset estimation means 142a, 142b Subtractor 150 Demodulation Processing unit 160a, 160b Reception memory 1411a, 1411b Partial average calculation unit 1412a, 1412b, 1415a, 1415b, 1417a, 1417b, 1418a, 1418b, 1419a, 1419b, 1420a, 1420b DC profile selection means 1413a, 1413b, 1416a, 1416b DC offset Voltage calculation means 1414a, 1414b Max value search means

Claims (12)

Memory means for accumulating baseband received I and Q data converted into digital values; partial average calculating means for calculating a partial average value for estimating a DC offset profile based on the received I and Q data;
DC profile selection means for selecting one likely DC offset profile among DC offset profile candidates of a pattern prepared in advance based on the partial average value calculated by the partial average calculation means;
DC offset estimation means comprising: DC offset voltage calculation means for calculating a DC offset voltage for each section based on the DC offset profile selected by the DC profile selection means;
A subtractor for removing the DC offset voltage component calculated by the DC offset voltage calculation means from the received I and Q data;
A receiving apparatus comprising:   The receiving apparatus according to claim 1, wherein the DC offset estimation means includes search means for searching for a maximum value of absolute values of differences among the partial average values calculated by the partial average calculation means. The DC offset estimating means sets a unit processing interval for DC offset processing as a time series sample RI, Q (j, t) (j: index of unit processing interval for DC offset processing) j of a received baseband signal composed of N symbols. = 1 .., t: Symbol index in the unit interval, t = 1..N), and I, which consists of {N1, N2, ... NI} for RI, Q (j, t) Set partial estimation intervals, find partial estimation values M (j, x) (x: index of partial estimation interval, x = 1..I) for each interval, and calculate the absolute value of the difference from adjacent intervals. Estimate the DC offset profile of the entire series sample RI, Q (t),
The receiving device according to claim 1, wherein the subtractor calculates a time-series sample R'I, Q (j, t) of a baseband signal by subtracting a DC offset profile from the time-series sample RI, Q (t). .   The DC offset estimation means is configured such that the absolute value of the difference between the partial estimated value M (j, x) for each section and the immediately preceding partial estimated value M (j, x-1) is equal to or less than a threshold th1. 4. The receiving apparatus according to claim 3, wherein the x-th interval and the (x−1) -th interval of partial estimation are regarded as one partial estimation interval.   The DC offset estimator searches the partial estimation section M (j, x) for an index x = xmax of a partial estimation section where the absolute value of the difference between adjacent partial estimation sections is maximum, and obtains xmax DC offset profile of two partial estimation intervals of partial estimation values M (j, 1) .. M (j, xmax) and M (j, xmax + 1) .. M (j, I) The receiver according to any one of claims 2 to 4, wherein the offset is estimated and the offset is removed.   The DC offset estimating means considers that xmax is absent when the absolute value of the difference between the adjacent partial estimation sections is equal to or less than the threshold th1, and M (j, 1) .. M (j, I 5. The receiving apparatus according to claim 3, wherein the DC offset profile is estimated using the partial estimation intervals up to) as one estimation interval, and offset removal is performed.   The DC offset estimator determines the current R ′ according to the reception likelihood value obtained from the demodulator that receives R′I, Q (j−1, t) obtained in the previous DC offset removal process. The receiving apparatus according to claim 4, wherein the threshold value th <b> 1 in the process for obtaining I, Q (j, t) is controlled. The DC offset estimation means considers that the absolute value of the difference between the adjacent partial estimation sections is equal to or less than a threshold th1 and the state continuously extends to a plurality of processing unit sections, and that xmax is absent. DC offset profile M (j, 1..I) obtained as a single estimation interval from the partial estimation interval up to M (j, 1) .. M (j, I) and its past L defined by a predetermined L -The absolute value of the difference of the moving average of DC offset profiles M (j- (L-1), 1..I) to M (j-1, 1..I) for one processing unit section is the threshold value If th4 or less, the average value of M (j, 1..I) and M (j- (L-1), 1..I) to M (j-1, 1..I) is currently processed R'I by DC offset correction processing as DC offset profile in the unit interval, Q (j, t) receiver according to any one of claims 7 to claim 4 seeking.   The DC offset estimator is a reception likelihood obtained from a demodulator that receives time-series samples R′I, Q (j, t) of a baseband signal obtained by the DC offset removal process in the previous processing unit. The receiving apparatus according to claim 7 or 8, wherein the threshold values th1 and th4 are controlled according to a degree value.   The receiving apparatus according to any one of claims 1 to 9, wherein the DC offset estimating means processes both the complex baseband samples I and Q independently.   The reception according to any one of claims 3 to 10, further comprising demodulation means for performing demodulation using time-series samples R'I, Q (j, t) of a baseband signal output from the DC offset estimation means. apparatus. A partial average calculating step for calculating a partial average value for DC offset profile estimation;
A DC profile selection step of selecting one likely DC offset profile among DC offset profile candidates based on the partial average value calculated in the partial average calculation step;
A DC offset voltage calculating step for calculating a DC offset voltage for each section based on the DC offset profile selected in the DC profile selecting step, and a DC offset estimating step comprising:
A subtraction step for removing the DC offset voltage component calculated by the DC offset voltage calculation step;
A DC offset removal method comprising:

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