JP4489491B2 - Interposer - Google Patents

Description

  The present invention relates to an interposer, and more specifically, a base substrate made of ceramic, an electronic component that passes through both front and back surfaces of the base substrate and is connected to one of the front and back surfaces, and a print that is connected to the other of the front and back surfaces. The present invention relates to an interposer including a plurality of conductor vias that electrically connect a wiring board.

With the recent progress of integrated circuit (IC) technology, the number of input / output terminals of an IC chip is increasing. In order to cope with this, a flip chip method may be adopted as a method of mounting an IC chip on a printed wiring board. In this flip chip method, input / output terminals are arranged two-dimensionally such as a grid or staggered pattern on the main plane of the IC chip, and pads are formed on the surface of the resin printed wiring board at positions corresponding thereto, Both are joined with solder bumps. By the way, since the IC chip has a remarkably small thermal expansion coefficient compared to a printed wiring board made of resin, heat is generated when the IC chip is mounted or used, so that the solder bump as a bonding material is sheared from the difference between the two thermal expansion coefficients. Stress will work. For this reason, when the temperature change accompanying the heat generation of the IC chip repeatedly occurs, the solder bump may be destroyed. Therefore, it is proposed to reduce the shear stress by interposing an interposer (relay substrate) having a thermal expansion coefficient intermediate between the IC chip and the printed wiring board between the IC chip and the printed wiring board. (Patent Document 1).
JP 10-12990 A (paragraph 0037)

  By the way, the multilayer printed wiring board has a larger coefficient of thermal expansion than that of the interposer. Therefore, when heating and cooling are repeated, stress is applied to the interposer by repeating expansion and contraction. This stress increases as the peripheral edge of the multilayer printed wiring board increases. On the other hand, this type of interposer is known to have a base substrate made of ceramic and conductor vias made of copper or the like penetrating both the front and back surfaces of the base substrate. Since the coefficient of thermal expansion is larger than that, when heating and cooling are repeated, stress is applied to the base substrate by repeating expansion and contraction. From the above, around the joint portion between the conductor via located at the periphery of the base substrate of the interposer and the multilayer printed wiring board, stress and conductor via caused by the multilayer printed wiring board are caused by repeated heating and cooling. The resulting stress is applied, and in some cases, cracks occur and the electrical resistance between the multilayer printed wiring board and the IC chip increases.

  The present invention has been made in order to solve such problems, and can prevent generation of cracks due to thermal expansion and contraction and can stably supply power to an electronic component such as an IC chip. The purpose is to provide.

  The present invention adopts the following means in order to achieve the above-mentioned object.

That is, the present invention includes a base substrate made of ceramic, an electronic component that penetrates both the front and back surfaces of the base substrate and is connected to one of the front and back surfaces, and a printed wiring board that is connected to the other of the front and back surfaces. An interposer comprising a plurality of electrically connected vias,
The conductor via has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and among the conductor vias, the aspect ratio Rasp of the outer conductor via disposed at the peripheral portion of the base substrate is disposed at the center of the base substrate. The inner conductor via has an aspect ratio Rasp or higher.

  Of the base substrate of this interposer, the stress caused by the printed wiring board (stress generated by being pulled by the printed wiring board) and the stress caused by the conductive via are applied around the conductor via when heating and cooling are repeated. However, since the aspect ratio Rasp of each conductor via is 4 or more, the stress caused by each conductor via is relatively small. Further, the stress caused by the printed wiring board is larger in the peripheral portion than in the central portion, but since the aspect ratio Rasp of the outer conductor via is equal to or larger than the aspect ratio Rasp of the inner conductor via, the stress caused by the conductor via is larger than that in the central portion. The periphery is small. Moreover, since each conductor via has a diameter exceeding 30 μm, it is easy to ensure electrical connection even if stress is applied. Therefore, according to this interposer, even if heating / cooling is repeated while being connected to the printed wiring board, there is no possibility that cracks due to thermal expansion / contraction will occur in the peripheral portion of the base substrate, such as an IC chip. Power can be stably supplied to the electronic components. In the present invention, the aspect ratio Rasp of the conductor via means the height of the conductor via / the diameter of the conductor via (the minimum diameter when the diameter is not uniform).

  In the interposer of the present invention, it is preferable that the aspect ratio Rasp of the outer conductor via among the conductor vias is not less than 1.25 times and not more than twice the aspect ratio Rasp of the inner conductor via. If it is this range, the effect of this invention will become remarkable.

  In the interposer of the present invention, it is preferable that at least the outer conductor via among the conductor vias is formed in a shape having a constriction. In this way, the rate of change in electrical resistance when heating / cooling is repeated can be further suppressed as compared with a substantially straight conductor via. The outer conductor via formed in such a shape having a crease preferably has a maximum diameter / minimum diameter of 2 or more and 4 or less.

  In the interposer of the present invention, when conductor vias are formed in multiple layers from the outermost periphery to the Nth row (N is an integer of 2 or more), the outer conductor vias are determined within the range from the outermost periphery to N × 2/3 rows. It is preferable that Since the stress applied to the conductor vias within this range is greater than the stress applied to the other conductor vias, it is significant to apply the present invention. For example, when N is 15, the outer conductor vias are determined within the range from the outermost periphery to the 10th column, so that only the outermost periphery 1 row, the outermost periphery to the 2nd row,. There is a way to define up to eyes.

  In the interposer of the present invention, the outer conductor via may be connected to a pad formed in a substantially flat shape on the printed wiring board. Since this pad is formed to be substantially flat, a void (void) is formed inside the bonding member when the bonding member such as solder is bonded to the interposer as compared to the case where the pad is formed in a recessed shape. No part is formed. Thus, since there are no voids or corners where stress tends to concentrate at the junction between the outer conductor via and the external pad, this junction is not easily destroyed. Therefore, the bonding reliability can be maintained over a long period.

  In the interposer of the present invention, the thickness of the base substrate is preferably at least 0.1 times the thickness of the printed wiring board. In this way, the ceramic base substrate is difficult to break.

  Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor mounting substrate 80 according to an embodiment of the present invention. In the following, “upper” and “lower” may be expressed, but this is merely a representation of the relative positional relationship for convenience. May be.

  The semiconductor mounting board 80 of this embodiment is manufactured by electrically connecting the interposer 60 to the multilayer printed wiring board 10. The multilayer printed wiring board 10 has a thickness of 1.02 mm in this embodiment, and electrically connects the wiring patterns 22 formed on the upper and lower surfaces through through-hole conductors 24 as shown in FIG. A core substrate 20, a buildup layer 30 formed above and below the core substrate 20, and a pad group 40 (see FIG. 2) formed on the uppermost surface of the buildup layer 30 are provided. An IC chip (thermal expansion coefficient is about 3.5 ppm / ° C.), which is an electronic component, is electrically connected to the interposer 60 of the semiconductor mounting substrate 80.

  The core substrate 20 includes wiring patterns 22 and 22 made of copper on both upper and lower surfaces of a core substrate body 21 made of BT (bismaleimide-triazine) resin, glass epoxy resin, and the like, and through holes penetrating the core substrate body 21 vertically. A through-hole conductor 24 made of copper is formed on the inner peripheral surface, and both wiring patterns 22 and 22 are electrically connected through the through-hole conductor 24. In this embodiment, the core substrate 20 has a thickness of 800 μm and a thermal expansion coefficient of about 12 to 20 ppm / ° C.

  The buildup layer 30 is obtained by alternately laminating resin insulating layers 31 and 34 and conductor layers 32 and 35 on the upper and lower surfaces of the core substrate 20. Here, examples of the resin insulating layers 31 and 34 include a modified epoxy resin sheet, a polyphenylene ether resin sheet, a polyimide resin sheet, and a cyanoester resin sheet, and the thickness is preferably about 20 to 80 μm. . In the build-up layer 30, the wiring pattern 22 of the core substrate 20 and the first conductor layer 32 are electrically connected via a first via hole 33, and the first conductor layer 32 and the second conductor layer are connected. 35 is electrically connected via a second via hole 36. Such a build-up layer 30 is formed by a known subtractive method or additive method (including a semi-additive method or a full additive method).

  The pad group 40 is a group composed of an external pad 41 and an internal pad 43 formed on the upper surface of the second resin insulating layer 34 forming the buildup layer 30. In the present embodiment, as shown in FIG. 2, the pad group 40 is composed of 30 vertical pads × 30 horizontal pads 41 and 43 arranged in a grid pattern. In other words, the pad group 40 is multiplexed from the outermost periphery to the 15th column. Is formed. The pads 41 and 43 are provided at positions corresponding to lands 64 formed on the lower surface of the interposer 60. Also, as shown in FIG. 2, the outer region Aext (shown by shading in FIG. 2) from the outermost periphery to the tenth column in the region where the pad group 40 is formed, is closer to the center than the outer region Aext. This area is called an inner area Aint. The pads arranged in the outer area Aext are called external pads 41, and the pads arranged in the inner area Aint are called internal pads 43. In FIG. 2, the external pad 41 extends from the outermost periphery to the 10th row, but only the outermost periphery may be used as the external pad 41, or the external pad extends from the outermost periphery to the nth row (n is an integer of 2 to 9). The pad 41 may be used. In FIG. 2, the pads 41 and 43 are arranged in a grid pattern. However, the arrangement is not limited to this. For example, the pads 41 and 43 may be arranged in a zigzag pattern. May be arranged in a zigzag pattern or randomly, or a part may be arranged in a zigzag pattern and the rest may be arranged in a grid pattern or randomly, or a part of them may be arranged randomly and the rest in a grid pattern or zigzag pattern. , May be randomly arranged throughout.

  The external pad 41 is electrically joined to the IC chip 70 via the interposer 60. The external pad 41 is formed on a substantially flat wiring portion of the wiring pattern 35 a drawn out in the outer peripheral direction in the second conductor layer 35 of the buildup layer 30. Further, the wiring pattern 35 a on which the external pad 41 is formed is electrically joined to the first conductor layer 32 below through a via hole 36 a formed outside the external pad 41.

  The internal pad 43 is electrically joined to the IC chip 70 via the interposer 60. The internal pad 43 penetrates the resin insulating layer 34 substantially directly below without being drawn outwardly on the upper surface of the second resin insulating layer 34 of the buildup layer 30 and the first conductor layer 32 below. Here, the second via hole 36b penetrating the second resin insulating layer 34 and the opening peripheral portion of the via hole 36b in the second conductor layer 35 are formed. The via hole 36b may be filled with a conductor to form a filled via, and a portion directly above the filled via may be used as the internal pad 43.

  The interposer 60 includes a base substrate 61 having a thickness of 200 μm formed of zirconia ceramic (thermal expansion coefficient is about 7 ppm / ° C.), a plurality of conductor vias 62 penetrating both the front and back surfaces of the base substrate 61, and the conductor vias 62. The lands 63 are formed on the upper surface side, and the lands 64 are formed on the lower surface side of the conductor vias 62. In this interposer 60, the lands 63 are electrically joined to the input / output terminals provided on the back surface of the IC chip 70 through solder bumps 71, and the lands 64 are external pads 41 forming the pad group 40 of the multilayer printed wiring board 10. Further, they are electrically joined via the internal pads 43 and the solder bumps 51 and 53. The lands 63 and 64 may not be formed, and the conductor via 62 and the IC chip 70 may be directly joined by solder, or the conductor via 62 and the multilayer printed wiring board 10 may be joined directly by solder. The conductor via 62 is formed in a shape having a constriction, specifically, a shape in which the diameter of the intermediate portion is smaller than the diameter of the upper portion or the lower portion. Of the conductor vias 62, those disposed at the peripheral edge of the interposer 60 are referred to as outer conductor vias 62a, and those disposed at the center are referred to as inner conductor vias 62b. In FIG. 1, only a few conductor vias 62 are shown for convenience. Actually, however, as shown in the layout diagram of the conductor vias 62 in FIG. The outer conductor vias 62a are formed up to the eyes (that is, up to 2/3 of the total 15 rows, indicated by shading in FIG. 3), and the others are used as the inner conductor vias 62b. Here, regarding the outer conductor via 62a and the inner conductor via 62b, the ratio of the height to the aspect ratio Rasp, that is, the minimum diameter (diameter of the intermediate portion) is 4 or more, and the minimum diameter is more than 30 μm. The aspect ratio Rasp of the outer conductor via 62a is designed to be greater than or equal to the aspect ratio Rasp of the inner conductor via 62b. Specifically, the aspect ratio Rasp of the outer conductor via 60a is greater than or equal to 1.25 times that of the inner conductor via 60b. Designed to be: Although FIG. 3 shows an example in which the conductor vias 62 are arranged in a grid pattern, the conductor vias 62 may be arranged in a zigzag pattern as shown in FIG. 4, or may be randomly arranged if the rows can be counted from the outer periphery. Also good.

  Next, a manufacturing example of the multilayer printed wiring board 10 will be described with reference to FIGS. Here, a starting material is a copper-clad laminate 201 in which copper foil 205 is laminated on both surfaces of an insulating substrate 203 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 0.8 mm (FIG. 5 ( a)), through-holes 207 are formed in the copper-clad laminate 201 by a drill, and electroless plating is performed followed by electrolytic plating to cover the upper and lower surfaces of the copper-clad laminate 201 and the surface of the through-holes 207 A layer 209 was formed (see FIG. 5B). Next, the through-hole filling resin composition 210 is filled into the through-hole 207 using a squeegee, dried and then polished and flattened until the conductor surface is exposed, and then subjected to heat treatment to fill the through-hole. The resin composition 210 was cured (see FIG. 5C). Next, the substrate was immersed in an electroless copper plating aqueous solution to form an electroless copper plating film 211 on the surface of the substrate, and then subjected to electrolytic copper plating to form an electrolytic copper plating film 213 (see FIG. 5D). ). Next, this substrate was etched into a pattern by a normal photographic method, whereby wiring patterns 22 were formed on both the upper and lower surfaces to form the core substrate 20 (see FIG. 5E). The insulating substrate 203 serves as the core substrate body 21, and the plating layer 209 in the through hole 207 serves as the through hole conductor 24.

Subsequently, the insulating layer resin films 301 are attached to both the front and back surfaces of the core substrate 20 by a vacuum pressure laminating method, and the insulating layer resin film 301 is through-holed by a CO ₂ gas laser through a mask in which through holes are formed. After forming 303, heat treatment was performed to completely cure the insulating layer resin film 301 to form the first resin insulating layer 31 (see FIG. 6A). Next, the substrate in the middle of the production is immersed in an electroless copper plating aqueous solution, and an electroless copper plating film 305 is formed on the surface of the first resin insulating layer 31 (including the inner wall surface of the through hole 303). A commercially available photosensitive dry film was attached, a mask was placed, and exposure / development was performed to provide a plating resist 307 (see FIG. 6B). Next, electrolytic copper plating is applied to the substrate to form an electrolytic copper plating film 309 in the plating resist non-forming portion, and then the plating resist 307 is peeled and removed, and then the portion of the electroless copper plating film 305 exposed on the surface Was removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide solution to form a first conductor layer 32 having an independent circuit pattern (see FIG. 6C). The first conductor layer 32 is composed of a laminate of an electroless copper plating film 305 and an electrolytic copper plating film 309 formed on the surface of the first resin insulation layer 31. At this time, the first conductor layer 32 is connected to the core substrate 20 via the first via hole 33 (a laminate of the electroless copper plating film 305 and the electrolytic copper plating film 309 formed in the through hole 303). The pattern 22 is electrically connected. The insulating layer resin film similar to the insulating layer resin film 301 used earlier is pasted on both the front and back surfaces of the substrate in the middle of the production by the vacuum pressure laminating method, and the insulating layer resin film pasted in the same procedure as before. Was processed into the second resin insulation layer 34, and the second conductor layer 35 and the second via hole 36 were formed to complete the build-up layer 30 (see FIG. 6D). Note that FIG. 6D and FIG. 7 described later show only the upper half of the substrate cross section.

  A solder resist layer 45 having a circular pattern (mask pattern) formed thereon was formed by applying a solder resist composition on both sides of the substrate on which the build-up layer 30 was formed, drying, and exposing and developing (FIG. 7 ( a)). At this time, a substantially flat wiring portion of the wiring pattern 35a formed on the outermost periphery of the second conductor layer 35 is opened to form an external pad 41, and a pattern other than the outermost periphery of the second conductor layer 35 is formed. The via hole 36 and its peripheral portion were opened to form an internal pad 43. Next, after forming a nickel plating layer on the pads 41 and 43 and further forming an electroless gold plating layer thereon, the solder bumps 51 and 53 are formed by printing solder paste on the pads 41 and 43 and reflowing them. Thus, the multilayer printed wiring board 10 was completed (see FIG. 7B). Then, an IC chip 70 was mounted on the multilayer printed wiring board 10 via an interposer 60. An underfill may be filled between the IC chip 70 and the interposer 60 and between the interposer 60 and the multilayer printed wiring board 10.

  Next, a method for manufacturing the interposer 60 will be described with reference to FIGS. Here, a zirconia substrate 641 which is an insulating substrate having a size of 32 mm × 32 mm × thickness 200 μm was used as a starting material (see FIG. 8A). The Young's modulus of this zirconia substrate 641 was 200 GPa as measured by a three-point bending method. A urethane resist 642 was formed on both surfaces of the zirconia substrate 641, and an opening 642a (for example, φ120 μm) was formed at a position to be the outer conductor via 62a in the future by a normal photographic method (see FIG. 8B). Next, by performing sandblast processing on both sides with a sandblasting device manufactured by Makina, a frustoconical cavity is formed from both the front and back surfaces, and these two cavities are connected inside the substrate to form a through hole 643a having a constriction. (See FIG. 8C). Thereafter, the resist 642 is peeled off, and a urethane-based resist 644 is formed again on both surfaces, and an opening 644b (for example, φ100 μm) is formed at a position to become the inner conductor via 62b by a normal photographic method (FIG. 8D). )reference). Next, by performing sandblast processing on both sides with the sandblasting device described above, a frustoconical cavity was formed from both the front and back surfaces, and these two cavities were connected inside the substrate to form a through hole 643b having a constriction ( (Refer FIG.8 (e)). The through hole 643a has a maximum diameter of 120 μm, a minimum diameter of 40 μm, and a height of 200 μm (aspect ratio Rasp = 5), and the through hole 643b has a maximum diameter of 100 μm, a minimum diameter of 50 μm, and a height of 200 μm (aspect ratio Rasp = 4). The conditions of the sandblasting device (abrasive material, abrasive grain average particle size, abrasive jetting pressure and number of shots) were set.

Thereafter, the resist 644 was peeled off (see FIG. 9A), and a metal film 645 was formed on the zirconia substrate 641 on which the through holes 643a and 643b were formed (see FIG. 9B). The metal film 645 is formed by first forming a 0.1 μm chromium film on the surface of the zirconia substrate 641 and the inner walls of the through holes 643a and 643b by sputtering, and then depositing a 0.14 μm nickel film on the chromium film. Further, the substrate 641 is immersed in an electroless copper plating aqueous solution to form an electroless copper plating film having a thickness of 0.6 to 3.0 μm on the surface of the substrate 641 and the inner walls of the through holes 643a and 643b. Formed. The composition of the electroless copper plating solution at this time is as follows. Copper sulfate 0.03 mol / l, EDTA 0.200 mol / l, HCHO 0.18 g / l, NaOH 0.100 mol / l, α, α′-bipyridyl 100 mg / l, polyethylene glycol (PEG) 0.10 g / l. The electroless copper plating was performed at a liquid temperature of 34 ° C. for 40 minutes. Subsequently, an electrolytic copper plating film 646 is formed on the surface of the substrate 641 by filling the through holes 643a and 643b using a plating solution and plating conditions preferentially deposited in the through holes 643a and 643b on the metal film 645. It formed (refer FIG.9 (c)). The composition of the electrolytic plating solution at this time is as follows. 150 g / l sulfuric acid, 160 g / l copper sulfate, 19.5 ml / l additive. The electrolytic plating conditions were a current density of 6.5 A / dm ² , a time of 80 minutes, a temperature of 22 ± 2 ° C., and stirring as jet stirring.

  Thereafter, both surfaces are polished until the surface of the substrate 641 is exposed (see FIG. 9D), and nickel (5 μm) and gold plating (0.03 μm) are applied on the copper plating of the via holes exposed on both surfaces. The land 63 was formed on the front side and the land 64 was formed on the back side to complete the interposer 60 (see FIG. 9E). The nickel plating was performed by immersing in an electroless nickel plating solution having a pH of 5 consisting of nickel chloride 30 g / l, sodium hypophosphite 10 g / l, and sodium citrate 10 g / l for 20 minutes. Gold plating is performed on an electroless gold plating solution composed of 2 g / l potassium gold cyanide, 75 g / l ammonium chloride, 50 g / l sodium citrate, and 10 g / l sodium hypophosphite at 93 ° C. for 23 seconds. This was done by dipping. In FIG. 9 (e), the metal film 645 and the electrolytic copper plating film 646 in the through hole 643a located at the peripheral edge correspond to the outer conductor via 62a, and the metal film 645 formed in the through hole 643b located in the center. The electrolytic copper plating film 646 corresponds to the inner conductor via 62 b, and the substrate 641 corresponds to the base substrate 61. Thereafter, solder bumps may be formed by printing solder on the lands 63 and 64 and then reflowing at 230 ° C. However, it is not particularly necessary to form solder bumps.

  In the present embodiment described in detail above, the multilayer printed wiring board 10 is repeatedly heated and cooled around the conductor via 62 (particularly, at the interface between the conductor via 62 and the base substrate 61) in the base substrate 61 of the interposer 60. However, since the aspect ratio Rasp of each conductor via 62 is 4 or more, the stress caused by each conductor via 62 is relatively small. Further, the stress caused by the multilayer printed wiring board 10 is larger in the peripheral portion than in the central portion, but is caused by the conductor via 62 because the aspect ratio Rasp of the outer conductor via 62a is greater than the aspect ratio Rasp of the inner conductor via 62b. On the contrary, the stress is smaller at the periphery than at the center. As a result, the difference between the stress caused by the multilayer printed wiring board 10 and the stress caused by the conductor via 62 is small between the central portion and the peripheral portion, so that the stress is not concentrated on the peripheral portion. Moreover, since each conductor via 62 has a diameter exceeding 30 μm, it is easy to ensure electrical connection even if stress is applied. Therefore, according to this interposer 60, there is no possibility that cracks due to thermal expansion / contraction will occur in the peripheral portion of the base substrate 61 even if heating / cooling is repeated while being connected to the multilayer printed wiring board 10. The IC chip 70 can be supplied with stable power. Further, since the diameter of the conductor via 62 exceeds 30 μm, the electrical resistance of the conductor via 62 is lowered.

  Further, since the aspect ratio Rasp of the outer conductor via 62a is not less than 1.25 times and not more than twice the aspect ratio Rasp of the inner conductor via 62b, the above-described effect can be more easily obtained. Furthermore, since the conductor via 62 is formed in a shape having a constriction, the rate of change in electrical resistance when heating and cooling are repeated can be further suppressed as compared with the case where the conductor via 62 is formed in a substantially straight shape. . Furthermore, the range of the conductor vias 62 from the outermost periphery to the 10th row (that is, 2/3 of the entire (15 rows)) is defined as the outer conductor via 62a. The stress caused by the conductor vias 62 in this range is Since the stress is larger than the stress caused by the other conductor vias 62, the significance of applying the present invention is great. Further, since the outer conductor via 62a is connected to the external pad 41 formed in a substantially flat shape on the multilayer printed wiring board 10, it is compared with the case where it is connected to the interpad 43 formed in a recessed shape. Since no voids (voids) or corners are formed inside the solder bumps, the joining portion is not easily broken, and the joining reliability can be maintained for a long time. Furthermore, since the thickness of the base substrate 61 is 200 μm and is 0.1 times or more the thickness of the printed wiring board 1.02 mm, the ceramic base substrate 61 is difficult to break.

  Particularly, in the interposer 60, the outer conductor via 62a is mainly connected to the signal terminal of the semiconductor chip 70, the inner conductor via 62b is connected to the power supply terminal of the semiconductor chip 70, and the outer conductor via 62b is connected to the ground terminal of the semiconductor chip 70. May be alternately arranged in a staggered pattern or a lattice pattern. By doing so, since the one connected to the power supply terminal and the one connected to the ground terminal are alternately arranged close to each other, the mutual inductance is reduced and the fluctuation of the power supply potential is reduced. As a result, even if the semiconductor chip 70 is in a high frequency region of 3 GHz or more, where power shortage of the transistor is likely to occur, power shortage is less likely to occur.

  It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

For example, in the embodiment described above, the interposer 60 is manufactured using a zirconia substrate, which is a ceramic substrate, as a starting material. However, the interposer 60 may be manufactured using a green sheet as a starting material, and an example is shown in FIG. First, 1 kg of AlN powder having an average particle size of 1.4 μm was mixed with 220 g of an acrylic binder, 50 g of Y ₂ O ₃ as a sintering aid, and 400 mL of an alcohol solvent. This mixture was uniformly kneaded with a ball mill to prepare a highly viscous raw material slurry. And according to the doctor blade method, the green sheet 651 was shape | molded from the raw material slurry (refer Fig.10 (a)). Next, a stamper 652a whose tip is formed in a conical shape to form the outer conductor via 62a (see FIG. 1) and a tip that is shaped in a conical shape to form the inner conductor via 62b (see FIG. 1). The stamper 652b is prepared, the stamper 652a is disposed at the position of the outer conductor via 62a on the surface of the green sheet 651, the stamper 652b is disposed at the position of the inner conductor via 62b, and both the stampers 652a and 652b are pressed to form a cone. The shape portion was penetrated from above (see FIG. 10B). Next, a stamper 652a is disposed at the position of the outer conductor via 62a on the back surface of the green sheet 651, and a stamper 652b is disposed at the position of the inner conductor via 62b, and both the stampers 652a and 652b are pressed to lower the conical portion. (See FIG. 10 (c)). As a result, a through hole 653a having a shape with a crease at the peripheral edge of the green sheet 651 was made transparent, and at the same time, a through hole 653b was made transparent at the center (see FIG. 10D). Next, 2 g of an acrylic binder, 3 mL of an ether solvent, and 0.1 g of an ether dispersant were mixed with 100 g of tungsten powder having an average particle size of 3 μm. This mixture was uniformly kneaded with a three-roll mixer to obtain a tungsten paste P for forming a conductor circuit. And the paste P was printed on the green sheet 651 using the screen printer. As a result, as shown in FIG. 10E, the through holes 653a and 653b were filled with the paste P, and disc portions were formed with the paste P on the upper and lower surfaces of the through holes 653a and 653b. Next, the green sheet 651 was placed in a dryer, and the green sheet 651 was heated at a temperature increase rate of 5.0 ° C./min. And after the temperature in a dryer reached 150 degreeC, the temperature was hold | maintained for about 24 hours, the green sheet 651 was fully dried, and it stood to cool to room temperature after that. Subsequently, the green sheet 651 was degreased and pre-baked at 1600 ° C. for 5 hours in an inert atmosphere. Further, the temporarily fired green sheet 651 was fired at 1850 ° C. for 3 hours in the same atmosphere. Thereby, an interposer 60 made of AlN was obtained (see FIG. 10F). In this interposer 60, the green sheet 651 becomes the base substrate 61 (thickness 200 μm), and the paste P filled in the through hole 653a becomes the outer conductor via 62a (maximum diameter 120 μm, minimum diameter 40 μm, height 200 μm). The paste P filled in 653b becomes the inner conductor via 62b (maximum diameter 100 μm, minimum diameter 50 μm, height 200 μm), and the disk portions formed on the upper and lower surfaces of the through holes 653a and 653b become the lands 63 and 64, respectively. In the stage of the green sheet 651 before firing, the thickness and the shape of the through holes 653a and 653b are set to values that allow for the shrinkage rate in the target numerical values.

  In the above-described embodiment, the outer conductor via 62a and the inner conductor via 62b have a shape with a neck, but may have a substantially straight shape. Also in this case, the conductor via 62 has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and among the conductor vias 62, the aspect ratio Rasp of the outer conductor via 62a is equal to or larger than the aspect ratio Rasp of the inner conductor via 62b ( (Refer FIG.11 (f)). An example of a manufacturing procedure of an interposer provided with a substantially straight conductor via 62 will be described with reference to FIG. First, a zirconia substrate 661 similar to that of the above-described embodiment is used as a starting material (see FIG. 11A), a urethane resist 662 is formed on the upper surface of the zirconia substrate 661, and a future outer conductor is formed by a normal photographic method. An opening 662a (for example, φ33 μm) was formed at a position to be the via 62a, and an opening 662b (for example, φ50 μm) was formed at a position to be the inner conductor via 62b in the future (see FIG. 11B). Next, sandblasting is performed on the upper surface with a sandblasting device manufactured by Makina to form a through hole 663a having a substantially straight shape and a small diameter from the opening 662a, and forming a through hole 663b having a substantially straight shape and a large diameter from the opening 662b. Thereafter, the resist 662 was peeled off (see FIG. 11C). Subsequent procedures were performed according to FIGS. 9 (a) to 9 (e). That is, a metal film 665 is formed on the zirconia substrate 661 in which the through holes 663a and 663b are formed (see FIG. 11D), and using a plating solution and plating conditions preferentially deposited in the through holes 663a and 663b, Filling the through holes 663a and 663b and forming an electrolytic copper plating film 666 on the surface of the substrate 661 (see FIG. 11E), then polishing both surfaces until the surface of the substrate 661 is exposed, and exposing the exposed vias on both surfaces. Lands 63 and 64 were formed on the hole copper plating to obtain an interposer 60 (see FIG. 11F). In FIG. 11 (f), the metal film 665 and the electrolytic copper plating film 666 in the through hole 663a located at the peripheral portion correspond to the outer conductor via 62a, and the metal film 665 formed in the through hole 663b located at the center. The electrolytic copper plating film 666 corresponds to the inner conductor via 62 b, and the substrate 661 corresponds to the base substrate 61.

  As another manufacturing procedure of the substantially straight conductor via 62, a case where a green sheet is used as a starting material will be described with reference to FIG. First, a green sheet 671 is formed in the same manner as in FIG. 10A (see FIG. 12A), and a substantially straight through-hole is formed at a position that will become the outer conductor via 62a in the future by punching, laser processing, or drilling. A hole 673a (for example, φ33 μm) was formed, and a substantially straight through hole 673b (for example, φ50 μm) was formed at a position that will become the inner conductor via 62b in the future (see FIG. 12B). Since the subsequent procedure is performed in accordance with FIGS. 10D to 10F, description thereof is omitted here.

  Below, the experiment example for demonstrating the effect of the interposer 60 of this embodiment is demonstrated. First, the relationship between the conductor via aspect ratio Rasp and the rate of change in electrical resistance after repeated heating and cooling will be described. Here, an interposer provided with conductor vias of Experimental Examples 1 to 24 shown in Table 1 (length 30 × width 30, that is, formed in multiple layers from the outermost periphery to the 15th column) was produced. In Table 1, the interposers of Experimental Examples 1 to 12 have conductor vias having the same minimum diameter and maximum diameter, that is, substantially straight columnar conductor vias, which are manufactured according to the manufacturing procedures of FIGS. 8 and 9. did. In addition, the interposers of Experimental Examples 13 to 24 have conductor vias having different minimum and maximum diameters, that is, conductor vias having a shape, which were manufactured according to the manufacturing procedure of FIG. An IC chip having a porous interlayer insulating film is mounted on a multilayer printed wiring board through the interposer of each experimental example thus obtained, and then between the IC chip and the interposer, and between the interposer and the multilayer printed wiring board. A sealing resin was filled in between to form an IC mounting substrate. Then, the electrical resistance of the specific circuit through the IC chip (the electrical resistance between the pair of electrodes exposed to the surface opposite to the IC chip mounting surface of the IC mounting substrate and conducting to the IC chip) is measured, The value was taken as the initial value. Thereafter, a heat cycle test was performed on these IC-mounted substrates, with -55 ° C. × 5 minutes and 125 ° C. × 5 minutes as one cycle, and this was repeated 2000 cycles. In this heat cycle test, the electrical resistance at 250th cycle, 500th cycle, 750th cycle, 1000th cycle, 1250th cycle, 1500th cycle, and 2000th cycle was measured, and the rate of change from the initial value (100 × (100 × ( Measured value−initial value) / initial value (%)). The results are shown in Table 1. In this table, when the rate of change in electrical resistance is within ± 5%, “excellent” (◎), when ± 5 to 10%, “good” (◯), and when it exceeds ± 10%, “bad” (X). Here, if the rate of change of electrical resistance is small, it means that the conductor vias of the interposer, particularly the outer conductor vias and their surroundings, are small and power can be stably supplied to the IC chip. If the rate of change of electrical resistance is large, the outside of the interposer This means that cracks are generated in the conductor via and its periphery, and the IC chip is damaged so that power cannot be stably supplied to the IC chip. The target specification was such that the rate of change at the 1000th cycle was within ± 10% (that is, “good” or “excellent” in evaluation).

表１から明らかなように、外側導体ビア及び内側導体ビアはいずれもアスペクト比Ｒａｓｐが４以上で直径が３０μｍを超え、しかも外側導体ビアのアスペクト比Ｒａｓｐが内側導体ビアのアスペクト比Ｒａｓｐ以上という条件を満足するもの（実験例２〜４，６〜１０，１４〜１６，１８〜２０，２４）については、いずれも１０００サイクル目まで評価が「良」以上であったのに対して、この条件を満足しないもの（実験例１，５，１１〜１３，１７，２１，２２）については、いずれも１０００サイクル目までのいずれかの段階で評価が「不良」であった。また、外側導体ビアのアスペクト比が内側導体ビアのアスペクト比の２倍を超える実験例２３では、７５０サイクル目までは評価が「良」で１０００サイクル目以降は「不良」、外側導体ビアのアスペクト比が内側導体ビアのアスペクト比の２倍である実験例２４では、１０００サイクル目までは評価が「良」で１２５０サイクル目以降は「不良」であった。なお、かっこ内の数値は抵抗変化率を示している。

As is apparent from Table 1, the outer conductor via and the inner conductor via both have an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and the outer conductor via aspect ratio Rasp is more than the inner conductor via aspect ratio Rasp. For those satisfying the above conditions (Experimental Examples 2 to 4, 6 to 10, 14 to 16, 18 to 20, 24), the evaluation was “good” or higher up to the 1000th cycle. For those not satisfying (Experimental Examples 1, 5, 11 to 13, 17, 21, 22), the evaluation was “bad” at any stage up to the 1000th cycle. In Experimental Example 23, the aspect ratio of the outer conductor via exceeds twice the aspect ratio of the inner conductor via, the evaluation is “good” until the 750th cycle, “bad” after the 1000th cycle, and the aspect of the outer conductor via. In Experimental Example 24 in which the ratio was twice the aspect ratio of the inner conductor via, the evaluation was “good” until the 1000th cycle, and “bad” after the 1250th cycle. The numbers in parentheses indicate the rate of resistance change.

  Further, for example, when Experimental Example 2 is compared with Experimental Examples 3 and 4, the outer conductor via aspect ratio Rasp is 1.25 times to twice the aspect ratio Rasp of the inner conductor via. The evaluation was “good” up to a longer cycle number than the former in which the aspect ratio Rasp of the via and the aspect ratio Rasp of the inner conductor via were equal. The same is true even if Experimental Example 6 and Experimental Examples 7 and 8 are compared, Experimental Example 14 and Experimental Examples 15 and 16 are compared, or Experimental Example 18 and Experimental Examples 19 and 20 are compared. I can say that.

  Further, for example, when Experimental Example 2 and Experimental Example 14 are compared with each other, the outer conductor vias are only one row at the outermost periphery, but the latter in which the conductor vias are constricted as compared with the former in which the conductor vias are straight. The evaluation was “good” up to a longer cycle number. The same can be said by comparing Experimental Example 3 and Experimental Example 15 or comparing Experimental Example 4 and Experimental Example 16. Also, the experimental example 6 and the experimental example 18 in which the outer conductor vias are from the outermost circumference to the tenth row are compared, the experimental example 7 and the experimental example 19 are compared, and the experimental example 8 and the experimental example 20 are compared. Even so, the evaluation was “excellent” or “good” up to a longer cycle number.

  Furthermore, for example, when Experimental Examples 3, 7, 9, and 10 are compared, all of these have an outer conductor via aspect ratio Rasp of 5 and an inner conductor via aspect ratio Rasp of 4, but the outermost outer periphery of the conductor vias. Experimental example 3 in which only one row is an outer conductor via, Experimental example 9 in which the outermost via to the third row are outer conductive vias, Experimental example 10 in which the outermost via to the sixth row are outer conductive vias, From the outermost periphery The evaluation tends to be “good” up to a longer cycle number in the order of Experimental Example 7 in which up to the 10th row is the outer conductor via.

  Next, the relationship between the position of the conductor via of the interposer and the stress applied to the position will be described. A 3D strip simulation is performed on an IC mounting substrate in which an IC chip having a porous interlayer insulating film is mounted on a multilayer printed wiring board via an interposer, and the number of conductor vias and the number of conductor vias and the base substrate of the interposer are determined. The relationship with the stress applied to the interface was calculated. Note that the conductor vias of the interposer were formed in multiple layers from the outermost periphery to the 15th row so as to correspond one-to-one with the pads of the multilayer printed wiring board. Also, the conductor vias had the same aspect ratio of 1, and the materials such as interposer, conductor via, IC chip, multilayer printed wiring board, and solder were the same. And it calculated by inputting those Young's modulus, Poisson's ratio, and thermal expansion coefficient. The results are shown in the table and graph of FIG. As is apparent from this table and graph, a relatively large stress is applied to the position of the conductor via of the interposer from the outermost circumference to the 10th column (the total number of rows × 2/3 rows), and the sixth row from the outermost circumference ( It can be seen that particularly large stress is applied up to the total number of rows × 2 / 5th column). As a result, since there is little need to relieve stress at the positions exceeding the total number of rows × 2/3 rows from the outermost circumference (conductor vias inside the 2/3 rows) of the conductor vias, It is preferable to set the outer conductor via within the range up to the number of columns × 2/3, and it is particularly preferable to set the outer conductor via within the range from the outermost circumference to the total number of columns × 2/5 columns. .

It is sectional drawing of the board | substrate for semiconductor mounting of this embodiment. It is a layout view of the pad group of the multilayer printed wiring board of the present embodiment. It is a layout view of conductor vias of the interposer of the present embodiment. It is an arrangement plan of other conductor vias. It is sectional drawing showing the preparation procedures of the multilayer printed wiring board of this embodiment. It is sectional drawing showing the preparation procedures of the multilayer printed wiring board of this embodiment. It is sectional drawing showing another preparation procedure of the multilayer printed wiring board of this embodiment. It is sectional drawing showing the interposer preparation procedure of this embodiment. It is sectional drawing showing the interposer preparation procedure of this embodiment. It is sectional drawing showing the other interposer preparation procedure. It is sectional drawing showing the other interposer preparation procedure. It is sectional drawing showing the other interposer preparation procedure. It is a table and a graph showing the relationship between the position of the conductor via of an interposer, and the stress concerning that position.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Multilayer printed wiring board, 20 ... Core board | substrate, 21 ... Core board | substrate body, 22 ... Wiring pattern, 24 ... Through-hole conductor, 30 ... Build-up layer, 31 ... 1st resin insulation layer, 32 ... 1st conductor Layer, 33 ... first via hole, 34 ... second resin insulating layer, 35 ... second conductor layer, 36 ... second via hole, 40 ... pad group, 41 ... external pad, 43 ... internal pad 45 ... solder resist layer, 51, 53 ... solder bump, 60 ... interposer, 62 ... conductor via, 62a ... outside conductor via, 62b ... inside conductor via, 63,64 ... land, 70 ... IC chip, 71 ... solder bump 80 ... Semiconductor mounting substrate, 201 ... Copper-clad laminate, 203 ... Insulating substrate, 205 ... Copper foil, 207 ... Through hole, 209 ... Plating layer, 210 ... Through-hole ,... Electroless copper plating film, 213. Electrolytic copper plating film, 301... Resin film for insulating layer, 303... Through hole, 305... Electroless copper plating film, 307. Electrolytic copper plating film, 641 ... Zirconia substrate, 642, 644 ... Resist, 642a, 644b ... Opening, 643a, 634b ... Through hole, 645 ... Metal film, 646 ... Electrolytic copper plating film, 651 ... Green sheet, 652a, 652b ... Stamper, 653a, 653b ... through hole, 661 ... zirconia substrate, 662 ... resist, 662a, 662b ... opening, 663a, 663b ... through hole, 665 ... metal film, 666 ... electrolytic copper plating film, 671 ... green sheet, 673a, 673b ... through hole.

Claims (7)

A base substrate made of ceramic;
An electronic component that penetrates both the front and back surfaces of the base substrate and is connected to one of the front and back surfaces and a printed wiring board that is connected to the other of the front and back surfaces are electrically connected to form a staggered, grid, or outer periphery row A plurality of conductor vias arranged in a random form ,
An interposer with
The conductor via has an aspect ratio Rasp of 4 or more and a diameter of more than 30 μm, and of the conductor vias, outer conductor vias arranged at a peripheral portion from the outermost periphery of the base substrate to a predetermined row toward the center . The aspect ratio Rasp is an interposer that is equal to or greater than the aspect ratio Rasp of the inner conductor via disposed in the central portion inside the predetermined row .   2. The interposer according to claim 1, wherein an aspect ratio Rasp of the outer conductor via among the conductor vias is not less than 1.25 times and not more than twice an aspect ratio Rasp of the inner conductor via.   The interposer according to claim 1 or 2, wherein at least the outer conductor via among the conductor vias is formed in a shape having a constriction.   4. The interposer according to claim 3, wherein the outer conductor via formed in a shape having a constriction has a maximum diameter / minimum diameter of 2 or more and 4 or less.   When the conductor vias are formed in multiples from the outermost circumference to the Nth row (N is an integer of 2 or more), the outer conductor vias are defined within a range from the outermost circumference to N × 2/3 rows, The interposer according to any one of claims 1 to 4.   The interposer according to any one of claims 1 to 5, wherein the outer conductor via is connected to a pad formed in a substantially flat shape on the printed wiring board.   The interposer according to any one of claims 1 to 6, wherein the thickness of the base substrate is at least 0.1 times the thickness of the printed wiring board.

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