JP4472064B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device using a crystalline semiconductor thin film. Note that the semiconductor device of the present invention includes not only a single element such as a thin film transistor but also an electronic device having a semiconductor circuit formed of a thin film transistor, typically a liquid crystal display device using an active matrix substrate, an image sensor, and the like. This category also includes electronic devices such as personal computers and digital cameras equipped with the above.
[0002]
[Prior art]
Thin film transistors (TFTs) are used in various integrated circuits. Since TFTs can be manufactured on insulating substrates such as glass and quartz, they are particularly suitable as switching elements for matrix circuits in active matrix liquid crystal display devices.
[0003]
As the semiconductor layer of the TFT, an amorphous silicon film or a polycrystalline silicon film is generally used. In order to form a driver circuit of a matrix circuit with TFTs, it is necessary to use a polycrystalline silicon film with high mobility as a semiconductor layer. In general, in order to form a polycrystalline silicon film used for a semiconductor layer, an amorphous silicon film is formed, thermal crystallization is performed by heat-treating the amorphous silicon film, or laser crystallization is performed by irradiating an excimer laser beam. Is used.
[0004]
Currently, the upper limit of the crystallization process temperature is required to be about 600 ° C. because of the heat resistance of the glass substrate used for the active matrix substrate. Due to the low temperature of crystallization, it takes 20 hours or more for thermal crystallization.
[0005]
On the other hand, a laser crystallization technique using an excimer laser is one of the techniques that makes it possible to lower the process temperature and shorten the process time. The energy of excimer laser light is absorbed and converted to heat at the extreme surface of amorphous silicon at a depth of about 10 nm, so that it is comparable to thermal annealing at around 1000 ° C. with almost no thermal effect on the substrate. Can be applied to the amorphous silicon film in a short time, and a highly crystalline semiconductor film can be formed.
[0006]
  As a TFT structure, a bottom gate type (typically an inverted stagger type) and a top gate type (typically a coplanar type) are typically known. The bottom gate type has a gate wiring (electrode) on the substrate.),The gate insulating film and the semiconductor layer are stacked in this order, and the top gate type is stacked in the order of the semiconductor layer, the gate insulating film, and the gate wiring (electrode).
[0007]
Referring to FIG. 18, a conventional TFT manufacturing process using inverted staggered polycrystalline silicon will be briefly described. FIG. 18 is a cross-sectional view of the TFT along the channel length (gate length).
[0008]
A metal film having a thickness of 300 to 500 nm, such as Cr or Ta, is formed on the glass substrate 1 by sputtering, and patterned into a tapered shape to form the gate wiring 2. Next, SiN is formed as the gate insulating film 3 by the CVD method._y(Silicon nitride) , SiO₂(Silicon oxide) is deposited to a thickness of 100 to 200 nm. Next, an amorphous silicon film 4 having a thickness of 50 to 100 nm is formed by CVD. (FIG. 18 (A))
[0009]
Crystallization is performed by irradiating excimer laser light to form a polycrystalline silicon film 5. (Fig. 18B)
[0010]
The polycrystalline silicon film 5 is patterned to form a semiconductor layer 6. Next, an impurity that becomes a donor or an acceptor is selectively added to the semiconductor layer 6 to form a source region 6S, a drain electrode 6D, and a channel formation region 6C. (Figure 18 (C))
[0011]
Next, as the interlayer insulating film 7, SiO is formed by CVD.₂A contact hole is formed in the interlayer insulating film 7, and a source electrode 8 and a drain electrode 9 are formed. (Fig. 18D)
[0012]
[Problems to be solved by the invention]
As shown in FIG. 18, in the manufacturing process of an inverted stagger type TFT using polycrystalline silicon, the thickness of the gate wiring is about 300 to 500 nm, and the thickness of the gate insulating film is 100 to 200 nm. As shown in FIG. 18A, the surface of the amorphous silicon film 4 has irregularities reflecting the shape of the gate wiring 2.
[0013]
In general, in laser crystallization, excimer laser light is shaped into a linear beam or a rectangular beam, and this beam is scanned and irradiated. However, due to the height difference of the surface of the amorphous silicon film 3, the focal position of the beam varies from place to place, and the energy given to the amorphous silicon film 3 varies from place to place. Since it is almost difficult to change the focal length of the beam according to this height difference, the polycrystalline silicon film 5 is subject to variations in crystallization due to the laser beam defocus. Variation in crystallization is a cause of variation in the threshold voltage of the TFT.
[0014]
  In addition, TFTs using polycrystalline silicon have a problem of large off-state current. The cause of off current, TThe reason is that when the FT is in the off state, the voltage applied to the drain electrode 9 is concentrated at the junction between the channel formation region 6C and the drain region 6D, and current flows through the trap at this junction. It has been.
[0015]
Further, in the TFT using polycrystalline silicon, the gate insulating film 3 is thinner than when amorphous silicon is used, and is 100 to 200 nm. Therefore, the edge 2a of the gate wiring 2 (see FIG. 18D) Step coverage is a problem. At the edge 2a, SiN is formed by CVD._y, SiO₂Therefore, the gate insulating film 2 becomes thin. For this reason, at the end 2a, the gate wiring 2 and the semiconductor layer 6 are short-circuited, electrons or holes are injected into the gate insulating film 3, the threshold voltage is shifted, and the gate insulating film 3 is static. Electrode breakdown is likely to occur, which causes the reliability of the TFT to deteriorate.
[0016]
An object of the present invention is to solve the above-described problems, and in a semiconductor device including a bottom gate type semiconductor element in which a gate wiring, a gate insulating film, and a semiconductor layer are stacked in this order, a structure for uniformizing laser crystallization, and It is to provide a manufacturing method thereof. At the same time, it is an object of the present invention to provide a structure of a bottom gate type semiconductor element in which off current is reduced and reliability is improved, and a manufacturing method thereof.
[0017]
[Means for Solving the Problems]
In order to solve the above-described problems, a semiconductor device of the present invention includes a gate electrode formed on an insulating surface, a planarization film formed of an insulating organic resin, and an insulating inorganic film formed to cover the gate electrode. A semiconductor device in which a gate insulating film having a stacked film and a semiconductor layer covering the gate insulating film are stacked, wherein the semiconductor layer is formed of a crystalline semiconductor film.
[0018]
Furthermore, the present invention is a method of manufacturing a semiconductor device having the above laminated structure,
Forming a gate wiring on the insulating surface;
Forming a planarization film made of an insulating organic resin so as to cover the gate wiring;
Forming an insulating inorganic film in contact with the planarization film;
Forming a semiconductor film having an amorphous component so as to cover the insulating inorganic film;
And a step of crystallizing the semiconductor film having an amorphous component to form a crystalline semiconductor film.
[0019]
Note that in this specification, a gate electrode refers to a portion where a gate wiring intersects with a semiconductor layer. The same applies to the relationship between the gate wiring and the gate electrode in the source / drain wiring and the source / drain electrode.
[0020]
In the above structure, the step of the gate electrode and the gate wiring is filled with the planarization film, so that the surface of the gate insulating film becomes flat. Therefore, since the semiconductor film having an amorphous component can be formed over a flat surface, the semiconductor film itself can be formed into a flat film. Therefore, even if crystallization is performed by irradiating with laser light, the focal position does not differ from part to part, so that crystallization can be made more uniform than in the conventional example.
[0021]
Further, the insulating organic resin film can be generally formed by a coating method, and the coating film has a much higher step coverage than the insulating inorganic film formed by the vapor phase method of the CVD method. Therefore, since the insulating resin film does not thin the organic resin film at the end of the gate wiring, the above-described short circuit between the gate wiring and the semiconductor layer and the dielectric breakdown of the gate insulating film can be prevented. The reliability and stability of the device can be improved.
[0022]
In addition, since the organic resin film has a relative dielectric constant smaller than that of the insulating inorganic film, the parasitic capacitance can be reduced even if the gate insulating film is a laminated film.
[0023]
Since the insulating inorganic film is formed by chemical vapor deposition such as CVD or physical vapor deposition such as sputtering, it contains less impurities than the organic resin film, and the size of the impurities is small. By having a laminated film of a resin film and an insulating inorganic film, pinholes in the gate insulating film can be reduced, and the interface between the semiconductor layer and the gate insulating film can be reduced rather than forming a semiconductor layer on the organic resin film. The level can be lowered.
[0024]
  NaOh,In the above structure, the semiconductor film having an amorphous component is a non-crystalline semiconductor film having no crystallinity or a semiconductor thin film having crystallinity but having almost no crystal grains on the order of 100 nm or more. Denotes an amorphous semiconductor film or a microcrystalline semiconductor film. A microcrystalline semiconductor film is a semiconductor film in a mixed phase of microcrystals including a crystal grain with a size of several nm to several tens of nm and an amorphous state.
[0025]
More specifically, the semiconductor film having an amorphous component is an amorphous silicon film, a microcrystalline silicon film, an amorphous germanium film, a microcrystalline germanium film, or an amorphous Si film._xGe_1-x(0 <x <1), and these semiconductor films are formed by a chemical vapor deposition method such as a plasma CVD method or a low pressure CVD method, or a physical vapor deposition method such as a sputtering method. The thickness of the semiconductor film is about 10 nm to 150 nm.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described with reference to FIGS. In this embodiment, an inverted stagger type TFT is used as a switching element of a matrix circuit of an active matrix substrate, that is, a so-called pixel TFT.
[0027]
Embodiment 1 This embodiment will be described with reference to FIG.
[0028]
As shown in FIG. 1A, a substrate 10 is prepared, and a base film 11 is formed on the surface of the substrate 10. The substrate 10 includes an insulating substrate such as a glass substrate, a quartz substrate, a ceramic substrate, a resin substrate, a single crystal silicon substrate, a stainless substrate, a Cu substrate, a refractory metal material such as Ta, W, Mo, Ti, Cr, or the like. A conductive substrate such as a substrate made of an alloy (for example, a nitrogen-based alloy) can be used.
[0029]
Moreover, when using the back surface exposure process used in the manufacturing process of bottom gate type TFT, the board | substrate 10 uses what has the transparency with respect to the light used for exposure. Typically, a glass substrate, a quartz substrate, a ceramic substrate, or a resin substrate can be used.
[0030]
The base film 11 is a film for preventing impurities from diffusing from the substrate into the semiconductor film. A bottom gate type semiconductor element is separated from a substrate by a gate insulating film, so that it does not need to be formed when an insulating substrate is used. However, by forming a base film 11, the bottom gate type semiconductor element is formed on the substrate 10. The adhesiveness of the insulating film and metal film to be formed can be improved.
[0031]
The base film 10 is made of silicon oxide (SiO 2) formed by CVD or the like.₂) Film or silicon nitride (SiN)_y) Film, silicon nitride oxide (SiO_xN_y) An insulating inorganic film such as a film can be used. For example, when a silicon substrate is used, the base film can be formed by oxidizing the surface by thermal oxidation. When a heat resistant substrate such as a quartz substrate or a stainless steel substrate is used, an amorphous silicon film may be formed and the silicon film may be thermally oxidized.
[0032]
In the case where the back exposure process is not used, as the base film 11, a high melting point metal film such as tungsten, chromium or tantalum or a film having high conductivity such as an aluminum nitride film is used as a lower layer, and the above insulating property is maintained. A laminated film in which an inorganic film is laminated on the upper layer may be used. In this case, since the heat generated in the semiconductor device is radiated from the coating under the base film 11, the operation of the semiconductor device can be stabilized.
[0033]
A conductive film is formed on the base film 11 and patterned to form the gate wiring 12. The conductive material for forming the gate wiring 12 is a material mainly composed of Al, or a high melting point metal such as Ta, W, Mo, Ti, Cr or an alloy thereof (for example, an alloy of high melting point metals, a high An alloy of a melting point metal and nitrogen can be used, and can be formed of a laminated film of listed materials, for example, a two-layer film of an Al film containing several weight percent of Sc and a Ta film, A three-layer film in which a Ta film is sandwiched between tantalum nitride alloy films can be used.
[0034]
In addition, when the back exposure process used in the manufacturing process of the bottom gate type TFT is used, the gate wiring material is a material having a light shielding property to the light used for the exposure.
[0035]
Next, a gate insulating film 13 is formed so as to cover the gate wiring 12. First, an insulating organic resin film is formed as the planarizing film 13a using a spin coater. Next, the insulating inorganic film 13b is laminated on the planarizing film 13a by sputtering or CVD. (Fig. 1 (A))
[0036]
The organic resin material used for the planarizing film 13a is a film on which the insulating inorganic film 13b can be deposited directly by sputtering or CVD, and raises the substrate temperature in the subsequent process to about 300 ° C. Select materials that can be capable. For example, benzocyclobutene (BCB), polyimide, or acrylic can be used.
[0037]
As the insulating inorganic film 13b, silicon oxide (SiO₂) Film, silicon nitride (SiN)_y) Film, silicon oxynitride (SiO_xN_y) A single-layer film or a laminated film thereof can be used.
[0038]
Since the insulating organic resin film can be formed by a coating method, the step due to the gate wiring 12 can be filled with the planarizing film 13a, and the gate insulating film 13 having a flat surface can be obtained. By forming the planarizing film 13a by a coating method, the thickness of the planarizing film 13a at the end portion of the gate wiring 12 is not reduced as in the prior art. Therefore, the gate wiring 12 and the semiconductor layer are short-circuited, electrons or holes are injected into the gate insulating film 13, and thus the threshold voltage is shifted, and the gate insulating film 13 is further electrostatically broken down. Can be prevented.
[0039]
Conventionally, in order to improve the coverage of the gate insulating film, the gate wiring 12 is patterned into a taper shape. However, the gate wiring 12 is covered with a planarizing film 13a having a sufficient thickness without being patterned into a taper shape. Is possible. Therefore, it is not necessary to use a complicated taper etching process.
[0040]
In addition, since the insulating inorganic film 13b is stacked on the planarizing film 13a, the pinhole density of the gate insulating film 13 can be reduced, and the shift of the threshold voltage can be reduced.
[0041]
In the gate insulating film 13, the thickness of the planarizing film 13 a is 10 nm to 0.1 μm at the portion sandwiched between the highest portion of the gate wiring 12 and the insulating inorganic film 13 b, and the insulating inorganic film 13 b The film thickness is 50 nm to 0.1 μm.
[0042]
Next, a semiconductor film 15 having an amorphous component is formed by a vapor phase method such as plasma CVD, low pressure CVD, or thermal CVD. Since the semiconductor film 15 is formed on the surface of the flat gate insulating film 13, there is no difference in height reflecting the shape of the gate wiring 12 as in the prior art. (Fig. 1 (B))
[0043]
Next, laser light with a wavelength of 400 nm or less or intense light with a wavelength of 400 nm or less is irradiated to crystallize the semiconductor film 15 to form a crystalline semiconductor film 16. For example, when an amorphous silicon film is crystallized, a polycrystalline silicon film is formed. (Figure 1 (C))
[0044]
An excimer laser can be used as a light source used for crystallization. For example, KrF excimer laser (wavelength 248 nm), XeCl excimer laser (wavelength 308 nm), XeF excimer laser (wavelength 351, 353 nm), ArF excimer laser (wavelength 193 nm), or the like can be used. A mercury lamp can be used as a light source that emits a wavelength of 400 nm or less.
[0045]
In the present invention, the semiconductor film 15 is formed flatter than in the prior art. Therefore, the focal length of the laser light or strong light irradiated in the crystallization step does not vary from part to part, and the light energy given to the semiconductor film becomes uniform, so that the crystallization variation can be reduced.
[0046]
Next, the obtained crystalline semiconductor film 16 is patterned into an island shape. Then, an impurity imparting a conductivity type that serves as a donor or an acceptor is selectively added to the island-shaped semiconductor film, so that the source region 17 and the drain region 18 are formed. The substantially intrinsic semiconductor layer portion is a channel formation region 19.
[0047]
After the patterning step of FIG. 1B, FIG. 1C, or the semiconductor film 16, a step of adding an impurity to the semiconductor film 26 or the semiconductor layer 28 in order to control the threshold value is added. It may be formed of an intrinsic semiconductor layer.
[0048]
Note that in this specification, intrinsic refers to a region that does not contain any impurities that can change the Fermi level of silicon. A substantially intrinsic semiconductor is a region in which electrons and holes are completely balanced to cancel the conductivity type, that is, a concentration range in which threshold control is possible (1 × 10 in SIMS analysis).¹⁴~ 1x10¹⁷atoms / cm^Three) Shows a region containing an impurity which imparts a conductivity type which becomes a donor or an acceptor, or a semiconductor whose conductivity type is offset by intentionally adding an impurity of a reverse conductivity type.
[0049]
And the semiconductor layer is made of SiO₂A source wiring 21 and a drain electrode 22 functioning as signal lines are formed by covering with an interlayer insulating film 20 made of, etc., and opening contact holes for the source / drain regions 17 and 18. Further, an interlayer insulating film 23 is formed so as to cover the source wiring 21 and the drain electrode 22. In order to make the cell gap uniform, it is preferable to form at least one leveling film such as BCB, polyimide, acrylic, etc. on the interlayer insulating film 23. Next, a contact hole for the drain electrode 22 is formed, and a pixel electrode 24 made of ITO or Al is formed.
[0050]
In FIG. 1, only the pixel TFTs arranged in one pixel are shown, but in actuality, they are arranged in a matrix on the substrate 10.
[0051]
Embodiment 2 This embodiment will be described with reference to FIGS. The present embodiment also relates to an example in which a bottom gate type TFT is applied to a pixel TFT of a matrix circuit, as in the first embodiment.
[0052]
In general, one or more pixel TFTs are formed in one matrix circuit, but it is required to make the characteristics of all the pixel TFTs uniform, in particular, the threshold voltage uniform. One of the major factors that shift the threshold voltage is the interface state between the channel and the gate insulating film.
[0053]
In view of this, in the present embodiment, a manufacturing method is shown in which the interface between the channel formation region of the semiconductor layer and the insulating film in contact with the channel formation region can be kept clean.
[0054]
  As in the first embodiment, the substrate 20ThePrepare a base film 21 on the surface of the substrate 20. A film made of the above-described conductive material is formed on the surface of the base film 21 and patterned into a tapered shape to form the gate wiring 22. Next, a gate insulating film 23 is formed so as to cover the gate wiring 22. First, an insulating organic resin film such as BCB, polyimide, or acrylic is formed as the planarizing film 23a using a spin coater. Next, SiO 2 is formed on the planarizing film 23a by sputtering or CVD.₂Film, SiN_yFilm, SiO_xN_yAn insulating inorganic film 23b such as a film is laminated. (Fig. 2 (A))
[0055]
  Next, the semiconductor film 24 having an amorphous component, and SiO₂, SiN_yOr SiO_xN_yThe protective film 25 is laminated without being exposed to the atmosphere. As the film forming means, a CVD method or a sputtering method can be used. By not exposing to the atmosphere, contaminants from the atmosphere are prevented from adhering to the interface between the semiconductor film 24 and the protective film 25. The semiconductor film 24 and the protective film 25 may be continuously formed in the same chamber, or each of the dedicated films is formed using a multitasking sputtering apparatus or a CVD apparatus.BaThe film may be formed by
[0056]
Alternatively, the insulating inorganic film 23b, the semiconductor film 24, and the protective film 25 are preferably stacked without being exposed to the atmosphere in order to keep the interface between the gate insulating film 23, the semiconductor film 24, and the protective film 25 clean. (Fig. 2 (B))
[0057]
The thickness of the protective film 25 is 5 to 50 nm, typically 10 to 20 nm. The protective film 25 protects the surface of the initial semiconductor film 24 from contamination by impurities in the atmosphere, or prevents the semiconductor film 24 from being contaminated by not forming a photoresist directly on the semiconductor film 24. It is. Further, the protective film 25 has an effect of improving the adhesion with the photoresist.
[0058]
When the state of FIG. 2B is obtained in this way, the semiconductor film 24 is irradiated with laser light having a wavelength of 400 nm or less or intense light equivalent thereto as described in the first embodiment, so that the crystalline semiconductor film 26 is formed. In this step, laser light or strong light equivalent thereto is irradiated through the protective film 25, so that the interface between the protective film 25 and the crystalline semiconductor film 26 is kept clean.
[0059]
Next, the protective film 25 and the crystalline semiconductor 26 are patterned into an island shape using the same photoresist mask to form the protective film 27 and the semiconductor layer 28. Thus, by maintaining the state in which the upper surface of the semiconductor layer 28 is covered with the protective film 27, the semiconductor layer 28 can be protected from air pollution. (Fig. 2 (D))
[0060]
Note that a step of adding impurities to the semiconductor film 26 or the semiconductor layer 28 may be added after the step of FIG. 2C or FIG.
[0061]
Next, a photoresist is applied and exposed from the back surface of the substrate 20 to form a resist mask 30 using the gate wiring 22 as a mask in a self-aligning manner. Here, the amount of exposure light is adjusted so that the gate electrode width in the channel length direction and the mask 30 width match, that is, the side surface of the gate electrode 22 and the side surface of the mask 30 match.
[0062]
Next, using this photoresist mask 30, an impurity that becomes a donor or an acceptor is added to the semiconductor layer 28 through the protective film 27 to form N-type or P-type impurity regions 31 and 32. Regions 31 and 32 are portions to be source / drain regions. (Fig. 3 (A))
[0063]
After the mask 30 is peeled off, a photoresist is applied again and exposed from the back surface of the substrate 20 to form a resist mask 34 in a self-aligning manner using the gate wiring 22 as a mask. In this case, the mask 34 is narrower than the gate electrode width in the channel length direction, and the side surface of the mask 34 is set to the inside of the gate wiring 22 by overexposure over the previous backside exposure. The mask 34 defines the length of the low concentration impurity region (LDD) and the channel length.
[0064]
An impurity which becomes a donor or an acceptor is added through the protective film 27 using the photoresist mask 34, and an N-type or P-type source region 35, an N-type or P-type drain region 36, N^-Mold or P^-Mold low concentration impurity regions 38 and 39 are formed. An intrinsic region to which no impurity is added in the two impurity addition steps becomes the channel formation region 37. After the impurity addition step, annealing is performed by irradiating excimer laser light in order to activate the added impurity.
[0065]
In this embodiment mode, the effect of reducing off-state current can be further increased by making the TFT have an LDD structure. Further, the gate wiring 22 is tapered, and the gate insulating film 23 has a laminated film including the planarizing film 23a and the insulating inorganic film 23b, so that the off-current can be further reduced.
[0066]
In other words, since the planarizing film 23a is formed so as to fill the step of the gate wiring 22, the thickness of the planarizing film 23a is such that the slope of the tapered portion of the gate wiring 22 (mostly low concentration impurities 38 and 39). The film thickness covering the lower portion) and the flat portion (portion existing under the channel formation region 37) are different, and the former is thicker. That is, the gate parasitic capacitance between the semiconductor layer 28 and the gate wiring 22 varies depending on the portion, the channel formation region 37 has a high gate parasitic capacitance, and the low concentration impurity regions 38 and 39 have a low parasitic capacitance.
[0067]
With this structure, a larger electric field is applied to the lower gate parasitic capacitance in the off state, so that the electric field concentrated at the end of the channel formation region 37 is dispersed in the low capacitance portions formed in the low concentration impurity regions 38 and 39. be able to. As a result, off-current can be reduced and deterioration of the gate insulating film 23 can be suppressed.
[0068]
  Next, SiO₂, SiN_yOr SiO_xN_yAn interlayer insulating film 40 composed of a single layer film or a multilayer film of an insulating film selected from the following is formed, contact holes for the source / drain regions 35 and 36 are formed, a metal film is formed and patterned, and signal lines and Source wiring 41, drainPowerThe pole 42 is formed.
[0069]
Further, an interlayer insulating film 43 that covers the source wiring 41 and the drain electrode 42 is formed. In the interlayer insulating film 43, it is preferable to form at least one leveling film such as BCB, polyimide, acrylic, etc. in order to make the cell gap uniform. Then, after forming contact holes for the source wiring 41 and the drain electrode 42 in the interlayer insulating film 43, a pixel electrode 44 made of ITO or Al is formed.
[0070]
【Example】
Hereinafter, examples of the present invention will be described with reference to FIGS.
[0071]
[Embodiment 1] In this embodiment, a manufacturing process for manufacturing a CMOS circuit using an inverted staggered TFT will be described. In this embodiment, the description will be given focusing on one CMOS circuit, but it goes without saying that a plurality of circuits can be formed on the same substrate.
[0072]
The present embodiment will be described with reference to FIGS. FIG. 4 shows a schematic top view of a CMOS circuit. In FIG. 4, reference numeral 102 denotes a gate wiring, 110 denotes a semiconductor layer of an N-channel TFT, and 111 denotes a semiconductor layer of a P-channel TFT. Reference numerals 145 and 146 denote contact portions between the semiconductor layers 110 and 111 and the source wiring, and reference numerals 147 and 148 denote contact portions between the semiconductor layers 110 and 111 and the drain wiring. Reference numeral 149 denotes a contact portion (gate contact portion) between the gate wiring 102 and the extraction wiring.
[0073]
The manufacturing process of the TFT will be described with reference to FIGS. In FIGS. 5 and 6, a cross-sectional view of the N-channel TFT is shown on the left side, and a cross-sectional view of the P-channel TFT is shown on the right side. The sectional view of each TFT corresponds to the sectional view taken along the chain line A-A 'and the chain line B-B' in FIG.
[0074]
First, a 1737 glass substrate manufactured by Cornings is used as the substrate 100. 200 nm-thick SiN as a base film 101 on the surface of the glass substrate 100_yIs deposited. Next, a laminated film of tantalum nitride film (30 nm) / tantalum film (300 nm) / tantalum nitride (300 nm) was formed by sputtering, and CF_FourAnd O₂The gate wiring 102 having a tapered cross section is formed by dry etching using a mixed gas.
[0075]
Next, a stacked film of a planarization film 103 to be a gate insulating film and an insulating inorganic film 104 is formed over the gate wiring 102. Note that the gate wiring 102 may be oxidized before the gate insulating film is formed. As the oxidation method, any one of a plasma oxidation method, an anodic oxidation method, and a thermal oxidation method may be used. In view of the throughput, the plasma oxidation method is preferable.
[0076]
A BCB film is formed as the planarizing film 103. First, the BCB solution is spin-coated by a spin coater, and the coater is further rotated to evaporate the solvent. Next, the BCB film 103 is formed on the entire surface of the substrate by baking at 200 to 250 ° C. in an inert atmosphere such as nitrogen or a reduced pressure atmosphere in a heating furnace. The thickness of BCB on the gate wiring 102 may be 50 to 200 nm. Next, as the insulating inorganic film 104, SiOB having a thickness of 60 nm in contact with the BCB film 103 is formed._xN_yA 55 nm thick amorphous silicon film 105 is formed on the insulating inorganic film 104, and a 100 nm thick SiO2 film is formed as the protective film 106._xN_yA film is formed.
[0077]
In this embodiment, the BCB film 103 is baked to SiO 2._xN_yThe protective film 106 is formed with a single CVD apparatus so that the substrate is not exposed to the atmosphere, and the interface state between the film 103 and the film 106 is improved.
[0078]
FIG. 7 is a schematic configuration diagram of a CVD apparatus used in this embodiment. 7A is a top view, and FIG. 7B is a cross-sectional view taken along the chain line XX ′ in FIG. 7A.
[0079]
In FIG. 7, 300 is a processing substrate, 301 is a common chamber, 302 and 303 are load lock chambers, 304 to 306 are CVD chambers, and 307 is a heating chamber. The chambers 302 to 307 are connected to the common chamber 301 while maintaining airtightness by gate valves 311 to 316. Each chamber is connected to an exhaust system for reducing the pressure and a gas supply system for supplying a gas for controlling the atmosphere and a reactive gas.
[0080]
The common chamber 301 has a robot arm 310 for moving the processing substrate 300. The robot arm 310 is movable three-dimensionally as indicated by an arrow. In the load lock chambers 302 and 303, cassettes for carrying the processing substrate 300 into and out of the apparatus are arranged.
[0081]
Each of the CVD chambers 304 to 306 has a substantially configuration, and in this embodiment, a parallel plate type plasma CVD apparatus having an upper electrode 341 connected to the ground potential and a lower electrode 342 connected to the RF power source 343 is used. . Other configurations may be used.
[0082]
The heating chamber 307 includes a substrate holder 351 for installing the processing substrate 300 and heating lamps 352 and 353.
[0083]
  Hereinafter, a method of forming a stacked film of the films 103 to 106 will be described using the apparatus shown in FIG. First, the substrate on which the BCB solution has been applied and dried by the spin coater is moved to the heating chamber 307. The BCB film 103 is formed by baking the heating chamber 307 in a nitrogen atmosphere at 250 ° C. Next, the robot arm 310 moves the substrate to the CVD chamber.304And the source gas is SiH₄And N₂Using O as the reaction gas, the substrate temperature is 300 ° C._xN_yA film (insulating inorganic film) 104 is formed. And SiH₄The amorphous silicon film 105 is formed at a substrate temperature of 300 ° C. Again, SiH₄And N₂O is supplied, and the substrate temperature is 300 ° C._xN_yA film (protective film) 106 is formed. The substrate on which the film has been formed is moved to the load lock chamber 302 or 303 and carried out of the apparatus.
[0084]
  Here, the films 104 to 106 are continuously formed in one CVD chamber 304 to avoid temperature change and contamination accompanying the movement of the substrate, but the process throughput, the design of the gas supply system of the apparatus, etc. In viewAffinityThe inorganic film 104, the semiconductor film 105, and the protective film 105 may be formed in separate CVD chambers. In addition, an amorphous silicon film 105 which is a semiconductor film and an inorganic film which is an insulating film104A CVD chamber in which the protective film 106 is formed may be separated.
[0085]
As shown in FIG. 5A, the gate wiring 102, the BCB film 103, and the SiO 2 are formed on the base film 101._xN_yFilm 104, amorphous silicon film 105, SiO_xN_yWhen the structure in which the film 107 is stacked is obtained, the amorphous silicon film 105 is irradiated with KrF excimer laser light and crystallized to form the polycrystalline silicon film 107. Irradiation conditions include a pulse frequency of 30 Hz and a laser energy density of 100 to 500 mJ / cm.²In this example, 350 mJ / cm²And Further, here, laser light is linearly shaped to 5 mm × 12 cm by an optical system and irradiated while scanning. (Fig. 5 (B))
[0086]
In this embodiment, since the semiconductor film 103 having an amorphous component was an amorphous silicon film at the stage before laser irradiation (film formation stage), the term “crystallization” was used. In the case of a polycrystalline silicon film or a microcrystalline silicon film, it is inappropriate. In that case, it would be more appropriate to improve crystallinity. That is, it is appropriate that the semiconductor film is changed to a semiconductor film having higher crystallinity by performing laser irradiation.
[0087]
Next, using the same photoresist mask,_xN_yThe protective film 106 and the polycrystalline silicon film 107 made of are patterned in an island shape to form protective films 108 and 109 and semiconductor layers 110 and 111. (Fig. 5 (C))
[0088]
After the previous photoresist mask is peeled off, a photoresist is applied and exposed from the back surface of the substrate 100, and a photoresist mask 112 is formed in a self-aligning manner using the gate wiring 102 as a mask. The amount of exposure light is adjusted so that the photoresist mask 112 has the same pattern as the gate wiring 102. Then, the protective films 108 and 109 are patterned using the photoresist mask 112 to form the protective films 113 and 114. (Fig. 5 (D))
[0089]
In the state where the photoresist mask 112 is present, phosphorus ions are added to the semiconductor layers 110 and 111 by plasma doping as impurity ions imparting N-type conductivity. N-type impurity regions 115S, 115D, 116S, and 116D are formed in the semiconductor layers 110 and 111, respectively. (Fig. 5 (E))
[0090]
After the photoresist mask 112 is peeled off, a photoresist is applied again and exposed from the back surface, and a photoresist mask 117 is formed using the gate wiring 102 as a mask. In this case, the exposure light amount is made larger than that of the previous backside exposure, that is, overexposure is performed, the mask 112 is made narrower than the width of the gate wiring 102, and the side surface of the mask 117 is more than the side surface of the gate wiring 102. Also be inside. The width of the mask 117 in the channel length direction determines the channel amount of the TFT, and the length of the mask 117 side surface shifted to the inside of the gate wiring 102 determines the length of the low concentration impurity region. Here, the mask 117 is set to be inward by about 1 μm.
[0091]
Using the photoresist mask 117 and the protective films 113 and 114 as masks, phosphorus ions are added again to the semiconductor layers 110 and 111. In this addition step, the accelerating voltage is increased so that it is added at a lower concentration than the previous step and phosphorus ions pass through the protective films 113 and 114. N in the semiconductor layers 110 and 111⁺Mold region 121S, 121D, 123S, 123D, N^-Mold regions 122S, 122D, 124S, 124D are formed. (Fig. 6 (A))
[0092]
In the semiconductor layer 110, N⁺The mold regions 121S and 121D become source / drain regions, and N^-The mold regions 122S and 122D become low concentration impurity regions. Further, in the two phosphorus addition steps, a region where phosphorus is not added, that is, a region 121C covered with the mask 117 becomes a channel formation region.
[0093]
In this embodiment, since the low concentration impurity regions 122S and 122D are formed by adding impurities in the presence of the protective film 113, it is easy to control the phosphorus concentration added to the low concentration impurity regions 122S and 122D. is there. Further, since the impurity is added to the source / drain regions 121S and 121D in the state where the protective film 113 is not present, it is easy to add phosphorus at a high concentration.
[0094]
Next, a photoresist mask 125 covering the N-channel TFT is formed with the photoresist mask 117 remaining. Boron ions are added to the semiconductor layer 111 using the photoresist mask 117 and the protective film 114 as a mask. In this addition step, the conductivity type of the N-type region formed in the semiconductor layer 111 is reversed, and P serving as a source / drain region is obtained.⁺Mold regions 131S and 131D are formed. The region 131C covered with the mask 117 becomes a channel formation region. (Fig. 6 (B))
[0095]
In the boron addition process, the conditions such as the acceleration voltage, the dose, the number of times of doping, etc. are appropriately set, so that P⁺Of the mold regions 131S and 131D, the boron concentration in the region covered with the protective film 114 is reduced, and P^-It can also be a mold area.
[0096]
When the source / drain regions are formed as described above, excimer laser light is irradiated to activate the added phosphorus and boron. Next, an interlayer insulating film 140 that covers the semiconductor layer is formed. Here, 50 nm thick SiN_yFilm and 900 nm thick SiO₂A laminated film made of the film is formed. SiN_yThe film functions as a passivation film for the semiconductor layer. SiO₂The film may be formed using a TEOS gas having a good step coverage as a raw material. In addition, SiO₂Instead of the film, an organic resin film such as BCB, polyimide, or acrylic having excellent flatness, or a silicon oxide-based coating film such as SOG, PSG, or BPSG may be used.
[0097]
Contact holes are formed in the contact portions 145 to 149 (see FIG. 4) in the interlayer insulating film 140, and further, the BCB film 103 and SiO are formed in the gate contact portion 149._xN_yContact holes are formed in the film 104. Next, a laminated film composed of a 150 nm thick Ti film / 300 nm thick Al film / 100 nm thick Ti film is formed and patterned to form wirings 141 to 143 and an extraction electrode 144. (Fig. 6 (C))
[0098]
A cross-sectional view taken along the chain line C-C '(see FIG. 4) of the CMOS circuit is shown in FIG. In this embodiment, the TFTs are divided for each TFT (FIG. 5C) and then patterned in a self-aligning manner using the gate wiring as a mask (FIG. 5D), so that the protective films 113 and 114 are formed. Even in the TFT sharing the gate wiring 102, the protective films 113 and 114 are independent of each other. The lengths of the protective films 113 and 114 in the channel width direction are the same as those of the semiconductor layers 110 and 111, that is, the same as the channel width. On the other hand, the length in the channel length direction is the same as the width of the gate wiring 102.
[0099]
  In this embodiment, since the gate wiring 102 is tapered, the thickness of the BCB film 103 is different between the inclined portion and the planar portion of the gate wiring 102 as described in the second embodiment. The smaller the outside, the smaller. Therefore, in the off state, the voltage applied to the channel formation regions 121C and 131C can be dispersed in a portion where the parasitic capacitance is small. Especially with P-channel TFTIsThe parasitic capacitance of the overlap portion is smaller than that of the channel formation region 131C, so that the voltage concentrated on the junction between the channel formation region 131C and the source / drain regions 131S and 131D is reduced. The off-state current can be reduced.
[0100]
Second Embodiment This embodiment is a modification of the first embodiment. In Example 1, the crystalline semiconductor film is patterned into an island shape, and then the source / drain regions are formed. In the manufacturing process of this example, after the source / drain regions are formed, the crystalline semiconductor film is patterned. .
[0101]
This embodiment will be described with reference to FIGS. 8 and 9, the same reference numerals as those in FIGS. 5 and 6 denote the same components. The top view of the CMOS circuit corresponds to FIG. 4, and the cross-sectional views of FIGS. 8 and 9 are cross-sectional views of the TFT along the channel length direction (chain lines AA ′ and BB ′ in FIG. 4). .
[0102]
First, in accordance with the steps shown in Example 1, the steps up to FIG. Then, a photoresist is applied, exposed from the back surface of the substrate 100, and a photoresist mask 151 is formed in a self-aligning manner using the gate wiring 102 as a mask. The exposure amount is adjusted so that the photoresist mask 151 has the same pattern as the gate wiring 102. Then, using the photoresist mask 151, SiO_xN_yThe protective film 106 is patterned to form a protective film 152. (Fig. 8 (A))
[0103]
In FIG. 8, the protective film 152 is divided, but the protective film 152 has the same pattern as the gate wiring 102 and is common to the two TFTs.
[0104]
  Using the photoresist mask 151 and the protective film 152 as a mask, phosphorus ions are added by a plasma doping method so that an N-type impurity region 153 is selectively formed in the polycrystalline silicon film.ShapeTo do. (Fig. 8 (B))
[0105]
After the photoresist mask 151 is peeled off, a photoresist is applied again and exposed from the back surface, and a photoresist mask 155 is formed in a self-aligning manner using the gate wiring 102 as a mask. In this case, the amount of exposure light is made larger than the previous back exposure, that is, overexposure is performed. That is, the photoresist mask 155 is made thinner than the width of the gate wiring 102 so that the side surface of the mask 155 is inside the side surface of the gate wiring 102. The width of the mask 155 in the channel length direction determines the channel length of the TFT, and the length of the side surface of the mask 155 shifted to the inside of the gate wiring 102 is the length of the low concentration impurity region. Here, the side of the mask 155 is shifted inward by about 1 μm.
[0106]
Using the photoresist mask 155 and the protective film 152 as a mask, phosphorus ions are added again. In this addition step, N is added at a lower concentration than the previous step, and the acceleration voltage is increased so that phosphorus ions pass through the protective film 152, and N⁺Mold region 156, N^-A mold region 157 is formed in the polycrystalline silicon film 107. (Fig. 8 (C))
[0107]
A photoresist mask 160 covering the N-channel TFT is formed with the photoresist mask 155 remaining. Boron ions are added to the polycrystalline silicon film 107 using the photoresist mask 155 and the protective film 152. In this addition step, the conductivity types of the N-type regions 156 and 157 of the P-channel TFT portion are inverted, and P which becomes source / drain regions⁺A mold region 161 is formed. (Fig. 8 (D))
[0108]
  In the boron addition process,By appropriately setting conditions such as fast voltage, dose, and number of dopings, P⁺In the mold region 161, the boron concentration in the region covered with the protective film 152 is reduced, and P⁻It can also be a mold area.
[0109]
After the photoresist masks 155 and 160 are peeled off, excimer laser light is irradiated to activate the added phosphorus and boron.
[0110]
Next, the polycrystalline silicon film 107 is patterned in an island shape for each TFT to divide the N-type region and the P-type region. Further, by this patterning, the protective film 152 is also divided for each TFT, and protective films 165 and 166 are formed.
[0111]
The N-channel TFT semiconductor layer has N⁺Source / drain regions 171S and 171D formed of a mold region 156, N^-Low-concentration impurity regions 172S and 172D formed of the mold region 157 and a channel formation region 171C formed of a region covered with the mask 155 are formed. On the other hand, the semiconductor layer of the P-channel TFT has P⁺Source / drain regions 181S and 181D made of the mold 161 and a channel forming region 181C made of the region covered with the mask 155 are formed. (Fig. 9 (A))
[0112]
  Next, an interlayer insulating film 190 that covers the semiconductor layer is formed. Here, 50 nm thick SiN_yFilm and 900 nm thick SiO₂A laminated film made of the film is formed. Source / drain regions in interlayer insulating film 190InA contact hole is formed for the contact hole and the gate contact portion. Furthermore, in the gate contact portion, SiO_xN_yThe insulating inorganic film 104 made of and the planarizing film 103 made of BCB are etched to form a contact hole reaching the gate wiring 102. Next, a laminated film composed of a 150 nm thick Ti film / 300 nm thick Al film / 100 nm thick Ti film is formed and patterned to form wirings 191 to 193 and an extraction electrode 194 to complete a CMOS circuit. . (Fig. 9 (B))
[0113]
A cross-sectional view of the N-channel TFT cut in the channel width direction of FIG. 9B is shown in FIG. Similarly to the protective films 113 and 114 of the first embodiment, the protective films 165 and 166 of this embodiment have the same length in the channel width direction as the channel width, and the length in the channel length direction is the width of the gate wiring 102. Is the same.
[0114]
Example 3 This example is a modification of Example 2. In Example 2, the protective film 152 does not exist on the source / drain regions, and the upper surface thereof is exposed. In this embodiment, the upper surface of the semiconductor layer is not exposed. Further, in this embodiment, a process for manufacturing the source / drain region of the N-channel TFT so as not to overlap with the gate wiring is shown. By eliminating this overlap, the deterioration of the TFT can be suppressed.
[0115]
This embodiment will be described with reference to FIGS. First, according to the process shown in Example 1, a SiO2 film having a thickness of 200 nm is formed on a glass substrate 200.₂A base film 201 is formed. A 500 nm thick Cr film is formed on the surface of the base film 201 and etched into a tapered shape to form a gate wiring 202. The CMOS circuit of this embodiment also corresponds to the top view of FIG. 4, and the gate wiring 202 is common to the two TFTs.
[0116]
Next, the BCB solution is applied with a spin coater, and the solvent is dried. Then, the BCB film 203 is baked at 250 ° C. in a nitrogen atmosphere. The film thickness of BCB on the gate wiring 202 is 50 to 200 nm. On the surface, SiN with a thickness of 50 nm_yA film 204, an amorphous silicon film 205 with a thickness of 50 nm, and a SiN film with a thickness of 50 nm as a protective film 206_yA laminated film of films is formed.
[0117]
Similarly to Example 1, in this example, the apparatus shown in FIG. 7 was used to perform the steps from the baking step of the BCB film 203 to the formation of the protective film 206 without opening to the atmosphere, and the substrate surface was not exposed to the atmosphere. Like that. In this embodiment, since impurities are added to the source / drain regions through the protective film 206, the film thickness is thinner than those in Embodiments 1 and 2, and preferably 10 to 60 nm. (Fig. 10 (A))
[0118]
The amorphous silicon film 205 is crystallized by irradiation with KrF excimer laser light to form a polycrystalline silicon film 207. Irradiation conditions are pulse frequency 30Hz and laser energy density 300mJ / cm.²Then, the light is shaped into a 5 mm × 12 cm line by the optical system and irradiated. (Fig. 10 (B))
[0119]
Next, a photoresist is applied, and a photoresist mask 208 is formed in a self-aligning manner by exposure from the back surface using the gate wiring 202 as a mask. In this case, overexposure is performed so that the mask 208 is thinner than the width of the gate wiring 202 so that the side surface of the mask 208 is inside the side surface of the gate wiring 202. The width of the mask 208 in the channel length direction determines the channel length of the TFT, and the length of the side surface of the mask 208 shifted to the inside of the gate wiring 202 determines the length of the low concentration impurity region. Here, the side surface of the mask 208 is shifted inward by about 1 μm.
[0120]
Subsequently, a photoresist mask 209 that covers the P-channel TFT is formed. Then, phosphorus is added to the polycrystalline silicon film 207, and N^-A mold region 210 is formed. (Fig. 10 (C))
[0121]
After removing the photoresist masks 208 and 209, a photoresist is applied and exposed again from the back surface of the substrate 200, and a photoresist mask 212 is formed in a self-aligning manner using the gate wiring 202 as a mask. The exposure amount is adjusted so that the photoresist mask 212 has the same pattern as the gate wiring 202. Using the mask 212, phosphorus ions are added by the plasma doping method, and N is added to the polycrystalline silicon film.⁺A mold region 213 and an N region 215 are selectively formed. (Figure 10 (D))
[0122]
Next, a photoresist mask 216 that covers the N-channel TFT is formed with the photoresist mask 212 remaining. Then, using the photoresist mask 212, boron ions are added to the polycrystalline silicon film 207, and P serving as source / drain regions is formed.⁺A mold region 217 is formed. (Fig. 11 (A))
[0123]
After the photoresist masks 212 and 216 are peeled off, a photoresist mask is formed, and the protective film 206 is patterned into an island shape for each TFT using the photoresist mask to form the protective films 235 and 236. Subsequently, the polycrystalline silicon film 207 is patterned into an island shape using the same photoresist mask to divide the N-type region and the P-type region.
[0124]
The N-channel TFT semiconductor layer has N⁺Source / drain regions 221S and 221D formed of a mold region 213, N^-Low-concentration impurity regions 222S and 222D formed of the mold region 210 and a channel formation region 221C formed of the region covered with the mask 208 are formed. On the other hand, the semiconductor layer of the P-channel TFT has P⁺Source / drain regions 231S and 231D made of the mold 217 and a channel forming region 231C made of the region covered with the mask 208 are formed. (Fig. 11 (B))
[0125]
Next, an interlayer insulating film 240 that covers the semiconductor layer is formed. Here, 50 nm thick SiN_yFilm and 900 nm thick SiO₂A laminated film made of the film is formed. A contact hole for the source / drain region and a contact hole are formed in the interlayer insulating film 240 for the gate contact portion. Furthermore, in the gate contact portion, SiN_yA contact hole reaching the gate wiring 202 is formed by etching the film 204 and the BCB film 203. Next, a laminated film composed of a 150 nm thick Ti film / 300 nm thick Al film / 100 nm thick Ti film is formed, and the conductive film is patterned to form wirings 241 to 243 and a take-out electrode 244 to form a CMOS circuit. Complete. (Fig. 11 (C))
[0126]
A cross-sectional view of the N-channel TFT cut in the channel width direction is shown in FIG. Unlike the first and second embodiments, the protective films 235 and 236 of this embodiment have the same pattern as the island-like semiconductor layer of the TFT.
[0127]
[Embodiment 4] In this embodiment, the TFT described in Embodiment 1 is applied to an active matrix substrate. The active matrix substrate of this embodiment is used for a flat-plate electro-optical device such as a liquid crystal display device or an EL display device.
[0128]
The present embodiment will be described with reference to FIGS. 12 to 14, the same reference numerals denote the same components. FIG. 12 is a schematic perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel matrix circuit 401, a scanning line driving circuit 402, and a signal line driving circuit 403 formed on the glass substrate 400. The scanning line driving circuit 402 and the signal line driving circuit 403 are connected to the pixel matrix circuit 401 by scanning lines 501 and 503, respectively, and these driving circuits 402 and 403 are mainly composed of CMOS circuits.
[0129]
  The scanning line 501 is formed for each row of the pixel matrix circuit 401, and the signal line 503 is formed for each column. There is a wiring near the intersection of the scanning line 501 and the signal line.501, 503 are connected to the pixel TFT 500. A pixel electrode 505 and a storage capacitor 550 that is a capacitor are connected to the pixel TFT 500.
[0130]
  First, in accordance with the TFT manufacturing process of Example 1,Road 4The N-channel TFTs 02 and 403, the P-channel TFTs, and the pixel TFT 500 of the pixel matrix circuit 401 are completed.
[0131]
FIG. 13A is a top view of the pixel matrix circuit 401 and is a top view of almost one pixel. FIG. 13B is a top view of a CMOS circuit included in the driver circuits 402 and 403. FIG. 14 is a cross-sectional view of an active matrix substrate, and is a cross-sectional view of a pixel matrix circuit 401 and a CMOS circuit. A cross-sectional view of the pixel matrix circuit 401 is a cross-sectional view taken along a chain line DD ′ in FIG. 13A, and a cross-sectional view of the CMOS circuit is a cross-sectional view taken along a chain line EE ′ in FIG. is there.
[0132]
The pixel TFT 500 of the pixel matrix circuit 401 is an N-channel TFT. On the base film 410, the scanning line 501 that is the first layer wiring, the planarizing film 420 made of an insulating organic resin film, the insulating inorganic film 430, and a semiconductor bent in a “U” shape (horse-shoe type) Layers 502 are stacked in this order.
[0133]
The semiconductor layer 502 includes N⁺Mold regions 511 to 513, two channel formation regions 514 and 515, low-concentration impurity regions (N^-Mold regions) 516 to 519 are formed. N⁺The mold regions 511 and 512 are source / drain regions. Protection films 509 and 510 are formed over the semiconductor layer 502.
[0134]
In the CMOS circuit, one gate wiring 601 intersects with two semiconductor layers 602 and 603 with the planarization film 420 and the insulating inorganic film 430 interposed therebetween. The semiconductor layer 602 includes source / drain regions (N⁺Mold regions) 611, 612, channel formation region 613, low concentration impurity region (N^-Mold regions) 614 and 615 are formed. The semiconductor layer 603 includes source / drain regions (P⁺Mold regions) 621 and 622 and a channel formation region 623 are formed.
[0135]
After the source / drain regions are formed in the semiconductor layers 502, 602, and 603, an interlayer insulating film 440 is formed over the entire surface of the substrate. On the interlayer insulating film 440, a signal line 503, a drain electrode 504, source electrodes 631 and 632, and a drain electrode 633 are formed as a second layer wiring / electrode. Protective films 609 and 610 are formed on the semiconductor layers 602 and 603.
[0136]
The scan line 501 and the signal line 503 are orthogonal to each other with the interlayer insulating film 440 interposed therebetween as shown in FIG. The drain electrode 504 is an extraction electrode for connecting the drain region 512 to the pixel electrode 505 and is a lower electrode of the storage capacitor 550. In order to increase the capacity of the storage capacitor 550, the drain electrode 504 is made as wide as possible as long as the aperture ratio is not lowered.
[0137]
As shown in FIG. 13B, the drain electrode 633 of the CMOS circuit is connected to the gate wiring 604 (first layer wiring) of another TFT.
[0138]
An interlayer insulating film 450 having a planarizing film is formed on the second layer wiring / electrode. In this embodiment, a laminated film of silicon nitride (50 nm) / silicon oxide (25 nm) / acryl (1 μm) is used as the interlayer insulating film 450. As the planarizing film, polyimide and benzocyclobutene (BCB) can be used in addition to acrylic.
[0139]
Next, a source wiring 641, a drain electrode 642, a drain wiring 643, and a black mask 520 made of a light-shielding conductive film such as titanium or chromium are formed on the interlayer insulating film 450 as a third-layer wiring. As shown in FIG. 13A, the black mask 520 is integrated with the pixel matrix circuit 401 and overlaps with the periphery of the pixel electrode 505 so as to cover all portions that do not contribute to display. Note that this is indicated by a dotted line in FIG. Further, the potential of the black mask 520 is fixed to a predetermined value.
[0140]
Prior to the formation of the third-layer wirings 641, 642, and 520, the interlayer insulating film 450 is etched to form a recess 530 on the drain electrode 504 leaving only the lowermost silicon nitride film.
[0141]
In the recess 530, the drain electrode 504 and the black mask 520 are opposed to each other with only the silicon nitride film interposed therebetween. A capacitor 550 is formed. Silicon nitride has a high relative dielectric constant, and a larger capacity can be secured by reducing the film thickness.
[0142]
An interlayer insulating film 460 is formed on the third-layer wirings 641, 642, and 530. The interlayer insulating film 460 is formed of acrylic having a thickness of 1.5 μm. In addition to acrylic, other planarizing films such as polyimide and BCB may be used. By forming the interlayer insulating film 460 with a planarizing film, the step formed for the storage capacitor 550 can be planarized.
[0143]
Contact holes are formed in the interlayer insulating films 450 and 460, and pixel electrodes 505 made of a transparent conductive film such as ITO or tin oxide are formed. Thus, the active matrix substrate is completed.
[0144]
When the active matrix substrate of this embodiment is used for a liquid crystal display device, an alignment film (not shown) is formed so as to cover the entire surface of the substrate. If necessary, the alignment film is rubbed
[0145]
Note that an active matrix substrate for a reflective AMLCD can be manufactured by using a conductive film having a high reflectance, typically aluminum or a material containing aluminum as a main component, as the pixel electrode 505.
[0146]
In this embodiment, the pixel TFT 500 has a double gate structure, but may have a single gate structure or a multi-gate structure such as a triple gate structure. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment.
[0147]
[Embodiment 5] In this embodiment, as an example of an electro-optical device using the active substrate shown in Embodiment 4, an example in which an active matrix liquid crystal display device (referred to as AMLCD) is configured will be described.
[0148]
The appearance of the AMLCD of this example is shown in FIG. 15A, the same reference numerals as those in FIG. 12 denote the same components. The active matrix substrate includes a pixel matrix circuit 401, a scanning line driving circuit 402, and a signal line driving circuit 403 formed on the glass substrate 400.
[0149]
The active matrix substrate and the counter substrate 700 are bonded together. Liquid crystal is sealed in the gap between these substrates. However, an external terminal is formed on the active matrix substrate in the TFT manufacturing process, and the portion where the external terminal is formed does not face the counter substrate 700. An FPC (flexible printed circuit) 710 is connected to the external terminal, and external signals and power are transmitted to the circuits 401 to 403 via the FPC 710.
[0150]
In the counter substrate 700, a transparent conductive film such as an ITO film is formed on the entire surface of a glass substrate. The transparent conductive film is a counter electrode with respect to the pixel electrode of the pixel matrix circuit 401, and the liquid crystal material is driven by an electric field formed between the pixel electrode and the counter electrode. Further, an alignment film and a color filter are formed on the counter substrate 700 if necessary.
[0151]
IC chips 711 and 712 are attached to the active matrix substrate of this embodiment using the surface to which the FPC 710 is attached. These IC chips are configured by forming circuits such as a video signal processing circuit, a timing pulse generation circuit, a γ correction circuit, a memory circuit, and an arithmetic circuit on a silicon substrate. In FIG. 15A, two IC chips are attached, but one IC chip or three or more IC chips may be used.
[0152]
Or the structure of FIG. 15 (B) is also possible. In FIG. 15B, the same components as those in FIG. Here, an example is shown in which the signal processing performed by the IC chip in FIG. 15A is performed by a logic circuit 720 formed of TFTs on the same substrate. In this case, similarly to the drive circuits 402 and 403, the logic circuit 720 is also configured based on a CMOS circuit.
[0153]
In this embodiment, a configuration in which a black mask is provided on an active matrix substrate (BM on TFT) is adopted, but in addition to this, a configuration in which a black mask is provided on the opposite side may be employed.
[0154]
Further, color display may be performed using a color filter, or the liquid crystal may be driven in an ECB (electric field control birefringence) mode, a GH (guest host) mode, or the like, and the color filter may not be used. Further, as described in JP-A-8-15686, a configuration using a microlens array may be used.
[0155]
[Example 6] The TFTs shown in Examples 1 to 3 can be applied to various other electro-optical devices and semiconductor circuits besides AMLCD.
[0156]
Examples of electro-optical devices other than AMLCDs include EL (electroluminescence) display devices and image sensors.
[0157]
Further, examples of the semiconductor circuit include an arithmetic processing circuit such as a microprocessor constituted by an IC chip, and a high-frequency module (such as MMIC) that handles input / output signals of portable devices.
[0158]
As described above, the present invention can be applied to all semiconductor devices that function by a circuit formed of an insulated gate TFT.
[0159]
[Example 7] The AMLCD shown in Example 5 can be used as a display device of various electronic devices. The electronic device described in this embodiment is defined as a product on which an active matrix display device is mounted.
[0160]
Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones or electronic books). Etc.). Examples of these are shown in FIGS.
[0161]
FIG. 16A illustrates a personal computer, which includes a main body 2001, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.
[0162]
FIG. 16B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0163]
FIG. 16C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0164]
FIG. 16D illustrates a goggle type display which includes a main body 2301, a display device 2302, and an arm portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0165]
FIG. 16E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display device 2402, a speaker portion 2403, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.
[0166]
FIG. 16F illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.
[0167]
FIG. 17A illustrates a front type projector, which includes a display device 2601 and a screen 2602. The present invention can be applied to display devices and other signal control circuits.
[0168]
FIG. 17B illustrates a rear projector, which includes a main body 2701, a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0169]
Note that FIG. 17C illustrates an example of the structure of the display devices 2601 and 2702 in FIGS. 17A and 17B. The display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2805 to 2807, dichroic mirrors 2803 and 2804, optical lenses 2808, 2809, and 2811, a liquid crystal display device 2810, and a projection optical system 2812. The projection optical system 2812 is configured by an optical system including a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 2810 is shown. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0170]
FIG. 17D illustrates an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes light sources 2813 and 2814, a combining prism 2815, collimator lenses 2816 and 2820, lens arrays 2817 and 2818, and a polarization conversion element 2819. Note that although the light source optical system shown in FIG. 17D uses two light sources, three or four or more light sources may be used. Of course, one light source may be used. In addition, the practitioner may appropriately provide an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, and the like in the light source optical system.
[0171]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-6.
[0172]
【The invention's effect】
In the present invention, the gate insulating film includes a planarized film made of an insulating organic resin and an insulating inorganic film, and the level difference caused by the gate wiring 12 is filled with the planarized film. A gate insulating film can be obtained.
[0173]
For this reason, since the semiconductor film formed on the surface of the gate insulating film can also be flattened, the shift of the focal point of the laser light does not vary from place to place, and the semiconductor film can be crystallized uniformly.
[0174]
Further, since the thickness of the planarization film does not become thin at the edge of the gate wiring, the threshold voltage is increased by short-circuiting the gate wiring and the semiconductor layer or injecting electrons or holes into the gate insulating film. It is possible to prevent shift and further electrostatic breakdown of the gate insulating film.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a pixel TFT according to a first embodiment.
FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT according to a second embodiment.
3 is a cross-sectional view showing a manufacturing process that follows the manufacturing process of FIG. 2;
4 is a top view of the CMOS circuit of Embodiment 1. FIG.
5 is a cross-sectional view showing a manufacturing step of the CMOS circuit of Embodiment 1. FIG.
6 is a cross-sectional view showing a manufacturing process that follows the manufacturing process of FIG. 5;
7 is a schematic view of a CVD apparatus used in Example 1. FIG.
8 is a cross-sectional view showing a manufacturing step of the CMOS circuit of Example 2. FIG.
FIG. 9 is a cross-sectional view showing a manufacturing process.
10 is a cross-sectional view showing a manufacturing step of the CMOS circuit of Embodiment 3. FIG.
11 is a cross-sectional view showing a manufacturing step that follows the manufacturing step of FIG. 10. FIG.
12 is a perspective view of an active matrix substrate of Example 4. FIG.
FIG. 13 is a top view of a pixel matrix circuit and a CMOS circuit.
FIG. 14 is a cross-sectional view of an active matrix substrate.
15 is a cross-sectional view of an active matrix liquid crystal panel of Example 5. FIG.
FIG. 16 is a configuration diagram of an electronic apparatus according to a seventh embodiment.
FIG. 17 is a configuration diagram of an electronic apparatus according to a seventh embodiment.
FIG. 18 is a cross-sectional view showing a manufacturing process of a conventional inverted stagger type TFT.
[Explanation of symbols]
200 substrates
201 Underlayer
202 Gate wiring
203 BCB film
204 SiO_xN_yfilm
205 Amorphous silicon film
206 SiO_xN_yfilm
207 Polycrystalline silicon film

Claims (6)

In a method for manufacturing a semiconductor device having a circuit using a thin film transistor formed on an insulating surface,
Forming a gate wiring on the insulating surface;
Forming a planarizing film made of an insulating organic resin by covering the gate wiring by a coating method;
Forming an insulating inorganic film in contact with the planarization film;
Forming a semiconductor film having an amorphous component on the insulating inorganic film;
Forming a protective film in contact with the semiconductor film having an amorphous component;
Crystallizing the semiconductor film having the amorphous component with laser light to form a crystalline semiconductor film;
Adding a impurity to the crystalline semiconductor film through at least a part of the protective film to form a source region and a drain region;
Have
A method of manufacturing a semiconductor device, wherein the insulating inorganic film, the semiconductor film having an amorphous component, and the protective film are sequentially stacked without being exposed to the atmosphere. In a method for manufacturing a semiconductor device having a circuit using a thin film transistor formed on an insulating surface,
Forming a gate wiring having a taper on an insulating surface;
Forming a planarizing film made of an insulating organic resin by covering the gate wiring by a coating method;
Forming an insulating inorganic film in contact with the planarization film;
Forming a semiconductor film having an amorphous component on the insulating inorganic film;
Forming a protective film in contact with the semiconductor film having an amorphous component;
Crystallizing the semiconductor film having an amorphous component with laser light to form a crystalline semiconductor film;
Adding a impurity to the crystalline semiconductor film through at least a part of the protective film to form a source region and a drain region;
Have
A method for manufacturing a semiconductor device, wherein the insulating inorganic film, the semiconductor film having an amorphous component, and the protective film are sequentially stacked without being exposed to the atmosphere. 3. The method for manufacturing a semiconductor device according to claim 1 , wherein the planarizing film is formed of benzocyclobutene, polyimide, or acrylic in the step of forming the planarizing film according to claim 1 . 4. The method for manufacturing a semiconductor device according to claim 1, wherein the planarizing film is formed using a spin coater. In the step of forming the protective film according to any one of claims 1 to 4, the protective film is made of SiO. _x N _y A method for manufacturing a semiconductor device, comprising: 6. The method for manufacturing a semiconductor device according to claim 1 , wherein the laser light is laser light having a wavelength of 400 nm or less or intense light .

Images