JP4468279B2 - Variable delay circuit and semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a variable delay circuit, a DLL circuit (Delayed Locked Loop Circuit) using the variable delay circuit, and a semiconductor integrated circuit device having the DLL circuit.

  2. Description of the Related Art In recent years, semiconductor integrated circuit devices have been increased in speed and integration, and it has become necessary to supply a clock signal whose phase is synchronized to a predetermined circuit with respect to the clock signal. Specifically, for example, in a synchronous DRAM (SDRAM), a signal synchronized in phase with an external clock signal is supplied to a plurality of output buffer circuits using a DLL (Delay Locked Loop) circuit. Yes. In order for the DLL circuit to cope with a high frequency, a highly accurate digital DLL circuit is required. In order to satisfy this requirement, the variable delay circuit constituting the DLL circuit needs to have high accuracy.

  FIG. 45 shows a conventional variable delay circuit. This circuit has, for example, 10 delay elements (hereinafter referred to as gates) G1 to G10 connected in series. The delay time of each gate is td. The input of each gate is operatively connected to the input node IN via the switches SW1 to SW10, respectively, and the output of the gate G10 is connected to the output node OUT.

  Opening and closing of these switches SW1 to SW10 is controlled by a control circuit (not shown). The control circuit closes one of the switches SW1 to SW10 according to the required delay time. In the illustrated example, only the switch SW7 is closed. Therefore, the signal at the input node IN is delayed by 4 gates, that is, 4td, and output from the output node OUT. Then, by appropriately selecting the switches SW1 to SW10, this variable delay circuit can obtain a delay time from td to 10td.

  The conventional variable delay circuit as shown in FIG. 45 can obtain a delay time that is a multiple of the unit delay time td. However, with such a circuit configuration, a delay time in steps (steps) smaller than the unit delay time, such as 2.5 td, cannot be obtained. In other words, the conventional variable delay circuit has low accuracy.

  Further, when the operating frequency of a semiconductor device such as SDRAM is slow, it can be dealt with by a normal digital DLL circuit. The digital DLL circuit generates an internal output clock signal that is phase-synchronized with the external input clock signal, eliminates the influence of delay caused by the clock wiring in the SDRAM, and outputs the data in synchronization with the external input clock signal. it can. However, a digital DLL circuit mounted on an SDRAM having an operation speed exceeding 100 MHz needs to be able to perform delay control with extremely high accuracy.

  As described above, the digital DLL circuit has a delay circuit in which a plurality of unit delay circuits composed of combinations of logic gates are connected in series. Usually, the unit delay circuit has a minimum delay amount of about 200 ps. In order to cope with an operation speed exceeding 100 MHz, a highly accurate digital DLL capable of controlling a delay amount of 200 ps or less is required. In principle, the accuracy of delay control can be improved by using a unit delay circuit having a delay amount of 200 ps or less.

  However, in a configuration using a unit delay circuit with a delay amount of 200 ps or less, a large number of unit delay circuits are required to secure a certain amount of delay, and the circuit scale increases. Accordingly, an object of the present invention is to provide a variable delay circuit capable of controlling the delay time with high accuracy.

  Another object of the present invention is to provide a configuration capable of performing highly accurate and smooth delay control without greatly increasing the circuit scale. Furthermore, an object of the present invention is to provide a circuit and a semiconductor integrated circuit device using the above delay control.

In order to solve the above-described problem, the first invention is a first DLL circuit (corresponding to the first DLL circuit 3 of the embodiment) for delaying an input clock signal, and a delay with higher accuracy than the first DLL circuit. A second DLL circuit (corresponding to the second DLL circuit 10 of the embodiment) that can control the phase of the first and second DLL circuits independently, and the second DLL circuit By making the delay amount control dependent on the operation of the first DLL circuit, the first and second DLL circuits are delayed so as to output an output clock signal having a predetermined phase relationship with respect to the input clock signal. A semiconductor integrated circuit device is characterized. In order to obtain a predetermined phase relationship by using two DLL circuits that can control different delay amounts, relatively rough phase control is performed in the first DLL circuit, and more accurate phase is controlled in the second DLL circuit. Control can be performed, and highly accurate delay control can be performed without significantly increasing the circuit scale. In particular, since the operation of the second DLL circuit is subordinate to the operation of the first DLL circuit, the carry-over operation between the first DLL circuit and the second DLL circuit can be performed smoothly.

In a second aspect based on the first aspect , the second DLL circuit is reset by receiving a reset signal from the first DLL circuit when the first DLL circuit controls the delay amount. A semiconductor integrated circuit device wherein the second DLL circuit is in a state in which a delay amount can be controlled when the phase of the input clock signal and phase of the output clock signal to be phase-compared by the first DLL circuit are matched. It is. The above dependency is specifically defined.

According to a third invention, in the first invention, the second DLL circuit has a delay circuit (corresponding to the high-precision delay circuit 12), and the predetermined value of the delay amount of the second DLL circuit is a delay circuit Is a center of the range of delay amount that can be controlled. An example of setting the delay amount of the second DLL circuit is defined, and smooth delay control between the layers of the first and second DLL circuits is performed by controlling the delay amount to increase and decrease from the center. Can be done.

In a fourth aspect based on the second aspect , each of the first and second DLL circuits includes a first path (a path including the delay circuit 33 and the high-accuracy delay circuit 12) and a first path through which the input clock signal passes. There is a second path (path including the dummy delay circuit 34 and the high-precision dummy delay circuit 14) for phase comparison with the path, and the second path is a delay amount when the second DLL circuit is reset And a dummy circuit (dummy circuit 43 in the embodiment) having the same delay amount. By providing a dummy circuit, the delay amount is the same as that in the first path.

In a fifth aspect based on the first aspect , the second DLL circuit includes first and second delay elements having different delay amounts, and the second delay element has a delay amount that is greater than that of the first delay element. In many cases, the semiconductor integrated circuit device is characterized in that the difference between the first and second delay amounts is made the accuracy of the second DLL circuit. An embodiment for providing a delay amount is defined.

According to a sixth invention, in any one of the first inventions, the first DLL circuit converts the first clock signal (S3) obtained from the input clock signal into a third delay element (delay circuit 423). And the phase of the second clock signal (S3) obtained from the output clock signal is compared, and the first clock signal and the second clock signal are compared with the fourth delay element (delay circuit 430). The semiconductor integrated circuit device is characterized in that the phase comparison with the signal delayed in step (1) is performed and the phase comparison result between the input clock signal and the output clock signal is output. Thereby, it can be determined whether the phase comparison result in the first DLL circuit is within the range of ± td.

In a seventh aspect based on the sixth aspect , the first DLL circuit has first and second flip-flops (421, 422), and the first flip-flop is delayed by a third delay element. The signal and the second clock signal are input to the set and reset terminals, respectively, and the second flip-flop inputs the signal delayed by the fourth delay element and the first clock signal to the set and reset terminals, respectively. The semiconductor integrated circuit device is characterized in that a phase comparison result is output by a combination of the first and second flip-flops. One embodiment of phase comparison is defined.

In an eighth aspect based on the sixth aspect , the first and second flip-flops have first and second NAND gates, respectively, and a first input of the first NAND gate is a set terminal and a second one. Is connected to the output of the second NAND gate to become an output Q, the first input of the second NAND gate is connected to the reset terminal, and the second input is connected to the output of the first NAND gate. The semiconductor integrated circuit device is characterized in that Q. By making the circuit conditions for the two input signals of each flip-flop the same, phase comparison with higher accuracy can be performed.

In a ninth aspect based on the sixth aspect , the first and second flip-flops have first and second NAND gates, respectively, and the second input of the first NAND gate is the set terminal and is the first. Is connected to the output of the second NAND gate to become an output Q, the second input of the second NAND gate is connected to the reset terminal, and the first input is connected to the output of the first NAND gate. The semiconductor integrated circuit device is characterized in that Q. By making the circuit conditions for the two input signals of each flip-flop the same, phase comparison with higher accuracy can be performed.

In a tenth aspect based on the eighth or ninth aspect , each of the first and second NAND gates includes a first and second P-channel transistor (Q10, Q11) and a first and second N-channel transistor ( Q12, Q13), the source of the first P-channel transistor is connected to the first power supply, the gate is connected to the first input, the drain is connected to the output, and the source of the second P-channel transistor is the first power supply, The gate is connected to the second input, the drain is connected to the output, the source of the first N-channel transistor is connected to the drain of the second N-channel transistor, the gate is connected to the first input, the drain is connected to the output, and the second N-channel transistor is connected to the output. The semiconductor is characterized in that the source of the channel transistor is connected to the second power source, the gate is connected to the second input, and the drain is connected to the source of the first N-channel transistor. An integrated circuit device. One embodiment in the case where the flip-flop is composed of a field effect transistor is defined.

An eleventh invention is the semiconductor integrated circuit according to the sixth invention, wherein the third and fourth delay elements have the same circuit as a circuit constituting one stage of the delay elements of the first DLL circuit. Circuit device. This defines one configuration example of the third and fourth delay elements provided for determining whether or not the phase comparison result in the first DLL circuit is within the range of ± td.

A twelfth invention is a semiconductor integrated circuit device according to the first invention, wherein each of the first and second DLL circuits has a delay circuit, and the delay circuit is composed of a combination of logic elements. is there. An embodiment of a delay circuit is defined.

In a thirteenth aspect based on the fifth aspect, the first and second delay elements are formed of logic elements, and the fanouts of the logic elements of the first delay circuit and the logic elements of the second delay circuit are made different. The semiconductor integrated circuit device is characterized in that a difference in delay amount between the first and second delay elements is formed. An embodiment of a delay element constituting the delay circuit of the second DLL circuit is defined.

In a fourteenth aspect based on the fifth aspect, the first and second delay elements are formed of logic elements, and power supply voltages applied to the logic elements of the first delay circuit and the logic elements of the second delay circuit, respectively. The semiconductor integrated circuit device is characterized in that the difference between the delay amounts of the first and second delay elements is formed by differentiating. An embodiment of a delay element constituting the delay circuit of the second DLL circuit is defined.

A fifteenth invention is a semiconductor integrated circuit device characterized in that the second DLL circuit of the first invention has a delay circuit, and this delay circuit has at least one of a capacitor and a resistor. One embodiment of the delay circuit of the second DLL circuit is defined.

In a sixteenth aspect of the invention, the second DLL circuit of the first aspect of the invention has a delay circuit having at least a capacitor, and the delay amount is controlled by changing the capacitance of the capacitor. It is. One embodiment of the delay circuit of the second DLL circuit is defined.

In a seventeenth aspect of the invention, the second DLL circuit of the first aspect of the invention has a delay circuit having at least a resistor, and the delay amount is controlled by changing the resistance value of the resistor. Device. One embodiment of the delay circuit of the second DLL circuit is defined.

In an eighteenth invention, the second DLL circuit of the first invention has a delay circuit having a capacitor and a resistor, and the delay amount is controlled by changing the capacitance of the capacitor and the resistance value of the resistor. The semiconductor integrated circuit device. One embodiment of the delay circuit of the second DLL circuit is defined.

In a nineteenth aspect of the invention, the second DLL circuit of the first aspect of the invention has a delay circuit having a shift register, and the predetermined value of the delay amount of the second DLL circuit is a range of the delay amount that can be controlled by the shift register. A semiconductor integrated circuit device characterized by being the center of the semiconductor integrated circuit device. One embodiment of the delay circuit of the second DLL circuit is defined.

In a twentieth invention according to the first invention, each of the first and second DLL circuits has a delay circuit, and the delay circuit of the second DLL circuit has a range larger than the accuracy of the first DLL circuit. It can be adjusted. As a result, a carry and a carry between the delay circuits of the first and second DLL circuits become smooth.

In a twenty- first aspect based on the first aspect, the first DLL circuit determines a delay amount such that the input clock signal and the output clock signal have a predetermined phase difference (in the first embodiment, The second DLL circuit has a predetermined phase difference between the input clock signal and the output clock signal (corresponding to a configuration including a phase comparison circuit 31, a delay control circuit 32, a delay circuit 33, and a dummy delay circuit 34). And a second control unit (corresponding to a configuration including the high-precision phase comparison circuit 14, the high-precision delay circuit 12, and the high-precision dummy delay circuit 13) that determines such a delay amount. Device .

In a twenty- second aspect based on the first aspect, the second DLL circuit compares the phase difference between the input clock signal and the output clock signal corresponding to a preset n number of phase differences. And a delay circuit (corresponding to the high-accuracy delay circuit 12) for setting a delay amount corresponding to the comparison result. . 1 shows an example of the configuration of a second DLL circuit.

A twenty- third invention is the semiconductor integrated circuit device according to the twenty-first invention, wherein n delay stages of the delay circuit can be set. 1 shows an example of the configuration of a delay circuit.

24th aspect, in the twenty-second invention, wherein the comparator (corresponding to the delay circuit 102～104,122～124) delay of the delay circuit having the same configuration and has a plurality, the delay amount of each delay unit In contrast, the semiconductor integrated circuit device is characterized in that the phase of the output clock signal delayed by each delay unit and the input clock signal are compared. An example of the configuration of a comparator is shown.

A twenty-fifth invention is the semiconductor integrated circuit device according to the first invention, wherein the semiconductor integrated circuit device has a memory and outputs data from the memory to the outside in synchronization with an output clock signal. 1 shows a specific configuration example of a semiconductor integrated circuit device.

  According to the present invention, it is possible to provide a variable delay circuit capable of changing the delay time with high accuracy. Further, if the variable delay circuit of the present invention is applied to a phase synchronization circuit for an internal clock signal and an external clock signal, the internal clock signal and the external clock signal can be synchronized with higher accuracy.

  Furthermore, when the variable delay circuit of the present invention is applied to a DLL circuit, the rising timing of the external clock and the output timing of data from the output circuit can be made to coincide with each other with high accuracy. Furthermore, according to the present invention, by using two DLL circuits that can control different delay amounts, in order to obtain a predetermined phase relationship, the first DLL circuit performs relatively rough phase control, and the second More accurate phase control can be performed by the DLL circuit, and highly accurate and smooth delay control can be performed without greatly increasing the circuit scale.

  FIG. 1 shows a variable delay circuit of the present invention. In FIG. 1, ten gates G1-G10 having a delay time td are connected in series. Also, nine gates G11 to G19 having a delay time 1.1td longer than the delay times of these gates G1 to G10 are connected in series.

  The variable delay circuit of FIG. 1 further includes ten switches SW0 to SW9. The switch SW0 is provided between the input node IN and the gate G1. The switches SW1 to SW9 are respectively provided between the intermediate nodes n1 to n9 of the first gate row including the gates G1 to G10 and the intermediate nodes n11 to n19 of the second gate row including the gates G11 to G19. .

  The signal is applied to the input node IN, delayed by a predetermined time, and then output from the output node OUT. The ten switches SW0 to SW9 are opened and closed by a control circuit (not shown). The control circuit closes one of the ten switches SW0 to SW9 according to the required delay time.

  In the example of FIG. 1, only the switch SW6 is closed. In this case, since the signal applied to the input node IN reaches the output node OUT via G11 → G12 → G13 → G14 → G15 → G16 → G7 → G8 → G9 → G10, the delay time is 6 × 1. .1td + 4 × td = 10.6 td. On the other hand, when only the switch SW0 is closed, the delay time is 10 td, and when only the switch SW1 is closed, the delay time is 10.1 td. Thus, in the variable delay circuit of FIG. 1, a delay time of 10 td to 10.9 td can be obtained in units of 0.1 td.

  Therefore, it is possible to obtain a delay time 10 times more accurate than the conventional variable delay circuit of FIG. In FIG. 1, the number of gates in the first gate row is ten, but the number is not limited to this. Various delay times can be obtained by combining a second gate row composed of a plurality of gates having a delay time of (n + 1) / n · td with respect to the n first inverter rows.

  Further, in the example of FIG. 1, the variable delay circuit capable of varying the delay time in units of 0.1 td has been described. For example, instead of the gates G11 to G19 of FIG. If a gate is used and a switch is provided on the output side of each inverter, a delay time of 10 td to 10.8 td can be obtained in units of 0.2 td.

  In the example of FIG. 1, the gate G11 has a delay time 1.1 times that of the gate G1, but various methods for adjusting the delay time of the gate are conceivable. When the gate has a CMOS configuration, various delay times can be obtained by changing the sizes (channel length and channel width) of the P-channel transistor and the N-channel transistor. Alternatively, the delay time can be extended by connecting a capacitor or a resistor to the output of the gate.

  As the switch in FIG. 1, for example, a MOS transistor can be used, and in that case, the on / off state of the transistor can be controlled by controlling the gate potential of the transistor. Next, an embodiment in which the variable delay circuit of FIG. 1 is used for a phase synchronization circuit for an external clock signal and an internal clock signal will be described.

  This phase synchronization circuit includes the variable delay circuit of FIG. 1 and the phase comparison circuit of FIG. The configuration of the variable delay circuit of FIG. 1 is as described above. However, when the variable delay circuit is used for the phase synchronization circuit, the internal clock signal Int. CLK is applied. By using the variable delay circuit of FIG. CLK can be delayed by a predetermined time from 10 td to 10.9 td in increments of 0.1 td. Internal clock signal Int. The amount of time that CLK is delayed is determined by a phase comparison circuit described later.

  FIG. 2 shows an example of a phase comparison circuit that controls the variable delay circuit of FIG. This phase comparison circuit has a first column of gates I1-I10 having a delay time td and a second column of gates I11-I20 having a delay time 1.1td. Further, a plurality of phase comparators 0-10 are provided between the intermediate nodes N0-N10 of the first column of gates and the intermediate nodes N0 ′, N11-N20 of the second column of gates corresponding thereto. It has been.

  The first column of gates has an external clock signal Ext. CLK is applied and the first column of this gate is connected to the external clock signal Ext. A signal obtained by delaying CLK by 10 td is output from the output node OUT. On the other hand, the second column of gates has the same internal clock signal Int. As applied to the input node of the variable delay circuit of FIG. CLK is applied. This internal clock signal is delayed by the gates I11 to I20 constituting the second column. In the example of FIG. 2, the applied internal clock signal appears as it is at the node N0 ', and the applied internal clock signal is applied to the node N11 as 1.. As the signal delayed by td appears, a signal obtained by delaying the applied internal clock signal by i × 1.1 td appears at each intermediate node N1i.

  Each of the phase comparators 1-10 of FIG. 2 has a phase of a signal appearing at one of the intermediate nodes of the first column of gates and one of the intermediate nodes of the second column of gates corresponding to that node. Compare the phase of the signal that appears. For example, the phase comparator 1 compares the phase of the signal at the intermediate node N1 with the phase of the signal at the intermediate node N11. When the phase of the signal at the intermediate node N11 is earlier than the phase of the signal at the intermediate node N1, the phase comparator 1 outputs, for example, a logic 1 signal from the node a. On the other hand, when the phase of the signal at the intermediate node N11 is later than the phase of the signal at the intermediate node N1, a logic 0 signal is output from the node a.

  The phase comparison circuit of FIG. 2 further includes a plurality of exclusive OR circuits EOR1-EOR10. Each of the plurality of exclusive OR circuits EOR1 to EOR10 receives output signals from two adjacent phase comparators, and determines whether the logical levels of the output signals match or do not match. The determination result is sent to the corresponding switches SW1-SW9 of the variable delay circuit of FIG.

For example, the exclusive OR circuit EOR2 receives the output signals from the phase comparison circuits 1 and 2 and compares the logical levels of both. If the two logic levels match, an output signal of one logic level is output to the corresponding switch SW1. If the two logic levels do not match, an output signal of the other logic level is output. Next, the operation of the clock synchronization circuit composed of the variable delay circuit of FIG. 1 and the phase comparison circuit of FIG. 2 will be described.
(1) External clock signal Ext. CLK and internal clock signal Int. In this case, the phase of the internal clock signal at the intermediate node N0 ′ is slightly earlier than the phase of the external clock signal at the intermediate node N0. Output the output signal. On the other hand, the remaining phase comparison circuits 1-9 output an output signal of logic level 0 because the phase of the corresponding intermediate node signal is earlier in phase on the external clock signal side than on the internal clock signal side.

  Of the plurality of exclusive OR circuits EOR1-EOR10, only EOR1 outputs the other logic level because the logic level of the input signal does not match, but the remaining EOR2-EOR10 matches the logic level of the input signal. Therefore, one logic level is output. Therefore, among the plurality of switches SW1 to SW9 in FIG. 1 that respectively receive the output signals of the plurality of exclusive OR circuits EOR1 to EOR10, only the switch SW0 is closed and the other switches remain open.

  As a result, the internal clock signal Int. A signal obtained by delaying CLK by 10 td is output. On the other hand, an external clock signal Ext. A signal obtained by delaying CLK by 10 td is output. Originally, the phases of the internal clock signal and the external clock signal are the same, so the phases of the internal clock signal and the external clock signal output from these two output nodes are the same. (2) When the phase of the internal clock signal is advanced from the phase of the external clock signal, a case where the phase of the internal clock signal is advanced by about 0.1 td from the phase of the external clock signal will be described as an example.

  In this case, only the phase comparators 0 and 1 out of the plurality of phase comparators 0-10 in FIG. 2 output the logic level 1 signal to the exclusive OR circuit, and the remaining phase comparators 2-10 Since a signal of logic level 0 is output, only EOR2 of the plurality of exclusive OR circuits EOR1-EOR10 outputs a signal of the other logic level. Accordingly, only SW1 is closed among the plurality of switches SW0 to SW9 in FIG.

  As a result, the internal clock signal Int. A signal obtained by delaying CLK by 10.1 td is output. On the other hand, an external clock signal Ext. A signal obtained by delaying CLK by 10 td is output. Originally, the phase of the internal clock signal is about 0.1 td ahead of the external clock signal, so the phase of the internal clock signal output from each of these two output nodes and the phase of the external clock signal are the same.

  FIG. 3 shows an example of a specific circuit of the variable delay circuit of FIG. Although FIG. 1 shows a 10-stage gate G1-G10 configuration, FIG. 3 shows an example of a 5-stage gate configuration. Gates G1-G5 in FIG. 3 are composed of NAND gates and inverters, which correspond to the gates G1-G10 in FIG. Similarly, the gates G11-G1T in FIG. 3 are composed of NAND gates and inverters, and these correspond to the gates G11-G19 in FIG.

  Further, in FIG. 3, the switches SW0 to SW4 are composed of NAND gates. When the output signal from the exclusive OR circuit in FIG. 2 is L, the output of the switch SW0-4 in FIG. Fixed. Therefore, in this case, the signal on the second gate row side is not transmitted to the first gate row G1-G5 side. Each gate G1-G5 of the first gate row and each gate G11-G15 of the second gate row functions as a simple two-stage inverter.

  On the other hand, when the output signal from the lower level of the exclusive OR in FIG. 2 is H, the switches SW0 to SW4 in FIG. 3 output a signal obtained by inverting the logic level of the input signal from the second gate row G11 to G15. 1 to the gate row G1-G5. In this case, each gate G1-G5 in the first gate row and each gate G11-G15 in the second gate row also function as a simple two-stage inverter.

  In the example of FIG. 3, only the switch SW <b> 2 is closed and the signal propagates while being delayed from the input node in to the output node out. In FIG. 3, the gates constituting the first gate row G1-G5 and the gates constituting the second gate row G11-G15 have the same circuit configuration and transistor size. That is, the delay time of the first gate and the second gate itself is the same. However, since one input of the NAND gate functioning as the switch SW0-S4 is connected to the intermediate node n11-n14 of the second gate row G11-G15, the second gate row G11-G15 is connected between the second gate rows G11-G15. The wiring load is larger than the wiring load between the first gate rows G1 to G5. Due to the difference in wiring load, the delay time in the second gate row G11-G15 is made longer than the delay time in the first gate row G1-G5.

  FIG. 4 is a diagram illustrating an example of a specific configuration of the second phase comparator of the present invention. This phase comparator has an internal clock signal Int. CLK and the external clock signal Ext. A first flip-flop circuit FF-12 that receives CLK, and a pulse signal generation circuit 91 that detects that both the internal clock signal and the external clock signal have become H level and outputs a pulse signal having a constant width from that point. And a second flip-flop circuit FF-34, and a gate circuit 92 for inverting the output signal of the first flip-flop circuit in response to the pulse signal and transferring it to the second flip-flop. ing.

  Next, the circuit operation of this phase comparator will be described. In the initial state, the internal clock signal Int. CLK and the external clock signal are at L level, and the output nodes a and b of the first flip-flop circuit are at H level. The first flip-flop has an internal clock signal Int. Of the CLK and the external clock signal, the output node with the earlier rise timing is inverted from the H level to the L level. For example, when the rising timing of the internal clock signal is earlier than that of the external clock signal, the output node a is inverted from the H level to the L level, but the output node b remains at the H level.

  Next, the internal clock signal Int. When both CLK and the external clock signal transition to H level and the output state of the first flip-flop is determined, the pulse generation circuit 91 outputs a pulse signal to the gate circuit 92. The gate circuit 92 opens in response to this pulse signal, and the output signals of the output nodes a and b of the first flip-flop circuit are inverted in the gate circuit and sent to the input node of the second flip-flop circuit FF-12. It is done. The second flip-flop circuit latches the transferred signal and outputs a signal obtained by inverting the signal at the node d to the output node OUT.

  As described above, the phase comparator of FIG. When the rising timing of CLK is earlier than the rising timing of the external clock signal, an L level signal is output from the output node OUT, and the internal clock signal Int. When the rising timing of CLK is later than the rising timing of the external clock signal, an H level signal is output from the output node COUT.

  Next, an example in which the variable delay circuit of the present invention is applied to a DLL circuit will be described. As will be apparent from the following description, the DLL circuit of the present invention is not merely characterized by including the variable delay circuit, but includes various improvements. For example, it includes improvements such as the use of two different precision DLL circuits, the use of a frequency divider, the delay amount control of a variable delay circuit, and the configuration of a phase comparison circuit.

  FIG. 5 is a block diagram showing a DLL circuit which is a semiconductor integrated circuit device according to an embodiment of the present invention. The illustrated semiconductor integrated circuit device includes a first DLL circuit 3 and a second DLL circuit 10. The second DLL circuit 10 is provided on the output side of the first DLL circuit 3 and has higher accuracy than the accuracy of the first DLL circuit 3. An input clock signal input from the outside via the clock input pad 1 and the input circuit 21 functioning as a clock buffer is delayed by the first DLL circuit 3, and the output is delayed with higher accuracy by the second DLL circuit 10. As a result, an output (internal) clock signal having a predetermined phase relationship with respect to the input clock signal is generated. The output of the second DLL circuit 10 is given to the output circuit 51 connected to the data bus via the clock wiring. The output circuit 51 buffers the data on the data bus in synchronization with the output clock signal from the second DLL circuit 10 and then outputs the data to the data output pad 6.

  The semiconductor integrated circuit device has a dummy output circuit 41, a dummy input circuit 42, and a dummy circuit 43. The dummy output circuit 41 is a circuit having a delay amount equal to the delay of the clock wiring from the second DLL circuit 3 to the output circuit 51 and the delay in the output circuit 51. The dummy circuit 42 has the same delay amount as the input circuit 21. The dummy circuit 43 has a predetermined delay amount to be described later.

  The first DLL circuit 3 and the second DLL circuit 10 operate independently (phase comparison). That is, the phase of the clock signal obtained from the dummy output circuit 41 via the dummy input circuit 42 is compared independently with the input clock signal from the input circuit 21, and the delay amount is controlled so that the phase difference has a predetermined relationship. To do. Specifically, the phase difference in a predetermined relationship is a state in which the dummy clock signal is delayed by at least k cycles with respect to the input clock signal (k is an integer of 1 or more). In this state, there is no apparent phase difference between the clock signal on the dummy side and the input signal. That is, data output from the output circuit 51 is synchronized with an external input clock signal applied to the clock input pad 1.

  However, the delay amount control of the second DLL circuit 10 is cascaded with the delay amount control of the first DLL circuit 3. Specifically, the second DLL circuit is reset by receiving a reset signal from the first DLL circuit 3 when the first DLL circuit controls the delay amount, and the first DLL circuit 3 is reset. When the signals S0 and S3 are in phase (in the accuracy of the first DLL circuit 3, the external clock signal input to the input pad 1 and the data output from the data output pad 6 are in phase) ) Is in a state in which the second DLL circuit 10 can control the delay amount. As a result, when a large delay amount is required (when the delay amount is greatly varied), the delay amount is controlled only by the first DLL 3 and the phases of the signals S0 and S3 are adjusted to the accuracy of the first DLL circuit 3. In this state, the phase is matched with the accuracy of the second DLL circuit 10 by controlling the delay amount with higher accuracy in the second DLL circuit 10.

  As described above, providing the first DLL circuit 3 and the second DLL circuit 10 having different accuracy results in a hierarchy of delay amount control, that is, phase control (in the case of the configuration shown in FIG. 5, the hierarchy consists of two layers). ) Means that. When the two layers are replaced with two digits, the lower digit (high precision) is controlled by the second DLL circuit 10 and the upper digit is controlled by the first DLL circuit 3. Accordingly, a carry operation and a carry operation are required between the first DLL circuit 3 and the second DLL circuit 10. For example, if the accuracy of the first DLL circuit 3 is td, the second DLL circuit 10 can control the delay amount in a range including ± td, and the phase comparison result of the first DLL circuit 3 is ± td. The first DLL circuit 3 outputs a reset signal to the second DLL circuit 10 when it is out of the range, and sets the delay amount of the second DLL circuit 10 to a predetermined value. The reset signal corresponds to a carry or a carry. The deviation from the range of ± td means that the delay amount control by the second DLL circuit 10 is not in time, and in this case, the delay amount is controlled (variable) by the first DLL circuit 3. . The variable operation of the delay amount by the first DLL circuit 3 means that a carry or a carry has occurred.

  When the phase comparison result of the first DLL circuit 3 is out of the range of ± td, the delay amount of the second DLL circuit 10 is set to a predetermined value. This is ½ of the range of delay amount that can be varied by the DLL circuit 10. In other words, when the second DLL circuit 10 is reset, a delay amount (hereinafter referred to as a reference delay amount) corresponding to ½ of the range of delay amount variable by the second DLL circuit 10 is the second DLL circuit. Given by circuit 10. When the second DLL circuit 10 is in an operable state, the delay amount of the second DLL circuit 10 is varied by increasing or decreasing the reference delay amount. As will be described later, the dummy circuit 43 described above gives the same delay amount as the reference delay amount.

  Hereinafter, the block configuration of the first DLL circuit 3 and the second DLL circuit 10 will be described, and then the details of each block will be described. The first DLL circuit 3 includes a frequency dividing circuit 30, a phase comparison circuit 31 that functions as a digital phase comparator, a delay control circuit 32, a delay circuit 33, and a dummy delay circuit 34. The frequency dividing circuit 30 divides the external clock signal S1 via the input circuit 21, and outputs signals S2 and S3 having the same frequency lower than the external clock signal S1. The signal S2 is output to the dummy delay circuit 34, and the signal S3 is output to the first input of the phase comparison circuit 31. The output signal of the dummy delay circuit 34 is given to the second input of the phase comparison circuit 31 via the dummy output circuit 41, the dummy input circuit 42, and the dummy circuit 43. Here, a signal output from the dummy circuit 43 is S0. The phase comparison circuit 31 compares the phases of the signals S0 and S3 and controls the delay control circuit 32. Specifically, the phase comparison circuit 31 determines whether or not the phase difference between the signals S0 and S3 is within a range of ± td. If it is determined that the delay amount is out of the range, it is determined that the delay amount needs to be largely changed, and the delay amounts of the delay circuit 33 and the dummy delay circuit 34 are set to one step (the minimum delay amount that can be changed, the first DLL). Which means the accuracy of the circuit 3). Note that the same delay amount is set in the delay circuit 33 and the dummy delay circuit 34. Further, in this case, the phase comparison circuit 31 outputs a reset signal to the second DLL circuit 10 to reset a high precision delay circuit 12 and a high precision dummy delay circuit 13 described later. When this reset signal is received, the delay amounts of the high-accuracy delay circuit 12 and the high-accuracy dummy delay circuit 13 are set to variable delay amounts corresponding to ½ of the range delay amount. Note that the output signal of the delay circuit 33 is supplied to the high-accuracy delay circuit 12 of the second DLL circuit 10.

  The second DLL circuit 10 includes a high precision phase comparison circuit 14 and a delay control circuit 15 in addition to the high precision delay circuit 12 and the high precision dummy delay circuit 13. The high-accuracy delay circuit 12 can control the delay amount with higher accuracy than the delay circuit 33. Similarly, the delay amount of the high-precision dummy delay circuit 13 can be controlled with higher accuracy than the dummy delay circuit 34. The high precision phase comparison circuit 14 compares the phase of the signal S3 output from the frequency dividing circuit 30 with the signal output from the high precision dummy delay circuit 13, and is identical to the high precision delay circuit 12 and the high precision dummy delay circuit 13. The delay control circuit 15 is controlled so as to set the delay amount. When the precision of the high precision delay circuit 12 and the high precision dummy delay circuit 13 is td ′, the high precision phase comparison circuit 14 determines whether or not the phase difference is in the range of 0 to td ′. When it is determined that the phase difference is outside this range, the delay amounts of the high precision delay circuit 12 and the high precision dummy delay circuit 13 are increased or decreased by td '. When the delay control circuit 15 receives the reset signal from the phase comparison circuit 31, the delay control circuit 15 resets the high precision delay circuit 12 and the high precision dummy delay circuit 13. By this reset, the high precision delay circuit 12 and the high precision dummy delay circuit 13 are set to the reference delay amount.

  Next, with reference to FIG. 6, the outline of the operation when the phases are matched will be described. The external clock signal φext shown in FIG. 6 is applied to the input terminal 1, delayed by tin, and applied to the frequency dividing circuit 30 as the signal S1. The phase comparison circuit 31 receives the signal S0 from the dummy circuit 43. The signal S0 has a total delay amount obtained by delaying the signal S1 by the delay circuit 33, the high-accuracy delay circuit 12, the output circuit 51, and the input circuit 21 (for convenience, the delay of the frequency dividing circuit 30 is ignored). . Therefore, the signal S0 is considered that the signal S1 is output through the dummy delay circuit 34, the dummy output circuit 41, the dummy input circuit 42, and the dummy circuit 43. Now, assuming that the delay amount of the dummy delay circuit 34 is Rtd and the delay amounts of the dummy output circuit 41, the dummy input circuit 42 and the dummy circuit 43 are tout, tin and th, the signal S0 is as shown in FIG. Here, the delay amount th of the dummy circuit 43 is ½ of the maximum delay amount of the high-accuracy delay circuit 12 (the same applies to the high-accuracy dummy delay circuit 13). That is, th is equal to the center point of the delay adjustable range. For example, if the high-accuracy delay circuit 12 can adjust the delay of 10 td to 10.8 td, th is 10.4 td. The halftone dot region of the signal S0 in FIG. 6 corresponds to the above-described range of ± td.

  The inputs to the high precision phase comparison circuit 14 are the signal S3 from the frequency dividing circuit 30 and the signal S4 output from the high precision dummy delay circuit 13. The signal S4 corresponds to a signal obtained by passing the signal S1 through the dummy output circuit 41, the dummy input circuit 42, and the high-precision dummy delay circuit 13. The delay amount of the high-precision dummy delay circuit 13 is Ptd. If Ptd = th, the signal S4 rises at the same timing as the signal S0. In this state, the output of the delay circuit 33 is delayed by the delay amount Rtd from the signal S1, as shown in FIG. 6, and further delayed by the delay amount Ptd by passing through the high-accuracy delay circuit 12, as shown in FIG. become. Since the output of the high precision delay circuit 12 is delayed by the delay amount tout (including the delay of the clock signal line) of the output circuit 51, the finally obtained internal (output) clock signal is synchronized with the external (input) clock signal φext. To do.

  In the configuration shown in FIG. 5, as described above, when the accuracy of the first DLL circuit 3 is td, the second DLL circuit 10 can control the delay amount in a range including ± td. When the phase comparison result of the DLL circuit 3 is out of the range of ± td, the first DLL circuit 3 outputs a reset signal to the second DLL circuit 10 and sets the delay amount of the second DLL circuit 10 to a predetermined value. Set. Hereinafter, operations of the first DLL circuit 3 and the second DLL circuit 10 including the carry and carry operations will be described with reference to FIGS.

  Now, when the circuit of FIG. 5 is in a steady state and operates stably (a state in which the delay amount set by the first DLL circuit 3 and the second DLL circuit 10 is maintained), some factor ( When the phase synchronization state between the input and output clocks cannot be maintained due to, for example, a change in power supply voltage or a change in temperature, the following delay amount control is performed.

  7 and FIG. 8, the top graph shows the phase difference between the signal S3 and the signal S4 (in other words, the external axis, the voltage on the vertical axis and the phase comparison on the horizontal axis with the high-precision phase comparator l14. The phase difference between the clock signal and the internal clock signal is shown. [0] to [5] indicate the phase comparison timing. Furthermore, the accuracy td (unit delay amount) of the delay circuit 33 is 200 ps, and the accuracy td '(unit delay amount) of the high-accuracy delay circuit 12 is 60 ps. Furthermore, the bar graphs [0] to [5] in FIG. 7 show the movement of the delay circuit 33 and the high-accuracy delay circuit 12 when carrying, especially until the phase difference between the signals S3 and S4 changes from 0 ps to 300 ps. The state of each delay circuit every 60 ps is shown. Further, the delay circuit 33 indicates the state of (N−1), (N), (N + 1) stages, where N is the number of stages (the number of delay elements having a unit delay amount) when the phase difference is 0 ps, The accuracy delay circuit 12 is shown as a whole. Further, FIG. 7 shows a carry operation, and FIG. 8 shows a carry operation.

  First, the operation at the time of carry will be described with reference to FIG. First, when the phase difference is 0 ps, the delay circuit 33 is in the Nth stage and the high-accuracy delay circuit 12 is set to the center (0 ps) (state [0]). When the phase difference reaches 60 ps, the high-accuracy delay circuit 12 is increased by one stage (state [1]). When the phase difference reaches 120 ps, the high-accuracy delay circuit 12 is further increased by one stage (state [2]). When the phase difference reaches 180 ps, the high-accuracy delay circuit 12 is further increased by one stage (state [3]). When the phase difference becomes 240 ps, the delay circuit 33 is increased from the Nth stage to the (N + 1) th stage when the phase difference becomes 200 ps, and the high-accuracy delay circuit 12 is reset to the center (state [ 4]). When the phase difference reaches 300 ps, the high-accuracy delay circuit 12 is increased by one stage (state [5]).

  Next, the operation at the time of carry-down will be described with reference to FIG. First, let state [4] shown in FIG. 7 be state [0] at the time of carry-down. That is, the phase difference is 200 ps, the delay circuit 33 is raised from the Nth stage to the (N + 1) th stage, and the high-accuracy delay circuit 12 is reset to the center. When the phase difference becomes −60 ps, the high-accuracy delay circuit 12 is lowered by one stage (state [1]). When the phase difference becomes −120 ps, the high-accuracy delay circuit 12 is further lowered by one stage (state [2]). When the phase difference becomes −180 ps, the high-accuracy delay circuit 12 is further lowered by one stage (state [2]). When the phase difference becomes −240 ps, when the phase difference becomes −200 ps, the delay circuit 33 goes down from the (N + 1) -th stage to the N-th stage, and the high-accuracy delay circuit 12 is reset to the center ( State [4]). When the phase difference becomes −300 ps, the high-accuracy delay circuit 12 goes down by one stage (state [5]).

  As described above, the delay circuit 33 is operated independently from the high-accuracy delay circuit 12, and when the delay circuit 33 is moved, the high-accuracy delay circuit 12 is automatically reset to the center. Since the high-accuracy delay circuit 12 can measure the delay of the stage, even if the values of the delay circuit 33 and the high-accuracy delay circuit 12 change due to changes in temperature and power supply voltage, the digit of the hierarchical DLL is smoothly changed. Up and down are performed. In particular, by setting the phase adjustable range of the high-accuracy delay circuit 12 to 200 ps or more, which is the accuracy of the delay circuit 33, the delay of the first DLL circuit 3 and the second DLL circuit 10 due to changes in temperature and power supply voltage. Even if the rate of change in the delay time of the line is different, smoother carry and carry can be performed.

  The basic configuration and the operation of the present invention have been described above. Next, details of the first DLL circuit 3 will be described. FIG. 9 is a circuit diagram showing a configuration example of the frequency dividing circuit 30 shown in FIG. 5, and FIG. 10 is a diagram showing signal waveforms at each node of the frequency dividing circuit 30 shown in FIG. As shown in FIG. 9, the frequency dividing circuit 30 includes three-stage counters 301 to 303 each including a plurality of NAND gates and inverters, and divides the signal S1 (external clock signal via the input circuit 21) to generate a signal. S2 and S3 are generated. In FIG. 10, reference numeral A is an output signal of the first counter 301, B is an output signal of the second counter 302, and each signal waveform is as shown in FIG. The frequency dividing circuit 30 is not limited to a three-stage counter composed of a plurality of NAND gates and inverters, and can be configured as a combination of various logic gates.

  As shown in FIG. 10, the frequency dividing circuit 30 divides the input clock signal S1 by 8, and a signal in which the period of one clock cycle of the external clock signal is at the high level H and the clock level of 7 clock cycles is the low level L S2 is generated. Further, the frequency dividing circuit 30 generates a signal S3 that is complementary to the signal S2. FIG. 11 is a diagram illustrating the phase relationship of the signals S0 to S3. As shown in the figure, the phase comparison circuit 31 performs phase comparison once every eight periods. The signal S0 is synchronized with the signal S1 with a delay of one cycle. Thereby, the output clock signal in the output circuit 51 is phase-synchronized with the external clock signal one clock cycle before.

  Note that by changing the period a of the signal S2 of the frequency dividing circuit 30, it is possible to adjust how many clocks before the output clock signal is generated from the external clock signal. For example, by setting the period a of the signal S2 to a length corresponding to 3 clocks, an output clock signal synchronized with the external clock signal 3 clocks before can be generated. In addition, by changing the period a + b of the signal S2, it is possible to adjust how many periods the phase comparison is performed.

  The sum of the minimum delay time of the input circuit 21 and the delay circuit 33, the minimum delay time of the high-precision delay circuit 12, the delay time of the clock wiring, and the delay time of the output circuit 51 is a time corresponding to one clock of the external clock signal (1 If it is shorter than (clock cycle), an internal clock signal that is phase-synchronized with the external clock one clock cycle before can be generated. On the other hand, when the total delay time exceeds one clock cycle of the external clock signal, it is necessary to synchronize the phase with the external clock signal before two or more clock cycles. In this case, the period a is set to 2 or more.

  FIG. 12 is a diagram for explaining a configuration example of the delay circuit 33 and the dummy delay circuit 34 of the first DLL circuit 3 having the same configuration. 1A shows the configuration of a delay circuit (unit delay circuit) for one bit, FIG. 1B is a timing diagram showing the operation of this unit delay circuit, and FIG. 1C shows the unit delay circuit. The configuration and operation when multiple stages are connected are shown.

  As shown in FIG. 12A, the unit delay circuit includes two NAND gates 401 and 402 and an inverter 403. The operation of the unit delay circuit will be described with reference to FIG. 12B. The input φE is an activation signal (enable signal), and the unit delay circuit operates at the high level H. FIG. 12B shows a state in which the enable signal φE is at the high level H and the signal can be accessed. In FIG. 12B, IN represents an input signal to the unit delay circuit, φN represents a signal from the adjacent right unit delay circuit among the delay circuits connected in a plurality of stages, and OUT represents the unit delay. The output signals of the circuit are shown, and 4a-1 and 4a-2 show the waveforms of the corresponding nodes in FIG. Therefore, OUT corresponds to the signal φN of the unit delay circuit adjacent on the left side.

  When the signal φN is at the low level L, the output signal OUT is always at the low level L. When the signal φN is at the high level H and the signal φE is at the low level, the output signal OUT is at the high level. When the signal φN is at a high level and the signal φE is at a high level, the output signal OUT is at a high level H if the input signal IN is at a low level L, and is at a low level L if IN is at a high level.

  According to the circuit of FIG. 12A, when the input signal IN rises while the enable signal φE is at the high level H, the input signal propagates to the path indicated by the arrow. The input signal IN is prevented from propagating to the output OUT along the path indicated by the arrow. FIG. 12C shows an example in which the unit delay circuits shown in FIG. Although only three stages are shown in FIG. 12 (c), in reality, multiple stages are connected so as to obtain a desired delay amount. The enable signal φE has a plurality of signal lines such as φE-1, φE-2, and φE-3 for each circuit element, and these signals are controlled by the delay control circuit 32.

  In FIG. 12C, the central unit delay circuit is activated and the enable signal φE-2 is at the high level H. In this case, when the input signal IN changes from the low level L to the high level H, the enable signals φE-1 and φE-3 of the left unit delay circuit and the right unit delay circuit are at the low level. The input signal IN is stopped by the NAND gates 401-1 and 401-3.

  On the other hand, since the enable signal φE-2 of the activated central unit delay circuit is at the high level H, the input signal IN passes through the NAND gate 401-2. Since the output signal OUT of the right unit delay circuit is at the high level H, the NAND gate 402-2 that is the input signal IN also passes through and the low level L signal is propagated as the output signal OUT. As described above, when the output signal OUT on the right side, that is, the enable signal φN is at the low level L, the output signal OUT is always at the low level L. The signals are sequentially transmitted to the inverter and taken out as a final output signal.

  In this way, the input signal IN is transmitted through the activated unit delay circuit so as to be turned back into a final output signal. That is, the amount of delay can be controlled by which part of the enable signal φE is set to the high level H. The delay amount (unit delay amount) for 1 bit is determined by the total signal propagation time of the NAND gate and the inverter, this time becomes the delay unit time of the DLL circuit, and the entire delay time passes through the unit delay amount. The amount multiplied by the number of steps to be performed.

  FIG. 13 is a circuit diagram showing one configuration of delay control circuit 32 shown in FIG. The delay control circuit 32 has a configuration in which unit delay control circuits 430-2 having the same unit delay circuit as described above are connected by the number of unit delay circuits of the delay circuit 33 and the dummy delay circuit 34, and the output of each stage. Becomes the remarkable enable signal φE of the delay circuit. The unit delay control circuit 430-2 includes transistors 435-2, 437-2, 438-2, 439-2 connected in series to both ends of a flip-flop composed of a NAND gate 432-2 and an inverter 433-2, and It has a NOR gate 431-2. The gate of the transistor 438-2 is connected to the node 5a-2 of the previous unit delay control circuit, and the gate of the transistor 439-2 is connected to the node 5a-5 of the subsequent unit delay control circuit to Have come to receive. On the other hand, set signals φSE and φSO when counting up and reset signals φRE and φRO when counting down are connected to the other transistor connected in series every other bit.

  As shown in FIG. 13, in the central unit delay control circuit 430-2, the set signal φSO is supplied to the gate of the transistor 435-2, the reset signal φRO is supplied to the transistor 437-2, and the transistor 437-2 is supplied. A reset signal φRO is supplied, and a set signal φSE and a reset signal φRE are supplied to the gates of the corresponding transistors in the circuits on both sides of the front stage and the rear stage of the unit delay control circuit 430-2, respectively. The NOR gate 431-2 is configured to receive the signals of the node 5 a-1 of the left (previous stage) circuit and the node 5 a-4 of the circuit 430-2. Note that φR is a signal for resetting the unit delay control circuit, and temporarily becomes a low level L after power-on, and thereafter is fixed at a high level H.

  FIG. 14 is a timing chart for explaining the operation of the delay control circuit 32 shown in FIG. As shown in FIG. 14, first, the reset signal φR temporarily becomes low level L, the nodes 5a-1, 5a-3, 5a-5 are at high level H, and 5a-2, 5a-4, 5a-6. Is set to low level L. When counting up, the count-up signals (set signals) φSE and φSO repeat high level H and low level L alternately.

  When the set signal φSE changes from the low level L to the high level H, the node 5a-1 is grounded to become the low level L, and the node 5a-2 changes to the high level H. In response to the change of the node 5a-2 to the high level H, the output signal (enable signal) φE-1 changes from the high level H to the low level L. Since this state is latched by the flip-flop, the enable signal φE-1 remains at the low level L even if the set signal φSE returns to the low level L. Then, in response to the change of the node 5a-1 to the low level L, the enable signal (output signal) φE-2 changes from the low level L to the high level H. Since the node 5a-2 is changed to the high level H, the transistor 438-2 is turned on, and when the set signal φSO is changed from the low level L to the high level H, the node 5a-3 is installed and becomes the low level L The node 5a-4 changes to the high level H. Furthermore, in response to the change of the node 5a-4 to the high level H, the enable signal φE-2 changes from the high level H to the low level L. Since this state is latched by the flip-flop, the enable signal φE-2 remains at the low level L even when the set signal φSO returns to the low level L.

  Then, in response to the change of the node 5a-3 to the low level L, the enable signal φE-3 changes from the low level L to the high level H. In FIG. 10, the set signals φSE and φSO are only output one pulse at a time, but the unit delay control circuit is connected in multiple stages, and the set signals φSE and φSO are alternately switched between the high level H and the low level L. Is repeated, the position of the stage where the output signal (enable signal) φE becomes the high level H is sequentially shifted to the right. Therefore, when it is necessary to increase the delay amount based on the comparison result of the phase comparison circuit 31, the pulses of the set signals φSE and φSO may be alternately input.

  If the count-up signals (set signals) φSE and φSO and the count-down signals (reset signals) φRE and φRO are not output, that is, a low level L state is maintained, the enable signal φE becomes a high level H level. The position is fixed. Therefore, when the delay amount needs to be maintained based on the comparison result of the phase comparison circuit 31, the pulses of the signals φSE, φSO, φRE, and φRO are not input.

  When counting down, if the pulses of the reset signals φRE and φRO are alternately input, the position of the stage where the output φE becomes the high level H is sequentially shifted to the left as opposed to when counting up. As described above, in the delay control circuit 32 shown in FIG. 13, by inputting a pulse, it is possible to move the position of the stage where the enable signal φE becomes the high level H one by one. If the delay circuit shown in FIG. 12C is controlled by the enable signal φE, the delay amount can be controlled by one unit (each unit delay time).

  Next, the configuration of the phase comparison circuit 31 shown in FIG. 5 will be described. The phase comparison circuit 31 includes a phase comparison unit shown in FIG. 15 and an amplification circuit unit shown in FIG. First, the phase comparison unit shown in FIG. 15 will be described with reference to FIG. In FIG. 16, reference signs φout and φext indicate an output signal (S0) and an external clock signal (S3) to be compared by the phase comparison circuit, and the phase of the signal φout is determined with reference to the signal φext. Also, φa to φe indicate output signals connected to the amplifier circuit section shown in FIG.

  As shown in FIG. 15, the phase comparison unit of the phase comparison circuit 31 includes flip-flop circuits 421 and 422 each composed of two NAND gates, latch circuits 425 and 426 that latch the state, and an activation signal for the latch circuit. , A delay circuit 423 that delays the external clock signal φext by a unit delay amount, and a delay circuit 430 that delays the signal φout by a unit delay amount. The flip-flop circuit 421 performs phase comparison in the range of -td, and the flip-flop circuit 422 performs phase comparison in the range of + td.

  FIG. 16A shows a case where the phase of the comparison target signal φout advances beyond the comparison reference signal φext by more than td, that is, the signal φout changes from the low level L to the high level H before the signal φext. Yes. When both the signal φout and the signal φext are at the low level L, the nodes 6a-2, 6a-3, 6a-4, and 6a-5 of the flip-flop circuits 421 and 422 are all at the high level H.

  When the signal φout changes from the low level L to the high level H, the node 6a-4 changes from the high level H to the low level L, and the node 6a-0 is delayed by one delay (td) from the low level L to the high level H. As a result, the node 6a-2 changes from the high level H to the low level L. Thereafter, the signal φext changes from the low level L to the high level H, and the node 6a-1 changes from the low level L to the high level H with a delay of one delay, but the potentials at both ends of the flip-flop are already determined. No change will occur. As a result, the node 6a-2 maintains the low level L, the node 6a-3 maintains the high level H, the node 6a-4 maintains the low level, and the node 6a-5 maintains the high level.

  On the other hand, in response to the change of the signal φext from the low level to the high level H, the output signal φa of the circuit 424 changes from the low level L to the high level H, and temporarily goes to the high level H at the node 6a-6. A pulse is applied. Since the node 6a-6 serves as an input to the NAND gates of the latch circuits 425 and 426, the NAND gate is temporarily activated, and the potential states at both ends of the flip-flop circuits 421 and 422 are changed. 426. Eventually, the output signal φb becomes the high level H, the output signal φc becomes the low level L, the output signal φd becomes the high level H, and the output signal φe becomes the low level L.

  Next, FIG. 16B shows a case where the phase of the comparison target signal φout and the comparison reference signal φext are substantially the same (within ± td), and the signal φout changes from the low level L to the high level H almost simultaneously with the signal φext. ing. When the signal φout changes from the low level L to the high level H within the time difference between the rising time of the signal φout and the rising time of the node 6a-1, first, the signal φext changes from the low level L to the high level H. The node 6a-3 at 421 changes from the low level L to the high level H. In the flip-flop 422, since the node 6a-1 remains at the low level L, the node 6a-4 changes from the high level H to the low level L. Thereafter, the node 6a-1 changes from the high level H to the low level L. However, since the state of the flip-flop 422 has already been determined, no change occurs. Thereafter, since the node 6a-6 temporarily becomes the high level H, this state is stored in the latch circuit. As a result, the output signal φb is the low level, the output signal φc is the high level H, and the output signal φd is the high level. H, and the output signal φe becomes low level.

  FIG. 16C shows a case where the phase of the comparison target signal φout is delayed from the comparison reference signal φext by more than td, and φout changes from the low level L to the high level H after φext. In this case, changes occur in the two flip-flop circuits 421 and 422 due to φext, and 6a-3 and 6a-5 change from the high level H to the low level L. Finally, φb becomes a low level, φc becomes a high level H, φd becomes a low level L, and φe becomes a high level H.

  Thus, with reference to the rise time of the signal (comparison reference signal) φext, the rise time of the signal (comparison target signal) φout has become the high level H before that, has been almost at the same time, or delayed to the high level H It becomes possible to detect whether or not. These detection results are latched as the values of the output signals φb, φc, φd, and φe, and based on these values, it can be determined whether the delay control circuit 32 is counted up or counted down.

  Next, a configuration example of the amplifier circuit section of the phase comparison circuit 31 will be described with reference to FIG. FIG. 18 is a timing chart for explaining the operation of the JK flip-flop shown in FIG. As shown in FIG. 17, the amplification circuit unit of the phase standard circuit 31 includes two parts, a JK flip-flop 427 and an amplification unit 428 including a NAND gate and an inverter. The JK flip-flop 427 receives the output signal φa from the phase comparison unit of FIG. Is configured to alternately repeat the low level L and the high level H. The amplifying unit 428 receives and amplifies the output signal of the JK flip-flop 427 and the signals φb and φd.

  First, the operation of the JK flip-flop 427 will be described with reference to the timing chart of FIG. When the signal φa changes from the high level H to the low level L at time T1, the nodes 7a-1 and 7a-10 change from the low level L to the high level H. On the other hand, the nodes 7a-5, 7a-6, and 7a-7 change according to the change of the node 7a-1, but the node 7a-8 does not change because the signal φa is the low level L. Eventually, the output (node) 7a-9 does not change, and only the output 7a-11 changes from the low level L to the high level H. Next, when φa changes from the low level L to the high level H at time T2, the node 7a-8 changes from the high level H to the low level L and 7a-10 changes to 7a- Since 7 does not change, the output 7a-9 changes from the low level L to the high level H, and the output 7a-11 does not change. As described above, the JK flip-flop circuit 427 causes the outputs 7a-9 and 7a-11 to alternately repeat the high level H and the low level L in accordance with the movement of the signal φa.

  FIG. 19 is a timing diagram (when counting up) showing the operation of the amplifier circuit section when counting up, FIG. 20 is a timing diagram showing the operation when maintaining the count of the amplifier circuit section, and FIG. It is a timing diagram which shows the operation | movement at the time of countdown of a part. With reference to these drawings, the operation of the amplifying unit 428 shown in FIG. 17 will be described.

  FIG. 19 shows a case where the comparison target signal φout first changes from the low level L to the high level H with respect to the rising edge of the comparison reference signal φext. In this case, the input signal from the phase comparison unit has the signal φb at the high level H, the signal φc at the low level L, the signal φd at the high level H, and the signal φe at the low level L. Eventually, the node 7a-12 becomes high level H, the node 7a-13 is fixed at low level L, and the set signals φSO and φSE change according to the state of the JK flip-flop, but the reset signals φRO and φRE are 7a. Since -13 is low level L, it does not change.

  FIG. 20 shows a case where the comparison target signal φout changes from the low level L to the high level H almost simultaneously with the comparison reference signal φext. In this case, the input signal from the phase comparison unit is such that the signal φb is low level L, the signal φc is high level, the signal φd is high level, and the signal φe is low level. Eventually, the nodes 7a-12 and 7a-13 are fixed at the low level L, the reset signals φSE and φSO are not affected by the output of the JK flip-flop, and the signals φSO, φSE, φRO and φRE are at the low level L. Will remain fixed.

  FIG. 21 shows a case where the comparison target signal φout changes from the low level L to the high level H with a delay from the rising of the comparison reference signal φext. In this case, the input signal from the phase comparison unit has a signal φb at a low level L, a signal φc at a high level H, a signal φd at a low level L, and a signal φe at a high level H. Eventually, the node 7a-12 is fixed to the low level L, the node 7a-13 is fixed to the high level H, and the reset signals φRO and φRE change according to the state of the JK flip-flop 427, but the set signals φSO and φSE Does not change because the node 7a-13 is at the low level L.

  FIG. 17 also shows a logic circuit 431 that generates a reset signal from the signals φb and φe. If φout exceeds the range of ± td with respect to φext, the reset signal is at H, and if within the range, the reset signal is L. Next, the second DLL circuit 10 will be described in detail. FIG. 22 is a circuit diagram showing a configuration example of the high-accuracy delay circuit 12. The high-precision delay circuit 12 is provided with a NAND gate 404-1 and an inverter 405-1 in addition to the NAND gates 401-1 and 402-1 and the inverter 403-1 shown in FIG. A delay line is formed. By adding the logic circuit of the shaded portion, that is, the NAND gate 404-1 and the inverter 405-1, the unit delay amount (for example, 200 ps) of the unit delay circuit configured by the NAND gate 402-1 and the inverter 403-1 is reduced. The amount of delay below can be controlled. The difference between the delay amounts of two unit delay circuits provided per stage is the difference between the delay between the NAND gate 402-1 and the inverter 403-1 and the delay between the NAND gate 404-1 and the inverter 405-1. It becomes the accuracy of the accuracy delay circuit 12.

  For example, in the illustrated case, the input signal in passes through two shaded unit delay circuits and three unit delay circuits, and an output signal out is obtained. For example, when only the right adjacent NAND gate 401 is opened, the input signal in passes through the three unit delay circuits and the two unit delay circuits. The difference between the delay amounts of the output signals in the above two cases is the difference between the delay amounts of the two unit delay circuits. For example, when the unit delay circuit composed of NAND gate 402-1 and inverter 403-1 has a delay amount of 200 ps, and the unit delay circuit composed of NAND gate 404-1 and inverter 405-1 has a delay amount of 260 ps. The difference 60 ps is the accuracy of the high-precision unit delay circuit 12. Therefore, by controlling the NAND gate 401, delay amounts of 60 ps, 120 ps, 180 ps, and 240 ps can be set. Since any route is always passed through one NAND gate 401, the delay amount of this circuit is always included. In other words, the delay amount difference is not affected. Further, if the configuration shown in FIGS. 7 and 8 (−300 ps to 300 ps) is supported, the high-accuracy delay circuit 12 has an 11-stage configuration.

  Various methods are conceivable to obtain different delay amounts. For example, NAND gates and inverters having different characteristics are used. For example, a NAND gate and an inverter are formed using transistors having different characteristics. In addition, transistors having the same characteristics are used, but the power supply voltage applied thereto is different. Furthermore, even with the same characteristics and the same power supply voltage, different delay amounts can be obtained depending on the fan-out difference. When all the same logic elements in FIG. 22 have the same characteristics, the fanout of the inverter 405-1 is 2, but the fanout of the inverter 403-1 is 1. Due to this difference in fan-out, a difference of 60 to 70 ps can be obtained even when all the same logic elements in FIG. 22 have the same characteristics.

  The high-precision dummy delay circuit 13 has the same configuration as the high-precision delay circuit 12. The high-accuracy phase comparison circuit 14 of the second DLL circuit 10 has the same configuration as the phase comparison circuit 31 shown in FIGS. 15 and 17 except for the following points. The difference is shown in FIG. FIG. 23 is a diagram illustrating a phase comparison unit of the high-accuracy phase comparison circuit 14. 23, the delay circuit 430 shown in FIG. 17 is provided between the flip-flop circuits 421 and 422. A NAND gate gate 431 is provided between the delay circuits 430 and 423, and the output of the inverter of the delay circuit 430 is input to the NAND gate of the delay circuit 423 via the NAND gate 431.

  The delay circuits 423 and 430 have the same configuration as the unit delay circuit of the high-accuracy delay circuit 12. In the illustrated configuration, the delay circuits 423 and 430 are composed of NAND gates and inverters. Note that the fanout of the inverter of the delay circuit 423 is 1, whereas the fanout of the inverter of the delay circuit 430 is 2 because the NAND gate 431 is provided. That is, the load on the inverter of delay circuit 430 is larger than the load on the inverter of delay circuit 423. By providing such delay circuits 423 and 430 between the flip-flop circuits 421 and 422, it is determined whether the signal S0 (φout) and the signal S3 (φext) are within the range of 0 to td ′. be able to. Other configurations including the phase amplification circuit unit and the like are the same as those shown in FIGS.

  FIG. 24 is a timing chart showing the operation of the phase comparison unit of the high-accuracy phase comparison circuit 14 shown in FIG. FIG. 24A shows the operation at the time of counting up. When φout rises from the low level L to the high level H, the node 7a-2 changes to the low level L. The node 7a-0 changes to the high level H with a delay of td + td 'from the change of the signal φout by the action of the delay circuit 430. Thereafter, the signal φext changes to the high level H, and the node 7a-1 changes to the high level H with a delay of td from the above change due to the action of the delay circuit 423. The nodes 7a-3 and 7a-5 remain at the high level H and do not change. Therefore, φb = H, φc = L, φd = H, and φe = L in response to the potential change of the node 7a-6.

  FIG. 24B shows the operation when maintaining the count. As shown in the figure, when the signals φout and φext are in the range of 0 to td ′, φb = L, φc = H, φd = H, and φe = L. FIG. 24C shows the operation at the time of countdown. As shown in the figure, φb = L, φc = H, φd = L, and φe = H. FIG. 25 is a circuit diagram showing a configuration of the delay control circuit 15. The left portion of the broken line in FIG. 25 is substantially the same as the circuit configuration shown in FIG. The right part of the broken line is slightly different from the left part. This is because when the reset signal is received from the phase comparison circuit 31, only the corresponding NOR gate outputs a high level H in order to reset the high precision delay circuit 12 and the high precision dummy delay circuit 13 to the center. Because. The output of the NAND gate 432-3 adjacent to the left side of the broken line is input to the preceding NOR gate 431-2, and the output of the inverter 433-3 is input to the NOR gate 431-3. The output of the NAND gate 432-4 adjacent to the right side of the broken line is input to the NOR gate 431-4, and the output of the inverter 433-4 is input to the NOR gate 431-3. When the reset signal becomes active (high level H), the level of each node is as shown in FIG. 25, and only the NOR gate 431-3 corresponding to the center of the high precision delay circuit 12 and the high precision dummy delay circuit 13 is high level. H is output, and all other NOR gates output low level L. The shift operation is the same as the shift operation described with reference to FIGS.

  In an actual circuit configuration, it is particularly preferable to consider the following points. The following points are considered when the NAND gates of the flip-flop circuits 421 and 422 constituting the phase comparison unit of the phase comparison circuit 31 and the high-accuracy phase comparison circuit 14 are constituted by MOS transistors. FIG. 26 is a circuit diagram of the NAND gate. The NAND gate includes two P channel MOS transistors Q10 and Q11 and two N channel MOS transistors Q12 and Q13. The source of the P-channel transistor Q10 is connected to the first power supply Vcc, the gate is connected to the first input IN1, and the drain is connected to the output OUT. The source of the P-channel transistor Q11 is connected to the first power supply Vcc, the gate is connected to the second input IN2, and the drain is connected to the output OUT. The source of the N-channel transistor Q12 is connected to the drain of the N-channel transistor Q13, the gate is connected to the first input IN1, and the drain is connected to the output OUT. The source of the N-channel transistor Q13 is connected to the second power supply (ground), the gate is connected to the second input IN2, and the drain is connected to the source of the N-channel transistor Q12.

  Here, the input / output response characteristics between the input signal IN1 and the output OUT and the input / output characteristics between the input signal IN2 and the output OUT are slightly different due to the circuit configuration. When the flip-flop circuits 421 and 422 are configured by using two such NAND gates, the two input signals of each flip-flop circuit are connected to receive the same conditions in order to obtain the highest possible accuracy. To do. For example, when the set terminal of the first NAND gate of the flip-flop circuit 421 receives the signal φout as IN1 shown in FIG. 26, the reset terminal of the second NAND gate receives the signal φext as IN1. In this case, the reset terminal IN2 of the first NAND gate is connected to the output of the second NAND gate to form a Q output, and the reset terminal IN2 of the second NAND gate is connected to the output of the first NAND gate. / Q output. Conversely, when the set terminal of one NAND gate of the flip-flop circuit 421 receives the signal φout as IN2 in FIG. 26, the reset terminal of the other NAND gate receives the signal φext as IN2. In this case, the reset terminal IN1 of the first NAND gate is connected to the output of the second NAND gate to form a Q output, and the reset terminal IN1 of the second NAND gate is connected to the output of the first NAND gate. / Q output.

  Thus, the circuit configuration conditions for the two input signals are the same, and high phase comparison accuracy can be maintained. FIG. 27 is a diagram showing another configuration example of the high precision delay circuit 12 and the high precision dummy delay circuit 13. The illustrated configuration is a two-stage configuration, and capacitors C1 and C2 are provided as delay elements in each stage. Capacitors C1 and C2 are selectively connected to the delay line via transistors Q1 and Q2. The delay control circuit 15 controls the transistors Q1 and Q2. For example, a capacity of 25 fF has a delay amount of 50 ps, and a capacity of 50 fF has a delay amount of 100 ps. Therefore, by using such a capacitor, the high-accuracy delay circuit 12 with higher accuracy than the delay circuit 33 can be realized.

  As another configuration, a plurality of resistors are connected in series, a switch that short-circuits both ends of each resistor is provided, and the amount of delay is varied by changing the number of resistors connected in series between input and output But you can. Furthermore, a delay circuit combining such a resistor and the capacitor may be used. The final delay amount includes the delay amounts of the inverters INV1 and INV2 shown in FIG.

  FIG. 28 is a diagram showing a modification of the configuration shown in FIG. The modification shown in FIG. 28 eliminates the frequency dividing circuit 30 shown in FIG. 5 and outputs the output signal S1 of the input circuit 21 directly to the dummy delay circuit 33, the phase comparison circuit 31, and the high-precision phase comparison circuit 14. Thus, the configuration is different from that shown in FIG. As described above, by providing the frequency dividing circuit 30, the clock to be phase-compared can be surely specified. However, the clock frequency is very low, the relative positional relationship between the clock from the input circuit 21 and the fed back clock does not fluctuate more than one cycle, and both clocks to be compared are at a high level. If there is a certain time, the frequency dividing circuit 30 is not always necessary. The modification shown in FIG. 28 is obtained by removing the frequency dividing circuit 30 shown in FIG. 5 from this viewpoint. The operation of the modification shown in FIG. 28 is the same as the operation described with reference to FIGS. Therefore, the description of the operation of the modification shown in FIG. 28 is omitted here.

  Next, a semiconductor integrated circuit device (DLL circuit) according to another embodiment of the present invention will be described. FIG. 29 shows a semiconductor integrated circuit device according to this embodiment. In FIG. 29, the same reference numerals are attached to the same components as those shown in the above-described drawings. The illustrated semiconductor integrated circuit device includes a first DLL circuit 3 and a second DLL circuit 10. However, unlike the configuration shown in FIG. 5, the first DLL circuit 3 and the second DLL circuit 10 operate independently, and the delay amount control is also performed independently, instead of the hierarchical configuration.

  Hereinafter, the configuration and operation of FIG. 29 will be described in detail. The second DLL circuit 10 is provided on the output side of the first DLL circuit 3 and has higher accuracy than the accuracy of the first DLL circuit 3. An input clock signal input from the outside via the clock input pad 1 and the input circuit 21 functioning as a clock buffer is delayed by the first DLL circuit 3, and the output is delayed with higher accuracy by the second DLL circuit 10. As a result, an output (internal) clock signal having a predetermined phase relationship with respect to the input clock signal is generated. The output of the second DLL circuit 10 is given to the output circuit 51 connected to the data bus via the clock wiring 41. The output circuit 51 buffers the data on the data bus in synchronization with the output clock signal from the second DLL circuit 10 and then outputs the data to the data output pad 6. The semiconductor integrated circuit device also includes a dummy input circuit 22 that functions as a clock buffer, a dummy wiring 42, a dummy output circuit 52 that functions as an output buffer, and a dummy load capacitor 7. These dummy input circuit 22, dummy wiring 42, and dummy output circuit 52 have the same circuit configuration as the input circuit 21, clock wiring 41, and output circuit 51, respectively, and have the same delay amount. The dummy load capacitance 7 is equal to the load capacitance coupled to the data output pad 6.

  The first DLL circuit 3 and the second DLL circuit 10 operate independently (phase comparison and delay amount control). That is, the clock signal obtained from the dummy output circuit 52 through the dummy input circuit 22 is phase-independently compared with the input clock signal from the input circuit 21, and the delay amount is controlled so that the respective phase differences have a predetermined relationship. To do. Specifically, the phase difference in a predetermined relationship is a state in which the dummy clock signal is delayed by at least k cycles with respect to the input clock signal (k is an integer of 1 or more). In this state, there is no apparent phase difference between the clock signal on the dummy side and the input signal. That is, data output from the output circuit 51 is synchronized with an external input clock signal applied to the clock input pad 1.

  The first DLL circuit 3 includes a frequency dividing circuit 30, a phase comparison circuit 31 that functions as a digital phase comparator, a delay control circuit 32, a delay circuit 33, and a dummy delay circuit 34. The frequency dividing circuit 30 divides the external clock signal S1 via the input circuit 21, and outputs signals S2 and S3 having the same frequency lower than the external clock signal S1. The signal S2 is output to the dummy delay circuit 34, and the signal S3 is output to the first input of the phase comparison circuit 31. The output signal of the dummy delay circuit 34 is given to the second input of the phase comparison circuit 31 via a high-precision dummy delay circuit 13, a dummy wiring 42, a dummy output circuit 52, and a dummy input circuit 22 described later. Here, a signal output from the dummy input circuit 22 is S0. The phase comparison circuit 31 compares the phases of the signals S0 and S3 and controls the delay control circuit 32. The delay control circuit 32 sets the same delay amount in the delay circuit 33 and the dummy delay circuit 34 in accordance with the output signal (phase comparison result) of the phase comparison circuit 31. The output signal of the delay circuit 33 is given to the high precision delay circuit 12 of the second DLL circuit 10.

  The second DLL circuit 10 includes the high-accuracy delay circuit 12, the high-accuracy dummy delay circuit 13, and the high-accuracy phase comparison circuit 14. The high-accuracy delay circuit 12 can control the delay amount with higher accuracy than the delay circuit 33. The delay amount of the high-precision dummy delay circuit 13 is fixed to a predetermined value. The high precision phase comparison circuit 14 compares the phases of the signals S0 and S3 and controls the delay amount of the high precision delay circuit 12. Due to the action of the first DLL circuit 3, the output clock signal in the output circuit 51 is almost synchronized with the external clock signal, and the delay amount of the high-accuracy delay circuit 12 depends on the comparison result of the high-accuracy phase comparator 14. By controlling this, phase control can be performed with high accuracy (the space between the accuracy of the first DLL circuit 3 is filled with the second DLL circuit 10).

  5 includes the dummy wiring 42, the dummy output circuit 52, and the dummy load capacitor 7 shown in FIG. Further, the output circuit 51 shown in FIG. 29 includes the clock wiring 41 shown in FIG. Next, although each part of the 1st DLL circuit 3 is demonstrated in detail, the description is abbreviate | omitted about the detail of a structure of the part same as each part of the 1st DLL circuit 3 shown in FIG.

  The configuration of the phase comparison circuit 31 shown in FIG. 29 will be described. The phase comparison circuit 31 includes a phase comparison unit shown in FIG. 30 and the above-described amplification circuit unit shown in FIG. First, the phase comparison unit shown in FIG. 8 will be described with reference to FIG. In FIG. 30, reference signs φout and φext indicate an output signal (S0) and an external clock signal (S1) to be compared by the phase comparison circuit, and the phase of the signal φout is determined with reference to the signal φext. Also, φa to φe indicate output signals connected to the amplifier circuit section shown in FIG.

  As shown in FIG. 30, the phase comparison unit of the phase comparison circuit 31 includes flip-flop circuits 421 and 422 each composed of two NAND gates, latch circuits 425 and 426 that latch the state, and an activation signal for the latch circuit. And a delay circuit 423 corresponding to a unit delay for obtaining a phase allowable value of the external clock signal φext.

  FIG. 31A shows a case where the phase of the comparison target signal φout is ahead of the phase of the comparison reference signal φext, that is, the case where the signal φout changes from the low level L to the high level H before the signal φext. When both the signal φout and the signal φext are at the low level L, the nodes 6a-2, 6a-3, 6a-4, and 6a-5 of the flip-flop circuits 421 and 422 are all at the high level H.

  When the signal φout changes from the low level L to the high level H, the nodes 6a-2 and 6a-4 both change from the high level H to the low level L. Thereafter, the signal φext changes from the low level L to the high level H, and the node 6a-1 changes from the low level L to the high level H with a delay of one delay, but the potentials at both ends of the flip-flop are already determined. No change will occur. As a result, the node 6a-2 maintains the low level L, the node 6a-3 maintains the high level H, the node 6a-4 maintains the low level, and the node 6a-5 maintains the high level.

  On the other hand, in response to the change of the signal φext from the low level to the high level H, the output signal φa of the circuit 424 changes from the low level L to the high level H, and temporarily goes to the high level H at the node 6a-6. A pulse is applied. Since the node 6a-6 serves as an input to the NAND gates of the latch circuits 425 and 426, the NAND gate is temporarily activated, and the potential states at both ends of the flip-flop circuits 421 and 422 are changed. 426. Eventually, the output signal φb becomes the high level H, the output signal φc becomes the low level L, the output signal φd becomes the high level H, and the output signal φe becomes the low level L.

  Next, FIG. 31B shows a case where the phase of the comparison target signal φout and the comparison reference signal φext are substantially the same, and the signal φout changes from the low level L to the high level H almost simultaneously with the signal φext. When the signal φout changes from the low level L to the high level H within the time difference between the rising time of the signal φout and the rising time of the node 6a-1, first, the signal φext changes from the low level L to the high level H. The node 6a-3 at 421 changes from the low level L to the high level H. In the flip-flop 422, since the node 6a-1 remains at the low level L, the node 6a-4 changes from the high level H to the low level L. Thereafter, the node 6a-1 changes from the high level H to the low level L. However, since the state of the flip-flop 422 has already been determined, no change occurs. Thereafter, since the node 6a-6 temporarily becomes the high level H, this state is stored in the latch circuit. As a result, the output signal φb is at the low level, the output signal is at the high level H, and the output signal φd is at the high level H. Then, the output signal φe becomes low level.

  FIG. 31C shows a case where the comparison target signal φout is delayed in phase from the comparison reference signal φext, and φout changes from the low level L to the high level H after φext. In this case, changes occur in the two flip-flop circuits 421 and 422 due to φext, and 6a-3 and 6a-5 change from the high level H to the low level L. Finally, φb becomes a low level, φc becomes a high level H, φd becomes a low level L, and φe becomes a high level H.

  Thus, with reference to the rise time of the signal (comparison reference signal) φext, the rise time of the signal (comparison target signal) φout has become the high level H before that, has been almost at the same time, or delayed to the high level H It becomes possible to detect whether or not. These detection results are latched as the values of the output signals φb, φc, φd, and φe, and based on these values, it can be determined whether the delay control circuit 32 is counted up or counted down.

  FIG. 32 is a circuit diagram showing a configuration example of the high-accuracy delay circuit 12. The high-accuracy delay circuit 12 includes an inverter circuit INV1 in which two inverters are connected in series, an inverter circuit INV2 in which two inverters are connected in series, two n-channel transistors Q1 and Q2, and two capacitors C1 (for example, 50 fF capacity) and C2 (for example, 25 fF capacity). By selectively connecting the capacitors C1 and C2 to the signal delay line via the transistors Q1 and Q2, the delay amount can be varied. That is, the delay amount of the high-accuracy delay circuit 12 is the sum of the fixed delay amount of the inverter circuits INV1 and INV2 and the delay amount determined by the capacitors C1 and C2. Control signals N12 and N03 output from the high precision phase comparison circuit 14 shown in FIG. 29 are applied to the gates of the transistors Q1 and Q2, respectively. For example, a capacity of 25 fF has a delay amount of 50 ps, and a capacity of 50 fF has a delay amount of 100 ps. Since the unit delay amounts of the delay circuit 33 and the dummy delay circuit 34 described above are, for example, 200 ps, the high-accuracy delay circuit 12 enables high-accuracy delay control.

  FIG. 33 is a circuit diagram showing a configuration example of a high-precision dummy delay circuit. Like the high-accuracy delay circuit 12, the high-accuracy delay circuit 13 includes two inverter circuits INV3 and INV4, two n-channel transistors Q3 and Q4, and two capacitors C3 (50 fF) and C4 (25 fF). Is done. However, since the gates of the transistors Q3 and Q4 are fixed to the ground level, the capacitors C3 and C4 are disconnected from the signal delay line. Therefore, the delay amount of the high-precision dummy delay circuit 13 is a fixed value determined by the two inverter circuits INV3 and INV4. Although the capacitors C3 and C4 do not function for delay, the circuit conditions for the clock signal are made the same by making the high-precision dummy delay circuit 13 the same circuit configuration as the high-precision delay circuit 12.

  FIG. 34 is a circuit diagram showing a configuration example of the high-accuracy phase comparison circuit 14. The high-accuracy phase comparison circuit 14 uses the external clock signal S3 output from the frequency dividing circuit 30 as a reference signal, gives a plurality of different delay amounts to the signal S0 output from the dummy input circuit 22, and obtains a plurality of signals obtained thereby. Is compared with the signal S3 to determine the delay amount of the high-accuracy delay circuit 12.

  As shown in FIG. 34, delay circuits 102, 103, and 104 having three different delay amounts are provided for the signal S0 output from the dummy input circuit 22. The circuit configuration of each of the delay circuits 102, 103, and 104 is the same as the circuit configuration of the high-accuracy delay circuit 12 described with reference to FIG. However, in order to set different delay amounts, the on / off control of the two transistors of the delay circuits 102, 103 and 104 is different. The delay circuit 102 has a 25 fF capacitor connected to the signal delay line, the delay circuit 103 has a 50 fF capacitor connected to the signal delay line, and the delay circuit 104 has both 25 fF and 50 fF capacitors connected to the signal delay line. . In order to set the same circuit conditions as those of the delay circuits 102 to 104, the delay circuit 101 having the same circuit configuration is provided for the reference signal S3. However, the two capacitors are both disconnected from the signal delay line.

  The high-precision phase comparison circuit 14 also includes flip-flop circuits 105, 106, and 107 configured by two NAND gates, latch circuits 109, 110, and 111 that latch the state thereof, and activation signals of these latch circuits. And a logic circuit 112 that generates a control signal for the transistor Q2 of the high-accuracy delay circuit 12 from the outputs of the circuit 108 and the latch circuits 109, 110, and 111 using three NAND gates.

  FIG. 35 is a timing chart showing the operation of the high-accuracy phase comparison circuit 14 shown in FIG. This timing diagram is a circuit operation when the unit delay amount of the unit delay circuit of the delay circuit 33 and the dummy delay circuit 34 is 200 ps, and a delay of 50 ps occurs when the capacity of the signal delay line increases by 25 fF. FIGS. 35 (a), (b), (c), and (d) show operations when the signal S0 is 40 ps, 90 ps, 140 ps, and 190 ps faster than S3, respectively. In FIG. 35, reference symbols A to D and a-1 to a-7, N01 to N03, N11 to N12, and N21 to N22 indicate signals of the circuit portion shown in FIG.

  FIG. 35A shows a case where the signal S0 is 40 ps faster than S3. In this case, it is necessary to disconnect both of the capacitors Q1 and Q2 in FIG. 32 and minimize the delay amount of the high-accuracy delay circuit 12. The signal of each circuit portion changes as shown in FIG. 35A, and the control signals N12 and N03 are both set to the low level L. FIG. 35B shows a case where the signal S0 is 90 ps faster than S3. In this case, it is necessary to increase the signal delay amount by 50 ps by connecting only the capacitor Q2 of FIG. The signal of each circuit part changes as shown in FIG. 35B, the control signal N12 becomes the low level L, and the control signal N03 becomes the high level H.

  FIG. 35C shows the case where the signal S0 is 140 ps faster than S3. In this case, it is necessary to increase the signal delay amount by 10 ps by connecting only the capacitor Q1 of FIG. The signal of each circuit part changes as shown in FIG. 35 (c), the control signal N12 becomes the high level H, and the control signal N03 becomes the low level L. FIG. 35D shows the case where the signal S0 is 190 ps faster than S3. In this case, it is necessary to connect both the capacitors Q1 and Q2 of FIG. 32 and increase the signal delay amount by 150 ps. The signal of each circuit portion changes as shown in FIG. 35 (d), and the control signals N12 and N03 are both at the high level H.

  As described above, the first DLL circuit 3 controls the delay amount with an accuracy of 200 ps, and the second DLL circuit 10 further controls the delay amount with an accuracy of 50 ps, thereby performing highly accurate delay control. In addition, an internal clock signal synchronized with the external clock signal CLK with high accuracy can be generated. Next, another configuration example of the second DLL circuit 10 will be described.

  FIG. 36 is a circuit diagram showing another configuration example of the high-accuracy delay circuit 12. The high-accuracy delay circuit 12 shown in FIG. 36 can control the delay amount below the unit delay amount 200 ps of the unit delay circuit 400 by adding a shaded logic circuit to the delay circuit shown in FIG. It is what. A unit delay circuit 400 ′ having a different delay amount is connected to each unit delay circuit 400 including NAND gates 401 and 402 and an inverter 403. The unit delay circuit 400 'includes a NAND gate 402' and an inverter 403 '. The difference in delay amount between the unit delay circuits 400 and 400 ′ is the difference between the delay between the NAND gate 402 ′ and the inverter 403 ′ and the delay between the NAND gate 402 and the inverter 403, and this is the accuracy of the high-precision delay circuit 12. For example, when only the NAND gate receiving the control signal N03 'is open, the input signal in passes through the two unit delay circuits 400' and the two unit delay circuits 400, and an output signal out is obtained. When only the NAND gate receiving the control signal N04 'is open, the input signal in passes through the three unit delay circuits 400' and one unit delay circuit 400. The difference between the delay amounts of the output signals in the above two cases is the difference between the delay amounts of the unit delay circuits 400 and 400 '. For example, when the unit delay circuit 400 has a delay amount of 200 ps and the unit delay circuit 400 ′ has a delay amount of 250 ps, the difference 50 ps becomes the accuracy of the high-precision unit delay circuit 12. Therefore, by controlling the NAND gate 401, delay amounts of 50 ps, 100 ps, and 150 ps can be set. Since any route is always passed through one NAND gate 401, the delay amount of this circuit is always included. In other words, the delay amount difference is not affected. Also, the control signals N01 'to N04' in FIG. 36 are output from the high-accuracy phase comparison circuit 14 to be described later with reference to FIG.

  FIG. 37 is a diagram showing another configuration example of the high-precision dummy delay circuit 13. High-precision dummy delay circuit 13 has the same configuration as high-precision delay circuit 12 shown in FIG. However, since only the first-stage NAND gate 401 is set to the high level H and the remaining corresponding NAND gates are set to the low level L, all the input signals in are output through the unit delay circuit 400.

  FIG. 38 is a circuit diagram showing a configuration example of the high-accuracy phase comparison circuit 14 when the configuration shown in FIGS. 36 and 37 is used. The same components as those shown in FIG. 34 are given the same reference numerals. Three delay circuits 122, 123, and 124 having different delay amounts with respect to the signal S0 from the dummy input circuit 22 are provided. The circuit configurations of the delay circuits 122, 123, and 124 are the same as those shown in FIG. However, in order to set different delay amounts, the level settings of the NAND gates are different. For example, the level setting of the NAND gate of the delay circuit 122 is L, H, L, and L in order from the left. In order to make the circuit conditions the same, a delay circuit 121 having the same circuit configuration as the delay circuits 122 to 124 is provided for the signal S3. Further, in place of the logic circuit 112 shown in FIG. 34, a logic circuit 125 including a NAND gate and an inverter is provided. The logic circuit 125 outputs control signals N01 'to N04'.

  FIG. 39 is a timing chart showing the operation of the high-accuracy phase comparison circuit 14 shown in FIG. In this timing diagram, the unit delay amount of the unit delay circuit of the delay circuit 33 and the dummy delay circuit 34 is 200 ps, and the number of unit delay circuits 400 ′ is one by shifting the delay circuits 122 to 124 one by one to the right. This is a circuit operation in the case where the delay amount of 50 ps increases with each increase. 39 (a), (b), (c), and (d) show operations when the signal S0 is 40 ps, 90 ps, 140 ps, and 190 ps faster than S3, respectively. Also, in FIG. 39, reference symbols A 'to D', b-1 to b-7, and N01 'to N04' indicate signals of the circuit portion shown in FIG.

  FIG. 39A shows a case where the signal S0 is 40 ps faster than S3. In this case, it is necessary to set the delay amount of the high-accuracy delay circuit 12 in FIG. 36 to be equal to the delay circuit 121 shown in FIG. 38 (minimum value). The signal of each circuit portion changes as shown in FIG. 39A, and only the control signal N01 'is set to the high level H. FIG. 39B shows a case where the signal S0 is 90 ps faster than S3. In this case, it is necessary to set the delay amount of the high-accuracy delay circuit 12 of FIG. 36 equal to that of the delay circuit 122 shown in FIG. The signal of each circuit portion changes as shown in FIG. 39B, and only the control signal N02 'is set to the high level H.

  FIG. 39 (c) shows a case where the signal S0 is 140 ps faster than S3. In this case, it is necessary to set the delay amount of the high-accuracy delay circuit 12 of FIG. 36 equal to the delay circuit 123 shown in FIG. The signal of each circuit portion changes as shown in FIG. 39C, and only the control signal N03 'is set to the high level H. FIG. 39D shows a case where the signal S0 is 190 ps faster than S3. In this case, it is necessary to set the delay amount of the high-accuracy delay circuit 12 of FIG. 36 equal to that of the delay circuit 124 shown in FIG. The signal of each circuit portion changes as shown in FIG. 39 (d), and only the control signal N04 'is set to the high level H.

  As described above, the first DLL circuit 3 controls the delay amount with an accuracy of 200 ps, and the second DLL circuit 10 further controls the delay amount with an accuracy of 50 ps, thereby performing highly accurate delay control. In addition, an internal clock signal synchronized with the external clock signal CLK with high accuracy can be generated. The circuit configurations of the high-accuracy delay circuit 12 and the high-accuracy dummy delay circuit 13 are not limited to those described above, and different delay amounts can be set by connecting a plurality of resistors in series and varying the number of resistors through which signals pass. It can be realized with various configurations such as a configuration to combine, a configuration in which a resistor and a capacitor are combined.

  40 is a diagram showing a configuration of a synchronous DRAM (SDRAM) as an example to which a semiconductor integrated circuit device (DLL) according to the present invention is applied, and FIG. 41 is a diagram for explaining the operation of the SDRAM of FIG. It is a timing chart. An SDRAM as an example of a semiconductor integrated circuit device to which the present invention is applied adopts, for example, a pipeline system, and is configured to have a 16M.2 bank.8 bit width.

  As shown in FIG. 40, the SDRAM is not only a DRAM core 108a, 108b of a general-purpose DRAM, but also a clock buffer 101, a command decoder 102, an address buffer / register & bank address select (address buffer) 103, an I / O data buffer / A register 104, control signal latches 105a and 105b, a mode register 106, and column address counters 107a and 107b are provided. Here, the / CS, / RAS, / CAS, and / WE terminals are different from the conventional operation, and the operation mode is determined by inputting various commands in combination. Various commands are decoded by the command decoder, and each circuit is controlled according to the operation mode. The / CS, / RAS, / CAS, and / WE signals are also input to the control signal latches 105a and 105b, and their states are latched until the next command is input.

  The address signal is amplified by the address buffer 103 and used as a load address for each bank, and is also used as an initial value for the column address counters 107a and 107b. The clock buffer 101 includes an internal clock generation circuit 121 and an output timing control circuit 122. The internal clock generation circuit 121 generates a normal internal clock signal from the external clock signal CLK, and the output timing control circuit 122 applies accurate delay control (phase control) by applying the DLL circuit as described above. For generating the clock signal.

  The I / O data buffer / register 104 includes a data input buffer 13 and a data output buffer (output circuit) 51, and signals read from the DRAM cores 108 a and 108 b are amplified to a predetermined level by the data output buffer 51. The data is output via the pads DQ0 to DQ7 at the timing according to the clock signal from the output timing control circuit 122. As for the input data, the data input from the pads DQ0 to DQ7 is taken in via the data input buffer 13. Here, the clock wiring 41 corresponds to the wiring from the output timing control circuit 122 to each data output buffer 51.

  The read operation of the SDRAM will be described with reference to FIG. First, the external clock signal CLK is a signal supplied from a system in which the SDRAM is used. In synchronization with the rising edge of the CLK, various commands, address signals, input data are fetched, or output data is output. To work.

  When reading data from the SRAM, an active (ACT) command is input to the command terminal from a combination of command signals (/ CS, / RAS, / CAS, / WE signal), and a row address signal is input to the address terminal. When this command and row address are input, the SDRAM is activated, selects a word line corresponding to the row address, outputs cell information on the word line to the bit line, and amplifies it by a sense amplifier.

  Further, a read command (Read) and a column address are input after the operation time (tRCD) of the portion related to the row address. According to the column address, the selected sense amplifier data is output to the data bus line, amplified by the data bus amplifier, further amplified by the output buffer, and output to the output terminal (DQ). These series of operations are exactly the same as those of a general-purpose DRAM. In the case of an SDRAM, a circuit related to a column address operates as a pipeline, and read data is output exclusively for each cycle. . As a result, the data transfer rate becomes the cycle of the external clock signal CLK.

  There are three types of access time in the SDRAM, all of which are defined with reference to the rising point of the external clock signal CLK. In FIG. 41, tRAC indicates a row address access time, tCAC indicates a column address access time, and tAC indicates a clock access time. FIG. 42 is a block diagram schematically showing a main configuration of the SDRAM of FIG. 40, for explaining the pipeline operation in the SDRAM, and shows a case where three stages of pipes are provided as an example. .

  The processing circuit related to the column address in the SDRAM is divided into a plurality of stages along the flow of processing, and the divided circuit of each stage is called a pipe. As described with reference to FIG. 40, the clock buffer 101 includes the internal clock generation circuit 121 and the output timing control circuit 122, and the output of the internal clock generation circuit 121 (ordinary internal clock Hisao Niio) is pipe-1 and pipe. -2, and the output of the output timing control circuit 122 (phase-controlled internal clock signal) is supplied to the output circuit 51 (data output buffer) of the pipe-3.

  Each pipe is controlled according to the supplied internal clock signal, and a switch for controlling the transmission timing of the signal between the pipes is provided between the pipes. These switches are also connected to the clock buffer 101 (internal clock generation circuit 121). ) Is controlled by the internal clock signal generated in (1). In the example shown in FIG. 42, in the pipe-1, the address signal is amplified by the column address buffer 116, the address signal is sent to the column decoder 118, and the information of the sense amplifier circuit 117 corresponding to the address address selected by the column decoder 118 is obtained. Until the data bus amplifier 119 amplifies the information on the data bus. Further, only the data bus control circuit 120 is provided in the pipe-2, and the pipe-3 is configured by the I / O buffer 104 (output circuit 51). The data input buffer 13 in the I / O buffer 104 is omitted in FIG.

  If the circuits in each pipe also complete the operation within the clock cycle time, data is relayed out by opening and closing a switch between the pipes in synchronization with the clock signal. As a result, processing in each pipe is performed in parallel, and data is continuously output to the output terminal in synchronization with the clock signal.

  FIG. 43 is a diagram for explaining a configuration example of the output circuit (data output buffer 51) in the semiconductor integrated circuit device according to the present invention. As shown in FIGS. 42 and 43, Data1 and Data2 in FIG. 43 correspond to the storage data read from the cell array 115 and output through the sense amplifier 117, the data bus amplifier 119, and the data bus control circuit 120. Data1 and Data2 are both at the low level L when the output data is at the high level H, and are at the high level H when the output data is at the low level L. It is also possible to take a high impedance state (hijet state) in which the output data is neither high level H nor low level L. In this case, in the data bus control circuit 120, Data1 is high level H and Data2 is low. Converted to level. The signal φof corresponds to the output signal (clock signal) of the output timing control circuit 122 (high-precision delay circuit 12 in FIG. 29) and functions as an enable signal for the output circuit.

  When the clock signal φof becomes high level H, information of Data1 and Data2 appears on the data output pads 6 (DQ0 to DQ7). For example, assuming that the high level H is output to the data output pad 6, the clock signal φof changes from the low level L to the high level H, the node 8a-1 changes to the low level L, and the node 8a-2 changes to the high level. Then, the transfer gate is turned on, and Data1 and Data2 are transmitted to the nodes 8a-3 and 8a-6. As a result, when the node 8a-5 is at the low level L and the node 8a-8 is at the high level, the output P-channel transistor 81 is turned on, and the N-channel transistor 82 is turned off. A high level H output appears. When the clock signal φof becomes low level L, the transfer gate is turned off and the output state up to that time is maintained.

  FIG. 44 is a diagram showing a configuration example of the dummy output circuit 52 shown in FIG. The dummy output circuit 52 has a circuit configuration similar to that of the output circuit 51 so that the delay time is substantially equal to that of the output circuit 51 of FIG. The difference from the output circuit 51 is that the latch units 51-3 and 51-4 of the output circuit 51 are replaced with latch circuits 52-3 and 52-4 each composed of an inverter and a NAND gate. In addition, an internal clock signal supplied from the high-accuracy delay circuit 12 shown in FIG. The latch circuits 52-3 and 52-4 output an inverted signal of the received internal clock signal. From the output node 8a-9 of the dummy output circuit 52, in response to the internal clock signal, the H level and the L level are output. Signals are output alternately. Further, a dummy load capacitor 7 is connected to the output node 8a-9 of the dummy output circuit 52. The capacitance value of the dummy load capacitor 7 is set to a value equal to the average value of the external loads connected to the output terminal 6 of the output circuit 51. The present invention is not limited to the above embodiments, and various modifications are possible. For example, a logic element that functions as a delay element included in the delay circuit is not limited to a NAND gate or an inverter, and can be configured using a logic element such as NOR or EOR.

  In the above description, the semiconductor integrated circuit device of the present invention has been described as an SDRAM. However, the present invention is not limited to an SDRAM, and any semiconductor integrated circuit device that outputs an output signal in synchronization with an externally input signal. It can be applied to anything.

It is a figure which shows one Example of the variable delay circuit of this invention. It is a figure which shows one Example of the phase comparison circuit by this invention. It is a figure which shows one specific example of the variable value piece circuit shown in FIG. It is a figure which shows one Example of the position comparison circuit of this invention. 1 is a block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 6 is a diagram showing an outline of operation of the semiconductor integrated circuit device of FIG. 5. FIG. 6 is a diagram showing a carry operation of the semiconductor integrated circuit device of FIG. 5. FIG. 6 is a diagram showing a carry-down operation of the semiconductor integrated circuit device of FIG. 5. FIG. 6 is a circuit diagram illustrating an example of a frequency dividing circuit in the semiconductor integrated circuit device of FIG. 5. It is a figure which shows the signal waveform of each node of the frequency divider circuit of FIG. FIG. 10 is a timing chart for explaining the operation of the semiconductor integrated circuit device using the frequency divider circuit of FIG. 9. It is a figure for demonstrating one structural example of the delay circuit in the semiconductor integrated circuit device of this invention. FIG. 6 is a diagram for explaining a configuration example of a delay control circuit 32 in the semiconductor integrated circuit device of the present invention. FIG. 14 is a timing chart for explaining the operation of the delay control circuit of FIG. 13. FIG. 4 is a diagram for explaining a configuration example of a phase comparison unit of a phase comparison circuit 31 in the semiconductor integrated circuit device of the present invention. FIG. 16 is a timing diagram for explaining the operation of the phase comparison unit of FIG. 15. FIG. 3 is a diagram for explaining a configuration example of an amplifier circuit section of a phase comparison circuit 31 in the semiconductor integrated circuit device of the present invention. FIG. 18 is a timing diagram for explaining the operation of a JK flip-flop in the amplifier circuit section of FIG. 17. FIG. 18 is a timing chart (when counting up) for explaining the operation of the amplifier circuit section of FIG. 17; FIG. 18 is a timing diagram for explaining the operation of the amplifier circuit unit in FIG. 17 (when the count is maintained). FIG. 18 is a timing chart (during countdown) for explaining the operation of the amplifier circuit section of FIG. 17. FIG. 6 is a circuit diagram illustrating a configuration example of the high-accuracy delay circuit 12 in FIG. 5. FIG. 3 is a diagram for explaining a configuration example of a phase comparison unit of a phase comparison circuit 14 in the semiconductor integrated circuit device of the present invention. FIG. 24 is a timing chart showing the operation of the phase comparison unit of the high-accuracy phase comparison circuit 14 shown in FIG. 23. FIG. 6 is a circuit diagram illustrating a configuration example of a delay control circuit 15 in FIG. 5. It is a circuit diagram which shows the structure of the NAND gate which comprises a flip-flop circuit. FIG. 6 is a circuit diagram showing another configuration example of the high-accuracy delay circuit 12 of FIG. 5. It is a figure which shows the modification of the structure shown in FIG. It is a block diagram of the semiconductor integrated circuit device by another Example of this invention. FIG. 30 is a diagram for describing a configuration example of a phase comparison unit of the phase comparison circuit 31 illustrated in FIG. 29. FIG. 31 is a timing chart for explaining the operation of the phase comparison unit of FIG. 30. FIG. 30 is a circuit diagram illustrating a configuration example of the high-accuracy delay circuit 12 in FIG. 29. FIG. 30 is a circuit diagram illustrating a configuration example of a high-precision dummy delay circuit 13 in FIG. 29. FIG. 30 is a circuit diagram illustrating a configuration example of a high-accuracy phase comparison circuit 14 in FIG. 29. FIG. 35 is a timing chart for explaining the operation of the high-accuracy phase comparison circuit 14 of FIG. 34. FIG. 30 is a circuit diagram illustrating another configuration example of the high-accuracy delay circuit 12 of FIG. 29. FIG. 30 is a circuit diagram illustrating another configuration example of the high-precision dummy delay circuit 13 of FIG. 29. FIG. 30 is a circuit diagram illustrating another configuration example of the high-accuracy phase comparison circuit 14 of FIG. 29. FIG. 39 is a timing chart for explaining the operation of the high-accuracy phase comparison circuit 14 of FIG. 38. It is a figure which shows the structure of the synchronous DRAM as an example to which the semiconductor integrated circuit device according to the present invention is applied. 41 is a timing chart for explaining the operation of the synchronous DRAM of FIG. 40. FIG. FIG. 41 is a block diagram schematically showing a main configuration of the synchronous DRAM of FIG. 40. It is a figure for demonstrating one structural example of the output circuit (data output buffer circuit) in the semiconductor integrated circuit device which concerns on this invention. FIG. 29 is a diagram showing a configuration example of a dummy output circuit shown in FIG. 28. It is a figure which shows the conventional variable delay circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 1st DLL circuit 10 2nd DLL circuit 12 High precision delay circuit 13 High precision dummy delay circuit 14 High precision phase comparison circuit 21 Input circuit 30 Dividing circuit 31 Phase comparison circuit 32 Delay control circuit 33 Delay circuit 34 Dummy delay Circuit 41 Dummy output circuit 42 Dummy input circuit 43 Dummy circuit

Claims (25)

A first DLL circuit for delaying an input clock signal; and a second DLL circuit connected to the output side of the first DLL circuit and capable of controlling the delay with higher accuracy than the first DLL circuit. The phase comparison between the first and second DLL circuits is operated independently, and the delay amount control of the second DLL circuit is made dependent on the operation of the first DLL circuit, so that a predetermined phase with respect to the input clock signal is obtained. A delay is provided in the first and second DLL circuits to output an output clock signal having a relationship;
If the accuracy of the first DLL circuit is td, the second DLL circuit can control the delay amount in the range including ± td, and the phase comparison result of the first DLL circuit is out of the range of ± td. In this case, the first DLL circuit outputs a reset signal to the second DLL circuit, sets the delay amount of the second DLL circuit to a center value, and controls the delay amount in the first DLL circuit. A semiconductor integrated circuit device.   The second DLL circuit is reset by receiving a reset signal from the first DLL circuit when the first DLL circuit controls the delay amount, and the input clock for phase comparison by the first DLL circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein when the signal and the output clock signal are in phase, the second DLL circuit is in a state where the delay amount can be controlled. 2. The semiconductor integrated circuit according to claim 1, wherein the second DLL circuit has a delay circuit, and the center value of the delay amount of the second DLL circuit is the center of the range of the delay amount that can be controlled by the delay circuit. Circuit device.   Each of the first and second DLL circuits has a first path through which an input clock signal passes and a second path for phase comparison with the first path. The second path is the second DLL circuit. 3. The semiconductor integrated circuit device according to claim 2, further comprising a dummy circuit having a delay amount equal to the delay amount when reset.   The second DLL circuit has first and second delay elements having different delay amounts. The second delay element has a larger delay amount than the first delay element, and the difference between the first and second delay amounts. 2. The semiconductor integrated circuit device according to claim 1, wherein the accuracy of the second DLL circuit.   The first DLL circuit performs phase comparison between a signal obtained by delaying the first clock signal obtained from the input clock signal by the third delay element and the second clock signal obtained from the output clock signal; and The phase comparison between the first clock signal and the second clock signal delayed by the fourth delay element is performed, and the phase comparison result between the input clock signal and the output clock signal is output. 2. The semiconductor integrated circuit device according to 1.   The first DLL circuit has first and second flip-flops, and the first flip-flop inputs the signal delayed by the third delay element and the second clock signal to the set and reset terminals, respectively. The second flip-flop inputs the signal delayed by the fourth delay element and the first clock signal to the set and reset terminals, respectively, and outputs the phase comparison result by the combination of the first and second flip-flops. The semiconductor integrated circuit device according to claim 6.   The first and second flip-flops have first and second NAND gates, respectively. The first input of the first NAND gate is a set terminal and the second input is connected to the output of the second NAND gate. 7. The output Q is obtained, and the first input of the second NAND gate is connected to the output of the reset terminal and the second input is connected to the output of the first NAND gate. Semiconductor integrated circuit device.   The first and second flip-flops have first and second NAND gates, respectively, the second input of the first NAND gate is a set terminal, and the first input is connected to the output of the second NAND gate. 7. The output Q is obtained, and the second input of the second NAND gate is connected to the reset terminal and the first input is connected to the output of the first NAND gate to become an output / Q. Semiconductor integrated circuit device.   Each of the first and second NAND gates has first and second P-channel transistors and first and second N-channel transistors, the source of the first P-channel transistor is a first power source, and the gate is The first input and drain are connected to the output, the source of the second P-channel transistor is connected to the first power supply, the gate is connected to the second input and the drain is connected to the output, and the source of the first N-channel transistor is connected to the first The drain and gate of the second N-channel transistor are connected to the first input, the drain is connected to the output, the source of the second N-channel transistor is the second power supply, the gate is the second input, and the drain is the first N-channel The semiconductor integrated circuit device according to claim 8, wherein the semiconductor integrated circuit device is connected to a source of the transistor.   7. The semiconductor integrated circuit device according to claim 6, wherein the third and fourth delay elements have the same circuit as a circuit constituting one stage of the delay elements of the first DLL circuit.   2. The semiconductor integrated circuit device according to claim 1, wherein each of the first and second DLL circuits has a delay circuit, and the delay circuit is configured by a combination of logic elements.   The first and second delay elements are logic elements, and the fan-outs of the logic elements of the first delay circuit and the logic elements of the second delay circuit are made different so that the delay amounts of the first and second delay elements are different. 6. The semiconductor integrated circuit device according to claim 5, wherein the difference is formed.   The first and second delay elements are formed of logic elements, and the first and second delay elements are applied with different power supply voltages applied to the logic elements of the first delay circuit and the logic elements of the second delay circuit, respectively. 6. The semiconductor integrated circuit device according to claim 5, wherein a difference in delay amount is formed.   2. The semiconductor integrated circuit device according to claim 1, wherein the second DLL circuit includes a delay circuit, and the delay circuit includes at least one of a capacitor and a resistor.   2. The semiconductor integrated circuit device according to claim 1, wherein the second DLL circuit includes a delay circuit having at least a capacitor, and the delay amount is controlled by changing a capacitance of the capacitor.   2. The semiconductor integrated circuit device according to claim 1, wherein the second DLL circuit includes a delay circuit having at least a resistor, and the delay amount is controlled by changing a resistance value of the resistor.   2. The semiconductor integrated circuit device according to claim 1, wherein the second DLL circuit includes a delay circuit having a capacitor and a resistor, and the delay amount is controlled by changing a capacitance value of the capacitor and a resistance value of the resistor. . The second DLL circuit has a delay control circuit having a shift register, and a center value of a delay amount of the second DLL circuit is a center within a range of the delay amount that can be controlled by the shift register. The semiconductor integrated circuit device according to claim 1.   2. The semiconductor according to claim 1, wherein each of the first and second DLL circuits has a delay circuit, and the delay circuit of the second DLL circuit can adjust a range larger than the accuracy of the first DLL circuit. Integrated circuit device.   The first DLL circuit includes a first control unit that determines a delay amount such that the input clock signal and the output clock signal have a predetermined phase difference, and the second DLL circuit includes the input clock signal and the output clock signal. The semiconductor integrated circuit device according to claim 1, further comprising: a second control unit that determines a delay amount such that and a predetermined phase difference is obtained.   The second DLL circuit sets a comparator that determines which of the n phase differences set in advance is equivalent to the phase difference between the input clock signal and the output clock signal, and sets a delay amount according to the comparison result 2. The semiconductor integrated circuit device according to claim 1, further comprising a delay circuit. 22. The semiconductor integrated circuit device according to claim 21 , wherein n delay stages of the delay circuit can be set. The comparator has a plurality of delay units having the same configuration as the delay circuit, compares the phases of the delay amount is different Do Ri, the input and output clock signal and the output clock signal is delayed by the delay of each delay unit 23. The semiconductor integrated circuit device according to claim 22 , wherein:   2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a memory and outputs data from the memory to the outside in synchronization with an output clock signal.

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