JP4327474B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to a semiconductor device used in an electronic apparatus such as a computer, and more particularly to a semiconductor device including an electrically rewritable semiconductor nonvolatile memory and a manufacturing method thereof.
[0002]
[Prior art]
FIG. 9 shows a cross-sectional view of a semiconductor device equipped with an electrically rewritable semiconductor nonvolatile memory according to the prior art (see, for example, Patent Document 1).
[0003]
An N-type (as the second conductivity type) source region 102 and an N-type drain region 103 are provided on the surface of the P-type (as the first conductivity type) silicon substrate 101 via the channel formation region 109. A gate oxide film 104, which is a silicon oxide film, is formed on the surface of the P-type silicon substrate 101. In particular, a tunnel oxide which is a thin film having a thickness of about 100 mm on the N-type drain region 103 is formed. A film 105 is formed. A floating gate electrode 106 is provided on the channel region 109 via the gate insulating film 104 so as to partially overlap the N-type source region 102 and the N-type drain region 103. The floating gate electrode 106 is strongly capacitively coupled to the control gate electrode 108 provided via the control insulating film 107. In the vicinity of the memory cell, a LOCOS oxide film 110 is formed, which is an oxide film thicker than the above-described oxide film, and for isolating electrical elements in the P-type silicon substrate 101.
[0004]
When a negative voltage of about minus 20 V is applied to the control gate electrode 108, a tunnel current flows through the silicon oxide film 105 of 100 Å, and electrons are injected from the N-type drain region 103 into the floating gate electrode 106. Further, when a positive voltage of about +20 V is applied to the control gate electrode 106, a tunnel current flows through the silicon oxide film 105 of 100 Å, and electrons are injected from the floating gate electrode 106 into the N-type drain region 103. .
[0005]
[Patent Document 1]
Japanese Examined Patent Publication No. 2-58788 (page 6 and FIG. 1 (b))
[0006]
[Problems to be solved by the invention]
However, in a semiconductor device equipped with an electrically rewritable semiconductor nonvolatile memory according to the prior art, the floating gate electrode 106 is tunneled over the N-type drain region 103 provided in the surface region of the P-type semiconductor substrate 101. It is formed through an oxide film 105. Even when the semiconductor device is used (when it is not electrically rewritten), a potential difference is generated between the N-type drain region 103 and the floating gate electrode 106 provided thereon via the tunnel oxide film 105. This potential difference is not so large as to inject carriers into the floating gate electrode 106 or release carriers from the floating gate electrode 106 in a short time.
[0007]
However, although this potential difference is slight, carriers are injected into the floating gate electrode 106 or carriers are released from the floating gate electrode 106. Therefore, when this semiconductor device is used for a long period of time, this potential difference causes a change in the carrier amount of the floating gate electrode 106, and there is a problem that stored information cannot be maintained for a long period of time.
[0008]
In a semiconductor device equipped with an electrically rewritable semiconductor nonvolatile memory according to the prior art, information is electrically rewritten when a tunnel current flows through the tunnel oxide film 105. When carriers pass through tunnel oxide film 105, tunnel oxide film 105 deteriorates. When a certain amount of carriers pass through the tunnel oxide film 105, the tunnel oxide film 105 deteriorates, and the storage information cannot be electrically rewritten due to this deterioration. Therefore, the number of times of rewriting stored information is limited due to deterioration of the tunnel oxide film 105.
[0009]
The present invention solves the above-described problems, and provides a semiconductor device including an electrically rewritable semiconductor nonvolatile memory that can maintain stored information for a long period of time and has an improved number of times of rewriting stored information, and a method for manufacturing the same. For the purpose.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has the following configuration.
[0011]
A source region and a drain region of a second conductivity type provided on the surface of the semiconductor substrate of the first conductivity type and spaced from each other, and a first gate insulating film above the source region, the drain region and the channel region. In a semiconductor device comprising a provided floating gate electrode and a control gate electrode capacitively coupled via the floating gate electrode and a second gate insulating film, a space is provided between the drain region and the floating gate electrode. .
[0012]
When there is a space between the drain region and the floating gate electrode, when memory information is read, carriers are injected from the drain region to the floating gate electrode even if a potential difference occurs between the drain region and the floating gate electrode, or Carriers are not released from the floating gate electrode to the drain region.
[0013]
Also, if there is a space between the drain region and the floating gate electrode, carriers can be injected from the drain region to the floating gate electrode without using a tunnel oxide film, and carriers can be released from the floating gate electrode to the drain region. It becomes possible to do.
[0014]
In the present invention, in order to inject carriers from the drain region to the floating gate electrode and to release carriers from the floating gate electrode to the drain region, the floating gate electrode has a structure having a mechanism that is displaced to the drain region side. To do.
[0015]
With this configuration, the floating gate electrode is in contact with the drain region only when carriers are injected and discharged, and when the floating gate electrode is in contact with the drain region and carriers are not injected and discharged, there is a sufficient interval. I can leave.
[0016]
A floating gate electrode is a discharge generated by applying a positive or negative voltage to the drain region with reference to the floating gate electrode, and the same effect can be achieved even in a configuration having a mechanism for emitting or absorbing carriers. It is.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. Example 1 will be described with reference to FIG.
[0018]
6 shows an N-type source region 2 and an N-type tunnel drain region 3 formed on a P-type silicon substrate 1, and a floating gate electrode provided on the channel region 9 with a first floating gate oxide film 4 interposed therebetween. 6 is a cross-sectional view of an electrically rewritable nonvolatile memory according to the present invention comprising a control gate electrode 8 capacitively coupled through a floating gate electrode 6 and a control gate oxide film 7 thereof.
[0019]
The semiconductor device is characterized by having a space 11 between the N-type tunnel drain region 3 and the floating gate electrode 6.
[0020]
A method for manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. The surface of the P-type silicon substrate 1 is oxidized to a thickness of 620 mm, and a nitride film is deposited on the oxide film surface by CVD. The nitride film is patterned for the LOCOS oxidation isolation region, and an 8000A oxide film is grown to form the LOCOS oxidation isolation region 10.
[0021]
Photolithography, the photoresist was subjected to 6.0E11cm ^-2 ion implantation into the channel region 9 of BF ₂ at 60KeV cell transistors as a mask, 90 KeV the N-type tunnel drain region 3 and the N-type source in region 2 As Then, 7.0E15 cm ⁻² ion implantation is performed (FIG. 1).
[0022]
Next, 4000 Å of polysilicon film 12 is deposited on the substrate surface and phosphorus predeposition is performed (FIG. 2). Thereafter, the polysilicon film 12 is etched using the photoresist as a mask to form the floating gate electrode 6 (FIG. 3).
[0023]
As shown in FIG. 7, the photoresist 13 is patterned using a photolithography technique so that a region 14 without photoresist is formed in a part of the periphery of the floating gate electrode 6 formed of polysilicon. If the silicon substrate is placed in the BHF solution in this state, isotropic etching starts from the floating gate oxide film portion not covered with the photoresist 13, and the floating gate oxide film 4 below the floating gate electrode 6 may be etched. it can. By this method, a space 11 can be formed in the silicon oxide film between the floating gate electrode 6 and the N-type tunnel drain region 3 (FIG. 4).
[0024]
A tunnel oxide film 5 exists between the space 11 formed under the floating gate electrode 6 and the N-type tunnel drain region 3. The tunnel oxide film 5 is formed so as to have a thickness of 100 mm because a tunnel current flows.
[0025]
The floating gate oxide film 4 is sputtered so that the opening of the floating gate oxide film 4 around the floating gate electrode 6 is filled. The floating gate oxide film 4 formed by sputtering other than the opening of the floating gate oxide film 4 is etched with a BHF solution using a photolithography technique.
[0026]
Oxidation is performed to form a 250-inch control gate oxide film 7. The polysilicon film 12 is deposited by 4000 mm, and phosphorus predeposition is performed (FIG. 5). Thereafter, the polysilicon film 12 is etched using the photoresist as a mask to form the control gate electrode 8 (FIG. 6).
[0027]
The semiconductor device of this embodiment can be manufactured through the above steps. In this embodiment, the floating gate electrode 6 can be displaced to the N-type tunnel drain region 3 side, carriers are emitted from the N-type tunnel drain region 3 and the floating gate electrode 6 absorbs the carriers, or the floating gate electrode 6 It is possible to realize that the floating gate electrode 6 is in contact with the tunnel oxide film 5 only when carriers are emitted from the N 6 and the N-type tunnel drain region 3 absorbs the carriers.
[0028]
Another embodiment 2 will be described with reference to FIG. In Example 2, only the space 11 exists between the N-type tunnel drain region 3 and the floating gate electrode 6 above the N-type tunnel drain region 3. The silicon oxide film as the tunnel oxide film 5 is not substantially left.
[0029]
By using this structure, even if the tunnel oxide film 5 is not used, the floating gate electrode 6 is displaced and directly contacts the N-type tunnel drain region 3, whereby carriers are emitted from the N-type tunnel drain region 3 and the floating gate. It is possible to realize a mechanism in which the electrode 6 absorbs carriers, or carriers are emitted from the floating gate electrode 6 and the N-type tunnel drain region 3 absorbs carriers. The second embodiment is an embodiment of a semiconductor device in which an electrically rewritable nonvolatile memory is mounted without using a tunnel oxide film.
[0030]
The manufacturing process of the semiconductor device of this embodiment is almost the same as that of the first embodiment. The difference is that the etching time in the BHF solution is increased so that the tunnel oxide film 5 formed of the silicon oxide film between the N-type tunnel drain region 3 and the floating gate electrode 6 is entirely etched. .
[0031]
In the second embodiment, the carrier is emitted from the N-type tunnel drain region 3 and the floating gate electrode 6 absorbs the carrier, or the carrier is emitted from the floating gate electrode 6 and the N-type tunnel drain region 3 absorbs the carrier. Can be performed by discharging. A discharge is generated by applying a negative potential to the N-type tunnel drain region 3 with respect to the floating gate electrode 6, electrons are emitted from the N-type tunnel drain region 3, and the electrons are absorbed by the floating gate electrode 6. . On the other hand, when a positive potential is applied to the N-type tunnel drain region 3 with respect to the floating gate electrode 6, a discharge is generated, and electrons are emitted from the floating gate electrode 6, and the electrons enter the N-type tunnel drain region 3. Absorbed.
[0032]
【The invention's effect】
In the semiconductor device of the present invention, even when a potential difference occurs between the tunnel drain region and the floating gate electrode in use, carriers are discharged from the tunnel drain region due to this potential difference, and the floating gate electrode absorbs the carriers, or the floating gate Carriers are released from the electrode and the tunnel drain region does not absorb the carriers. Therefore, stored information can be maintained for a longer period than a conventional semiconductor device.
[0033]
In the semiconductor device of the present invention, even if there is no tunnel insulating film between the floating gate electrode and the tunnel drain region, the floating gate electrode and the tunnel drain region are directly contacted or discharged from the tunnel drain region by discharge. The carrier can be absorbed by the floating gate electrode, or the carrier discharged from the floating gate electrode can be absorbed by the tunnel drain region. Therefore, the tunnel insulating film is unnecessary, and the problem that the number of times of rewriting stored information is limited by the deterioration of the tunnel insulating film is solved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a step I in Example 1. FIG.
2 is a sectional view showing a step II in Example 1. FIG.
3 is a cross-sectional view showing a process III in Example 1. FIG.
4 is a cross-sectional view showing a process IV in Example 1. FIG.
5 is a cross-sectional view showing a process V in Example 1. FIG.
6 is a cross-sectional view (Embodiment 1) of an electrically rewritable nonvolatile memory according to the present invention. FIG.
FIG. 7 is a plan view before etching for space formation.
FIG. 8 is a cross-sectional view (Embodiment 2) of an electrically rewritable nonvolatile memory according to the present invention.
FIG. 9 is a cross-sectional view of an electrically rewritable nonvolatile memory according to the prior art.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 N-type source region 3 N-type tunnel drain region 4 Floating gate oxide film 5 Tunnel oxide film 6 Floating gate electrode 7 Control gate oxide film 8 Control gate electrode 9 Channel region 10 Locos oxidation isolation region 11 Space 12 Poly Silicon film 13 Photoresist 14 Non-photoresist region 101 P-type silicon substrate 102 N-type source region 103 N-type tunnel drain region 104 Floating gate oxide film 105 Tunnel oxide film 106 Floating gate electrode 107 Control gate oxide film 108 Control gate electrode 109 Channel Region 110 Locos oxidation separation region

Claims (1)

Forming a second conductivity type source region and a drain region provided on the surface of the first conductivity type semiconductor substrate at a distance from each other;
Forming a floating gate electrode via a floating gate oxide film on a part of the source region and a part of the drain region and a channel forming region between the source region and the drain region;
Forming a photoresist so that a region without photoresist is formed in a part of the periphery of the floating gate electrode;
By isotropically etching from the floating gate oxide film portion not covered with the photoresist, a space that overlaps only with the drain region is formed immediately below the floating gate electrode and is covered with the photoresist. Forming an opening in the floating gate oxide in a non-region;
To fill the opening in the oxide film, a step of sputtering the oxide film, then removed by etching the oxide film formed on other than the opening,
Forming a control gate electrode capacitively coupled to the floating gate electrode through a control gate oxide film.

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