JP4306330B2 - Electro-optical device and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention belongs to a technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus such as a liquid crystal projector including the electro-optical device.
[0002]
[Background]
In this type of liquid crystal device or the like, for example, liquid crystal is sandwiched between an element substrate and a counter substrate. On the element substrate, there are provided a pixel electrode and a thin film transistor (hereinafter referred to as “TFT” as appropriate) connected to each of the pixel electrodes, and a scanning line and a data line connected to each of the TFTs. Signal lines. On the other hand, a counter electrode is provided on the counter electrode so as to face the pixel electrode. During the operation, a counter electrode potential is supplied to the counter electrode. The supply of the counter electrode potential is usually performed from the counter electrode potential line provided on the element substrate via the vertical conduction material provided between the two substrates. In parallel with the supply of the counter electrode potential, an image signal potential is supplied as an image signal to the pixel electrode via each TFT. Then, liquid crystal driving by an active matrix driving method is performed by a liquid crystal driving voltage applied between these electrodes.
[0003]
On the other hand, in this type of liquid crystal device, in order to display a higher quality image, each pixel electrode is provided with a storage capacitor in parallel with the liquid crystal capacitor in order to improve charge retention characteristics.
[0004]
[Problems to be solved by the invention]
In this type of electro-optical device, in order to display a brighter image, the area occupied on the substrate of various signal lines and storage capacitors is made smaller, and light that actually contributes to image display in each pixel is transmitted or reflected. It is generally desired to increase the aperture ratio of each pixel by increasing the light transmission region that is an emission region. In addition, it is generally desired to improve the driving frequency and to save power in order to increase the definition of the display image. In order to achieve these objects, it is necessary to reduce the pixel pitch or the wiring pitch, and in particular to reduce the wiring width of various wirings.
[0005]
However, if the capacitor line constituting the storage capacitor is also finely formed, the wiring resistance of the capacitor line increases and the wiring time constant increases. As a result, there is a technical problem that potential fluctuations occur in the capacitance line that is originally assumed to be a predetermined potential, which may eventually cause crosstalk or ghosting in the display image. Furthermore, since the capacitance line is wired in a limited area on the substrate, even if the increase in the wiring resistance is suppressed, other various types that come closer in three dimensions with miniaturization and miniaturization. The parasitic capacitance with the signal line becomes relatively large. For this reason, problems such as crosstalk may become more serious.
[0006]
In order to cope with this, it is not unimaginable to reduce the resistance of the capacitance line, that is, to reduce the wiring time constant by increasing the film thickness of the wiring while maintaining the wiring width of the capacitance line. However, it is difficult to say that this is a sufficient measure that can meet the general request to prevent the image quality problems such as crosstalk while miniaturizing and narrowing each component in the apparatus as described above.
[0007]
The present invention has been made in view of the above problems, and an electro-optical device capable of preventing image quality problems such as crosstalk by reducing the time constant of a capacitance line, and the electro-optical device It is an object to provide an electronic device including the above.
[0008]
[Means for Solving the Problems]
  In order to solve the above problems, the electro-optical device of the present invention providesAn electro-optical material is sandwiched between a pair of element substrates and a counter substrate, a counter electrode having a predetermined potential is provided on the counter substrate, and a plurality of electrodes disposed on the element substrate so as to face the counter electrode. A pixel electrode; a plurality of signal lines and electronic elements for supplying image signals to the plurality of pixel electrodes; a capacitor line constituting a storage capacitor connected to the plurality of pixel electrodes; the element substrate; A counter electrode potential line for supplying the predetermined potential to the counter electrode via a vertical conduction member disposed between the substrates, and the counter electrode potential line and the capacitor line on the element substrate. An electro-optical device in which an inter-wiring capacity is constructed, wherein the inter-wiring capacity is formed of a part of the counter electrode potential line, or is extended from the counter electrode potential line, or the counter electrode potential First connected to the line An electric layer and a second conductive layer made of a part of the capacitive line, or extended from the capacitive line or connected to the capacitive line, are arranged opposite to each other on the element substrate via a dielectric film. The counter electrode potential line and the first conductive layer are connected via one contact hole, and the capacitor line and the second conductive layer are connected via another contact hole. And are connected.
[0009]
According to the electro-optical device of the present invention, during the operation, an image signal is supplied to the pixel electrode by a signal line such as a data line and a scanning line and an electronic element such as a pixel switching TFT. At the same time, a predetermined potential is supplied to the counter electrode via the counter electrode potential line and the vertical conductive material. For example, the vertical conduction members are provided at the four corners on the element substrate, and the counter electrode potential lines are wired so as to pass through the four corners. By supplying these potentials, it is possible to drive an electro-optical material such as liquid crystal sandwiched between both electrodes. At this time, the charge retention characteristic of each pixel electrode is improved by the storage capacitor. Here, in particular, an inter-wiring capacitance is constructed between the counter electrode potential line and the capacitance line on the element substrate. All of these wirings have a very high power supply capability on the element substrate. Therefore, by constructing such an inter-wiring capacitance, the time constant in the capacitance line can be reduced very efficiently.
[0010]
Therefore, even if the capacitor line is formed finely, it is possible to effectively suppress an increase in the wiring time constant, and potential fluctuations in the capacitor line scheduled to be fixed to the ground potential or the counter electrode potential can be prevented. Remarkably reduced. As a result, it is possible to finally reduce crosstalk, ghost, etc. in the display image, and display a high-quality image.
[0012]
  Furthermore, according to the electro-optical device of the invention,The inter-wiring capacitance is formed, for example, by disposing a first conductive layer connected to the counter electrode potential line and a second conductive layer connected to the capacitor line through a dielectric film. Alternatively, the first conductive layer made of a part of the counter electrode potential line and the second conductive layer made of a part of the capacitor line are arranged to face each other with a dielectric film on the element substrate. In any case, the time constant in the capacitor line can be lowered very efficiently by constructing the inter-wiring capacitance between the counter electrode potential line and the capacitor line having a very high power supply capability on the element substrate.
[0014]
  If configured like the electro-optical device of the present invention,By interposing the conductive layer constituting the counter electrode potential line and the first conductive layer different from the conductive layer, and the conductive layer constituting the capacitance line and the second conductive layer different from each other, an interwiring capacitance can be constructed. Therefore, for example, it is possible to construct an inter-wiring capacitance by overlapping with a region where the counter electrode potential line or the capacitance line is wired in a plan view, and the capacitance value can be increased. In addition, for example, even if the counter electrode potential line and the capacitor line are formed of the same conductive layer, the wiring capacity can be constructed from two conductive layers different from the same conductive layer, so that both wirings are most excellent in conductivity. It is also possible to form the same conductive layer.
[0015]
  In order to solve the above-described problem, the electro-optical device of the present invention includes a counter electrode having a predetermined potential on the counter substrate, in which an electro-optical material is sandwiched between the pair of element substrates and the counter substrate. A plurality of pixel electrodes disposed opposite to the counter electrode on the element substrate; a plurality of signal lines and electronic elements for supplying image signals to the plurality of pixel electrodes; and the plurality of pixel electrodes A capacitor line constituting the storage capacitor, and a counter electrode potential line for supplying the predetermined potential to the counter electrode via a vertical conductive material disposed between the element substrate and the counter substrate, An electro-optical device in which an inter-wiring capacitance is constructed between the counter electrode potential line and the capacitance line on the element substrate, wherein the inter-wiring capacitance includes a part of the counter electrode potential line. Or extended from the counter electrode potential line A first conductive layer formed or connected to the counter electrode potential line, a second conductive layer formed of a part of the capacitor line, extended from the capacitor line, or connected to the capacitor line; Is constructed so as to be opposed to each other via a dielectric film on the element substrate, and at least one of a pixel potential side capacitor electrode and a fixed potential side capacitor electrode constituting the storage capacitor is the first electrode It is characterized by comprising one conductive layer or the same layer as the second conductive layer.
[0016]
According to this aspect, since the storage capacitor and the inter-wiring capacitor are at least partially made of the same conductive layer, it is possible to simplify the laminated structure on the element substrate and the manufacturing process.
[0017]
In this aspect, the inter-wiring capacitor and the storage capacitor may be configured to have the same stacked structure formed simultaneously in the same process at the time of manufacture.
[0018]
If comprised in this way, it will become possible to achieve remarkable simplification of the laminated structure on the element substrate and the manufacturing process.
[0019]
In another aspect of the electro-optical device of the present invention, the counter electrode potential line and the capacitor line are formed of the same conductive layer formed simultaneously in the same process at the time of manufacture.
[0020]
According to this aspect, it is possible to simplify the laminated structure and the manufacturing process on the element substrate. In particular, both wirings can be formed from the same conductive layer having the best conductivity.
[0021]
In another aspect of the electro-optical device of the present invention, an image display region in which the plurality of pixel electrodes are arranged is defined on the element substrate, and a peripheral region is defined around the image display region, The interwiring capacitance is at least partially disposed in the peripheral region.
[0022]
According to this aspect, the inter-wiring capacitance can be constructed using the peripheral region. It should be noted that the area where the inter-wiring capacitance is arranged is more advantageous as it is closer to the image display area, which is the area where the capacitance line functions for the storage capacitor, in the peripheral area.
[0023]
In the aspect in which the inter-wiring capacitance is arranged in the peripheral region, the inter-wiring capacitance may be arranged in a region of the peripheral region facing the counter substrate.
[0024]
With this configuration, it is possible to construct the interwiring capacitance in an area relatively close to the image display area in the peripheral area.
[0025]
In this case, furthermore, the element substrate and the counter substrate are bonded together by a sealing material along their edges in the peripheral region, and the inter-wiring capacitance is at least partially in the peripheral region. You may comprise so that it may be arrange | positioned in the existing seal | sticker area | region.
[0026]
If comprised in this way, the capacity | capacitance between wiring can be constructed | assembled in the area | region very close to an image display area among peripheral areas using a seal | sticker area | region.
[0027]
In this case, a plurality of dummy patterns are further provided on the element substrate for maintaining a gap between the element substrate and the counter substrate at a predetermined value, and the interwiring capacitance is planar on the element substrate. In view of the above, it may be configured such that it is divided into a plurality of portions corresponding to the gaps of the plurality of dummy patterns or provided in a comb shape.
[0028]
If comprised in this way, using the dummy pattern, while making it possible to photocure the sealing material which consists of photocurable resin, and maintaining the gap between board | substrates to a predetermined value, Corresponding to the gap, a plurality of divided or comb-like interwiring capacitances can be constructed.
[0029]
In the aspect in which the inter-wiring capacitance is disposed in the peripheral region described above, a peripheral drive circuit that drives the plurality of signal lines is disposed in a region along one side or a plurality of sides of the element substrate in the peripheral region. The inter-wiring capacitance may be arranged at least partially in a region along another side of the peripheral region different from the one side or the plurality of sides.
[0030]
By configuring in this way, among the four regions along the four sides of the peripheral region, one or a plurality of regions that can ensure a wide region for creating the inter-wiring capacitance because the peripheral drive circuit is not arranged, The capacitance between the wirings can be built in, and the capacitance value can be increased relatively easily.
[0031]
In the aspect in which the interwiring capacitance is disposed in the peripheral region described above, a plurality of external circuit connection terminals including the terminal for the counter electrode potential line are disposed in a region along one side of the element substrate in the peripheral region. The inter-wiring capacitance may be arranged at least partially in a region along the other side of the peripheral region facing the one side.
[0032]
If configured in this way, of the four regions along the four sides of the peripheral region, the external circuit connection terminal is not arranged, so that one or a plurality of regions that can secure a wide region for creating the inter-wiring capacitance are provided. The capacitance between the wires can be built in, and the capacitance value can be increased relatively easily.
[0033]
In the aspect in which the inter-wiring capacitance is arranged in the peripheral region described above, the plurality of signal lines cross the plurality of data lines to which the image signal is supplied and a plurality of the scanning signals are supplied. The electronic element includes a thin film transistor for pixel switching that supplies the image signal from the data line to the pixel electrode in response to the supply of the scanning signal.
[0034]
According to this aspect, during the operation, the scanning signal is supplied from the scanning line to the thin film transistor, and the image signal supplied from the data line is supplied to the pixel electrode via the thin film transistor in response to this. As a result, TFT active matrix driving capable of displaying a high-quality image is possible by the inter-wiring capacitance constructed in the peripheral region.
[0035]
In this aspect, the capacitance value of the interwiring capacitance may be configured to be equal to or greater than the total capacitance value of the plurality of data lines.
[0036]
With this configuration, when the AC inversion drive is used to prevent deterioration of electro-optical materials such as liquid crystals and reduce flicker, the potential fluctuation of the capacitor line due to the potential inversion of the data line is changed. It can be reduced to about half or less. Preferably, the potential value of the data line during the inversion drive is increased by increasing the capacitance value of the interwiring capacitance to, for example, several times to several tens of times or several tens of times the total capacitance value of the plurality of data lines. It is possible to suppress the potential fluctuation of the capacitor line due to the above to one-tenth to one-tenth or several tenths of the potential fluctuation of the data line.
[0037]
In order to solve the above-described problems, an electronic apparatus according to the present invention includes the electro-optical device according to the present invention described above (including various aspects thereof).
[0038]
According to the electronic apparatus of the present invention, since the electro-optical device of the present invention described above is included, a projection display device (liquid crystal projector), a liquid crystal television, a mobile phone, and an electronic notebook that can display a high-quality image. Various electronic devices such as a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, a touch panel can be realized.
[0039]
Such an operation and other advantages of the present invention will become apparent from the embodiments described below.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the electro-optical device of the present invention is applied to a TFT active matrix driving type liquid crystal device.
[0041]
(First embodiment)
First, the overall configuration of the first embodiment according to the electro-optical device of the invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view of the electro-optical device when the TFT array substrate is viewed from the side of the counter substrate together with the components formed thereon, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG. It is. Here, a TFT active matrix driving type liquid crystal device with a built-in driving circuit, which is an example of an electro-optical device, is taken as an example.
[0042]
1 and 2, in the electro-optical device according to the first embodiment, the TFT array substrate 10 and the counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material provided in a seal region 52a located around the image display region 10a. 52 are bonded to each other.
[0043]
The sealing material 52 is made of, for example, a photo-curing resin, a thermosetting resin, or the like for bonding both substrates, and after being applied on the TFT array substrate 10 in the manufacturing process, it is cured by ultraviolet irradiation, heating, or the like. Is. Further, in the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance (inter-substrate gap) between the TFT array substrate 10 and the counter substrate 20 to a predetermined value is dispersed.
[0044]
In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing are provided on one side of the TFT array substrate 10. A scanning line driving circuit 104 for driving the scanning line by supplying a scanning signal to the scanning line at a predetermined timing is provided along two sides adjacent to the one side.
[0045]
Needless to say, if the delay of the scanning signal supplied to the scanning line is not a problem, the scanning line driving circuit 104 may be provided on only one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a.
[0046]
On the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting the scanning line driving circuits 104 provided on both sides of the image display region 10a. Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the TFT array substrate 10 and the counter substrate 20.
[0047]
In addition, vertical conduction members 106 that function as vertical conduction terminals between the two substrates are disposed at the four corners of the counter substrate 20. On the other hand, the TFT array substrate 10 is provided with a vertical conduction terminal in a region facing these four corner portions. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.
[0048]
In FIG. 2, on the TFT array substrate 10, an alignment film is formed on the pixel electrode 9a after the pixel switching TFT, the scanning line, the data line and the like are formed. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.
[0049]
In addition to the data line driving circuit 101, the scanning line driving circuit 104, and the like, the image signal on the image signal line is sampled and supplied to the data line on the TFT array substrate 10 shown in FIGS. Sampling circuit, precharge circuit for supplying a precharge signal of a predetermined voltage level to a plurality of data lines in advance of an image signal, for inspecting the quality, defects, etc. of the electro-optical device during production or at the time of shipment An inspection circuit or the like may be formed.
[0050]
In the first embodiment, in particular, among the peripheral areas of the image display area 10a, the inter-wiring capacitance is included in an area along one side of the image display area 10a where the data line driving circuit 101 and the scanning line driving circuit 104 are not arranged. It is characterized by being formed. This point will be described in detail later.
[0051]
Next, the configuration in the image display region 10a of the electro-optical device according to the first embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms the image display region 10a of the electro-optical device.
[0052]
In FIG. 3, a pixel electrode 9 a and a TFT 30 for controlling the switching of the pixel electrode 9 a are formed in a plurality of pixels formed in a matrix that constitutes the image display region of the electro-optical device according to the present embodiment. The data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data line 6a may be supplied line-sequentially in this order, but in the present embodiment, the image signals S1, S2,. The image data are serially / parallel-developed into a simple image signal and can be supplied from the N image signal lines 115 to the N data lines 6a adjacent to each other for each group.
[0053]
In the peripheral area outside the image display area, one end (the lower end in FIG. 3) of the data line 6 a is connected to the switching circuit element 202 constituting the sampling circuit 301. The switching circuit element may be an n-channel TFT as shown in the figure, or a p-channel TFT. Further, a complementary TFT or the like can be applied (hereinafter, the switching circuit element 202 shown in FIG. 3 is referred to as “TFT 202”). In this case, the lower end of the data line 6 a in FIG. 3 is connected to the drain of the TFT 202 via the lead wiring 206, and the image signal line 115 is connected to the source of the TFT 202 via the lead wiring 116. In addition, a sampling circuit driving signal line 114 connected to the data line driving circuit 101 is connected to the gate of the TFT 202. The image signals S1, S2,..., Sn on the image signal line 115 are sampled by the sampling circuit 301 in response to the sampling signal being supplied from the data line driving circuit 101 through the sampling circuit driving signal line 114, It is configured to be supplied to each data line 6a.
[0054]
In this way, the image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, and may be supplied for each of a plurality of adjacent data lines 6a. It may be. In the present embodiment, as shown in FIG. 3, a set of six data lines 6a is set, and an image signal is supplied at a time to this set.
[0055]
Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.
[0056]
Image signals S 1, S 2,..., Sn written in a liquid crystal as an example of an electro-optical material via the pixel electrode 9 a are held for a certain period with the counter electrode formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to the image signal is emitted from the electro-optical device as a whole.
[0057]
In addition, the transmittance of the liquid crystal is determined by the effective value of the applied voltage, and when a DC voltage is applied to the liquid crystal, the composition changes and problems such as so-called image sticking occur. For this reason, in the electro-optical device according to the present embodiment, AC inversion driving is performed to invert the voltage polarity applied to the liquid crystal at a predetermined period. That is, in order to perform AC inversion driving, the voltage polarity of the image signal is inverted every predetermined period such as one horizontal scanning period (one frame) or one field (for example, two frames).
[0058]
In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side with the scanning line 3a, and includes a capacitor line 300 that includes a fixed potential side capacitor electrode and is fixed at a constant potential. The storage capacitor 70 improves the charge retention characteristics of each pixel electrode.
[0059]
On the TFT array substrate 10, the counter electrode potential line 503 is wired so as to pass through the four 0 corners on the TFT array substrate 10, connected to the above-described vertical conduction member 106. Here, a predetermined potential is supplied to the counter electrode 21 via the vertical conduction member 106 and the counter electrode potential line 503. By supplying these potentials, the liquid crystal sandwiched between the pixel electrode 9a and the counter electrode 21 as described above can be driven.
[0060]
Particularly in the present embodiment, as shown in FIG. 3, in the peripheral area of the image display area 10a and at the position facing the data line driving circuit 101 across the image display area 10a, that is, at the upper end of FIG. A wiring capacitance 501 is attached. The inter-wiring capacitor 501 has another conductive layer connected to the counter electrode potential line 503 maintained at a predetermined potential with a conductive layer (first conductive layer 511 described later) connected to the capacitor line 300 as one capacitor electrode. A second conductive layer 512 (to be described later) is used as the other capacitor electrode, and a dielectric film (a dielectric film 75 to be described later) is sandwiched between them. In the inter-wiring capacitor 501, charges corresponding to the difference between the potential of the capacitor line 300 and the potential of the counter electrode potential line 503 are accumulated.
[0061]
Here, the capacitor line 300 and the counter electrode potential line 503 both have a very high power supply capability on the TFT array substrate 10. Therefore, by constructing such an inter-wiring capacity, the capacity around the capacity line 300 is appropriately secured, and the time constant of the capacity line 300 itself can be lowered very efficiently.
[0062]
Therefore, even if the capacitor line 300 is finely formed, it is possible to effectively suppress an increase in the wiring time constant, and the potential in the capacitor line 300 that is electrically connected to the constant potential source to be a fixed potential. The fluctuation can be significantly reduced. As a result, it is possible to finally reduce crosstalk, ghost, etc. in the display image, and display a high-quality image. In the more specific configuration of this embodiment described later with reference to FIG. 4, the interwiring capacitor 501 is connected to the capacitor line 300 via the capacitor line connection wiring 505 (see FIG. 4). However, such a detailed configuration will be described later.
[0063]
(Seal area)
Hereinafter, an arrangement configuration of the seal region 52a, various wirings, the inter-wiring capacitance 501 and the like on the TFT array substrate 10, particularly in the peripheral region of the image display region 10a will be described with reference to FIG. Here, FIG. 4 is a plan view of the electro-optical device in which the corner portion of the TFT array substrate 10 in FIG. 1, that is, the region C of FIG. In FIG. 4, only components particularly relevant to the present invention are shown, and other configurations are omitted as appropriate.
[0064]
As shown in FIG. 4, a seal region 52a in which a seal material 52 is disposed is formed in the peripheral region of the image display region 10a. More specifically, the outer periphery of the counter substrate 20 indicated by a dotted line in FIG. 4 is arranged on the inner side of the outer periphery of the TFT array substrate 10, and is on the inner side of the counter substrate 20 and along the outer periphery of the counter substrate 20. The sealing material 52 is disposed in the sealing region 52a, and both the TFT array substrate 10 and the counter substrate 20 are bonded together as described above. The vertical conductive material 106 is disposed at the corner portion (upper right in FIG. 4) of the seal region 52a, and the counter electrode potential line 503 passes through the vertical conductive material 106 and extends along the outer periphery of the seal region 52a. Has been placed.
[0065]
On the other hand, in the peripheral area of the image display area 10a, the capacitor line connection wiring 505 is arranged along the inner periphery of the seal area 52a inside the seal area 52a, that is, on the image display area 10a side. . Here, the capacitor line connection wiring 505 is made of, for example, a metal such as aluminum or a low resistance material such as an alloy, and is formed so as to overlap with the formation region of the scanning line 3a on the plane shown in FIG. Each of the plurality of capacitor lines 300 is connected via a contact hole 507. The detailed configuration and laminated structure of the various wirings including the capacitance line 300 and various components in the image display area 10a will be described in detail later.
[0066]
Here, in the present embodiment, as shown in FIG. 4, inter-wiring capacitors 501 are arranged in a region sandwiched between the counter electrode potential line 503 and the capacitor line connection wiring 505 in the peripheral region of the image display region 10 a. Has been. In other words, the inter-wiring capacitor 501 is arranged so that most of its area is covered with the seal region 52a in a plan view.
[0067]
Here, with reference to the perspective view of FIG. 5, the arrangement configuration of the inter-wiring capacitance 501 will be described. In FIG. 5, the main purpose is to show the arrangement relationship of each component of the inter-wiring capacitance 501, so that it will be described in detail later with reference to FIG. 7 such as the dielectric film 75 and each interlayer insulating film. The illustration of some components is omitted.
[0068]
As shown in FIG. 5, the interwiring capacitor 501 includes a first conductive layer 511 connected to the capacitor line connection wiring 505 and a second conductive layer 512 connected to the counter electrode potential line 503. The conductive layer 511 and the second conductive layer 512 are configured to face each other on the TFT array substrate 10 with a dielectric film 75 (not shown) interposed therebetween. With this configuration, a capacitance is formed between the counter electrode potential line 503 and the capacitor line 300, both of which have high power supply capability, and the capacitor line 300. Capacity is secured appropriately. Therefore, as described above, the time constant of the capacitor line 300 itself can be reduced very efficiently, and the potential fluctuation in the capacitor line 300 can be significantly reduced.
[0069]
In addition, since the wiring layer constituting the capacitor line connection wiring 505 is different from the first conductive layer, the wiring layer of the counter electrode potential line 503 is arranged opposite to the second conductive layer. By further extending the first conductive layer and the second conductive layer, the inter-wiring capacitor 501 is formed so as to overlap the region where the capacitor line connecting wiring 505 or the counter electrode potential line 503 is wired in plan view. It is also possible to increase the capacitance value easily.
[0070]
Further, as shown in FIG. 4, the inter-wiring capacitor 301 having such a configuration includes the data line driving circuit 101, the scanning line driving circuit 104, and the external circuit connection terminal 102 in the peripheral area of the image display area 10a. They are arranged in a region along one side that is not arranged, and are arranged so that most of the area is covered with the seal region 52a in plan view. That is, the inter-wiring capacity 501 is a region where a wide area for forming the inter-wiring capacity 501 can be secured because the peripheral driving circuit as described above is not disposed, and in the past, “dead space”. It is formed by effectively utilizing the area that was. Therefore, it is possible to relatively easily form a relatively large inter-wiring capacitance 501 without newly providing a special region on the TFT array substrate 10. In addition, the inter-wiring capacitor 501 is very advantageous from the viewpoint that it can be formed in a region relatively close to the image display region 10 a that is a region where the capacitor line 300 functions for the storage capacitor 70.
[0071]
Here, in the present embodiment, preferably, the capacitance value of the inter-wiring capacitance 501 is equal to or greater than the total capacitance value of the plurality of data lines 6a, and is, for example, about several to ten times the total capacitance value of the plurality of data lines 6a. Or it is about several tens of times. More specifically, the film thicknesses of the first conductive layer and the second conductive layer, the distance between the first conductive layer and the second conductive layer, and the dielectric film 75 constituting the two upper and lower electrodes of the inter-wiring capacitor 501. The capacitance value of the inter-wiring capacitor 501 increases in proportion to the area on the substrate plane shown in FIG. On the other hand, the total capacitance value of the plurality of data lines 6a is governed mainly by the wiring width of each data line 6a under the condition that the material and film thickness thereof and the number of each data line 6a are constant. It increases in proportion to the total area on the substrate plane. Accordingly, the inter-wiring capacitance 501 in the present embodiment secures a width as much as possible in the arrangement between the counter electrode potential line 503 and the capacitive line connection wiring 505 in the Y direction in FIG. By adjusting the length in the X direction in FIG. 4 in accordance with the wiring width, it is possible to set a sufficient capacity for the total capacity value of the data lines 6a.
[0072]
As described above, by configuring the inter-wiring capacitance 501 to be equal to or greater than the total capacitance value of the plurality of data lines 6a, the AC inversion driving for inverting the voltage polarity applied to the liquid crystal as described above at a predetermined period. Thus, the potential fluctuation of the capacitor line 300 due to the potential inversion of the data line 6a can be suppressed to about half or less of the potential fluctuation of the data line 6a. Furthermore, by increasing the capacitance value of the inter-wiring capacitance 501 from, for example, several times to several tens of times or several tens of times the total capacitance value of a plurality of data lines, the data line 6a in the AC inversion driving is obtained. It is possible to suppress the potential fluctuation of the capacitor line 300 due to the potential inversion to a fraction of one to tenths or a few tenths of the potential fluctuation of the data line 6a.
[0073]
In the present embodiment, the inter-wiring capacitor 501 is preferably arranged as close as possible to the image display area 10a in the Y direction shown in FIG. 4, but the X-direction arrangement position shown in FIG. Is not particularly limited in translating from the arrangement position shown in FIG. 4 in the seal region 52a.
[0074]
Hereinafter, a more specific configuration of the electro-optical device that realizes the above-described circuit operation using the data line 6a, the scanning line 3a, the TFT 30, and the like will be described with reference to FIGS. 6 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed, and FIG. 7 is a cross-sectional view taken along line AA ′ of FIG. In FIG. 7, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.
[0075]
First, the electro-optical device according to the present embodiment includes a transparent TFT array substrate 10 and a transparent counter substrate 20 disposed to face the transparent TFT array substrate 10 as shown in FIG. It has. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.
[0076]
As shown in FIG. 7, the TFT array substrate 10 is provided with a pixel electrode 9a, and an alignment film 16 on which a predetermined alignment process such as a rubbing process has been performed is provided above the pixel electrode 9a. Among these, the pixel electrode 9a is made of a transparent conductive film such as an ITO (Indium Tin Oxide) film. On the other hand, a counter electrode 21 is provided over the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is made of a transparent conductive film such as an ITO film, for example, and the alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example. The liquid crystal layer 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9a is not applied.
[0077]
On the other hand, in FIG. 6, a plurality of the pixel electrodes 9a are provided in a matrix on the TFT array substrate 10 (the outline is indicated by the dotted line portion 9a ′), and the pixel electrodes 9a are respectively arranged at the vertical and horizontal boundaries. A data line 6a and a scanning line 3a are provided along the line. The data line 6a is made of, for example, a metal film such as an aluminum film or an alloy film, and the scanning line 3a is made of, for example, a conductive polysilicon film. Further, the scanning line 3a is disposed so as to face the channel region 1a 'indicated by the hatched region rising to the right in the drawing in the semiconductor layer 1a, and the scanning line 3a functions as a gate electrode. That is, each of the intersections between the scanning lines 3a and the data lines 6a is provided with a pixel switching TFT 30 in which the main line portion of the scanning line 3a is disposed opposite to the channel region 1a ′ as a gate electrode.
[0078]
As shown in FIG. 7, the TFT 30 has an LDD (Lightly Doped Drain) structure, and, as described above, the scanning line 3a functioning as a gate electrode, for example, a polysilicon film is used as a constituent element. The channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by the electric field from 3a, the insulating film 2 including the gate insulating film that insulates the scanning line 3a from the semiconductor layer 1a, the low-concentration source region 1b in the semiconductor layer 1a, and the low A concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e are provided.
[0079]
The TFT 30 preferably has an LDD structure as shown in FIG. 7, but may have an offset structure in which impurities are not implanted into the low concentration source region 1b and the low concentration drain region 1c, or a part of the scanning line 3a. A self-aligned TFT may be used in which a high concentration source region and a high concentration drain region are formed in a self-aligned manner by implanting impurities at a high concentration using a gate electrode made of In the present embodiment, only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e. However, two or more gates are interposed between these gate electrodes. An electrode may be arranged. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the off-time current can be reduced. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single crystal layer or a single crystal layer. A known method such as a bonding method can be used for forming the single crystal layer. By making the semiconductor layer 1a a single crystal layer, it is possible to improve the performance of peripheral circuits in particular.
[0080]
On the other hand, in FIG. 7, the storage capacitor 70 includes a relay layer 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor line 300 as a fixed potential side capacitor electrode. A part thereof is formed so as to be opposed to each other through the dielectric film 75. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a.
[0081]
The relay layer 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the relay layer 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy, similarly to the capacitor line 300 described later. The relay layer 71 has a function of relaying and connecting the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 via the contact holes 83 and 85, in addition to the function as a pixel potential side capacitor electrode.
[0082]
The capacitor line 300 is made of, for example, a conductive film containing a metal or an alloy, extends from the image display region 10a where the pixel electrode 9a is disposed, and is electrically connected to a constant potential source having a relatively low potential. By functioning as a fixed potential, the storage capacitor 70 functions as a fixed potential side capacitor electrode. When viewed in a plan view, the capacitor line 300 is formed so as to overlap the region where the scanning line 3a is formed, as shown in FIG. More specifically, the capacitor line 300 includes a main line portion that extends along the scanning line 3a, a protruding portion that protrudes upward along the data line 6a from each location that intersects the data line 6a, and a contact hole. A portion corresponding to 85 is provided with a constricted portion slightly constricted. Of these, the protruding portion contributes to an increase in the formation region of the storage capacitor 70 using the region above the scanning line 3a and the region below the data line 6a.
[0083]
As shown in FIG. 7, the dielectric film 75 is, for example, a relatively thin silicon oxide film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film having a film thickness of about 5 to 200 nm, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained.
[0084]
6 and 7, in addition to the above, a lower light-shielding film 11 a is provided below the TFT 30. The lower light-shielding film 11a is patterned in a lattice pattern, thereby defining an opening area of each pixel. The opening area is also defined by the data line 6a in FIG. 6 and the capacitor line 300 formed so as to intersect with the data line 6a. Similarly to the case of the capacitance line 300, the lower light-shielding film 11a is also extended from the image display area to the periphery thereof in order to prevent the potential fluctuation from adversely affecting the TFT 30. It may be connected to a potential source.
[0085]
A base insulating film 12 is provided under the TFT 30. In addition to the function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 is roughened during the surface polishing or remains after cleaning. For example, the pixel switching TFT 30 has a function of preventing characteristic changes.
[0086]
In addition, a first interlayer insulating film 41 in which a contact hole 81 leading to the high-concentration source region 1d and a contact hole 83 leading to the high-concentration drain region 1e are respectively formed on the scanning line 3a is formed.
[0087]
A relay layer 71 and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 that leads to the high-concentration source region 1d and a contact hole 85 that leads to the relay layer 71 are formed on each of them. An opened second interlayer insulating film 42 is formed.
[0088]
In addition, data lines 6a are formed on the second interlayer insulating film 42, and a third interlayer insulating film 43 in which a contact hole 85 leading to the relay layer 71 is formed is formed thereon. Yes.
[0089]
(Configuration of inter-wiring capacitance)
Hereinafter, with reference to FIG. 8, which shows the stacked structure of each component of the inter-wiring capacitor 501, which is characteristic in the present embodiment, corresponding to the stacked structure of the pixel portion described above with reference to FIG. 7. This will be described in more detail. FIG. 8 is a cross-sectional view taken along the line BB ′ in FIG. In FIG. 8, the scale of each layer / member is different for each layer / member so that each layer / member can be recognized on the drawing.
[0090]
As described with reference to FIGS. 4 and 5, the inter-wiring capacitor 501 uses the first conductive layer 511 connected to the capacitor line 300 via the capacitor line connecting wire 505 as one capacitor electrode, and the counter electrode The second conductive layer 512 connected to the potential line 503 is used as the other capacitor electrode, and a dielectric film 75 is sandwiched between them.
[0091]
Among these, first, the second conductive layer 512 is formed on the first interlayer insulating film 41 as shown in FIG. That is, as can be seen by comparing FIG. 7 and FIG. 8, the second conductive layer 512 is formed as the same film as the relay layer 71 constituting the storage capacitor 70.
[0092]
The second conductive layer 512 is connected to the counter electrode potential line 503 through the contact hole 582. Here, the contact hole 582 is formed through the second interlayer insulating film 42.
[0093]
Here, the counter electrode potential line 503 is wired so as to pass along the outer periphery of the counter substrate 20 through the vertical conductive material 106, and is formed as the same film as the data line 6a. That is, when the data line 6a is formed including aluminum as described above, the counter electrode potential line 503 is also formed including aluminum. As described above, if the counter electrode potential line 503 is formed including a low-resistance material such as aluminum, the wiring delay or the like is not a problem. With this configuration, the second conductive layer 512 has the same potential as the counter electrode potential line 503.
[0094]
On the other hand, as shown in FIG. 8, the first conductive layer 511 is formed on the dielectric film 75 formed on the second conductive layer 512 so as to face the second conductive layer 512. The first conductive layer 511 is connected to a capacitor line connection wiring 505 formed on the second interlayer insulating film 42 via a contact hole 581. The contact hole 581 is formed through the second interlayer insulating film 42 in the same manner as the contact hole 582.
[0095]
Here, the capacitor line connection wiring 505 extends along the outer periphery of the image display region 10a, and is a contact hole in a region between the image display region 10a and the scanning line driving circuit 104 in the peripheral region of the image display region 10a. The capacitor line 300 is connected to the capacitor line 507. As shown in FIG. 8, the capacitor line connection wiring 505 is formed as the same film as the data line 6a. That is, when the data line 6a is formed including aluminum as described above, the capacitor line connection wiring 505 is also formed including aluminum. In this way, if the capacitor line connection wiring 505 is formed to include a low-resistance material such as aluminum, the wiring delay does not become a problem. With this configuration, the first conductive layer 511 has the same potential as that of the capacitor line 300.
[0096]
By configuring the inter-wiring capacitor 501 according to the present embodiment as described above, it is clear from the comparison between FIG. 7 and FIG. 8 that the member constituting the storage capacitor 70 has the same opportunity in the manufacturing process. To be formed. Specifically, as described above, the first conductive layer 511 and the second conductive layer 512 are formed as the same film as the capacitor line 300 and the relay layer 71, respectively. The dielectric film 75 is shared by the inter-wiring capacitor 501 and the storage capacitor 70. In the present embodiment, the data line 6a, the counter electrode potential line 503, and the capacitor line connection wiring 505 are further formed as the same film.
[0097]
As described above, in the present embodiment, the interwiring capacitor 501 and the configuration related thereto are formed at the same time as the components (the data line 6a, the storage capacitor 70, etc.) formed in the image display area 10a. Therefore, the laminated structure on the TFT array substrate and the manufacturing process can be simplified, or the manufacturing cost can be reduced accordingly.
[0098]
The counter electrode potential line 503 is connected to a predetermined potential source for supplying a predetermined potential such as a fixed potential or an inversion potential inverted to AC inversion drive to the counter electrode 21 (not shown). Accordingly, the second conductive layer 512 is also set to a predetermined potential. On the other hand, the capacitor line connection wiring 505 is connected to the capacitor line 300, and the capacitor line 300 is fixed for supplying a relatively low fixed potential to the capacitor line 300 constituting the storage capacitor 70. Since it is connected to a potential source, the first conductive layer 511 is also set to a fixed potential. In this embodiment, in order to set the first conductive layer 511 and the second conductive layer 512 to a predetermined potential in this way, the power source for the capacitor line 300 and the power source for the counter electrode 21 can be used. Since it is not necessary to provide a special power source for the conductive layer and the second conductive layer 512, the device configuration can be simplified correspondingly.
[0099]
The dielectric film 75 that is an insulating layer of the inter-wiring capacitor 501 is the same as the dielectric film 75 of the storage capacitor 70 described above, as is clear from its name and symbol. That is, the dielectric film 75 is shared by the inter-wiring capacitor 501 and the storage capacitor 70.
[0100]
(Second Embodiment)
A second embodiment of the electro-optical device according to the invention will be described with reference to FIGS. FIG. 9 is an enlarged view of the area C in FIG. 1 having the same concept as in FIG. 4, and the wiring formed in the peripheral area of the image display area in the electro-optical device according to the second embodiment. It is a top view which shows the structure of a capacity | capacitance. 10 is a cross-sectional view taken along the line BB ′ of FIG.
[0101]
Compared with the first embodiment described above, the second embodiment adjusts the inter-wiring capacitance on the plane and the distance between both the TFT array substrate and the counter substrate, that is, the inter-substrate gap. The difference is that a dummy pattern is provided. Accordingly, the circuit configuration and operation in the image display area, and the overall configuration of the liquid crystal device are the same as those in the first embodiment. Therefore, in the following, a configuration different from the first embodiment will be described. 9 to 10, the same reference numerals are given to the same components as those of the first embodiment shown in FIGS. 1 to 8, and the description thereof is omitted.
[0102]
As shown in FIG. 9, in the present embodiment, the distance between both the TFT array substrate 10 and the counter substrate 20 in the seal region 52a on the TFT array substrate 10, that is, the gap between the substrates is maintained at a predetermined value. A dummy pattern 600 is provided. Here, the adjustment of the inter-substrate gap by the dummy pattern 600 will be described.
[0103]
In the electro-optical device according to the present embodiment, the structure in which both the TFT array substrate 10 and the counter substrate 20 are bonded is a predetermined coating applied to the entire surface of the seal region 52a as shown in FIGS. The gap between the substrates is kept at a predetermined value by the sealing material 52 containing a plurality of spherical gap materials having a diameter. However, here, when the seal area 52a is compared with each other in the four areas corresponding to the four sides of the image display area 10a, various wiring layers wired from the peripheral drive circuit to the image display area 10a across the seal area 52a. Therefore, the height of each portion, that is, the height of the portion to be the base of the gap material is different. More specifically, in the area corresponding to the left and right and lower three sides of the image display area 10a shown in FIGS. 1 and 3 in the seal area 52a, scanning wired from the left and right scanning line driving circuits 104. There is a higher position than the other regions due to the line 3a, the lead-out wiring 116 wired from the data line driving circuit 101 arranged below. Therefore, in the area corresponding to the upper side of the image display area 10a shown in FIG. 1 in the seal area 52a, since the above-described various wirings do not exist, the uppermost layer in the laminated structure of the TFT array substrate 10, That is, the layer to be the base of the gap material is formed lower than the other three sides. Due to such circumstances, the dummy pattern 600 is provided in the region corresponding to the above one side in order to match the height with the other three sides.
[0104]
The dummy pattern 600 formed for the purpose as described above is formed as a plurality of patterns in parallel on the substrate plane in correspondence with the arrangement of the plurality of data lines 6a as shown by dotted lines in FIG.
[0105]
In this embodiment, particularly, as shown in FIG. 9, the interwiring capacitance 501 is divided into a plurality of portions corresponding to the gaps of the plurality of dummy patterns 600 when viewed in plan on the TFT array substrate 10. It has been.
[0106]
More specifically, the counter electrode potential line 503 wired in the X direction along the upper side of the counter substrate 20 in FIG. 9 extends in a comb shape in the Y direction corresponding to the plurality of dummy patterns 600 described above. Provided, and connected to a plurality of second conductive layers 512 constituting a plurality of inter-wiring capacitors 501 through contact holes 582.
[0107]
On the other hand, the capacitor line connection wiring 505 wired in the X direction so as to extend along the upper side of the image display area 10a in FIG. 9 has a comb-teeth shape in a direction opposite to the Y direction corresponding to the plurality of dummy patterns 600 described above. Are connected to a plurality of first conductive layers 511 constituting a plurality of inter-wiring capacitors 501 through contact holes 581.
[0108]
With this configuration, the inter-wiring capacitor 501 as the capacitor between the capacitor line 300 and the counter electrode potential line 503 is constructed by being divided into a plurality of parts, similar to the first embodiment described above. It will be.
[0109]
If comprised as mentioned above, after the sealing material 52 which consists of photocurable resin is apply | coated on the TFT array substrate 10 in a manufacturing process in order to bond both substrates, for example, the back surface side of the TFT array substrate 10 When being cured by irradiation with ultraviolet light or the like, the irradiation light reaches the sealing material 52 by sewing the gaps between the dummy patterns 600 formed in a comb shape and the inter-wiring capacitance 501 as described above. . That is, even if the opaque dummy pattern 600 and the inter-wiring capacitor 501 are formed in the seal region 52a as in the present embodiment, the irradiation light effectively reaches the seal material because these have a plurality of gaps. The sealing material 52 can be cured by light irradiation without being obstructed by the dummy pattern 600 and the inter-wiring capacitance 501.
[0110]
The plurality of inter-wiring capacitors 501 of the present embodiment are formed in the same region as the inter-wiring capacitors 501 in the first embodiment shown in FIG. 4 on the substrate plane shown in FIG. In other words, since the peripheral drive circuit and the like are not arranged, the area that can be used to make the inter-wiring capacitance 501 wide can be effectively used. It is formed by utilizing. Therefore, it is possible to relatively easily form a plurality of inter-wiring capacitors 501 having a relatively large capacity without newly providing a special region on the TFT array substrate 10.
[0111]
In addition, the total capacitance value of the plurality of inter-wire capacitances 501 in this embodiment is equal to or greater than the total capacitance value of the plurality of data lines 6a, and is preferably several times to ten times the total capacitance value of the plurality of data lines 6a. It is about several times or about several tens of times. As described in the first embodiment, the total capacitance value of the inter-wiring capacitors 501 increases in proportion to the total value of the areas of the plurality of inter-wiring capacitors 501 on the substrate plane shown in FIG. Accordingly, the inter-wiring capacitance 501 is set to the wiring width of each data line 6a while ensuring the width as much as possible in the arrangement between the counter electrode potential line 503 and the capacitance line connection wiring 505 in the Y direction in FIG. Accordingly, it is possible to set a sufficient capacity for the total capacity value of the data lines 6a by adjusting the width in the X direction shown in FIG.
[0112]
Next, with reference to FIG. 10, a laminated structure of the inter-wiring capacitance 501 and the dummy pattern 600 in the present embodiment will be described below. FIG. 10 is a cross-sectional view taken along the line BB ′ of FIG. 9, and shows a stacked structure having the same concept as FIG.
[0113]
As shown in FIG. 10, a plurality of inter-wiring capacitors 501 are formed in the present embodiment, and each laminated structure is the same as the laminated structure in the first embodiment shown in FIG.
[0114]
In the present embodiment, in particular, a dummy pattern 600 made of the same layer as the scanning line 3 a shown in FIG. 7 is formed on the base insulating film 12.
[0115]
In particular, as shown in FIG. 10, the seal material 52 is disposed in the seal region 52a so as to cover a part of the region where the dummy pattern 600 is formed and the region where the interwiring capacitance 501 is formed. The height of the portion to be the base of the gap material included in the sealing material 52 is the same as that in FIG. 10 in which the dummy pattern 600 is formed in the wiring layer of the counter electrode potential line 503 positioned at the top in the laminated structure. It is defined by the height of part D. That is, even if the inter-wiring capacitance 501 is provided so as to correspond to the plurality of dummy patterns 600 in a plan view as shown in FIG. 9, the inter-wiring capacitance 501 is as shown in the stacked structure of FIG. The uppermost layer of the region to be formed is formed to be the same as or lower than the uppermost layer of the region D in which the dummy pattern 600 is formed. Height is not affected.
[0116]
Therefore, using the dummy pattern 600, the sealing material 52 made of a photocurable resin can be photocured and the gap between the substrates can be kept at a predetermined value, and the gap between the dummy patterns 600 can be maintained. Correspondingly, it is possible to construct an inter-wiring capacitance that is divided into a plurality of parts or has a comb shape.
[0117]
In addition, the formation location in the laminated structure of the dummy pattern 600 is not limited to the above-mentioned embodiment, for example, it may be directly formed on the TFT array substrate 10 and formed in the same layer as other wiring layers. May be.
[0118]
Finally, in this embodiment, the operation and effect of the inter-wire capacitance 501 configured as described above and the gain obtained thereby are the same as those of the inter-wire capacitance 501 in the first embodiment.
[0119]
(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail as a light valve will be described. FIG. 11 is a schematic cross-sectional view of the projection type color display device.
[0120]
In FIG. 11, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device having a drive circuit mounted on a TFT array substrate, each of which is a light valve for RGB. It is configured as a projector used as 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, the light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. The light is divided into B and led to the light valves 100R, 100G and 100B corresponding to the respective colors. In particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.
[0121]
The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, electronic devices are also included in the technical scope of the present invention.
[Brief description of the drawings]
FIG. 1 is a plan view showing an overall configuration of an electro-optical device according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.
FIG. 3 is a circuit diagram showing an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image display region in the electro-optical device according to the first embodiment of the invention.
4 is a plan view of the electro-optical device showing a region C of FIG. 1 in an enlarged manner. FIG.
FIG. 5 is a perspective view showing a configuration of an interwiring capacitance according to the first embodiment of the present invention.
6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed in the electro-optical device according to the first embodiment of the invention. FIG.
FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG.
FIG. 8 is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 9 is a plan view illustrating a configuration of a capacitance between wirings formed in a peripheral region of an image display region in an electro-optical device according to a second embodiment.
10 is a cross-sectional view taken along the line BB ′ of FIG.
FIG. 11 is a schematic cross-sectional view showing a color liquid crystal projector as an example of a projection type color display device which is an embodiment of the electronic apparatus of the invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 10 ... TFT array substrate, 10a ... Image display area, 20 ... Counter substrate, 21 ... Common electrode, 50 ... Liquid crystal layer, 52 ... Sealing material 52a ... Sealing area, 70 ... Storage capacitor, 100 ... Liquid crystal panel, 101 ... Data line driving circuit, 102 ... External circuit connection terminal, 104 ... Scanning line driving circuit, 106 ... vertical conduction member, 110 ... image display area, 501 ... inter-wiring capacitance, 503 ... counter electrode potential line, 505 ... capacitance line connection wiring, 511 ... first conductive layer 512 ... 2nd conductive layer, 581, 582 ... Contact hole, 600 ... Dummy pattern

Claims (13)

An electro-optical material is sandwiched between a pair of element substrates and a counter substrate,
A counter electrode having a predetermined potential is provided on the counter substrate,
A plurality of pixel electrodes disposed on the element substrate so as to face the counter electrode, a plurality of signal lines and electronic elements for supplying an image signal to the plurality of pixel electrodes, and the plurality of pixel electrodes connected to the plurality of pixel electrodes. A capacitor line that constitutes the storage capacitor, and a counter electrode potential line that supplies the predetermined potential to the counter electrode via a vertical conductive material disposed between the element substrate and the counter substrate,
An electro-optical device in which an inter-wiring capacitance is constructed between the counter electrode potential line and the capacitance line on the element substrate ,
The inter-wiring capacitance includes a first conductive layer made of a part of the counter electrode potential line or extended from the counter electrode potential line or connected to the counter electrode potential line, and a part of the capacitor line Or a second conductive layer that is extended from the capacitor line or connected to the capacitor line, and is constructed so as to be opposed to each other via a dielectric film on the element substrate,
The counter electrode potential line and the first conductive layer are connected through one contact hole, and the capacitor line and the second conductive layer are connected through another contact hole. Electro-optic device. An electro-optical material is sandwiched between a pair of element substrates and a counter substrate,
A counter electrode having a predetermined potential is provided on the counter substrate,
A plurality of pixel electrodes disposed on the element substrate so as to face the counter electrode, a plurality of signal lines and electronic elements for supplying an image signal to the plurality of pixel electrodes, and the plurality of pixel electrodes connected to the plurality of pixel electrodes. A capacitor line that constitutes the storage capacitor, and a counter electrode potential line that supplies the predetermined potential to the counter electrode via a vertical conductive material disposed between the element substrate and the counter substrate,
An electro-optical device in which an inter-wiring capacitance is constructed between the counter electrode potential line and the capacitance line on the element substrate ,
The inter-wiring capacitance includes a first conductive layer made of a part of the counter electrode potential line or extended from the counter electrode potential line or connected to the counter electrode potential line, and a part of the capacitor line Or a second conductive layer that is extended from the capacitor line or connected to the capacitor line, and is constructed so as to be opposed to each other via a dielectric film on the element substrate,
An electro-optical device, wherein at least one of the pixel potential side capacitor electrode and the fixed potential side capacitor electrode constituting the storage capacitor is formed of the same layer as the first conductive layer or the second conductive layer. . 3. The electro-optical device according to claim 2 , wherein the inter-wiring capacitor and the storage capacitor have the same laminated structure formed simultaneously in the same process at the time of manufacture. 4. The electro-optical device according to claim 1, wherein the counter electrode potential line and the capacitor line are formed of the same conductive layer formed simultaneously in the same process at the time of manufacture. On the element substrate, an image display area in which the plurality of pixel electrodes are arranged is defined, and a peripheral area is defined around the image display area,
5. The electro-optical device according to claim 1 , wherein the inter-wiring capacitance is at least partially disposed in the peripheral region. The electro-optical device according to claim 5 , wherein the inter-wiring capacitance is disposed in a region facing the counter substrate in the peripheral region. The element substrate and the counter substrate are bonded together by a sealing material along their edges in the peripheral region,
The electro-optical device according to claim 6 , wherein the inter-wiring capacitance is at least partially disposed in a sealing region in the peripheral region where the sealing material is present. On the element substrate, further comprising a plurality of dummy patterns for maintaining a gap between the element substrate and the counter substrate at a predetermined value,
7. The inter-wiring capacitance, characterized in that provided in the element planarly viewed the plurality or comb shape corresponding to the gap between the dummy patterns are divided into a plurality on the substrate The electro-optical device according to 1. A peripheral drive circuit for driving the plurality of signal lines is disposed in a region along one side or a plurality of sides of the element substrate in the peripheral region,
The wiring capacitance is at least partially, any one of claims 5 to 8, characterized in that disposed in the region along the other different sides and the one side or more sides of said peripheral region The electro-optical device according to Item. A plurality of external circuit connection terminals including a terminal for the counter electrode potential line are arranged in a region along one side of the element substrate in the peripheral region,
The wiring capacitance is at least in part, according to any one of claims 5 9, characterized in that it is disposed in the region along the other side opposite to one side of the peripheral area Electro-optic device. The plurality of signal lines include a plurality of data lines to which the image signal is supplied and a plurality of scanning lines that intersect the plurality of data lines and to which a scanning signal is supplied,
10. The pixel switching transistor according to claim 5 , wherein the electronic element includes a pixel switching thin film transistor that supplies the image signal from the data line to the pixel electrode in response to the supply of the scanning signal. 10. The electro-optical device according to 1. The electro-optical device according to claim 11 , wherein a capacitance value of the interwiring capacitance is equal to or greater than a total capacitance value of the plurality of data lines. An electronic apparatus comprising the electro-optical device according to claim 1 .

Images