JP4392715B2

JP4392715B2 - IPS liquid crystal display array structure and manufacturing method thereof

Info

Publication number: JP4392715B2
Application number: JP2003345131A
Authority: JP
Inventors: 泰信廣升; 薫草深; 充池崎
Original assignee: Chi Mei Optoelectronics Corp
Current assignee: Chi Mei Optoelectronics Corp
Priority date: 2003-10-03
Filing date: 2003-10-03
Publication date: 2010-01-06
Anticipated expiration: 2023-10-03
Also published as: JP2005114780A; TWI304900B; CN100416387C; TW200513729A; CN1603920A

Description

本発明は、開口率を落とさずにゲート線からの電界の影響をシールドして、ディスプレイの焼け付きが起こりにくいＩＰＳ液晶ディスプレイに関するものである。 The present invention relates to an IPS liquid crystal display that shields the influence of an electric field from a gate line without reducing the aperture ratio and hardly causes display burn-in.

広視野角を得る液晶のＩＰＳ（Ｉｎ−ＰｌａｎｅＳｗｉｔｃｈｉｎｇ）方式は、印加電場が基板面に平行であり、横電界方式とも呼ばれる。ＩＰＳ方式では基板に沿った電場のｏｎ／ｏｆｆにより液晶分子の配列が基板面内で変化する。そしてこの特有な分子配列の変化がツイスティド・ネマティク（ＴｗｉｓｔｅｄＮｅｍａｔｉｃ；ＴＮ）方式等の縦電界方式には見られない画期的な広視野角を生む。以下、本明細書においてＩＰＳ方式の液晶ディスプレイをＩＰＳ液晶ディスプレイという。 In an IPS (In-Plane Switching) method of liquid crystal that obtains a wide viewing angle, an applied electric field is parallel to the substrate surface and is also called a lateral electric field method. In the IPS system, the arrangement of liquid crystal molecules changes in the substrate plane by turning on / off the electric field along the substrate. This unique change in molecular arrangement produces an epoch-making wide viewing angle that cannot be seen in a vertical electric field system such as the Twisted Nematic (TN) system. Hereinafter, an IPS liquid crystal display is referred to as an IPS liquid crystal display in this specification.

ＩＰＳ液晶ディスプレイは、絶縁基板とカラーフィルター基板が一定間隔で対向し、両基板の間に液晶が充填されている。図２３に示す一般的なＩＰＳ液晶ディスプレイ１０１の製造は下記の（１）〜（８）の順でおこなう。（１）ガラス基板１１０などの透明絶縁基板を準備する。（２）ガラス基板上にゲート線１１２およびＣＳ（storage capacity）線１１６を形成する。（３）ＣＶＤ（chemical vapor deposition）によって絶縁層１１４を形成する。（４）ゲート線１１２の一部をゲート電極としたＴＦＴ（thin
film transistor）１３２、ＴＦＴ１３２のドレイン電極に接続されるシグナル線１２４、絶縁層１１４を介してＣＳ線１１６と対向する対向電極１２６、対向電極１２６とＴＦＴ１３２のソース電極１２８とを接続する画素内配線１２９を同一層に形成する。（５）それらの上に絶縁層１２２を積層する。（６）対向電極１２６上の絶縁層１２２にスルーホール１３５を形成する。（７）画素電極１４２およびパッド１４０、共通電極線１３６、共通電極１３８を形成する。（８）共通電極１３８及び画素電極１４２を形成した層の上に配向層を形成する。 In the IPS liquid crystal display, an insulating substrate and a color filter substrate are opposed to each other at a predetermined interval, and liquid crystal is filled between both the substrates. The general IPS liquid crystal display 101 shown in FIG. 23 is manufactured in the following order (1) to (8). (1) A transparent insulating substrate such as a glass substrate 110 is prepared. (2) A gate line 112 and a CS (storage capacity) line 116 are formed on the glass substrate. (3) The insulating layer 114 is formed by CVD (chemical vapor deposition). (4) TFT (thin using a part of the gate line 112 as a gate electrode)
film transistor) 132, signal line 124 connected to the drain electrode of TFT 132, counter electrode 126 facing CS line 116 via insulating layer 114, and intra-pixel wiring 129 connecting counter electrode 126 and source electrode 128 of TFT 132. Are formed in the same layer. (5) The insulating layer 122 is laminated thereon. (6) A through hole 135 is formed in the insulating layer 122 on the counter electrode 126. (7) The pixel electrode 142, the pad 140, the common electrode line 136, and the common electrode 138 are formed. (8) An alignment layer is formed on the layer on which the common electrode 138 and the pixel electrode 142 are formed.

以下、上記工程により製造されるＩＰＳ液晶ディスプレイの構造を図１９〜図２５を用いて詳細に説明する。 Hereinafter, the structure of the IPS liquid crystal display manufactured by the above process will be described in detail with reference to FIGS.

上記工程（２）を図１９を用いて説明する。複数のゲート線１１２がガラス基板１１０上に相互に平行に敷設され、ＣＳ線１１６は相互に隣接するゲート線１１２の間にゲート線１１２と平行に敷設する。ここでＣＳ線１１６は電極部１１８を有し、電極部１１８の両端部からはゲート線１１２の方向に軸部１２０ａ、１２０ｂ、１２０ｃ、１２０ｄが伸張している。又、軸部１２０ａ、１２０ｂ及び１２０ｃ、１２０ｄはそれぞれ平行に形成されている。以後軸部１２０ａ、１２０ｂ、１２０ｃ、１２０ｄを総称して翼部１２０という。 The step (2) will be described with reference to FIG. A plurality of gate lines 112 are laid in parallel to each other on the glass substrate 110, and the CS lines 116 are laid in parallel with the gate lines 112 between the adjacent gate lines 112. Here, the CS line 116 has an electrode portion 118, and shaft portions 120 a, 120 b, 120 c, and 120 d extend from both ends of the electrode portion 118 in the direction of the gate line 112. The shaft portions 120a, 120b and 120c, 120d are formed in parallel. Hereinafter, the shaft portions 120a, 120b, 120c, and 120d are collectively referred to as the wing portion 120.

工程（３）では、図２０に示すように第１絶縁層１１４が積層される。 In step (3), the first insulating layer 114 is stacked as shown in FIG.

上記工程（４）は図２１を用いて説明する。シグナル線１２４はＣＳ線１１６の翼部１２０を挟んで、翼部１２０と平行に、ゲート線１１２と交差して第１絶縁層１１４上に敷設される。又、対向電極１２６はシグナル線１２４間にＣＳ線１１６の電極部１１８と第１絶縁層１１４を挟んで形成される。更にソース電極１２８は対向電極１２６と画素内配線１２９により接続されて前記第１絶縁層１１４上に形成され、ドレイン電極１３０はシグナル線１２４と接続されて同じく第１絶縁層１１４に形成される。そしてソース電極１２８とドレイン電極１３０とゲート線１１２とでＴＦＴ１３２が構成される。尚、画素内配線１２９はシグナル線１２４と平行に配置される。 The step (4) will be described with reference to FIG. The signal line 124 is laid on the first insulating layer 114 across the gate line 112 in parallel with the wing part 120 with the wing part 120 of the CS line 116 interposed therebetween. The counter electrode 126 is formed by sandwiching the electrode portion 118 of the CS line 116 and the first insulating layer 114 between the signal lines 124. Further, the source electrode 128 is connected to the counter electrode 126 by the intra-pixel wiring 129 and formed on the first insulating layer 114, and the drain electrode 130 is connected to the signal line 124 and is also formed on the first insulating layer 114. The source electrode 128, the drain electrode 130, and the gate line 112 constitute a TFT 132. The intra-pixel wiring 129 is arranged in parallel with the signal line 124.

工程（５）で第２絶縁層１２２が積層される。この第２絶縁層１２２は、シグナル線１２４とソース電極１２８とドレイン電極１３０及び対向電極１２６を覆って積層されるため、図２２に示すように対向電極１２６上の第２絶縁層１２２にスルーホール１３５が開口される。 In the step (5), the second insulating layer 122 is laminated. Since the second insulating layer 122 is laminated so as to cover the signal line 124, the source electrode 128, the drain electrode 130, and the counter electrode 126, a through hole is formed in the second insulating layer 122 on the counter electrode 126 as shown in FIG. 135 is opened.

上記工程（７）では、図２３に示すように、パッド１４０は対向電極１２６上に形成され、スルーホール１３５を介して対向電極１２６と電気的に接続される。又、第２絶縁層１２２上で、パッド１４０からゲート線１１２の方向にシグナル線１２４と平行に画素電極１４２を伸張させる。１画素中の画素電極１４２の数は任意であるが、そのうち一本は画素内配線１２９と重なるように形成される。 In the step (7), as shown in FIG. 23, the pad 140 is formed on the counter electrode 126 and is electrically connected to the counter electrode 126 through the through hole 135. On the second insulating layer 122, the pixel electrode 142 is extended in parallel with the signal line 124 in the direction from the pad 140 to the gate line 112. The number of pixel electrodes 142 in one pixel is arbitrary, but one of them is formed so as to overlap with the intra-pixel wiring 129.

また、共通電極線１３６は第２絶縁層１２２上で、ゲート線１１２を覆ってこれと平行に敷設される。更に、共通電極１３８はシグナル線１２４及びＣＳ線１１６の軸部１２０ａ、１２０ｂ、１２０ｃ、１２０ｄを覆って、隣接する共通電極１３６を接続する。共通電極１３６と画素電極１４２によってガラス基板１１０と平行な電界を発生させ、電界の強弱で液晶の配向を変化させる。 The common electrode line 136 is laid on the second insulating layer 122 so as to cover the gate line 112 and in parallel therewith. Further, the common electrode 138 covers the shaft portions 120a, 120b, 120c, and 120d of the signal line 124 and the CS line 116, and connects the adjacent common electrodes 136. An electric field parallel to the glass substrate 110 is generated by the common electrode 136 and the pixel electrode 142, and the alignment of the liquid crystal is changed by the strength of the electric field.

しかし、ＩＰＳ方式の液晶ディスプレイ１０１では、共通電極１３８と画素電極１４２間に直流電圧をかけ続けるとディスプレイにいわゆる焼き付きが発生する。そのため両極間には交流電圧が印加されるが、従来ゲート線１１２やシグナル線１２４からの漏れ電界に起因するディスプレイの焼け付きやフリッカーが問題となっていた。 However, in the IPS liquid crystal display 101, when a DC voltage is continuously applied between the common electrode 138 and the pixel electrode 142, so-called burn-in occurs on the display. For this reason, an alternating voltage is applied between the two electrodes, but display burn-in and flicker caused by a leakage electric field from the gate line 112 and the signal line 124 have been problems.

このため、ゲート線１１２やシグナル線１２４からの漏れ電界をシールドする必要があるが、この漏れ電界のシールド法が特許文献１に開示されている。即ち、特許文献１では、ゲート線やシグナル線を共通電極で完全に覆うことによって漏れ電界をシールドする方法が開示されている。 For this reason, it is necessary to shield the leakage electric field from the gate line 112 and the signal line 124. A method for shielding this leakage electric field is disclosed in Patent Document 1. That is, Patent Document 1 discloses a method of shielding a leakage electric field by completely covering a gate line and a signal line with a common electrode.

上述した構造の従来のＩＰＳ液晶ディスプレイ１０１も、共通電極線１３６はゲート線１１２を覆い、共通電極１３８はシグナル線１２４を覆っているので、ゲート線１１２及びシグナル線１２４からの漏れ電界をシールドすることができる。上記構造の従来のＩＰＳ液晶ディスプレイ１０１は、更にＣＳ線１１６の電極部１１８の両端部からゲート線１１２の方向に軸部１２０ａ、１２０ｂ、１２０ｃ、１２０ｄが伸張している。そのため軸部がゲート線１１２及びシグナル線１２４からの漏れ電界をシールドし、特許文献１に開示されたＩＰＳ液晶ディスプレイより効果的に漏れ電界に起因して発生する液晶ディスプレイのフリッカーや焼き付きを更に防ぐことができる。 Also in the conventional IPS liquid crystal display 101 having the above-described structure, since the common electrode line 136 covers the gate line 112 and the common electrode 138 covers the signal line 124, the leakage electric field from the gate line 112 and the signal line 124 is shielded. be able to. In the conventional IPS liquid crystal display 101 having the above structure, shaft portions 120 a, 120 b, 120 c, and 120 d extend from both ends of the electrode portion 118 of the CS line 116 toward the gate line 112. Therefore, the shaft portion shields the leakage electric field from the gate line 112 and the signal line 124, and more effectively prevents flicker and image sticking of the liquid crystal display caused by the leakage electric field than the IPS liquid crystal display disclosed in Patent Document 1. be able to.

しかし、ＩＰＳ液晶ディスプレイ１０１の構造でも漏れ電界のシールドは十分でないことが分かっている。即ち、ＩＰＳ液晶ディスプレイ１０１の構造であってもフリッカーや焼き付きが発生し得る。 However, it has been found that even the structure of the IPS liquid crystal display 101 is not sufficient to shield the leakage electric field. That is, even the structure of the IPS liquid crystal display 101 can cause flicker and image sticking.

図９（ａ）は、ＩＰＳ液晶ディスプレイ１０１の共通電極１３８と画素電極１４２の間に印加される、理想的な電位の様子を表す模式断面図である。断面図の下のグラフは横軸が画素電極１４２からの距離を表し、縦軸が共通電極１３８を基準とした時の両電極間の電位を表す。また両電極間の電界は、電位を表すグラフの傾きである。 FIG. 9A is a schematic cross-sectional view showing an ideal potential state applied between the common electrode 138 and the pixel electrode 142 of the IPS liquid crystal display 101. In the graph below the cross-sectional view, the horizontal axis represents the distance from the pixel electrode 142, and the vertical axis represents the potential between the two electrodes when the common electrode 138 is used as a reference. Moreover, the electric field between both electrodes is the inclination of the graph showing an electric potential.

液晶ディスプレイ１０１の表示を行なう際は選択した画素電極１４２に電圧を印加するが、この画素電極１４２に電圧を印加することを書き込みという。上述のようにＩＰＳ液晶ディスプレイ１０１では焼き付きを防ぐため両電極間に交流電圧を印加するため、画素電極１４２の書き込み時の電圧は+Ｖｐ又は−Ｖｐとなる。画素電極１４２の電圧が+Ｖｐとなる場合を上書き込み、−Ｖｐとなる場合を下書き込みという。 When displaying on the liquid crystal display 101, a voltage is applied to the selected pixel electrode 142. Applying a voltage to the pixel electrode 142 is called writing. As described above, in the IPS liquid crystal display 101, an AC voltage is applied between both electrodes in order to prevent burn-in, so that the voltage at the time of writing to the pixel electrode 142 is + Vp or -Vp. The case where the voltage of the pixel electrode 142 is + Vp is referred to as upper writing, and the case where it is −Vp is referred to as lower writing.

図９（ａ）において、両電極間の電位を表すグラフは上書き込みの場合も下書き込みも直線であり、その傾きは大きさが同じで符号が逆となる。従ってＩＰＳ液晶ディスプレイ１０１の理想的な電界の様子は、両電極間において上書き込みの場合も下書き込みの場合も等しく一定であり、方向は反対となる。 In FIG. 9A, the graph representing the potential between both electrodes is a straight line for both the upper writing and the lower writing, and the slope is the same in magnitude but the sign is reversed. Therefore, the ideal state of the electric field of the IPS liquid crystal display 101 is the same and constant in both the upper writing and the lower writing between the electrodes, and the directions are opposite.

ところがＩＰＳ液晶ディスプレイ１０１の電極間の電位の様子は、ゲート線近傍において図２（ｂ）のようになっている。これはゲート線１１２からの漏れ電界によって、電極間の電界が乱されるためである。両電極間における電位は、上書き込みの場合も下書き込みの場合も理想的な電位よりも低くなる傾向がみられる。 However, the state of the potential between the electrodes of the IPS liquid crystal display 101 is as shown in FIG. This is because the electric field between the electrodes is disturbed by the leakage electric field from the gate line 112. There is a tendency that the potential between both electrodes tends to be lower than the ideal potential in both the upper writing and the lower writing.

図２（ｂ）において曲線の傾きから分かるように、画素電極１４２近傍では上書き込みの場合は電界が大きく、下書き込みの場合は電界が小さい。一方共通電極１３８近傍では、上書き込みの場合は電界が略０であり、下書き込みの場合は電界が大きい。このような上書き込みと下書き込みの電界の理想値からのズレが交流電圧の印加により交互に繰り返されるため、フリッカー、焼け付きが共通電極１３８近傍で起こる。 As can be seen from the slope of the curve in FIG. 2B, in the vicinity of the pixel electrode 142, the electric field is large for the upper writing, and the electric field is small for the lower writing. On the other hand, in the vicinity of the common electrode 138, the electric field is substantially zero in the case of upper writing, and the electric field is large in the case of lower writing. Such a deviation from the ideal value of the electric field for the upper writing and the lower writing is alternately repeated by the application of the AC voltage, so that flicker and burn-in occur in the vicinity of the common electrode 138.

特開平２０００−８９２４０号公報（図１）Japanese Unexamined Patent Publication No. 2000-89240 (FIG. 1)

本発明の目的は、開口率を下げずにゲート線からの電界の影響をシールドして、ディスプレイのフリッカー、焼け付きが起こりにくいＩＰＳ液晶ディスプレイを提供することにある。 An object of the present invention is to provide an IPS liquid crystal display which shields the influence of an electric field from a gate line without lowering the aperture ratio and hardly causes display flicker and burn-in.

本発明のＩＰＳ液晶ディスプレイは、絶縁基板と、該絶縁基板上に形成された第１共通電極線を含み、該第１共通電極線に囲まれた画素が前記絶縁基板上に形成されたＩＰＳ液晶ディスプレイであって、前記画素は、前記絶縁基板上に相互に平行に敷設された複数のゲート線と、前記ゲート線を覆って前記絶縁基板上に積層された第１絶縁膜と、隣接する前記ゲート線の間に該ゲート線と平行に前記第１絶縁膜上に敷設された翼部を有するＣｓ線と、前記Ｃｓ線を覆って前記絶縁基板上に積層された第２絶縁膜と、前記Ｃｓ線の翼部を挟んで、前記ゲート線と交差して相互に平行に前記第２絶縁膜上に敷設されたシグナル線と、前記シグナル線間に前記Ｃｓ線と対向して前記第２絶縁膜上に形成された対向電極と、前記対向電極と接続されて前記第２絶縁膜上に形成されたソース電極と、前記シグナル線と接続されて前記第２絶縁膜上に形成されたドレイン電極と、前記ゲート線をゲート電極とし、前記ソース電極とドレイン電極とから構成されるスイッチング素子と、前記シグナル線とスイッチング素子及び対向電極を覆って積層された第３絶縁膜と、前記対向電極上の前記第３絶縁膜に開けられたスルーホールを介して該対向電極と電気的に接続され、該対向電極上に形成されたパッド電極と、前記第３絶縁膜上で、前記パッド電極から前記ゲート線の方向に相互に平行に伸張した画素電極と、前記第３絶縁膜上で、前記ゲート線と対向して相互に平行に敷設された共通電極線と、前記第３絶縁膜上で、隣接する前記共通電極線を接続する相互に平行な共通電極と、を含み、前記Ｃｓ線の中空の翼部が、該中空の翼部の端部において前記ゲート線に近接する。 An IPS liquid crystal display according to the present invention includes an insulating substrate and a first common electrode line formed on the insulating substrate, and an IPS liquid crystal in which pixels surrounded by the first common electrode line are formed on the insulating substrate. In the display, the pixel includes a plurality of gate lines laid parallel to each other on the insulating substrate, a first insulating film that covers the gate line and is stacked on the insulating substrate, and the adjacent pixels. A Cs line having a wing portion laid on the first insulating film in parallel with the gate line between the gate lines; a second insulating film stacked on the insulating substrate so as to cover the Cs line; A signal line laid on the second insulating film across the gate line across the wing portion of the Cs line and parallel to each other, and the second insulation facing the Cs line between the signal lines A counter electrode formed on the film and connected to the counter electrode A source electrode formed on the second insulating film, a drain electrode connected to the signal line and formed on the second insulating film, the gate line as a gate electrode, the source electrode and the drain electrode, A switching element composed of: a third insulating film laminated to cover the signal line, the switching element, and the counter electrode; and the counter electrode via a through hole opened in the third insulating film on the counter electrode A pad electrode electrically connected to the electrode and formed on the counter electrode; a pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode on the third insulating film; A common electrode line laid in parallel to each other on the third insulating film so as to face the gate line; a common electrode parallel to each other connecting the adjacent common electrode lines on the third insulating film; Including, before Wings hollow Cs lines, adjacent to the gate line at an end of the hollow of the wings.

本発明のＩＰＳ液晶ディスプレイは、絶縁基板と、前記絶縁基板上に相互に平行に敷設された複数のゲート線と、前記ゲート線を覆って前記絶縁基板上に積層された第１絶縁膜と、隣接する前記ゲート線の間に該ゲート線と平行に前記第１絶縁膜上に敷設された中空の翼部を有するＣｓ線と、前記Ｃｓ線を覆って前記絶縁基板上に積層された第２絶縁膜と、前記Ｃｓ線の翼部を挟んで、前記ゲート線と交差して相互に平行に前記第２絶縁膜上に敷設されたシグナル線と、前記シグナル線間に前記Ｃｓ線と対向して前記第２絶縁膜上に形成された対向電極と、前記対向電極と接続されて前記第２絶縁膜上に形成されたソース電極と、前記シグナル線と接続されて前記第２絶縁膜上に形成されたドレイン電極と、
前記ゲート線をゲート電極とし、前記ソース電極とドレイン電極とから構成されるスイッチング素子と、前記シグナル線とスイッチング素子及び対向電極を覆って積層された第３絶縁膜と、前記対向電極上の前記第３絶縁膜に開けられたスルーホールを介して該対向電極と電気的に接続され、該対向電極上に形成されたパッド電極と、前記第３絶縁膜上で、前記パッド電極から前記ゲート線の方向に相互に平行に伸張した画素電極と、前記第３絶縁膜上で、前記ゲート線と対向して相互に平行に敷設された共通電極線と、前記第３絶縁膜上で、隣接する前記共通電極線を接続する相互に平行な共通電極と、を含み、前記Ｃｓ線の中空の翼部が、該中空の翼部の端部において前記ゲート線に近接する。 The IPS liquid crystal display of the present invention includes an insulating substrate, a plurality of gate lines laid in parallel to each other on the insulating substrate, a first insulating film that is stacked on the insulating substrate so as to cover the gate lines, A Cs line having a hollow wing portion laid on the first insulating film in parallel with the gate line between the adjacent gate lines, and a second layer laminated on the insulating substrate so as to cover the Cs line. An insulating film, a signal line laid on the second insulating film in parallel with each other across the gate line across the wing portion of the Cs line, and the Cs line opposed to each other between the signal lines The counter electrode formed on the second insulating film, the source electrode connected to the counter electrode and formed on the second insulating film, and the signal line connected to the second insulating film A drain electrode formed;
The gate line as a gate electrode, a switching element composed of the source electrode and the drain electrode, a third insulating film laminated to cover the signal line, the switching element and the counter electrode, and the above-described electrode on the counter electrode A pad electrode electrically connected to the counter electrode through a through hole formed in the third insulating film; and a pad electrode formed on the counter electrode; and the gate line extending from the pad electrode to the gate line on the third insulating film. Adjacent to each other, on the third insulating film, on the third insulating film, on the third insulating film, on the third insulating film, on the third insulating film, and on the third insulating film. A common electrode parallel to each other for connecting the common electrode line, and the hollow wing portion of the Cs line is close to the gate line at the end of the hollow wing portion.

本発明のＩＰＳ液晶ディスプレイは、絶縁基板と、前記絶縁基板上に相互に平行に敷設された複数のゲート線と、隣接する前記ゲート線の間に該ゲート線と平行に前記絶縁基板上に敷設された中空の翼部を有するＣｓ線と、前記Ｃｓ線を覆って前記絶縁基板上に積層された第２絶縁膜と、前記Ｃｓ線の翼部を挟んで、前記ゲート線と交差して相互に平行に前記第２絶縁膜上に敷設されたシグナル線と、前記シグナル線間に前記Ｃｓ線と対向して前記第２絶縁膜上に形成された対向電極と、前記対向電極と接続されて前記第２絶縁膜上に形成されたソース電極と、前記シグナル線と接続されて前記第２絶縁膜上に形成されたドレイン電極と、前記ゲート線をゲート電極とし、前記ソース電極とドレイン電極とから構成されるスイッチング素子と、前記シグナル線とスイッチング素子及び対向電極を覆って積層された第３絶縁膜と、前記対向電極上の前記第３絶縁膜に開けられたスルーホールを介して該対向電極と電気的に接続され、該対向電極上に形成されたパッド電極と、前記第３絶縁膜上で、前記パッド電極から前記ゲート線の方向に相互に平行に伸張した画素電極と、前記第３絶縁膜上で、前記ゲート線と対向して相互に平行に敷設された共通電極線と、前記第３絶縁膜上で、隣接する前記共通電極線を接続する相互に平行な共通電極と、
を含み、前記Ｃｓ線の中空の翼部が、該中空の翼部の端部において前記ゲート線に近接する。 The IPS liquid crystal display according to the present invention includes an insulating substrate, a plurality of gate lines laid in parallel to each other on the insulating substrate, and a gate line between the adjacent gate lines in parallel to the gate line. A Cs line having a hollow wing portion formed thereon, a second insulating film laminated on the insulating substrate so as to cover the Cs line, and crossing the gate line across the wing portion of the Cs line. A signal line laid on the second insulating film in parallel to the second insulating film, a counter electrode formed on the second insulating film opposite to the Cs line between the signal lines, and connected to the counter electrode. A source electrode formed on the second insulating film, a drain electrode connected to the signal line and formed on the second insulating film, the gate line as a gate electrode, the source electrode and the drain electrode, Switching element consisting of A third insulating film laminated to cover the signal line, the switching element and the counter electrode, and electrically connected to the counter electrode through a through hole opened in the third insulating film on the counter electrode; A pad electrode formed on the counter electrode; a pixel electrode extending in parallel to the direction of the gate line from the pad electrode on the third insulating film; and the gate on the third insulating film. A common electrode line laid parallel to and opposite to the line, and a parallel common electrode connecting the adjacent common electrode lines on the third insulating film;
The hollow wing portion of the Cs line is close to the gate line at the end of the hollow wing portion.

本発明のＩＰＳ液晶ディスプレイは、前記共通電極は、前記Ｃｓ線の中空の翼部及びシグナル線を覆って形成され得る。 In the IPS liquid crystal display of the present invention, the common electrode may be formed to cover the hollow wing portion and the signal line of the Cs line.

本発明のＩＰＳ液晶ディスプレイの製造方法は、絶縁基板を準備するステップと、前記絶縁基板上に相互に平行な複数のゲート線を敷設するステップと、前記ゲート線を覆って前記絶縁基板上に第１絶縁膜を積層するステップと、隣接する前記ゲート線の間に該ゲート線と平行に前記第１絶縁膜上に中空の翼部を有し、前記中空の翼部が、該中空の翼部の端部において前記ゲート線に近接するＣｓ線を敷設するステップと、前記Ｃｓ線を覆って前記絶縁基板上に第２絶縁膜を積層するステップと、前記Ｃｓ線の翼部を挟んで、前記ゲート線と交差して相互に平行に前記第２絶縁膜上にシグナル線を敷設するステップと、前記シグナル線間に前記Ｃｓ線と対向して前記第２絶縁膜上に対向電極を形成するステップと、前記対向電極と接続されて前記第２絶縁膜上にソース電極を形成するステップと、
前記シグナル線と接続されて前記第２絶縁膜上にドレイン電極を形成するステップと、前記シグナル線とソース電極とドレイン電極及び対向電極を覆って第３絶縁膜を積層するステップと、前記対向電極上の前記第３絶縁膜にスルーホールを形成するステップと、前記スルーホールを介して前記対向電極と電気的に接続され、該対向電極上にパッド電極を形成するステップと、前記第３絶縁膜上に、前記パッド電極から前記ゲート線の方向に相互に平行に伸張した画素電極を形成するステップと、前記第３絶縁膜上に、前記ゲート線と対向して相互に平行に共通電極線を敷設するステップと、前記第３絶縁膜上に、隣接する前記共通電極線を接続する相互に平行な共通電極を形成するステップと、を含む。 The IPS liquid crystal display manufacturing method of the present invention includes a step of preparing an insulating substrate, a step of laying a plurality of gate lines parallel to each other on the insulating substrate, and a step of covering the gate lines on the insulating substrate. A step of laminating one insulating film, and a hollow wing portion on the first insulating film parallel to the gate line between the adjacent gate lines, the hollow wing portion including the hollow wing portion. Laying a Cs line adjacent to the gate line at an end of the substrate, laminating a second insulating film on the insulating substrate so as to cover the Cs line, and sandwiching a wing part of the Cs line, Laying a signal line on the second insulating film so as to cross the gate line and parallel to each other; and forming a counter electrode on the second insulating film so as to face the Cs line between the signal lines. And connected to the counter electrode Forming a source electrode on the serial second insulating film,
Forming a drain electrode on the second insulating film connected to the signal line; stacking a third insulating film covering the signal line, the source electrode, the drain electrode and the counter electrode; and the counter electrode Forming a through hole in the upper third insulating film; electrically connecting to the counter electrode through the through hole; and forming a pad electrode on the counter electrode; and the third insulating film Forming a pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode; and forming a common electrode line on the third insulating film in parallel with each other so as to face the gate line. And laying, and forming, on the third insulating film, common electrodes parallel to each other for connecting the adjacent common electrode lines.

本発明のＩＰＳ液晶ディスプレイの製造方法は、絶縁基板を準備するステップと、前記絶縁基板上に相互に平行な複数のゲート線を敷設するステップと、隣接する前記ゲート線の間に該ゲート線と平行に前記絶縁基板上に中空の翼部を有し、該中空の翼部が、該中空の翼部の端部において前記ゲート線に近接するＣｓ線を敷設するステップと、前記Ｃｓ線を覆って前記絶縁基板上に第２絶縁膜を積層するステップと、前記Ｃｓ線の翼部を挟んで、前記ゲート線と交差して相互に平行に前記第２絶縁膜上にシグナル線を敷設するステップと、前記シグナル線間に前記Ｃｓ線と対向して前記第２絶縁膜上に対向電極を形成するステップと、前記対向電極と接続されて前記第２絶縁膜上にソース電極を形成するステップと、前記シグナル線と接続されて前記第２絶縁膜上にドレイン電極を形成するステップと、
前記シグナル線とソース電極とドレイン電極及び対向電極を覆って第３絶縁膜を積層するステップと、前記対向電極上の前記第３絶縁膜にスルーホールを形成するステップと、前記スルーホールを介して該パッド電極と電気的に接続され、対向電極上にパッド電極を形成するステップと、前記第３絶縁膜上に、前記パッド電極から前記ゲート線の方向に相互に平行に伸張した画素電極を形成するステップと、前記第３絶縁膜上に、前記ゲート線と対向して相互に平行に共通電極線を敷設するステップと、前記第３絶縁膜上に、隣接する前記共通電極線を接続する相互に平行な共通電極を形成するステップと、を含む。 The method of manufacturing an IPS liquid crystal display according to the present invention includes a step of preparing an insulating substrate, a step of laying a plurality of gate lines parallel to each other on the insulating substrate, and the gate line between the adjacent gate lines. A hollow wing portion on the insulating substrate in parallel, the hollow wing portion laying a Cs line adjacent to the gate line at an end of the hollow wing portion; and covering the Cs line A step of laminating a second insulating film on the insulating substrate; and a step of laying a signal line on the second insulating film so as to cross the gate line and be parallel to each other across the wing portion of the Cs line And forming a counter electrode on the second insulating film opposite to the Cs line between the signal lines, and forming a source electrode on the second insulating film connected to the counter electrode. Connected to the signal line Forming a drain electrode on the second insulating film Te,
A step of laminating a third insulating film covering the signal line, the source electrode, the drain electrode and the counter electrode; a step of forming a through hole in the third insulating film on the counter electrode; Forming a pad electrode on the counter electrode and electrically connected to the pad electrode; and forming a pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode on the third insulating film A step of laying a common electrode line on the third insulating film so as to face the gate line in parallel with each other, and a connection between the adjacent common electrode lines on the third insulating film. Forming a common electrode parallel to the substrate.

本発明のＩＰＳ液晶ディスプレイは、Ｃｓ線をゲート線近傍に配置したので、ゲート線からの電界の影響をシールドすることができる。従って、液晶ディスプレイのフリッカー、焼け付きを大きく抑制することができる。 In the IPS liquid crystal display of the present invention, since the Cs line is disposed in the vicinity of the gate line, the influence of the electric field from the gate line can be shielded. Accordingly, flicker and burn-in of the liquid crystal display can be greatly suppressed.

また、本発明のＩＰＳ液晶ディスプレイは、絶縁層を介してＣＳ線をゲート線近傍に配置したので、各画素中のＣｓ線の電極部を小さくすることができ、開口率を上げることができる。 In the IPS liquid crystal display according to the present invention, since the CS line is arranged in the vicinity of the gate line through the insulating layer, the electrode portion of the Cs line in each pixel can be reduced, and the aperture ratio can be increased.

また、本発明のＩＰＳ液晶ディスプレイは、絶縁層を介してＣＳ線をゲート線の近傍に配置したので、製造工程でＣｓ線とゲート線の接触不良を防ぐことができる。従ってＩＰＳ液晶ディスプレイの製造の歩留まりを上げることができる。 In the IPS liquid crystal display of the present invention, since the CS line is disposed in the vicinity of the gate line through the insulating layer, it is possible to prevent contact failure between the Cs line and the gate line in the manufacturing process. Therefore, the production yield of the IPS liquid crystal display can be increased.

本発明の第１の実施形態のＩＰＳ液晶ディスプレイは、上述した従来のＩＰＳ液晶ディスプレイ１０１と同様に、下記の（１）〜（８）の工程順に製造される。即ち、図１８を参照して、（１）ガラス基板６０などの透明絶縁基板を準備する。（２）ガラス基板上にゲート線６２および中空翼部７０と電極部を持つＣＳ線６６を形成する。（３）ＣＶＤ法によって第１絶縁層６４を形成する。（４）ゲート線６２の一部をゲート電極としたＴＦＴ８２、ＴＦＴ８２のドレイン電極８０に接続されるシグナル線７４、第１絶縁層６４を介してＣＳ線６６の電極部と対向する対向電極７６、対向電極７６とＴＦＴ８２のソース電極７８とを接続する画素内配線７９を絶縁層６４上に形成する。（５）それらの上に第２絶縁層７２を積層し、対向電極７６上の第２絶縁層７２にスルーホール８６を形成する。（６）共通電極線８６と共通電極８８とパッド９０及び画素電極９２を形成する。（７）共通電極８８及び画素電極９２を形成した層の上に配向層を形成する。 The IPS liquid crystal display according to the first embodiment of the present invention is manufactured in the order of the following steps (1) to (8), like the conventional IPS liquid crystal display 101 described above. That is, referring to FIG. 18, (1) a transparent insulating substrate such as a glass substrate 60 is prepared. (2) The CS line 66 having the gate line 62, the hollow blade part 70 and the electrode part is formed on the glass substrate. (3) The first insulating layer 64 is formed by the CVD method. (4) TFT 82 using a part of the gate line 62 as a gate electrode, a signal line 74 connected to the drain electrode 80 of the TFT 82, a counter electrode 76 facing the electrode part of the CS line 66 via the first insulating layer 64, In-pixel wiring 79 that connects the counter electrode 76 and the source electrode 78 of the TFT 82 is formed on the insulating layer 64. (5) The second insulating layer 72 is laminated on them, and a through hole 86 is formed in the second insulating layer 72 on the counter electrode 76. (6) The common electrode line 86, the common electrode 88, the pad 90, and the pixel electrode 92 are formed. (7) An alignment layer is formed on the layer on which the common electrode 88 and the pixel electrode 92 are formed.

上述のような工程で製造された本発明のＩＰＳ液晶ディスプレイ５１の構造を、以下に詳説する。 The structure of the IPS liquid crystal display 51 of the present invention manufactured by the above process will be described in detail below.

上記工程（２）においては、図１２に示すように、複数のゲート線６２がガラス基板６０上に相互に平行に敷設させる。更に、ＣＳ線６６がガラス基板６０上に、ガラス基板６０上の相互に隣接するゲート線６２の間にゲート線６２と平行に敷設される。ここでＣＳ線６６は中空の翼部７０を有し、中空の翼部７０に囲まれる部分には電極部６８が形成されている。又、２つの中空の翼部７０は軸部７０ａ、７０ｂ、７０ｃ、７０ｄ及び接続部７０ｅ、７０ｆから構成される。軸部７０ａ、７０ｂ、７０ｃ、７０ｄは電極部６８の両端部からゲート線６２の方向に伸張し、接続部７０ｅ、７０ｆはゲート線６２の極近傍のＣＳ線６６側でゲート線６２と平行に配置され、それぞれ軸部７０ａと７０ｂ、７０ｃと７０ｄを接続する。 In the step (2), as shown in FIG. 12, a plurality of gate lines 62 are laid on the glass substrate 60 in parallel with each other. Further, the CS line 66 is laid on the glass substrate 60 between the mutually adjacent gate lines 62 on the glass substrate 60 in parallel with the gate line 62. Here, the CS line 66 has a hollow wing portion 70, and an electrode portion 68 is formed in a portion surrounded by the hollow wing portion 70. The two hollow wing parts 70 are constituted by shaft parts 70a, 70b, 70c, 70d and connection parts 70e, 70f. The shaft portions 70 a, 70 b, 70 c and 70 d extend from both ends of the electrode portion 68 in the direction of the gate line 62, and the connection portions 70 e and 70 f are parallel to the gate line 62 on the CS line 66 side near the gate line 62. Arranged to connect the shaft portions 70a and 70b, 70c and 70d, respectively.

工程（３）では、図１３に示すように、第１絶縁層６４はゲート線６２及びＣＳ線６６を覆ってガラス基板６０上に全面に積層される。また、図１４及び図１５においてＩＰＳ液晶ディスプレイ５１は、図１３で示す製造段階と同一の状態である。 In step (3), as shown in FIG. 13, the first insulating layer 64 is laminated on the entire surface of the glass substrate 60 so as to cover the gate line 62 and the CS line 66. 14 and 15, the IPS liquid crystal display 51 is in the same state as the manufacturing stage shown in FIG.

工程（４）においては、図１６に示すように、シグナル線７４はＣＳ線６６の翼部７０を挟んで、翼部７０の軸部７０ａ、７０ｂ、７０ｃ、７０ｄと平行に、ゲート線６２と交差して第１絶縁層６４上に敷設される。又、対向電極７６はシグナル線７４間にＣＳ線６６の電極部６８と第１絶縁層６４を挟んで形成される。更にソース電極７８は対向電極７６と画素内配線７９により接続されて前記第１絶縁層６４上に形成され、ドレイン電極８０はシグナル線７４と接続されて同じく第１絶縁層６４上に形成される。そしてソース電極７８とドレイン電極８０とゲート線６２とでＴＦＴ８２が構成される。尚、画素内配線７９はシグナル線７４と平行に配置される。 In step (4), as shown in FIG. 16, the signal line 74 sandwiches the wing part 70 of the CS line 66 and is parallel to the shaft parts 70 a, 70 b, 70 c, and 70 d of the wing part 70 and the gate line 62. Crossing and laying on the first insulating layer 64. The counter electrode 76 is formed by sandwiching the electrode portion 68 of the CS line 66 and the first insulating layer 64 between the signal lines 74. Further, the source electrode 78 is connected to the counter electrode 76 by the intra-pixel wiring 79 and formed on the first insulating layer 64, and the drain electrode 80 is connected to the signal line 74 and is also formed on the first insulating layer 64. . The source electrode 78, the drain electrode 80, and the gate line 62 constitute a TFT 82. The intra-pixel wiring 79 is disposed in parallel with the signal line 74.

工程（５）では、図１７に示すように、第２絶縁層７２がシグナル線７４とソース電極７８とドレイン電極８０を覆って積層され、対向電極７６上の第２絶縁層７２にスルーホール８５が開口される。 In step (5), as shown in FIG. 17, the second insulating layer 72 is laminated so as to cover the signal line 74, the source electrode 78, and the drain electrode 80, and a through hole 85 is formed in the second insulating layer 72 on the counter electrode 76. Is opened.

工程（６）では、図１８に示すように、パッド９０が対向電極７６上に形成され、スルーホール８５を介して対向電極７６と電気的に接続される。又、第２絶縁層７２上で、パッド９０からゲート線６２の方向にシグナル線７４と平行に画素電極９２が伸張する。そして共通電極線８６は第２絶縁層７２上で、ゲート線６２を覆ってこれと平行に敷設される。更に、共通電極８８はシグナル線７４及びＣＳ線６６の中空の翼部７０の軸部７０ａ、７０ｂ、７０ｃ、７０ｄを覆って、隣接する共通電極８６を接続する。 In step (6), as shown in FIG. 18, the pad 90 is formed on the counter electrode 76 and is electrically connected to the counter electrode 76 through the through hole 85. On the second insulating layer 72, the pixel electrode 92 extends in parallel with the signal line 74 in the direction from the pad 90 to the gate line 62. The common electrode line 86 is laid on and parallel to the gate line 62 on the second insulating layer 72. Further, the common electrode 88 covers the shaft portions 70a, 70b, 70c, and 70d of the hollow wing portion 70 of the signal line 74 and the CS line 66, and connects the adjacent common electrodes 86 to each other.

上記構造の本発明のＩＰＳ液晶ディスプレイ５１は、Ｃｓ線６６をゲート線６２近傍に配置したので、ゲート線６２からの漏れ電界をシールドすることができる。従って、従来のＩＰＳ液晶ディスプレイ１０１よりもディスプレイに生じるフリッカー、焼け付きを抑制することができる。 In the IPS liquid crystal display 51 of the present invention having the above structure, since the Cs line 66 is disposed in the vicinity of the gate line 62, the leakage electric field from the gate line 62 can be shielded. Therefore, it is possible to suppress flicker and burn-in that occur in the display more than the conventional IPS liquid crystal display 101.

以下に本発明のＩＰＳ液晶ディスプレイの別の実施態様を説明し、本発明のＩＰＳ液晶ディスプレイが従来のディスプレイに比べてどの程度ゲート線からの漏れ電界をシールド可能かを示す。 Hereinafter, another embodiment of the IPS liquid crystal display of the present invention will be described to show how much the leakage electric field from the gate line can be shielded by the IPS liquid crystal display of the present invention compared to the conventional display.

図１に示す本発明の第２の実施形態のＩＰＳ液晶ディスプレイは、絶縁基板とカラーフィルター基板が一定間隔で対向して両基板の間に液晶が充填され、図２〜図８に示されるように、下記の（１）〜（８）の工程順に製造される。（１）ガラス基板１０などの透明絶縁基板を準備する。（２）図２に示すように、ガラス基板上にゲート線１２を形成する。（３）図３に示すように、ＣＶＤ法によって第１絶縁層１４を形成する。（４）図４に示すように、絶縁層１４上に中空翼部２０と電極部１８を持つＣＳ線１６を形成する。（５）図５に示すように、ＣＶＤ法によって第２絶縁層２２を形成する。（６）図６に示すように、ゲート線１２の一部をゲート電極としたＴＦＴ３２、ＴＦＴ３２のドレイン電極３０に接続されるシグナル線２４、第２絶縁層２２を介してＣＳ線１６の電極部１８と対向する対向電極２６、対向電極２６とＴＦＴ３２のソース電極２８とを接続する画素内配線２９を第２絶縁層２２上に形成する。（７）図７に示すように、それらの上に第３絶縁層３４を積層し、対向電極２６上の絶縁層３４にスルーホール３５を形成する。（８）図８に示すように、共通電極線３６と共通電極３８とパッド４０及び画素電極４２およびを形成する。（９）共通電極３８及び画素電極４２を形成した層の上に配向層を形成する。 The IPS liquid crystal display according to the second embodiment of the present invention shown in FIG. 1 has an insulating substrate and a color filter substrate facing each other at regular intervals, and liquid crystal is filled between the two substrates, as shown in FIGS. In addition, they are manufactured in the order of the following steps (1) to (8). (1) A transparent insulating substrate such as a glass substrate 10 is prepared. (2) As shown in FIG. 2, the gate line 12 is formed on the glass substrate. (3) As shown in FIG. 3, the first insulating layer 14 is formed by the CVD method. (4) As shown in FIG. 4, the CS wire 16 having the hollow blade portion 20 and the electrode portion 18 is formed on the insulating layer 14. (5) As shown in FIG. 5, the second insulating layer 22 is formed by the CVD method. (6) As shown in FIG. 6, the TFT 32 having a part of the gate line 12 as a gate electrode, the signal line 24 connected to the drain electrode 30 of the TFT 32, and the electrode portion of the CS line 16 through the second insulating layer 22 On the second insulating layer 22, a counter electrode 26 that opposes the electrode 18 and an intra-pixel wiring 29 that connects the counter electrode 26 and the source electrode 28 of the TFT 32 are formed. (7) As shown in FIG. 7, the third insulating layer 34 is laminated thereon, and a through hole 35 is formed in the insulating layer 34 on the counter electrode 26. (8) As shown in FIG. 8, the common electrode line 36, the common electrode 38, the pad 40, and the pixel electrode 42 are formed. (9) An alignment layer is formed on the layer where the common electrode 38 and the pixel electrode 42 are formed.

上述のような工程で製造された本発明のＩＰＳ液晶ディスプレイは、次のような構造を持つ。即ち、工程（２）において、複数のゲート線１２はガラス基板１０上に相互に平行に敷設される。工程（３）では、上記実施形態のＩＰＳ液晶ディスプレイ５１と異なり、第１絶縁層１４はゲート線１２を覆ってガラス基板１０上に全面に積層される。 The IPS liquid crystal display of the present invention manufactured by the above process has the following structure. That is, in the step (2), the plurality of gate lines 12 are laid in parallel to each other on the glass substrate 10. In step (3), unlike the IPS liquid crystal display 51 of the above embodiment, the first insulating layer 14 is laminated on the entire surface of the glass substrate 10 so as to cover the gate lines 12.

工程（４）では、ＣＳ線１６は第１絶縁層１４上に、ガラス基板１０上の相互に隣接するゲート線１２の間にゲート線１２と平行に敷設させる。ＣＳ線１６は、上記実施形態のＩＰＳ液晶ディスプレイ５１と同様に、中空の翼部２０を有し、中空の翼部２０に囲まれる部分には電極部１８が形成されている。又、２つの中空の翼部２０は軸部２０ａ、２０ｂ、２０ｃ、２０ｄ及び接続部２０ｅ、２０ｆから構成されることも同様である。軸部２０ａ、２０ｂ、２０ｃ、２０ｄは電極部１８の両端部からゲート線１２の方向に伸張し、接続部２０ｅ、２０ｆはゲート線１２の極近傍のＣＳ線１６側でゲート線１２と平行に配置され、それぞれ軸部２０ａと２０ｂ、２０ｃと２０ｄを接続する。 In step (4), the CS line 16 is laid on the first insulating layer 14 in parallel with the gate line 12 between the gate lines 12 adjacent to each other on the glass substrate 10. Similarly to the IPS liquid crystal display 51 of the above embodiment, the CS line 16 has a hollow wing portion 20, and an electrode portion 18 is formed in a portion surrounded by the hollow wing portion 20. Similarly, the two hollow wing parts 20 are composed of shaft parts 20a, 20b, 20c, 20d and connecting parts 20e, 20f. The shaft portions 20 a, 20 b, 20 c, and 20 d extend from both ends of the electrode portion 18 in the direction of the gate line 12, and the connection portions 20 e and 20 f are parallel to the gate line 12 on the CS line 16 side near the gate line 12. Arranged to connect the shaft portions 20a and 20b, 20c and 20d, respectively.

次に工程（５）で、第２絶縁層２２はＣＳ線１６を覆って第１絶縁層１４上に全面に積層される。 Next, in step (5), the second insulating layer 22 is laminated on the entire surface of the first insulating layer 14 so as to cover the CS line 16.

工程（６）では、シグナル線２４はＣＳ線１６の翼部２０を挟んで、翼部２０の軸部２０ａ、２０ｂ、２０ｃ、２０ｄと平行に、ゲート線１２と交差して第２絶縁層上２２に敷設される。又、対向電極２６はシグナル線２４間にＣＳ線１６の電極部２６と第２絶縁層２２を挟んで形成される。更にソース電極２８は対向電極２６と画素内配線２９により接続されて前記第２絶縁層２２上に形成され、ドレイン電極３０はシグナル線２４と接続されて同じく第２絶縁層２２上に形成される。そしてソース電極２８とドレイン電極３０とゲート線１２とでＴＦＴ（ＴｈｉｎＦｉｌｍＴｒａｎｇｉｓｔｅｒ）３２が構成される。尚、画素内配線２９はシグナル線２４と平行に配置される。 In step (6), the signal line 24 crosses the gate line 12 on the second insulating layer in parallel with the shaft parts 20a, 20b, 20c, and 20d of the wing part 20 with the wing part 20 of the CS line 16 interposed therebetween. 22 is laid. The counter electrode 26 is formed by sandwiching the electrode portion 26 of the CS line 16 and the second insulating layer 22 between the signal lines 24. Further, the source electrode 28 is connected to the counter electrode 26 by the intra-pixel wiring 29 and formed on the second insulating layer 22, and the drain electrode 30 is connected to the signal line 24 and is also formed on the second insulating layer 22. . The source electrode 28, the drain electrode 30, and the gate line 12 constitute a TFT (Thin Film Transistor) 32. The intra-pixel wiring 29 is arranged in parallel with the signal line 24.

工程（７）においては、第３絶縁層３４がシグナル線２４とソース電極２８とドレイン電極３０を覆って積層され、対向電極２６上の第３絶縁層３４にスルーホール３５が開口される。 In step (7), the third insulating layer 34 is laminated so as to cover the signal line 24, the source electrode 28, and the drain electrode 30, and a through hole 35 is opened in the third insulating layer 34 on the counter electrode 26.

工程（８）では、パッド４０が対向電極３６上に形成され、スルーホール３５を介して対向電極２６と電気的に接続される。又、第３絶縁層３４上で、パッド４０からゲート線１２の方向にシグナル線２４平行に画素電極４２が伸張する。そして共通電極線３６は第３絶縁層３４上で、ゲート線１２を覆ってこれと平行に敷設される。更に、共通電極３８はシグナル線２４及びＣＳ線１６の中空の翼部２０の軸部２０ａ、２０ｂ、２０ｃ、２０ｄを覆って、隣接する第１共通電極３６を接続する。 In step (8), the pad 40 is formed on the counter electrode 36 and is electrically connected to the counter electrode 26 through the through hole 35. On the third insulating layer 34, the pixel electrode 42 extends in parallel with the signal line 24 in the direction from the pad 40 to the gate line 12. The common electrode line 36 is laid on and parallel to the gate line 12 on the third insulating layer 34. Further, the common electrode 38 covers the shaft portions 20a, 20b, 20c, and 20d of the hollow wing portion 20 of the signal line 24 and the CS line 16, and connects the adjacent first common electrodes 36.

このような工程で製造された本発明のＩＰＳ液晶ディスプレイ１の構成は、上述した第１の実施形態のＩＰＳ液晶ディスプレイ５１の構成と略同一である。ただし、上記のように、ＩＰＳ液晶ディスプレイ５１では上記工程（２）においてゲート線６２とＣｓ線６６の両方がガラス基板６０上に形成されたのに対して、本実施形態のＩＰＳ液晶ディスプレイ１はゲート線１２とＣｓ線１６が第１絶縁層１４を隔てて形成される。従ってＩＰＳ液晶ディスプレイ１の製造工程は、ＩＰＳ液晶ディスプレイ５１の製造工程より１工程多くなる。 The configuration of the IPS liquid crystal display 1 of the present invention manufactured by such a process is substantially the same as the configuration of the IPS liquid crystal display 51 of the first embodiment described above. However, as described above, in the IPS liquid crystal display 51, both the gate line 62 and the Cs line 66 are formed on the glass substrate 60 in the step (2), whereas in the IPS liquid crystal display 1 of the present embodiment, A gate line 12 and a Cs line 16 are formed with the first insulating layer 14 therebetween. Accordingly, the number of manufacturing steps for the IPS liquid crystal display 1 is one more than that for the IPS liquid crystal display 51.

しかし、第１絶縁層１４をゲート線１２とＣｓ線１６間に挟むことによって、電界の遮蔽効果をより高めることができる。 However, the electric field shielding effect can be further enhanced by sandwiching the first insulating layer 14 between the gate line 12 and the Cs line 16.

図１０（ｂ）は本発明のＩＰＳ液晶ディスプレイ１における、ゲート線１２付近の共通電極３８と画素電極４２間の電場の様子を表した断面図である。一方、図１０（ａ）は従来のＩＰＳ液晶ディスプレイ１０１における、ゲート線１１２付近の共通電極１３８と画素電極１４２間の電場の様子を表した断面図である。 FIG. 10B is a cross-sectional view showing an electric field between the common electrode 38 and the pixel electrode 42 near the gate line 12 in the IPS liquid crystal display 1 of the present invention. On the other hand, FIG. 10A is a cross-sectional view showing a state of an electric field between the common electrode 138 near the gate line 112 and the pixel electrode 142 in the conventional IPS liquid crystal display 101.

図１０（ａ）及び図１０（ｂ）は、シミュレーションにより得られたものである。共通電極３８、１３８には７Ｖを画素電極４２、１４２には１４Ｖを、ゲート線１２には−１０Ｖを与えている。また、図１０（ｂ）において、絶縁層１４を挟んでゲート線１２に近接している中空の翼部２０の接続部２０ｅ又は２０ｆには、７Ｖを与えている。したがって、図１０（ａ）及び図１０（ｂ）は上書き込みの場合の電界の様子である。 FIG. 10A and FIG. 10B are obtained by simulation. 7 V is applied to the common electrodes 38 and 138, 14 V is applied to the pixel electrodes 42 and 142, and −10 V is applied to the gate line 12. In FIG. 10B, 7V is applied to the connection portion 20e or 20f of the hollow wing portion 20 adjacent to the gate line 12 with the insulating layer 14 interposed therebetween. Accordingly, FIGS. 10A and 10B show the state of the electric field in the case of the upper write.

図１０（ｂ）において、共通電極３８と画素電極４２間の距離は１０μｍであり、中空の翼部２０の接続部２０ｅ又は２０ｆ間の距離は２μｍである。また、図１０（ａ）及び図１０（ｂ）の全体の横方向の長さは４５μｍである。 In FIG. 10B, the distance between the common electrode 38 and the pixel electrode 42 is 10 μm, and the distance between the connection portions 20e or 20f of the hollow wing portion 20 is 2 μm. Further, the overall lateral length of FIGS. 10A and 10B is 45 μm.

図１０（ａ）及び図１０（ｂ）において、Ａの領域は略−１０Ｖであり、Ｂの領域は略−５Ｖであり、Ｃの領域は０Ｖ前後、Ｄの領域は中空の翼部２０の接続部２０ｅの電位である略７Ｖである。以後Ｅの領域、Ｆの領域の順に電位が高くなり、Ｇの領域で略１０Ｖとなる。そして、Ｈの領域を経て、Ｉの領域で略１４Ｖとなる。 10 (a) and 10 (b), the region A is approximately −10V, the region B is approximately −5V, the region C is around 0V, and the region D is the hollow wing portion 20. The potential of the connecting portion 20e is approximately 7V. Thereafter, the potential increases in the order of the E region and the F region, and becomes approximately 10 V in the G region. Then, after passing through the H region, it becomes approximately 14 V in the I region.

図１０（ａ）及び図１０（ｂ）を比較して分かるように、図１０（ｂ）では約７Ｖ以下の領域は接続部２０ｅよりゲート線１２側にあるのに対し、図１０（ａ）ではこれらの低電位領域が画素電極１４２の方に広がっている。従って、従来のＩＰＳ液晶ディスプレイ１０１ではシールドできないゲート線１１２からの漏れ電界は、本発明のＩＰＳ液晶ディスプレイ１では略完全にシールドされていることが分かる。 As can be seen by comparing FIG. 10 (a) and FIG. 10 (b), in FIG. 10 (b), the region of about 7V or less is on the gate line 12 side from the connecting portion 20e, whereas FIG. Then, these low potential regions extend toward the pixel electrode 142. Therefore, it can be seen that the leakage electric field from the gate line 112 that cannot be shielded by the conventional IPS liquid crystal display 101 is almost completely shielded by the IPS liquid crystal display 1 of the present invention.

次に図１１（ａ）及び図１１（ｂ）を比較する。図１１（ａ）は図１０（ａ）に対応していて従来のＩＰＳ液晶ディスプレイ１０１における共通電極１３８と画素電極１４２間の電位である。また、図１１（ｂ）は図１０（ｂ）に対応していて本発明のＩＰＳ液晶ディスプレイ１における共通電極３８と画素電極４２間の電位である。図１１（ａ）及び図１１（ｂ）は上述したシミュレーションと同じ計算により得られたグラフである。 Next, FIG. 11 (a) and FIG. 11 (b) are compared. FIG. 11A corresponds to FIG. 10A and shows the potential between the common electrode 138 and the pixel electrode 142 in the conventional IPS liquid crystal display 101. FIG. 11B corresponds to FIG. 10B and shows the potential between the common electrode 38 and the pixel electrode 42 in the IPS liquid crystal display 1 of the present invention. FIG. 11A and FIG. 11B are graphs obtained by the same calculation as the simulation described above.

図１１（ａ）及び図１１（ｂ）において、上の曲線はゲート線１２、１１２から離れた位置の電位分布を表す。又、両図において、太い曲線はゲート線１２、１１２近傍の電位分布を表す。 In FIG. 11A and FIG. 11B, the upper curve represents the potential distribution at a position away from the gate lines 12 and 112. In both figures, the thick curve represents the potential distribution near the gate lines 12 and 112.

図１１（ａ）では、上述したようにゲート線１１２からの電界の影響で、電位がほぼ全領域にわたって下げられているのに対して、図１１（ｂ）ではそのような影響はほとんど見られない。従って本発明のＩＰＳ液晶ディスプレイ１は、ゲート線１２の漏れ電流を略完全にシールドすることに成功している事がわかる。 In FIG. 11A, the potential is lowered over almost the entire region due to the influence of the electric field from the gate line 112 as described above, whereas such an influence is almost seen in FIG. Absent. Therefore, it can be seen that the IPS liquid crystal display 1 of the present invention succeeds in shielding the leakage current of the gate line 12 almost completely.

尚、上記本発明のＩＰＳ液晶ディスプレイ５１でも本実施形態のＩＰＳ液晶ディスプレイ１と同様、ゲート線１２の漏れ電界を略完全にシールドする効果が得られる。 Note that the IPS liquid crystal display 51 of the present invention also provides an effect of almost completely shielding the leakage electric field of the gate line 12 as in the IPS liquid crystal display 1 of the present embodiment.

次に、本実施形態のＩＰＳ液晶ディスプレイ１は、ゲート線１２とＣｓ線１６間に第１絶縁層１４を挟んだので、製造工程において起こり得るゲート線１２とＣｓ線１６の接触を防ぐことができる。即ち、Ｃｓ線１６の中空の翼部２０は電界を遮蔽するために接続部２０ｅ、２０ｆをゲート線１２に近接して配置される。そのため同一ガラス基板６０上にゲート線１２とＣｓ線１６が形成されるＩＰＳ液晶ディスプレイ５１の製造工程においては、ゲート線１２とＣｓ線１６の中空の翼部２０が接触する不良を起こす危険があり得る。しかしＩＰＳ液晶ディスプレイ１では、ゲート線１２とＣｓ線１６の間に第１絶縁層１４が形成されるため、上記接触不良を略完全に防ぐことができる。 Next, since the first insulating layer 14 is sandwiched between the gate line 12 and the Cs line 16 in the IPS liquid crystal display 1 of the present embodiment, it is possible to prevent contact between the gate line 12 and the Cs line 16 that may occur in the manufacturing process. it can. That is, the hollow wing portion 20 of the Cs line 16 has the connection portions 20e and 20f disposed close to the gate line 12 in order to shield the electric field. Therefore, in the manufacturing process of the IPS liquid crystal display 51 in which the gate line 12 and the Cs line 16 are formed on the same glass substrate 60, there is a risk of causing a defect that the hollow wing portion 20 of the gate line 12 and the Cs line 16 is in contact. obtain. However, in the IPS liquid crystal display 1, since the first insulating layer 14 is formed between the gate line 12 and the Cs line 16, the contact failure can be prevented almost completely.

また、ＣＳ線１６の電極部１８を、ゲート線１２とは第１絶縁層１４を介して第１絶縁層上に形成したので、従来のＩＰＳ液晶ディスプレイ１０１及び上記実施形態のＩＰＳ液晶ディスプレイ５１よりも各画素中の電極部１８を小さくすることができる。第１絶縁層により、電極部１８と対向電極２６間の電位を下げようとするゲート線１２等の漏れ電界の影響を、更に小さくできるためである。 Further, since the electrode portion 18 of the CS line 16 is formed on the first insulating layer with the gate line 12 through the first insulating layer 14, the conventional IPS liquid crystal display 101 and the IPS liquid crystal display 51 of the above embodiment are used. Also, the electrode portion 18 in each pixel can be made small. This is because the first insulating layer can further reduce the influence of the leakage electric field of the gate line 12 or the like that lowers the potential between the electrode portion 18 and the counter electrode 26.

このように、上記構造の本発明のＩＰＳ液晶ディスプレイ１は、従来のＩＰＳ液晶ディスプレイ１０１及び上記実施形態のＩＰＳ液晶ディスプレイ５１よりも開口率を上げることができる。又、上記実施形態のＩＰＳ液晶ディスプレイ５１と同様、Ｃｓ線１６をゲート線１２近傍に配置したのでゲート線１２からの漏れ電界をシールドすることができる。従ってゲート線１２からの漏れ電界に起因するディスプレイのフリッカー、焼け付きを抑制することができる。 Thus, the IPS liquid crystal display 1 of the present invention having the above structure can increase the aperture ratio compared to the conventional IPS liquid crystal display 101 and the IPS liquid crystal display 51 of the above embodiment. Further, similarly to the IPS liquid crystal display 51 of the above embodiment, since the Cs line 16 is disposed in the vicinity of the gate line 12, a leakage electric field from the gate line 12 can be shielded. Accordingly, it is possible to suppress display flicker and burn-in caused by a leakage electric field from the gate line 12.

また、本発明のＩＰＳ液晶ディスプレイ１は、第１絶縁層１４を介してＣＳ線１６をゲート線１２の近傍に配置したので、製造工程でＣｓ線１６とゲート線１２が接触する不良を防ぐことができる。従ってＩＰＳ液晶ディスプレイ１の製造の歩留まりを上げることができる。 Further, in the IPS liquid crystal display 1 of the present invention, since the CS line 16 is disposed in the vicinity of the gate line 12 through the first insulating layer 14, the defect that the Cs line 16 and the gate line 12 are in contact in the manufacturing process is prevented. Can do. Therefore, the production yield of the IPS liquid crystal display 1 can be increased.

以上、本発明のＩＰＳ液晶ディスプレイの実施形態について説明したが、本発明は上記２つの実施形態のみに限定されるものではない。Ｃｓ線の中空の翼部はゲート線に近接する部分が必須である以外に形状は限定されないが、開口率を下げないように共通電極及び共通電極線と重畳して配置されるのが望ましい。または、Ｃｓ線の中空の翼部をＩＴＯ（ＩｎｄｉｕｍＴｉｎＯｘｉｄｅ）等の透明素材で形成するのであれば中空である必要はなく、ゲート線に近接する部分を含めてＣｓ線の形状は限定されない。又、Ｃｓ線はＡｌ等で形成されるが、特に材料は限定されない。 As mentioned above, although the embodiment of the IPS liquid crystal display of the present invention has been described, the present invention is not limited to the above two embodiments. The shape of the hollow wing portion of the Cs line is not limited except that a portion close to the gate line is essential, but it is preferable to overlap the common electrode and the common electrode line so as not to lower the aperture ratio. Or if the hollow wing | blade part of Cs line is formed with transparent materials, such as ITO (Indium Tin Oxide), it does not need to be hollow and the shape of Cs line including the part close | similar to a gate line is not limited. The Cs line is formed of Al or the like, but the material is not particularly limited.

絶縁基板は透明かつ絶縁体であればガラス板に限定されず、スイッチング素子もＴＦＴに特に限定されない。又、絶縁層は、ポリマー等で形成されるが、絶縁体であればとくに材料は限定されない。 The insulating substrate is not limited to a glass plate as long as it is transparent and an insulator, and the switching element is not particularly limited to a TFT. The insulating layer is formed of a polymer or the like, but the material is not particularly limited as long as it is an insulator.

本発明のＩＰＳ液晶ディスプレイは、その他の構成部品の種類、材料及びその配置、絶縁層の数も限定されない。本発明には、Ｃｓ線をゲート線の近傍に配置することによってゲート線からの漏れ電界をシールドできるすべてのＩＰＳ液晶ディスプレイが含まれる。 In the IPS liquid crystal display of the present invention, the types of other components, materials and arrangement thereof, and the number of insulating layers are not limited. The present invention includes all IPS liquid crystal displays that can shield a leakage electric field from the gate line by arranging the Cs line in the vicinity of the gate line.

その他、本発明は、その主旨を逸脱しない範囲で当業者の知識に基づき種々の改良、修正、変更を加えた態様で実施できるものである。 In addition, the present invention can be carried out in a mode in which various improvements, modifications, and changes are added based on the knowledge of those skilled in the art without departing from the gist thereof.

液晶テレビやパソコンディスプレイ、その他のＩＰＳ液晶ディスプレイすべてに利用可能である。 It can be used for all types of liquid crystal televisions, personal computer displays, and other IPS liquid crystal displays.

本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第２工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第３工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 3rd process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第４工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 4th process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第５工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 5th process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第６工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 6th process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第７工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 7th process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第８工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 8th process of the manufacturing method of the IPS liquid crystal display in the 2nd Embodiment of this invention. （ａ）共通電極と画素電極の間に印加される、理想的な電位の様子を表す模式断面図である。（ｂ）従来のＩＰＳ液晶ディスプレイ中のゲート線付近における、共通電極と画素電極の間の電位の様子を表す模式断面図である。(A) It is a schematic cross section showing the mode of the ideal electric potential applied between a common electrode and a pixel electrode. (B) It is a schematic cross section showing the electric potential between the common electrode and the pixel electrode in the vicinity of the gate line in the conventional IPS liquid crystal display. （ａ）従来のＩＰＳ液晶ディスプレイ中の電界の様子を表す断面図である。（ｂ）本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイ中の電界の様子を表す断面図である。(A) It is sectional drawing showing the mode of the electric field in the conventional IPS liquid crystal display. (B) It is sectional drawing showing the mode of the electric field in the IPS liquid crystal display in the 2nd Embodiment of this invention. （ａ）従来のＩＰＳ液晶ディスプレイ中のゲート線付近における、画素電極と共通電極間の電位の変化を表すグラフである。（ｂ）本発明の第２の実施形態におけるＩＰＳ液晶ディスプレイ中のゲート線付近における、画素電極と共通電極間の電位の変化を表すグラフである。(A) It is a graph showing the change of the electric potential between a pixel electrode and a common electrode in the gate line vicinity in the conventional IPS liquid crystal display. (B) It is a graph showing the change of the electric potential between a pixel electrode and a common electrode in the gate line vicinity in the IPS liquid crystal display in the 2nd Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第２工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第２工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第２工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第３工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 3rd process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第４工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 4th process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第５工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 5th process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 本発明の第１の実施形態におけるＩＰＳ液晶ディスプレイの製造方法の第６工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 6th process of the manufacturing method of the IPS liquid crystal display in the 1st Embodiment of this invention. 従来のＩＰＳ液晶ディスプレイの製造方法の第２工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 2nd process of the manufacturing method of the conventional IPS liquid crystal display. 従来のＩＰＳ液晶ディスプレイの製造方法の第３工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 3rd process of the manufacturing method of the conventional IPS liquid crystal display. 従来のＩＰＳ液晶ディスプレイの製造方法の第４工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 4th process of the manufacturing method of the conventional IPS liquid crystal display. 従来のＩＰＳ液晶ディスプレイの製造方法の第６工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 6th process of the manufacturing method of the conventional IPS liquid crystal display. 従来のＩＰＳ液晶ディスプレイの製造方法の第７工程におけるＩＰＳ液晶ディスプレイの平面図である。It is a top view of the IPS liquid crystal display in the 7th process of the manufacturing method of the conventional IPS liquid crystal display.

Explanation of symbols

１、５１、１０１：ＩＰＳ液晶ディスプレイ
１０、６０、１１０：ガラス基板
１２、６２、１１２：ゲート線
１４、６４、１１４：第１絶縁層
１６、６６、１１６：ＣＳ線
１８、６８、１１８：電極部
２０、７０：中空の翼部
２０ａ、２０ｂ、２０ｃ、２０ｄ、７０ａ、７０ｂ、７０ｃ、７０ｄ、１２０ａ、１２０ｂ、１２０ｃ、１２０ｄ：軸部
２０ｅ、２０ｆ、７０ｅ、７０ｆ：接続部
１２０：翼部
２２、７２、１２２：第２絶縁層
２４、７４、１２４：シグナル線
２６、７６、１２６：対向電極
２８、７８、１２８：ソース電極
２９、７９、１２９：画素内配線
３０、８０、１３０：ドレイン電極
３２、８２、１３２：ＴＦＴ
３４：第３絶縁層
３５、８５、１３５：スルーホール
３６、８６、１３６：共通電極線
３８、８８、１３８：共通電極
４０、９０、１４０：パッド
４２、９２：画素電極
４４：液晶層
1, 51, 101: IPS liquid crystal display 10, 60, 110: Glass substrate 12, 62, 112: Gate line 14, 64, 114: First insulating layer 16, 66, 116: CS line 18, 68, 118: Electrode Portions 20, 70: Hollow wing portions 20a, 20b, 20c, 20d, 70a, 70b, 70c, 70d, 120a, 120b, 120c, 120d: Shaft portions 20e, 20f, 70e, 70f: Connection portion 120: Wing portion 22 72, 122: second insulating layers 24, 74, 124: signal lines 26, 76, 126: counter electrodes 28, 78, 128: source electrodes 29, 79, 129: intra-pixel wiring 30, 80, 130: drain electrodes 32, 82, 132: TFT
34: third insulating layers 35, 85, 135: through holes 36, 86, 136: common electrode lines 38, 88, 138: common electrodes 40, 90, 140: pads 42, 92: pixel electrodes 44: liquid crystal layer

Claims

An IPS liquid crystal display including an insulating substrate and a first common electrode line formed on the insulating substrate, wherein a pixel surrounded by the first common electrode line is formed on the insulating substrate;
The pixel is
A plurality of gate lines laid in parallel to each other on the insulating substrate;
A first insulating film stacked on the insulating substrate so as to cover the gate line;
A Cs line having a wing portion laid on the first insulating film in parallel with the gate line between the adjacent gate lines;
A second insulating film laminated on the insulating substrate so as to cover the Cs line;
A signal line laid on the second insulating film across the wing portion of the Cs line and crossing the gate line in parallel with each other;
A counter electrode formed on the second insulating film opposite the Cs line between the signal lines;
A source electrode connected to the counter electrode and formed on the second insulating film;
A drain electrode connected to the signal line and formed on the second insulating film;
A switching element comprising the gate line as a gate electrode and the source electrode and the drain electrode;
A third insulating film laminated to cover the signal line, the switching element and the counter electrode;
A pad electrode electrically connected to the counter electrode through a through hole opened in the third insulating film on the counter electrode, and formed on the counter electrode;
A pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode on the third insulating film;
On the third insulating film, a common electrode line laid in parallel with each other to face the gate line;
A common electrode parallel to each other connecting the adjacent common electrode lines on the third insulating film;
Including
An IPS liquid crystal display in which a hollow wing portion of the Cs line is disposed between a pixel electrode and a gate line in the vicinity of the gate line at an end of the hollow wing portion.

An insulating substrate;
A plurality of gate lines laid in parallel to each other on the insulating substrate;
A first insulating film stacked on the insulating substrate so as to cover the gate line;
A Cs line having a hollow wing portion laid on the first insulating film in parallel with the gate line between the adjacent gate lines;
A second insulating film laminated on the insulating substrate so as to cover the Cs line;
A signal line laid on the second insulating film across the wing portion of the Cs line and crossing the gate line in parallel with each other;
A counter electrode formed on the second insulating film opposite the Cs line between the signal lines;
A source electrode connected to the counter electrode and formed on the second insulating film;
A drain electrode connected to the signal line and formed on the second insulating film;
A switching element comprising the gate line as a gate electrode and the source electrode and the drain electrode;
A third insulating film laminated to cover the signal line, the switching element and the counter electrode;
A pad electrode electrically connected to the counter electrode through a through hole opened in the third insulating film on the counter electrode, and formed on the counter electrode;
A pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode on the third insulating film;
On the third insulating film, a common electrode line laid in parallel with each other to face the gate line;
A common electrode parallel to each other connecting the adjacent common electrode lines on the third insulating film;
Including
An IPS liquid crystal display in which a hollow wing portion of the Cs line is disposed between a pixel electrode and a gate line in the vicinity of the gate line at an end of the hollow wing portion.

An insulating substrate;
A plurality of gate lines laid in parallel to each other on the insulating substrate;
A Cs line having a hollow wing portion laid on the insulating substrate parallel to the gate line between the adjacent gate lines;
A second insulating film laminated on the insulating substrate so as to cover the Cs line;
A signal line laid on the second insulating film across the wing portion of the Cs line and crossing the gate line in parallel with each other;
A counter electrode formed on the second insulating film opposite the Cs line between the signal lines;
A source electrode connected to the counter electrode and formed on the second insulating film;
A drain electrode connected to the signal line and formed on the second insulating film;
A switching element comprising the gate line as a gate electrode and the source electrode and the drain electrode;
A third insulating film laminated to cover the signal line, the switching element and the counter electrode;
A pad electrode electrically connected to the counter electrode through a through hole opened in the third insulating film on the counter electrode, and formed on the counter electrode;
A pixel electrode extending in parallel with each other in the direction of the gate line from the pad electrode on the third insulating film;
On the third insulating film, a common electrode line laid in parallel with each other to face the gate line;
A common electrode parallel to each other connecting the adjacent common electrode lines on the third insulating film;
Including
An IPS liquid crystal display in which a hollow wing portion of the Cs line is disposed between a pixel electrode and a gate line in the vicinity of the gate line at an end of the hollow wing portion.

4. The IPS liquid crystal display according to claim 1, wherein the common electrode is formed so as to cover a hollow wing of the Cs line and a signal line. 5.

Preparing an insulating substrate; and
Laying a plurality of gate lines parallel to each other on the insulating substrate;
Laminating a first insulating film on the insulating substrate so as to cover the gate line;
A hollow wing on the first insulating film parallel to the gate line between the adjacent gate lines;
The hollow wing portion laying a Cs line adjacent to the gate line at an end of the hollow wing portion;
Laminating a second insulating film on the insulating substrate so as to cover the Cs line;
Laying a signal line on the second insulating film in parallel with each other across the gate line across the wing portion of the Cs line;
Forming a counter electrode on the second insulating film opposite to the Cs line between the signal lines;
Forming a source electrode on the second insulating film connected to the counter electrode;
Forming a drain electrode connected to the signal line on the second insulating film;
Laminating a third insulating film covering the signal line, the source electrode, the drain electrode and the counter electrode;
Forming a through hole in the third insulating film on the counter electrode;
Electrically connecting to the counter electrode through the through hole and forming a pad electrode on the counter electrode;
Forming on the third insulating film pixel electrodes extending in parallel with each other in the direction of the gate line from the pad electrode;
Laying a common electrode line parallel to each other on the third insulating film so as to face the gate line;
Forming, on the third insulating film, common electrodes parallel to each other for connecting the adjacent common electrode lines;
Only including,
An IPS liquid crystal display in which a hollow wing portion of the Cs line is disposed between the pixel electrode and the gate line by laying the gate line, laying the Cs line, and forming a pixel electrode. Manufacturing method.

Preparing an insulating substrate; and
Laying a plurality of gate lines parallel to each other on the insulating substrate;
Between the adjacent gate lines, there is a hollow wing on the insulating substrate in parallel with the gate line, and the hollow wing is close to the gate line at the end of the hollow wing. Laying a line;
Laminating a second insulating film on the insulating substrate so as to cover the Cs line;
Laying a signal line on the second insulating film in parallel with each other across the gate line across the wing portion of the Cs line;
Forming a counter electrode on the second insulating film opposite to the Cs line between the signal lines;
Forming a source electrode on the second insulating film connected to the counter electrode;
Forming a drain electrode connected to the signal line on the second insulating film;
Laminating a third insulating film covering the signal line, the source electrode, the drain electrode and the counter electrode;
Forming a through hole in the third insulating film on the counter electrode;
Electrically connecting to the pad electrode through the through hole and forming a pad electrode on the counter electrode;
Forming on the third insulating film pixel electrodes extending in parallel with each other in the direction of the gate line from the pad electrode;
Laying a common electrode line parallel to each other on the third insulating film so as to face the gate line;
Forming, on the third insulating film, common electrodes parallel to each other for connecting the adjacent common electrode lines;
Only including,
An IPS liquid crystal display in which a hollow wing portion of the Cs line is disposed between the pixel electrode and the gate line by laying the gate line, laying the Cs line, and forming a pixel electrode. Manufacturing method.