JP4386743B2 - Resonant circuit - Google Patents

Description

  The present invention relates to a resonance circuit in which both ends of a DC power supply are connected to a series circuit of a high side switch and a low side switch, and the high side switch and the low side switch are alternately turned on and off.

  The resonance circuit is shown in FIG. In the resonance circuit, both ends of the DC power source 1 are connected to a series circuit of a high-side switch 2 and a low-side switch 3, and a control circuit 10 is connected to the gate terminals of these switches 2 and 3. Further, in parallel with the low-side switch 3, a series circuit of the primary winding 5 of the transformer 4 and the resonance capacitor 7 which are insulated between the primary and secondary is connected, and the high-side switch 2 and the low-side switch 3 are alternately turned on.・ It is configured to turn off. A current detection resistor 8 is connected in series with the resonance capacitor 7, and a control circuit 10 is connected to one end of the current detection resistor 8.

  A control circuit 10 according to a conventional example is shown in FIG. The control circuit 10 detects a first level detection circuit that detects whether or not the current flowing through the resonance circuit detected by the current detection resistor 8 is less than or equal to a positive detection level, and detects whether or not the current is greater than or equal to a negative detection level. A phase control circuit 11 having a second level detection circuit for performing the control, an oscillator 12 that oscillates a control triangular wave, and a high-side switch 2 and a low-side switch 3 that are turned on and off by the triangular wave oscillated from the oscillator 12. And a pulse forming circuit 13 for generating the control pulse. The first and second level detection circuits constituting the phase control circuit 11 include comparators 61 and 62, NOT circuits 63 and 64, flip-flop circuits 65 and 66, AND circuits 67 and 68, an OR circuit 69, and a switch 70, respectively. It is.

  The current detection resistor 8 is connected to the detection terminal of the comparator 61 constituting the first level detection circuit, and the output terminal of the comparator 61 is connected to the set terminal of the flip-flop circuit 65. The input terminal of the NOT circuit 63 is connected to the output on the high side of the pulse control circuit 13, and the output terminal of the NOT circuit 63 is connected to the reset side of the flip-flop circuit 65. The input terminal of the AND circuit 67 is connected to the output terminal of the comparator 61 on the one hand and to the output terminal of the flip-flop circuit 65 on the other hand.

  On the other hand, the current detection resistor 8 is connected to the detection terminal of the comparator 62 constituting the second level detection circuit, and the output terminal of the comparator 62 is connected to the set terminal of the flip-flop circuit 66. The input terminal of the NOT circuit 64 is connected to the output on the low side of the pulse control circuit 13, and the output terminal of the NOT circuit 64 is connected to the reset side of the flip-flop circuit 66. The input terminal of the AND circuit 68 is connected to the output terminal of the comparator 62 on the one hand and to the output terminal of the flip-flop circuit 66 on the other hand.

The output terminals of the two AND circuits 67 and 68 are connected to respective input terminals of the OR circuit 69. The output terminal of the OR circuit 69 is connected to the control terminal of the switch 70 so as to control the oscillation timing of the oscillator 12 (see, for example, Patent Document 1).
JP-A-9-308243

  As the operation, as shown in the timing chart of FIG. 7, it is detected that the current flowing through the current detection resistor 8 becomes a negative current or zero during the period when the gate signal of the high-side switch 2 is on, and the high-side switch 2 The gate of the low side switch 3 is detected by inverting the gate of the switch 2 and detecting that the current flowing through the current detection resistor 8 becomes a positive current or zero while the gate signal of the low side switch 3 is on. Invert.

  The resonance circuit ideally operates as close as possible to the resonance frequency determined by the inductance of the transformer and the capacitance of the capacitor. In other words, the detection level of the current flowing through the resonance circuit is ideally as close to zero as possible. However, in the conventional detection method, if the detection level is brought close to zero, malfunction due to noise occurs or resonance deviation due to response delay of the control circuit cannot be avoided, and it is difficult to operate at a frequency close to the resonance frequency. Further, when the resonance is lost, the high side switch and the low side switch may be broken due to excessive stress such as di / dt mode.

  The di / dt mode is a mode in which, in a half-bridge resonant circuit, the other switch is turned on while a current is flowing through the body diode of one switch. At this time, when a current is suddenly drawn from the body diode of the switch, an excessive stress may be applied to the switch or the diode to cause destruction.

  In order to prevent breakdown in the di / dt mode, a method is required in which the other switch is not turned on (that is, resonance does not shift) while a current flows through the body diode on one side of the switch.

  The present invention has been made in view of the above problems, and provides a novel resonance circuit that prevents the switch from being broken by preventing the resonance from deviating without malfunctioning.

  In order to solve the above problems, the resonance circuit of the present invention connects both ends of a DC power supply to a series circuit of a high-side switch and a low-side switch, connects a control circuit to the gate terminal of these switches, and connects the low-side switch to the low-side switch. A resonance circuit in which a high-side switch and a low-side switch are alternately turned on and off by connecting a series circuit of a primary winding of a transformer and a resonance capacitor in parallel between the primary and secondary in parallel, A current detection means is connected in series with a resonant capacitor or the low-side switch, the control circuit is connected to one end of the current detection means, and the control circuit is connected to one end of the current detection means. It is detected whether or not the current flowing through the resonance circuit detected by the detection means exceeds the first detection level within the heavy load detection period. When the output level is exceeded, it is further detected that the current flowing through the resonance circuit has dropped below the second detection level set below the first detection level, and the gate signals of the high side switch and the low side switch are detected. Inverted.

  The control circuit includes first level detection means for detecting whether a current flowing through the resonance circuit detected by the current detection means has exceeded a first detection level within a heavy load detection period; and the first detection A phase control means comprising a second level detection means for detecting that the current flowing through the resonance circuit has dropped below the second detection level when the level is exceeded, and turning on the high side switch and the low side switch A pulse forming means for forming a control pulse for turning off is provided.

  The phase control means compares the current flowing through the resonance circuit detected by the current detection means with a positive first detection level, and detects whether the detection current exceeds a first level. And a comparator for comparing the current flowing through the resonance circuit detected by the current detecting means with a negative first detection level, and detecting whether or not the detected current exceeds the first level. A first timing circuit that connects the output terminals of these comparators to the respective input terminals of the OR circuit and matches the output terminal of the OR circuit with the clock waveform formed by the pulse forming means. And a current flowing through the resonance circuit detected by the current detection means is compared with a positive second detection level to detect whether the detection current exceeds a second level. Three comparators A fourth comparator for comparing the current flowing through the resonance circuit detected by the current detection means with a negative second detection level and detecting whether the detection current exceeds the second level; The output terminals of these comparators are connected to the respective input terminals of the NOR circuit, and the output terminals of the NOR circuit are connected to a second timing circuit that matches the timing with the clock waveform formed by the pulse forming means. is there.

  The first detection level and the second detection level are equal.

  According to the present invention, it is possible to create a power supply circuit that does not deviate from resonance, and it is possible to prevent the switch from being destroyed by di / dt. Further, since the frequency up to immediately before the resonance is lost can be used, the efficiency of the power source can be increased, and the resonance circuit can be reduced in size. Further, since the light load state and the heavy load state can be distinguished, it is possible to design a circuit that is unlikely to malfunction, and in addition, there is an effect that the circuit design can be simplified.

  A circuit diagram of the best mode for carrying out the invention is shown in FIG. In the resonance circuit shown in FIG. 1, both ends of the DC power source 1 are connected to a series circuit of a high-side switch 2 and a low-side switch 3, and a control circuit 10 is connected to the gate terminals of these switches 2 and 3. Further, in parallel with the low-side switch 3, a series circuit of the primary winding 5 of the transformer 4 and the resonance capacitor 7 which are insulated between the primary and secondary is connected, and the high-side switch 2 and the low-side switch 3 are alternately turned on.・ It is configured to turn off. A current detection resistor 8 is connected in series with the resonance capacitor 7, and a control circuit 10 is connected to one end of the current detection resistor 8.

  The present invention detects whether or not the current flowing through the resonance circuit has exceeded the first detection level within the heavy load detection period, and if the current exceeds the first detection level, the current flowing through the resonance circuit is further reduced to the first level. It is characterized in that the gate signals of the high-side switch 2 and the low-side switch 3 are inverted by detecting that the second detection level is set below the detection level. In order to reproduce this feature, the control circuit 10 is configured as follows.

  The control circuit 10 includes a phase control circuit 11, and this phase control circuit 11 is provided with first level detection means and second level detection means. The first level detection means is means for detecting whether or not the current flowing through the resonance circuit detected by the current detection resistor 8 has exceeded the first detection level within the heavy load detection period. The second level detection means is means for detecting that the current flowing through the resonance circuit further falls below the second detection level when the first detection level is exceeded. In addition, the control circuit 10 is provided with a pulse forming circuit 13 that forms control pulses for turning on and off the high-side switch 2 and the low-side switch 3.

  By configuring as described above, the following operations are performed. First, when the high-side switch 2 is turned on and a current equal to or higher than the first detection level flows through the current detection resistor 8, the first detection level signal is transmitted to the control pulse forming circuit 13 and the clock signal is held. Subsequently, after a current equal to or higher than the first detection level flows through the current detection resistor 8, when the current decreases below the second detection level, a second detection level signal is transmitted to the control pulse forming circuit 13, and oscillation occurs. Shift the timing. As a result, a power supply circuit that does not deviate from resonance can be created, and destruction of the switch due to di / dt can be prevented. Further, the frequency up to immediately before the resonance is lost can be used, so that the power source can be highly efficient and downsized. Furthermore, a light load state and a heavy load state can be distinguished.

  On the other hand, when the low-side switch 3 is turned on, a current opposite to that when the high-side switch 2 is turned on flows through the current detection resistor 8. When the low-side switch 3 is turned on and a current lower than the negative first detection level (a negative current, which is larger than the detection level in absolute value) flows through the current detection resistor 8, the first current is supplied to the control pulse forming circuit 13. A detection level signal is transmitted and a clock signal is held. Subsequently, when a current lower than the first negative detection level flows through the current detection resistor 8 and then a current equal to or higher than the second detection level flows, a second detection level signal is transmitted to the control pulse forming circuit 13 to oscillate. Shift the timing. As a result, a power supply circuit that does not deviate from resonance can be created, and destruction of the switch due to di / dt can be prevented.

  FIG. 2 shows a circuit diagram of a first embodiment of the control circuit 10 according to the resonance circuit of the present invention. The control circuit 10 includes a phase control circuit 11, an oscillator 12, and a pulse forming circuit 13. The phase control circuit 11 includes two positive and negative first level detecting means and two positive and negative second level detecting means. The first level detection means is means for detecting whether or not the current detected by the current detection resistor 8 exceeds the first detection level within the heavy load detection period. The second level detection means is means for detecting that the current flowing through the resonance circuit is further reduced from the second detection level when the first detection level detected by the first level detection means is exceeded. . The pulse forming circuit 13 is a circuit that forms a control pulse for turning on and off the high-side switch 2 and the low-side switch 3 from a pulse oscillated by the oscillator 12.

  The positive first level detection means and the positive second level detection means related to the phase control circuit 11 are means for controlling the ON period of the high-side switch 2. The positive first and positive second level detection means include a first comparator 21 and a third comparator 23. The first comparator 21 compares the current detected by the current detection resistor 8 with a positive first detection level, and detects whether or not the detected current exceeds the first level. The third comparator 23 compares the current detected by the current detection resistor 8 with a positive second detection level, and detects whether or not the detected current has fallen below the second level. The output terminal of the first comparator 21 is connected to the input terminal of the OR circuit 25, and the output terminal of the second comparator 23 is connected to the input terminal of the NOR circuit 26.

  The negative first level detection means and the negative second level detection means related to the phase control circuit 11 are means for controlling the ON period of the low-side switch 3. The negative first and negative second level detection means include a second comparator 22 and a fourth comparator 24. The second comparator 22 compares the current detected by the current detection resistor 8 with the negative first detection level, and determines whether or not the detection current is lower than the first level (it is a negative current and has an absolute value). Then, it is detected whether or not it exceeds. The fourth comparator 24 compares the current detected by the current detection resistor 8 with a negative second detection level, and detects whether or not the detection current exceeds the second level. The output terminal of the second comparator 22 is connected to the input terminal of the OR circuit 25, and the output terminal of the fourth comparator 24 is connected to the input terminal of the NOR circuit 26.

  The pulse forming circuit 13 is provided with a first comparator 41 that determines the heavy load detection period. The first timing circuit is composed of a flip-flop circuit 27, and the second timing circuit is composed of a flip-flop circuit 28. The output terminal of the OR circuit 25 is connected to the data terminal of the first flip-flop circuit 27 that synchronizes with the heavy load detection period, and the output terminal of the NOR circuit 26 is synchronized with the clock waveform formed by the pulse forming circuit 13. The second flip-flop circuit 28 is connected to the clock terminal.

  The oscillator 12 includes a phototransistor 31, and the phototransistor 31 is connected via a transistor 33 between a DC power supply terminal and the ground. In addition to the transistor 33, a transistor 34 is provided. The emitter of the transistor 34 is connected to a power supply terminal, and the collector of the transistor 34 is connected to the ground via a capacitor 35 for generating a triangular wave. A resistor 32 is connected in parallel with the phototransistor 31.

  The pulse forming circuit 13 includes two comparators 41 and 42, three AND circuits 43, 46, and 47, a flip-flop circuit 45, a NOT circuit 48, and a switch 49. A detection terminal of a first comparator 41 is connected to the oscillator 12, and the first comparator 41 transmits a heavy load detection period as a signal to the first flip-flop circuit 27. Similarly, the reference terminal of the second comparator 42 is connected to the collector of the switch 49 constituting the oscillator 12 and the phase control circuit 11 via the current source 40. A switch 44 is connected to the detection terminal of the comparator 42, and the switch 44 is connected to reference voltage portions V1 and V2 having different potential differences. The output terminal of the second comparator 42 is connected to the input terminal of the AND circuit 43. The other input terminal of the AND circuit 43 is connected to the inverting output terminal of the second flip-flop circuit 28 provided in the phase control circuit 11.

  The output terminal of the AND circuit 43 is connected to the control terminal of the voltage switching switch 44 so that the switch 44 is switched according to the output of the AND circuit 43. The output terminal of the AND circuit 43 is connected to the input terminal of the NOT circuit 48 and the flop flip circuit 45. Further, a clear terminal of the first and second flip-flop circuits 27 and 28 constituting the phase control circuit 11 is connected to an input terminal of the NOT circuit 48, and a switch 49 in which an output terminal of the NOT circuit 48 is constituted by a transistor. Connected to the base. The collector of the switch 49 is connected to the reference terminal of the comparator 42 via the current source 40. The output terminal of the AND circuit 43 is connected to one input terminal of the AND circuits 46 and 47. The other input terminal of the second AND circuit 46 is connected to the output terminal of the flip-flop circuit 45, and the other input terminal of the third AND circuit 47 is connected to the phase inversion output terminal of the flip-flop circuit 45. is there. The high-side switch 2 is connected to the output terminal of the second AND circuit 46 via the level shift circuit 9, and the low-side switch 3 is connected to the output terminal of the third AND circuit 47.

  The reference voltage V3 is also connected to the first comparator 41. The voltage of the reference voltage section is set so that V2> V3> V1. The output terminal of the first comparator 41 is connected to the clock terminal of the first flip-flop circuit 27 of the phase control circuit 11.

The resonant circuit configured as described above operates as follows. A timing chart of this resonance circuit is shown in FIG. First, when the high-side switch 2 is turned on and the voltage of the capacitor Ct of the oscillator reaches the reference voltage V3 of the first comparator 41, if a current of E3 or more flows through the current detection resistor 8, the first comparison The device 21 is turned on. On the other hand, the second comparator 22 is off. When the signal from the first comparator 21 is transmitted to the OR circuit 25, the OR circuit 25 is turned on. As a result, a signal is input to the data terminal of the first flip-flop circuit 27. Next, since the signal of the heavy load detection period is input from the comparator 41 to the clock terminal of the flip-flop circuit 27 and the output signal of the flip-flop circuit 27 is held, the input signal of the data terminal of the flip-flop circuit 28 is held. Is done.

When a current equal to or higher than E3 set to an arbitrary set level flows through the current detection resistor 8 and then decreases to E1 set lower than E3, the first comparator 21 is turned off and the third comparator 23 is turned off. Also turn off. A signal from the third comparator 23 is transmitted to the NOR circuit 26. At this time, since the fourth comparator 24 is off, the NOR circuit 26 is turned on. As a result, a signal is output from the phase inversion output terminal of the second flip-flop circuit 28, and the signal is transmitted to the first AND circuit 43 of the pulse forming circuit 13, thereby shifting the oscillation timing. As a result, a power supply circuit that does not deviate from resonance can be created, and destruction of the switch due to di / dt can be prevented. Further, the frequency up to immediately before the resonance is lost can be used, and the efficiency of the power source can be improved. Further, it is possible to distinguish between a light load state and a heavy load state.

  On the other hand, when the low-side switch 3 is turned on, a current opposite to that when the high-side switch 2 is turned on flows through the current detection resistor 8. When the low-side switch 3 is turned on and a current equal to or lower than E4 flows through the current detection resistor 8, the second comparator 22 is turned on. On the other hand, the fourth comparator 24 is off. When the signal from the second comparator 22 is transmitted to the OR circuit 25, the OR circuit 25 is turned on. As a result, a signal is input to the data terminal of the first flip-flop circuit 27. Next, when a signal is input from the first comparator 41 to the clock terminal of the flip-flop circuit 27, the output of the flip-flop circuit 27 is held, and the input signal is held at the data terminal of the flip-flop circuit 28.

When a current equal to or lower than E4 flows after a current equal to or lower than E4 flows through the current detection resistor 8, the second comparator 22 is turned off, and then the fourth comparator 24 is turned on. A signal from the fourth comparator 24 is transmitted to the NOR circuit 26, and the NOR circuit 26 is turned on. As a result, a signal is output from the phase inversion output terminal of the second flip-flop circuit 28, and the signal is also transmitted to the first AND circuit 43 of the pulse forming circuit 13, thereby shifting the oscillation timing. This makes it possible to create a power supply circuit that does not deviate from resonance, and to prevent destruction of the switch due to di / dt . Further, the frequency up to immediately before the resonance is lost can be used, and the efficiency of the power supply can be increased. Further, it is possible to distinguish between a light load state and a heavy load state.

  Note that the control circuit 10 shown in this embodiment can be integrated as an integrated circuit. When the control circuit 10 is incorporated as an integrated circuit, a first detection level and a second detection level lower than the first detection level are provided, and the current flowing through the resonance circuit detected by the current detection resistor 8 is overlapped. It is detected whether or not the first detection level is exceeded within the load detection period, and when the first detection level is exceeded, it is further detected that the current flowing through the resonance circuit has decreased from the second detection level. When configured, the control circuit 10 having the same operation as this embodiment can be obtained.

  FIG. 4 shows a circuit diagram of a second embodiment of the control circuit 10 according to the resonance circuit of the present invention. The control circuit 10 includes a phase control circuit 11, an oscillator 12, and a pulse forming circuit 13. First, in this embodiment, unlike the first embodiment, the first detection level and the second detection level are made equal. The phase control circuit 11 includes a first comparator 51. The first comparator 51 compares the current flowing through the resonance circuit detected by the current detection resistor 8 with a positive detection level, and detects whether or not the detection current exceeds the positive detection level. Subsequently, the phase control circuit 11 includes a second comparator 52. The second comparator 52 compares the current flowing through the resonance circuit detected by the current detection resistor 8 with a negative detection level, and detects whether or not the detection current exceeds the negative detection level. The output terminals of the first comparator 51 and the second comparator 52 are connected to the input terminal of the AND circuit 53. A timing circuit that synchronizes the timing with the heavy load detection period formed by the first comparator 41 includes a flip-flop circuit 54. The output terminal of the AND circuit 53 is connected to the clock terminal of the flip-flop circuit 54.

  The oscillator 12 includes a phototransistor 31, and the phototransistor 31 is connected via a transistor 33 between a DC power supply terminal and the ground. A transistor 34 is provided in addition to the transistor 33. The emitter of the transistor 34 is connected to a power supply terminal, and the collector is connected to the ground via a capacitor 35 for generating a triangular wave. A resistor 32 is connected in parallel with the phototransistor 31.

  The pulse forming circuit 13 includes two comparators 41 and 42, three AND circuits 43, 46 and 47, a flip-flop circuit 45, two NOT circuits 48 and 55, and a switch 49. The detection terminal of the comparator 41 is connected. Similarly, the reference terminal of the second comparator 42 is connected to the collector of the switch 49 constituting the oscillator 12 and the phase control circuit 11 via the current source 40. A switch 44 is connected to the detection terminal of the comparator 42, and the switch 44 is connected to reference voltage portions V1 and V2 having different potential differences. The output terminal of the second comparator 42 is connected to the input terminal of the AND circuit 43. The other input terminal of the AND circuit 43 is connected to the phase inversion output terminal of the flip-flop circuit 54 provided in the phase control circuit 11.

  The output terminal of the AND circuit 43 is connected to the control terminal of the voltage switching switch 44 so that the switch 44 is switched according to the output of the AND circuit 43. The output terminal of the AND circuit 43 is connected to the input terminal of the NOT circuit 48 and the flip-flop circuit 45. The output terminal of the NOT circuit 48 is connected to the base of a switch 49 formed of a transistor. The collector of the switch 49 is connected to the reference terminal of the comparator 42 via the current source 40. The output terminal of the AND circuit 43 is connected to one terminal of the AND circuits 46 and 47. The other terminal of the second AND circuit 46 is connected to the output terminal of the flip-flop circuit 45, and the other terminal of the third AND circuit 47 is connected to the phase inversion output terminal of the flip-flop circuit 45. The high-side switch 2 is connected to the output terminal of the second AND circuit 46 via the level shift circuit 9, and the low-side switch 3 is connected to the output terminal of the third AND circuit 47.

  A reference voltage unit V3 is connected to the first comparator 41. The voltage of the reference voltage section is set so that V2> V3> V1. The input terminal of the second NOT circuit 55 is connected to the output terminal of the first comparator 41. The output terminal of the NOT circuit 55 is connected to the clear terminal of the flip-flop circuit 54 of the phase control circuit 11.

  The resonant circuit configured as described above operates as follows. A timing chart of this resonance circuit is shown in FIG. First, when the high-side switch 2 is turned on and a current equal to or greater than E1 flows through the current detection resistor 8, the first comparator 51 is turned off, and this signal is transmitted to the AND circuit 53. At this time, since the second comparator 52 is on, the AND circuit 53 is off. Next, an ON signal is output from the comparator 41 at the timing of the heavy load detection period, and this signal is input to the NOT circuit 55. As a result, the output of the NOT circuit 55 is turned off, and the clear signal of the flip-flop circuit 54 is released. When the current flowing through the current detection resistor 8 decreases below E1, the comparator 51 is turned on and the AND circuit 53 is turned on. An OFF signal is output from the terminal, the clock signal of the control pulse forming circuit 13 is inverted, and the oscillation timing is shifted. As a result, a power supply circuit that does not deviate from resonance can be created, the switch can be prevented from being destroyed by di / dt, and the frequency up to immediately before the resonance deviates can be used, so that the efficiency of the power supply can be improved. Further, it is possible to distinguish between a light load state and a heavy load state.

  On the other hand, when the low-side switch 3 is turned on, a current opposite to that when the high-side switch 2 is turned on flows through the current detection resistor 8. When the low-side switch 3 is turned on and a current equal to or less than E2 (current in absolute value) flows through the current detection resistor 8, the second comparator 52 is turned off. On the other hand, since the first comparator 51 is on, the AND circuit 25 is turned off. Next, an ON signal is output from the comparator 41 at the timing of the heavy load detection period, and this signal is input to the NOT circuit 55. Since the output of the NOT circuit 55 is turned off, the clear signal of the flip-flop circuit 54 is canceled. When the current flowing through the current detection resistor 8 becomes equal to or greater than E2 (decreases as current), the comparator 52 is turned on and the AND circuit 53 is turned on, so that the clock signal is input to the flip-flop circuit 54 and the flip-flop An off signal is output from the phase inversion output terminal of the circuit 54, the clock signal of the control pulse forming circuit 13 is inverted, and the oscillation timing is shifted. As a result, a power supply circuit that does not deviate from resonance can be created, the switch can be prevented from being destroyed by di / dt, and the frequency up to immediately before the resonance deviates can be used, so that the efficiency of the power supply can be improved. Further, it is possible to distinguish between a light load state and a heavy load state.

  Note that the control circuit 10 shown in this embodiment can be integrated as an integrated circuit. When the control circuit 10 is incorporated in an integrated circuit, a detection level is provided to detect whether or not the current flowing through the resonance circuit detected by the current detection resistor 8 has exceeded the detection level within the heavy load detection period. If it is exceeded, it is possible to obtain a control circuit 10 that operates in the same manner as in this embodiment by further detecting that the current flowing through the resonance circuit has fallen below the detection level.

  The resonance circuit of the present invention can create a power supply circuit that does not deviate from resonance, and can prevent destruction of the switch due to di / dt. Further, the frequency up to immediately before the resonance is lost can be used, and the efficiency and size of the power source can be increased. Further, since the light load state and the heavy load state can be distinguished, it is difficult to malfunction, and the power supply design can be simplified.

It is a circuit diagram of the resonant circuit which concerns on this invention. It is the circuit diagram which showed the principal part of the 1st Example which concerns on this invention resonance circuit. 2 is a timing chart in the embodiment shown in FIG. It is the circuit diagram which showed the principal part of the 2nd Example which concerns on this invention resonant circuit. 4 is a timing chart in the embodiment shown in FIG. It is the circuit diagram which showed the principal part of the prior art example in this invention resonant circuit. 7 is a timing chart of the conventional example shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 High side switch 3 Low side switch 4 Transformer 5 Primary winding 6 of transformer 4 Secondary winding 7 of transformer 4 Resonant capacitor 8 Current detection resistor 9 Level shift circuit 10 Control circuit 11 Phase control circuit 12 Oscillator 13 Pulse formation Circuits 21, 22, 23, 24 Comparator 25 OR circuit 26 NOR circuit 27, 28 Flip-flop circuit 31 Phototransistor 32 Resistor 33, 34 Transistor 35 Triangle wave generating capacitor 40 Current source 41, 42 Comparators 43, 46, 47 AND Circuit 44 switch 45 flip-flop circuit 48 NOT circuit 49 switch 51, 52 comparator 53 AND circuit 54 flip-flop circuit 55 NOT circuit 61, 62 comparator 63, 64 NOT circuit 65, 66 flip-flop circuit 67, 68 AND circuit 69 OR circuit 70 switch

Claims (4)

Connect both ends of the DC power supply to the series circuit of the high-side switch and low-side switch, connect the control circuit to the gate terminal of these switches, and in parallel with the low-side switch, the transformer between the primary and secondary is insulated A resonance circuit in which a high-side switch and a low-side switch are alternately turned on / off by connecting a series circuit of a primary winding and a resonance capacitor, and one of the high-side switch and the low-side switch is turned on. A heavy load detection period which is a predetermined period after switching, a current detection means is connected in series with the resonant capacitor or the low-side switch, and the control circuit is connected to one end of the current detection means; the current flowing through the resonant circuit detected by said current detecting means, a first detection in said heavy load detection period Detecting whether exceeds bell, the current after the first detection level over current flows set at least any set level detection means, second detection set below the first detection level When the current decreases below the level, the second detection level signal is transmitted to pulse forming means for forming a control pulse for alternately turning on and off the high-side switch and the low-side switch, thereby shifting the oscillation timing. Resonant circuit characterized by that. The control circuit detects whether or not the current flowing through the resonance circuit detected by the current detection means exceeds a first detection level set to an arbitrary set level or higher within the heavy load detection period. A phase control means comprising: a level detection means; and a second level detection means for detecting that the current flowing through the resonance circuit has dropped below the second detection level when the first detection level is exceeded. The resonance circuit according to claim 1, wherein the resonance circuit is provided. The phase control means compares the current flowing through the resonance circuit detected by the current detection means with a positive first detection level, and detects whether the detection current exceeds a first level. And a comparator for comparing the current flowing through the resonance circuit detected by the current detecting means with a negative first detection level, and detecting whether the detected current has fallen below the first level. A first timing circuit that connects the output terminals of these comparators to the respective input terminals of the OR circuit and matches the output terminal of the OR circuit with the clock waveform formed by the pulse forming means. And a current flowing through the resonance circuit detected by the current detection means is compared with a positive second detection level to detect whether the detection current has fallen below the second level. Third A fourth comparison for comparing the current flowing through the resonance circuit detected by the current detection means with a negative second detection level and detecting whether the detection current exceeds the second level. And connecting the output terminals of these comparators to the respective input terminals of the NOR circuit, and setting the output terminal of the NOR circuit to a second timing circuit that matches the timing with the clock waveform formed by the pulse forming means. The resonance circuit according to claim 2, wherein the resonance circuit is connected. 4. The resonance circuit according to claim 1, wherein the first detection level and the second detection level are equal.

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