JP4383945B2 - Alignment method, exposure method, and exposure apparatus - Google Patents

Description

  The present invention relates to a relative position between a fine electronic circuit pattern such as an IC, LSI, VLSI or the like formed on a reticle surface as a first object and a wafer as a second object, for example, in an exposure apparatus for manufacturing a semiconductor. The present invention relates to an alignment method for performing alignment (alignment), an exposure method using the alignment method, and an exposure apparatus. In particular, alignment is performed at high speed and with high accuracy in a situation in which WIS (Wafer Induced Shift) that is a wafer process error can occur. Regarding the method.

  Along with miniaturization and high density of circuits, a projection exposure apparatus for manufacturing semiconductor devices is required to be able to project and expose a circuit pattern on a reticle (mask) surface on a wafer surface with high resolution. The projection resolution of the circuit pattern depends on the numerical aperture (NA) of the projection optical system and the exposure wavelength. Therefore, as a method of increasing the resolution, a method of increasing the NA of the projection optical system or a method of shortening the exposure light wavelength is employed. Regarding the latter method, the exposure light source is shifting from g-line to i-line, and further from i-line to excimer laser. In the excimer laser, exposure apparatuses having oscillation wavelengths of 248 nm and 193 nm have already been put into practical use. Currently, a 157 nm vacuum ultraviolet (VUV) exposure method with a shorter oscillation wavelength and an extreme ultraviolet (EUV) exposure method with a wavelength of 13 nm are considered as candidates for the next generation exposure method. Has been.

  In addition, semiconductor device manufacturing processes are diversified. As a flattening technique that solves the problem of insufficient depth of focus of an exposure apparatus, a technique such as a W-CMP (Tungsten Chemical Mechanical Polishing) process, or a Cu developed with recent miniaturization of LSIs is known. Dual damascene wiring technology, a technology using a low dielectric constant (Low-k) material for an interlayer insulating layer, and the like.

  There are a wide variety of semiconductor device structures and materials. For example, P-HEMT (Pseudomorphic High Mobility Transistor) and M-HEMT (Metamorphe-HEMT) proposed by combining compounds such as GaAs and InP, as well as HBT (Heterojunction) using SiGe, SiGeC, etc. Has been.

  On the other hand, it is also required to align the reticle and the wafer on which the circuit pattern on the reticle is projected with high accuracy, and the required accuracy is about 1/3 of the circuit line width. For example, the required accuracy in a circuit design with a line width of 180 nm is 60 nm.

  As an alignment method in an exposure apparatus, for example, there is one disclosed in Patent Document 1. In this system, an optical image of an alignment mark formed on a wafer is imaged on an image sensor such as a CCD camera, and the electrical signal is image-processed using various parameters to detect the position of the mark on the wafer. Is going.

In general, when aligning a reticle and a wafer, the major factors that degrade the alignment accuracy of the wafer include non-uniformity in the thickness of the resist applied on the wafer alignment mark and asymmetry in the step shape of the alignment mark. Is mentioned. Such an alignment error factor caused by the wafer is called WIS (Wafer Induced Shift).
JP-A-6-151274

  Improving the “overlapping accuracy” of a wafer as one of the three major performances of an exposure apparatus is an important issue in improving the performance of semiconductor elements and in manufacturing yield. However, due to the introduction of a special semiconductor manufacturing technique such as a W-CMP process, there is a problem that a defect is generated in the alignment mark, that is, a WIS (process error) occurs although the structure of the circuit pattern is good.

  It is considered that one of the causes of the occurrence of WIS is that the difference between the line width of the circuit pattern and the line width of the alignment mark is increased with the miniaturization of the circuit pattern. In other words, the generation of WIS is optimized for circuit patterns with fine line widths in process conditions such as film formation, etching, and CMP, and alignment marks with large line widths (line widths of 0.6 to 4.0 μm) are used. This is due to not being optimized.

  For example, over-polishing of alignment marks in the W-CMP process is an example. In this case, an alignment mark having an optimum line width is determined by preparing an alignment mark having a plurality of line widths and evaluating the exposure, or by changing the processing conditions of the process while determining the optimum condition for both the alignment mark and the circuit pattern. The conditions are determined so that

  Further, a method of exposing an initial several wafers in a lot in a certain process and determining an offset amount based on an inspection result of an overlay inspection apparatus is generally used as a method for improving overlay accuracy. This method is effective when the WIS of each wafer is substantially constant between lots or within lots. However, the WIS may differ between lots in the same process, or the WIS may differ from wafer to wafer in the same lot. The above-described method has a problem in that the overlay accuracy is deteriorated because the change in WIS after the offset amount is determined for the first few wafers of the first lot is not considered.

  The present invention has been made in view of the above circumstances, an alignment method capable of aligning a reticle and a wafer with high speed and high accuracy even when WIS occurs, an exposure method using the method, and It is an exemplary object to provide an exposure apparatus.

In order to achieve the above object, an alignment method as an exemplary aspect of the present invention includes a step of detecting an alignment mark on a substrate to obtain an alignment signal, and a waveform evaluation value indicating the orderliness of the waveform of the alignment signal. Calculating based on the alignment signal, calculating the in-plane evaluation value indicating the distribution of the waveform evaluation value in the substrate plane based on the waveform evaluation value, and inspecting the alignment state of the substrate by the inspection apparatus calculating a step, a step of associating the inspection result and the substrate surface evaluation values, from the board plane evaluation value, the alignment correction amount based on the correlation between the test results and the substrate surface evaluation value associated with the a method, characterized by having a.

  An exposure method according to another exemplary aspect of the present invention is an exposure method in which an alignment mark on a substrate is used to align the reticle and the substrate to expose a pattern on the reticle onto the substrate, the alignment method described above. The step of calculating the alignment correction amount by the step, the step of aligning the reticle and the substrate based on the correction amount, and the step of projecting the pattern on the reticle onto the substrate after the alignment are characterized.

  The waveform evaluation value may indicate the symmetry of the waveform of the alignment mark signal, or may indicate the contrast of the waveform of the alignment mark signal. The substrate in-plane evaluation value may be an index of the rate of change of the waveform evaluation value in the substrate surface. The inspection result may be a magnification component of the substrate or a rotation component of the substrate.

    An exposure apparatus according to still another exemplary aspect of the present invention is an exposure apparatus that performs alignment between a reticle and a substrate using alignment marks on the substrate to expose a pattern on the reticle onto the substrate, and the position of the reticle. A reticle stage that adjusts the position of the substrate, a substrate stage that adjusts the position of the substrate, a detection optical system that detects alignment marks on the substrate, and a waveform evaluation value that indicates the orderliness of the waveform of the alignment signal acquired by the detection optical system And the in-board evaluation value indicating the distribution of the waveform evaluation value in the substrate surface, and the correlation between the inspection result indicating the alignment state of the substrate obtained by the inspection apparatus and the in-board evaluation value A calculation unit for calculating an alignment correction amount based on the relationship, and a reticle stage and a substrate stage based on the alignment correction amount. And having a control unit.

  The exposure apparatus may further include a storage unit that stores a plurality of correlations calculated for a plurality of different exposure apparatuses or stores a plurality of correlations calculated for a plurality of different semiconductor manufacturing processes. Good.

  According to still another exemplary aspect of the present invention, there is provided a device manufacturing method including a step of projecting a pattern onto a substrate by the exposure apparatus, and a step of performing a predetermined process on the substrate subjected to the projection exposure. To do.

  Other objects and further features of the present invention will be made clear by embodiments described below with reference to the accompanying drawings.

According to the present invention, highly accurate alignment can be performed even in a situation where WIS (Wafer Induced Shift), which is a wafer process error, can occur.
In particular, even when the WIS is different between lots or wafers within the same lot, the overlay accuracy can be improved. As a result, it is possible to perform exposure projection of a highly accurate pattern and manufacture a device such as a high-performance semiconductor chip.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 is a block diagram showing a schematic configuration of a semiconductor exposure apparatus (hereinafter referred to as an exposure apparatus) 1. The exposure apparatus 1 includes an illumination optical system 615, a reticle stage 614 that holds a reticle 10, a projection optical system 615, a wafer chuck 612 that holds a wafer (substrate) 20, a wafer stage (substrate stage) 611, an alignment unit (detection optical system). 617, which is roughly configured to include a control unit 640 for controlling the overall operation and a calculation unit 660. The exposure apparatus 1 guides the exposure light from the laser light source unit 602 to the reticle 10 by the illumination optical system 615 and exposes and projects the pattern of the reticle 10 onto the wafer 20 by the projection optical system 613.

  Laser light (exposure light) from the laser light source unit 602 is shaped by the illumination optical system 615 to illuminate the pattern of the reticle 10. The reticle 10 is held on a reticle stage 614 that can move in the reticle scanning direction within the XY plane in FIG. The projection optical system 613 having a predetermined reduction magnification projects the pattern of the reticle 10 illuminated via the illumination optical system 615 onto one shot area of the wafer 20. Thereby, the shot area of the wafer 20 is exposed based on the pattern of the reticle 10.

  A resist (photoconductor) is applied to the wafer 20 and a latent image is formed by exposure. The wafer 20 is placed on a wafer stage 611 via a wafer chuck 612. Reference numeral 617 denotes an alignment unit (alignment scope) that can detect the alignment mark 30 (see FIGS. 3 and 4A) formed on the wafer 20.

  The wafer stage 611 can move and position the wafer 20 in the XYZ axial directions and the rotational directions around the respective axes. The projection optical system 613 can be focused on the wafer 20 by controlling the positioning of the wafer stage 611 in the Z-axis direction. Note that the movement and positioning control of the reticle stage 614 and the wafer stage 611 are performed based on the position and orientation information of the stages 611 and 614 measured by a sensor (not shown).

  Reticle stage 614 and wafer stage 611 are each connected to control unit 640. The reticle stage 614 and the wafer stage 611 exchange data in real time via the control unit 640, thereby enabling synchronous control thereof. Similarly, the laser light source unit 602 is connected to the control unit 640, and the timing of light emission and the movement of the stages 614 and 611 can be controlled synchronously.

  Hereinafter, the principle of alignment mark position measurement will be described with reference to FIG. FIG. 3 is a block diagram showing a schematic configuration of the alignment unit 617. The illumination light from the light source 918 is reflected by the beam splitter 919, passes through the lens 920, and illuminates the alignment mark 30 on the wafer 20. The diffracted light from the alignment mark 30 passes through the lens 920, the beam splitter 919, and the lens 921, is divided by the beam splitter 922, and is received by the CCD sensors 923 and 924, respectively.

  The alignment mark 30 is magnified by an imaging magnification of about 100 times by the lenses 920 and 921, and is imaged on the CCD sensors 923 and 924. The CCD sensors 923 and 924 are for measuring the position of the alignment mark 30 in the X direction and for measuring the position of the alignment mark 30 in the Y direction, respectively. It is installed with a degree of rotation.

  Hereinafter, the measurement principle in the X direction will be described, but the measurement principle in the Y direction is substantially the same except that X and Y are interchanged. As shown in FIG. 4 (a), the alignment mark 30 of the present embodiment is a strip-shaped position detection mark element (hereinafter referred to as 4 μm in the alignment measurement direction (X direction) and 30 μm in the non-measurement direction (Y direction). A plurality of mark elements 32) are arranged at predetermined intervals in the X direction. In the present embodiment, the distance L is 20 μm, and the number is four. As shown in FIG. 4B, the cross-sectional structure of the mark element 32 has a concave shape by etching, and a resist (not shown) is applied on the mark element 32.

  FIG. 4C shows an alignment signal obtained by photoelectrically converting the reflected light obtained by irradiating the plurality of mark elements 32 with illumination light by the CCD sensors 922 and 923. Appropriate signal processing is performed on the alignment signal including signals from the four mark elements, and the respective element positions (M1, M2, M3, and M4 in order from the left in FIG. 4C) are detected.

  Next, an alignment operation procedure for controlling the alignment (alignment) between the reticle 10 and the wafer 20 will be described. First, as a preparation stage for the apparatus setting job, the wafer 20 and the reticle 10 are set in the semiconductor exposure apparatus 1. The apparatus setting job is a process of projecting and exposing the circuit pattern of the reticle 10 on the wafer 20. An alignment parameter (referred to as an apparatus setting job parameter) necessary for alignment between the wafer 20 and the reticle 10 in the apparatus setting job is set to a predetermined value. Based on the apparatus setting job parameters, the alignment unit 617 and the wafer stage 611 that holds the wafer 20 are driven to measure information on the position and the like. The apparatus setting job parameter may be stored in a memory (storage unit) 650 in the semiconductor exposure apparatus 1.

  The semiconductor exposure apparatus 1 is provided with a laser interferometer (not shown) for measuring the position of the wafer stage 611. Based on the position information of the alignment mark 30 from the alignment unit 617 and the output of the laser interferometer, the wafer position (shift amount) on the wafer stage 611, the wafer rotation amount, the wafer magnification, and the like are measured.

  This measurement is performed using an AGA (Advanced Global Alignment) method. AGA selects a part of the exposure area from multiple exposure areas on the wafer as a sample shot for alignment, measures the position of the selected sample shot, and performs statistical processing, removal of abnormal values, etc. This is a position detection method for obtaining the wafer magnification, wafer rotation, and wafer shift amount of the entire wafer (total exposure area).

[Embodiment 1]
An alignment method according to Embodiment 1 of the present invention will be described with reference to the flowchart shown in FIG. Various operations described below, for example, calculation of waveform evaluation values, calculation of evaluation values in the wafer surface, calculation of correlation between in-wafer surface inspection results and evaluation values in the wafer surface, and an alignment correction amount based on the correlation The calculation and the like are all performed by the calculation unit 650. First, the position of each mark element 32 of the alignment mark 30 is measured from the acquired alignment signal (S.10). As a measuring method of the mark element 32, for example, there are the following methods.

  As one method, as shown in FIG. 5A, a section A and a section B are set with respect to the alignment signal, a filter process for removing random noise is performed in each section, and then a first-order differentiated signal There is a method of calculating the mark position based on the above.

  Another method is shown in FIG. That is, S (x) in the measurement direction x with respect to the signal sequence y is defined as the following equation (1). The expression (1) corresponds to the case where a = WC−WW / 2 and b = WC + WW / 2 in Expression 24 disclosed in Japanese Patent Laid-Open No. 8-94315.

As shown in FIG. 5B, S (x) at a certain point x is obtained from the equation (1), and then S (x) is acquired while changing x. This is a method of determining the minimum value (minimum value) of the S (x) curve, that is, the maximum value (maximum value) of 1 / S (x) shown in FIG.

Next, a waveform evaluation value is calculated (S.11). In the first embodiment, the waveform evaluation value indicates the symmetry of the alignment signal waveform. FIG. 6 is a conceptual diagram showing a method of setting a predetermined section on the left and right of the alignment signal waveform corresponding to one mark element 32 and quantifying the symmetry of the signal waveform in those sections. For example, the waveform evaluation value C1 when the maximum value of the signal sequence y in the left section is a _L , the minimum value is b _L , the maximum value of the signal sequence y in the right section is a _R , and the minimum value is b _R is (2 ) Expression.

Further, the length L _R of the box when the signal train y in the left section is represented by a boxplot used as a statistical method, and the length of the box when the signal train y in the right section is represented by a boxplot. The waveform evaluation value C2 when _LR is defined is defined by equation (3).

Since the waveform evaluation values C1 and C2 are acquired for each alignment mark element, for example, when there are four mark elements 32 as in the first embodiment, each of the four waveform evaluation values 1 and C2 is provided. The average value is used.

  Next, statistical processing is performed on the acquired measurement position of the mark element 32 (S.12), and the wafer magnification, wafer rotation, and wafer shift amount are calculated, and exposure processing is performed (S.13).

  Further, an in-wafer evaluation value (in-substrate evaluation value) is calculated by converting the average value of the waveform evaluation values C1 and C2 acquired for each alignment mark 30 into the rate of change in the wafer 20 surface (S.14). . FIG. 7 is a conceptual diagram for explaining the details of the method for calculating the wafer in-plane evaluation value.

  In this figure, the waveform evaluation value X_C2 of the alignment mark 30 in the X direction is plotted along the X axis for eight shots of AGA, and the waveform evaluation value Y_C2 of the alignment mark 30 in the Y direction is plotted along the Y axis. And plotted. It is empirically known that the waveform evaluation value X_C2 of the alignment mark 32 in the X direction has a linear relationship. In the first embodiment, the slope of this regression line is defined as a wafer in-plane evaluation value SLOPE (X_Ci) (where i = 1, 2, 3,...). The same applies to the Y direction, and the slope of the regression line indicated by the waveform evaluation value Y_C2 is defined as the wafer in-plane evaluation value SLOPE (Y_Ci) (where i = 1, 2, 3,...).

  The exposed wafer 20 is inspected by the overlay inspection apparatus (inspection apparatus) (S.15), and the inspection result within the wafer 20 surface is calculated from the inspection result (S.16). Specifically, the magnification component of the entire wafer is calculated from the inspection result of each inspection shot of the wafer 20.

  Subsequently, a correlation between the wafer in-plane evaluation values SLOPE (X_Ci) and SLOPE (Y_Ci) and the inspection result in the wafer surface is derived (S.17). For example, FIG. 8A shows the wafer in-plane evaluation value SLOPE (Y_C2) of the alignment mark 30 formed on the first wafer W1 and the alignment mark 30 formed on the second wafer W2. The wafer in-plane evaluation value SLOPE (Y_C2) is shown. When the wafer in-plane evaluation value SLOPE (Y_C2) of the alignment mark 30 and the in-wafer in-plane inspection result are plotted for each wafer, a linear correlation is obtained as shown in FIG. 8B.

  FIG. 9 is a graph in which, for each wafer, a wafer magnification component (substrate magnification component) ΔMagX in the X-axis direction of the wafer in-plane inspection result is plotted against the wafer in-plane evaluation value SLOPE (X_C2) in the X-axis direction. Indicates. On the other hand, FIG. 10 shows, for each wafer, the wafer magnification component ΔMagY in the Y-axis direction of the wafer in-plane inspection result with respect to the wafer in-plane evaluation value SLOPE (Y_C2) of the wafer in-plane evaluation value. The plotted graph is shown. 9 and 10 show that the in-plane evaluation value of the wafer and the wafer magnification component have a linear correlation in both the X axis and the Y axis.

  Such a linear correlation indicates that the waveform evaluation value in the wafer surface quantitatively indicates the WIS, and that the overlay error is linearly affected by the WIS. Incidentally, when there is no change in WIS between lots, the regression lines in FIGS. 9 and 10 are the same straight line independent of lots. Further, when there is no change in the WIS due to the wafers in the same lot, the slope of this regression line becomes zero.

  In the first embodiment, C2 is used as the waveform evaluation value. However, the present invention is not limited to this, and waveform evaluation value C1 may be used. Furthermore, the present invention is not limited to the case where the waveform evaluation values C1 and C2 are used, and the present invention can be applied to any index value indicating the symmetry of the alignment signal waveform.

  In the first embodiment, the wafer magnification components ΔMagX and ΔMagY have been described as the inspection results in the wafer 20 plane. However, a wafer rotation component (substrate rotation component) may be used as a matter of course. Further, in the first embodiment, one wafer in-plane inspection result is associated with one wafer in-plane evaluation value to obtain a 1: 1 correlation. However, the present invention is not limited to this, and M pieces of M (M is an integer of 2 or more) wafer in-plane evaluation values can be obtained when M: 1 correlations are made to correspond to one wafer in-plane inspection result. The present invention is also applied to the case where the correlation between M: N multivariates that associate N (N is an integer of 2 or more) wafer in-plane inspection results with the in-wafer in-plane evaluation value. Is possible. For example, when the contrast and symmetry as the waveform evaluation values are changed simultaneously, it has been confirmed that a plurality of in-plane inspection results such as wafer magnification and wafer rotation change due to the synergistic effect.

[Embodiment 2]
The second embodiment of the present invention will be described below. FIG. 11 is a graph in which the correlation between the wafer in-plane evaluation value and the in-wafer in-plane inspection result is plotted for the three exposure apparatuses A, B, and C. If the in-plane evaluation value of the wafer in a certain exposure apparatus can be calculated by tabulating this correlation between a plurality of exposure apparatuses, the overlay error after exposure in that exposure apparatus can be indirectly specified. Therefore, by calculating the wafer in-plane evaluation value before exposure, the predicted wafer overlay error can be fed back to the exposure apparatus in advance, so that overlay accuracy can be improved. If the data of this table is stored in the memory 650, the correlation in a specific exposure apparatus can be easily used.

[Embodiment 3]
The third embodiment of the present invention will be described below. FIG. 12 is a graph plotting the correlation between the in-wafer evaluation value and the in-wafer inspection result for the four semiconductor manufacturing processes A, B, C, and D. If the in-plane evaluation value of the wafer in a certain process can be calculated by tabulating this correlation by the process, the overlay error after the exposure in that process can be indirectly specified. Therefore, by calculating the wafer in-plane evaluation value before exposure, the predicted wafer overlay error can be fed back to the exposure apparatus in advance, so that overlay accuracy can be improved. If the data of this table is stored in the memory 650, the correlation in a specific process can be easily used.

  Next, an embodiment of a device manufacturing method using the above-described exposure apparatus 1 will be described with reference to FIGS. FIG. 13 is a flowchart for explaining how to fabricate devices (ie, semiconductor chips such as IC and LSI, LCDs, CCDs, and the like). Here, the manufacture of a semiconductor chip will be described as an example. In step 101 (circuit design), a device circuit is designed. In step 102 (reticle fabrication), a reticle on which the designed circuit pattern is formed is fabricated. In step 103 (wafer manufacture), a wafer (substrate) is manufactured using a material such as silicon. Step 104 (wafer process) is called a pre-process, and an actual circuit is formed on the wafer by lithography using the reticle and wafer. Step 105 (assembly) is called a post-process, and is a process for forming a semiconductor chip using the wafer created in step 104, and includes processes such as an assembly process (dicing and bonding) and a packaging process (chip encapsulation). . In step 106 (inspection), inspections such as an operation confirmation test and a durability test of the semiconductor device created in step 105 are performed. Through these steps, the semiconductor device is completed and shipped (step 107).

  FIG. 14 is a detailed flowchart of the wafer process in Step 104. In step 111 (oxidation), the wafer surface is oxidized. In step 112 (CVD), an insulating film is formed on the surface of the wafer. In step 113 (electrode formation), an electrode is formed on the wafer by vapor deposition or the like. In step 114 (ion implantation), ions are implanted into the wafer. In step 115 (resist process), a photosensitive agent is applied to the wafer. Step 116 (exposure) uses the exposure apparatus 1 to expose a reticle circuit pattern onto the wafer. In step 117 (development), the exposed wafer is developed. In step 118 (etching), portions other than the developed resist image are removed. In step 119 (resist stripping), the resist that has become unnecessary after the etching is removed. By repeatedly performing these steps, multiple circuit patterns are formed on the wafer. According to this manufacturing method, since the apparatus parameters optimized for the exposure apparatus 1 are set, a high-quality semiconductor device can be manufactured with a high yield.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to these, and various modifications and changes can be made within the scope of the gist thereof. For example, the present invention can be applied not only to a single crystal substrate for a semiconductor wafer as described in the above embodiment, but also to a glass substrate for a liquid crystal display (LCD) as an object to be exposed.

It is a flowchart explaining the alignment method which concerns on Embodiment 1 of this invention. It is a block diagram which shows schematic structure of the exposure apparatus for implement | achieving the alignment method which concerns on this invention. It is a block diagram which shows schematic structure of the alignment unit of the exposure apparatus shown in FIG. (A) is a top view which shows the structure of the alignment mark on a wafer, (b) is sectional drawing of the alignment mark shown in (a), (c) is the alignment mark shown in (a) with an alignment scope. It is a waveform which shows the detected alignment signal. (A) is a figure explaining one method of measuring the position of a mark element from an alignment signal, (b) is a figure explaining another method of measuring the position of a mark element from an alignment signal. It is a conceptual diagram which shows the method of quantifying the symmetry of an alignment signal waveform. It is a conceptual diagram explaining the detail of the calculation method of a wafer in-plane evaluation value. It is a conceptual diagram explaining the method of acquiring the correlation between an overlay inspection result and a wafer in-plane evaluation value. It is the graph which plotted the wafer magnification component with respect to the evaluation value in the wafer surface in a X direction. It is the graph which plotted the wafer magnification component with respect to the wafer in-plane evaluation value in a Y direction. In this embodiment, it is a figure explaining the detail of the correlation of the Y-axis direction. It is the graph which plotted the correlation of a wafer in-plane evaluation value and a wafer in-plane inspection result about three exposure apparatuses. It is the graph which plotted the correlation of a wafer in-plane evaluation value and a wafer in-plane inspection result about four semiconductor manufacturing processes. 3 is a flowchart for explaining a device manufacturing method by the exposure apparatus shown in FIG. 14 is a detailed flowchart of Step 104 shown in FIG. 13.

Explanation of symbols

1: Semiconductor exposure apparatus 10: Reticle 20: Wafer (substrate)
30: Alignment mark 32: Mark element 602: Laser light source unit 611: Wafer stage (substrate stage)
612: Wafer chuck 613: Projection optical system 614: Reticle stage 615: Illumination optical system 617: Alignment unit (detection optical system)
640: Control unit 650: Memory (storage unit)
660: calculation unit

Claims (11)

Detecting an alignment mark on the substrate and obtaining an alignment signal;
Calculating a waveform evaluation value indicating the order of the waveform of the alignment signal based on the alignment signal;
Calculating a substrate in-plane evaluation value indicating a distribution of the waveform evaluation value in the substrate surface based on the waveform evaluation value;
Inspecting the alignment state of the substrate by an inspection device;
Associating the inspection result with the in-plane evaluation value;
An alignment method comprising: calculating an alignment correction amount based on a correlation between the associated inspection result and the in-plane evaluation value from the in-plane evaluation value . An exposure method for aligning a reticle and the substrate using an alignment mark on the substrate to expose a pattern on the reticle onto the substrate,
Calculating an alignment correction amount by the alignment method according to claim 1 ;
Aligning the reticle and the substrate based on the correction amount;
And a step of projecting a pattern on the reticle onto the substrate after the alignment. The exposure method according to claim 2 , wherein the waveform evaluation value indicates the symmetry of the waveform of the alignment mark signal. The exposure method according to claim 2 , wherein the waveform evaluation value indicates a contrast of a waveform of the alignment mark signal. The exposure method according to claim 2 , wherein the in-plane evaluation value indicates a rate of change of the waveform evaluation value in the substrate plane. The exposure method according to claim 2 , wherein the inspection result is a magnification component of the substrate. The exposure method according to claim 2 , wherein the inspection result is a rotation component of the substrate. An exposure apparatus that performs alignment between a reticle and the substrate using an alignment mark on the substrate to expose a pattern on the reticle onto the substrate,
A reticle stage for adjusting the position of the reticle;
A substrate stage for adjusting the position of the substrate;
A detection optical system for detecting alignment marks on the substrate;
A waveform evaluation value that indicates the orderliness of the waveform of the alignment signal acquired by the detection optical system and a substrate in-plane evaluation value that indicates a distribution of the waveform evaluation value in the substrate surface are calculated, and an inspection apparatus A calculation unit that associates the inspection result indicating the obtained alignment state of the substrate with the in-plane evaluation value, and calculates an alignment correction amount based on the correlation;
An exposure apparatus comprising: a control unit that controls the reticle stage and the substrate stage based on the alignment correction amount. The exposure apparatus according to claim 8 , further comprising a storage unit that stores a plurality of correlations calculated for a plurality of different exposure apparatuses. The exposure apparatus according to claim 8 , further comprising a storage unit that stores a plurality of correlations calculated for a plurality of different semiconductor manufacturing processes. A device manufacturing method comprising the steps of projection exposure the pattern on the substrate by the exposure apparatus described, and performing a predetermined process on the substrate that has been projected and exposed to any one of claims 10 claim 8.