JP4380116B2

JP4380116B2 - Manufacturing method of semiconductor device

Info

Publication number: JP4380116B2
Application number: JP2002198184A
Authority: JP
Inventors: 温夫平林
Original assignee: Fuji Electric Device Technology Co Ltd
Current assignee: Fuji Electric Co Ltd
Priority date: 2002-07-08
Filing date: 2002-07-08
Publication date: 2009-12-09
Anticipated expiration: 2022-07-08
Also published as: JP2004040007A

Description

【０００１】
【発明の属する技術分野】
この発明は、ＳＯＩ（ＳｉｌｉｃｏｎｏｎＩｎｓｕｌａｔａｒ）基板を用いて製造される誘電体分離型の半導体装置の製造方法に関する。
【０００２】
【従来の技術】
ＳＯＩ基板を用いた誘電体分離技術は、素子間を絶縁膜で分離するため、ｐｎ接合を用いた接合分離技術に比べ、狭い分離領域で高耐圧の素子間分離を実現できる技術である。
図２９から図４０は、従来の誘電体分離技術を用いてＳＯＩ基板に形成される半導体装置の製造方法で、工程順に示した要部工程断面図である。
【０００３】
支持基板１上に第１の絶縁層２を介して形成した半導体層３で構成されるＳＯＩ基板（ＳＯＩウエハ）にエッチングマスク層４ａ、４ｂを形成し、このエッチングマスク層４ａのトレンチ形成領域５を一般的なフォトリソグラフ法（フォトリソグラフィー）を用いて選択的に開口する（図２９）。
このエッチングマスク層４ａ、４ｂをマスクとしてトレンチ６を形成する。エッチングマスク層４ａ、４ｂには熱酸化法により形成された熱酸化膜が用いられる（図３０）。
【０００４】
つぎに、エッチングマスク層４ａ、４ｂをフッ化水素酸溶液を用いて除去し、素子間を分離する第２の絶縁層７ａ（このとき、ＳＯＩウエハの裏面に第２の絶縁層７ｂも同時に形成される）を形成し、さらに充填材をトレンチ６に充填した後（このとき、ＳＯＩウエハの裏面にも充填材が形成される）、トレンチ６内に充填材を残して、また、ＳＯＩウエハの裏面の充填材も残し、半導体層３上に形成された充填材を除去する。このとき、トレンチ６内に充填された充填材充填層８ａとなり、ＳＯＩウエハの裏面（支持基板１の表面）には残留した充填材は充填層８ｂとなる。（図３１）
つぎに、半導体層３上に形成された第２の絶縁層７ａをフォトリソグラフ法を用いて選択的に除去する（図３２）。
【０００５】
つぎに、前記トレンチ６により区画され第２の絶縁層７ａが除去された半導体層３のｐ型ＭＯＳＦＥＴ形成領域１０１、ｎ型ＭＯＳＦＥＴ形成領域１０２および高耐圧デバイス形成領域１０３にイオン注入法および熱拡散法により拡散層（ウエル領域、ベース領域、バッファ領域など）を形成する（図３３）。
つぎに、第５の絶縁層１１ａ、１１ａ' １１ｂおよび耐酸化層１２ａ、１２ｂを形成する（図３４）。
【０００６】
つぎに、フォトリソグラフ法を用いてｐ型ＭＯＳＦＥＴ形成領域１０１、ｎ型１ＭＯＳＦＥＴ形成領域１０２および高耐圧デバイス領域１０３の活性領域に耐酸化層１２ａを残し、またＳＯＩウエハの裏面の耐酸化層１２ｂも残す（図３５）。
つぎに、この耐酸化層１２ａ、１２ｂをマスクとして選択的に第６の絶縁層１４ａ、１４ａ' を形成する（図３６）。
【０００７】
つぎに、耐酸化層１２ａ、１２ｂおよび第５の絶縁層１１ａ、１１ｂを除去した後、第７の絶縁層１５ａ（同時にＳＯＩウエハの裏面に第７の絶縁層１５ｂも形成される）及びゲート電極１６ａ（同時にＳＯＩウエハの裏面にゲート電極１６ｂ（多結晶シリコン膜）も形成される）を形成し、高濃度拡散層を形成する（図３７）。
【０００８】
つぎに、層間絶縁膜１７を堆積する（図３８）。
つぎに、コンタクト孔を形成して金属電極１８を形成する（図３９）。
つぎに、最終保護膜１９を形成する工程を経て半導体チップとなる素子ユニットが多数内蔵されたＳＯＩウエハが出来上がる（図４０）。
【０００９】
【発明が解決しようとする課題】
図４１は、半導体装置の製造工程を示す図である。図４２は、図４１の各工程でのＳＯＩウエハの反り量を示す図である。ＳＯＩウエハは半導体層側が凸になるように反る。製造プロセス投入前（初期状態）のＳＯＩウエハの反り量は約６０μｍである。工程が進むにつれて反り量が大きくなっていく。工程Ｎｏ５のＬＯＣＯＳ形成工程（図３６の第６の絶縁層１４ａを形成する工程）で反り量は急激に大きくなり１８０μｍ程度となる。この反り量が２００μｍを超えると、ＳＯＩウエハを次工程へ搬送するための搬送治具にウエハを真空固定することが困難となり、ＳＯＩウエハが搬送治具から落下して、割れるという搬送トラブルが発生する。そのため、余裕を見て、ＳＯＩウエハの反り量の上限を１５０μｍに抑えて、搬送トラブルを確実に防止することが求められている。
【００１０】
ＳＯＩウエハは、支持基板１と絶縁層２および半導体層３で構成される。通常、支持基板１と半導体層３はシリコンであり、絶縁層２は酸化シリコンが用いられる。シリコンと酸化シリコンの熱膨張係数は２．６×１０^-6、０．５×１０^-6（／℃）であり５倍の差がある。このため熱処理を施すと支持基板１および半導体層３と第１の絶縁層２の間に応力が発生し、ＳＯＩウエハは製造工程に入る前の初期状態（工程Ｎｏ１）で、図４２に示すように半導体層３が凸の反りが発生している。この初期状態でのＳＯＩウエハの反りを抑制する方法としてＳＯＩウエハの裏面に酸化シリコン膜を形成する方法が特開平９−４５８８２号公報や特開平３−２５０６１７号公報などで開示されている。
【００１１】
しかし、ＳＯＩウエハの裏面に酸化シリコン膜を形成した場合でも、トレンチを形成し、このトレンチに充填される多結晶シリコンである充填層８ａの表面が、ＬＯＣＯＳ工程などで酸化されると、充填層８ａに体積膨張が生じて、前記のように、ＳＯＩウエハの反り量が１５０μｍを超える場合が生じる。また、図４３に示すように、多結晶シリコン内に、表面が露出する空洞があると、この空洞箇所での酸化により充填層８ａの体積膨張が大きくなり、図４２のＮｏ８のウエハのように反り量が４００μｍ程度と大きくなる場合もある。このトレンチの充填層８ａの酸化によるＳＯＩウエハの反りについて、その詳細な説明は後述することとする。
【００１２】
また、初期的に前記公報の対策が施されたＳＯＩウエハにおいて、従来のように熱酸化法によりエッチングマスク層４ａ、４ｂを形成すると、ＳＯＩウエハの裏面、すなわち支持基板１表面には既にシリコン酸化膜が形成されているため、ＳＯＩウエハの裏面の酸化はほとんど進行しない。このため、トレンチ６形成後にエッチングマスク層４ａ、４ｂを除去する際、ＳＯＩウエハの裏面（支持基板１表面）に形成されたエッチングマスク層４ｂと初期に形成された酸化シリコン膜を除去すると、その後の半導体装置の製造過程で生じるＳＯＩウエハの反りを防止することはできない。また、初期に形成された酸化シリコン膜をＳＯＩウエハの裏面に残したとしても、トレンチ６内に形成された充填層８ａがＬＯＣＯＳ工程で酸化されると、充填層８ａの体積膨張により、ＳＯＩウエハは反ってしまう。
【００１３】
ＳＯＩウエハを用いた誘電体分離型の半導体装置ではウエハの反りは第１の絶縁層２の膜厚にも依存するが、トレンチ６で形成される素子分離領域の有無にも影響される。
図４４は、ＳＯＩウエハを用いて製造した半導体装置の最終工程における反り量と第１の絶縁層２の膜厚との関係を示す図である。反り量はトレンチ６の有無に関わらず第１の絶縁層２の厚さに依存し、トレンチ６がある場合の反り量はない場合の反り量に比べ、およそ５０〜８０μｍ大きくなる。
【００１４】
詳細な調査を実施した結果、トレンチ６に起因する反り量の増大は構造的な要因に加えて、充填層８ａの充填材に用いる多結晶シリコンが図３６に示すＬＯＣＯＳ工程（熱酸化工程）で酸化されることにより反りが増大することが明らかとなった（図３６の第６の絶縁層１４ａ’の形成により反りが増大する）。
図４５は、多結晶シリコンの酸化量と反り量の関係を示す図である。酸化膜厚が厚くなるに従い反り量は増大し、０．６μｍの膜厚では酸化しない場合に比べ約３０μｍ反り量が増加する。また、反り量のばらつきはトレンチ６の形状や充填材８の埋込性および図３１に示す充填材８ａの表面層に形成される空洞（隙間）の大きさなどのばらつきに起因している。
【００１５】
図４６は、底部に比べ上部の開口幅が広いトレンチ６を第２の絶縁層７ａと充填層８ａで埋め込んだ直後の分離領域の上部断面図である。充填層８ａは第２の絶縁層７ａの両側の端面から成長し、トレンチ６の中央部分で接触することによりトレンチ６の内部を充填する。充填層８ａが接触した領域は成長した領域に比べて緻密性に劣るため、次の表面の充填層８ａの除去工程においても接触部でのエッチングは進行し、充填層８ａの窪みより大きくなる。
【００１６】
図４７に示す露出した接触部（イ部）は、第６の絶縁層１４を形成するＬＯＣＯＳ工程（酸化工程）で、図示しない半導体層（単結晶シリコン層）の成長領域に比べて、酸化が速く進む（図４８）。充填層８ａに対してクサビ状に酸化が進行するため、体積膨張により水平方向に応力が発生し反りを増大させる。
一方、トレンチ６の形状が、垂直あるいは上部に比べて底部の幅が広い場合、図４９に示すようにトレンチ６の形状に起因してトレンチ６中央部に空洞が発生する。この場合、次の除去工程では空洞部が開口するため（図５０）、通常よりさらに充填層８ａ内部まで酸化が進行する（図５１）。従ってより応力は大きくなりさらに反り量を増大させる。
【００１７】
このように、トレンチ６の形状バラツキや多結晶シリコンの埋込のばらつきによって、ＳＯＩウエハの反り量のばらつきが生じる。
この発明の目的は、前記の課題を解決して、製造過程でのＳＯＩウエハの反り量と反り量のばらつきを低減できる半導体装置の製造方法を提供することにである。
【００２５】
【課題を解決するための手段】
前記の目的を達成するために、支持基板上に第一の絶縁層を介して半導体層を形成したＳＯＩ基板全面に第一の酸化膜を形成し、該第一の酸化膜を選択的に開口し前記半導体層表面から前記第一の絶縁層に達する分離溝を形成する工程と、
前記ＳＯＩ基板全面に第二の酸化膜を形成し、前記分離溝の内壁および前記支持基板の裏面に第二の酸化膜を形成する工程と、
前記ＳＯＩ基板全面に多結晶半導体膜を形成し、前記第二の酸化膜で被覆された分離溝内を充填し、前記支持基板の裏面の前記第二の酸化膜上に多結晶半導体膜を形成し、前記半導体層表面に形成された前記多結晶半導体膜を除去する工程と、
前記ＳＯＩ基板全面にＣＶＤ酸化膜を形成する工程と、
前記半導体層上に形成された前記ＣＶＤ酸化膜を、前記分離溝に充填された多結晶半導体膜上は残して除去する工程と、
前記ＳＯＩ基板全面にイオン注入時の犠牲酸化膜を形成する酸化工程と、
前記分離溝で分離された前記半導体層表面層に前記イオン注入および熱拡散により拡散層を形成する工程と、
前記ＳＯＩ基板全面に耐酸化膜を形成する工程と、
前記半導体層上に形成された前記耐酸化膜を、前記分離溝に充填された多結晶半導体膜の上部は残し、前記半導体層表面上は選択的に除去する工程と、
熱酸化により前記半導体層表面に熱酸化膜を形成する工程と、
を有し、これらの工程をこの順に行う製造方法とするとよい。
【００２６】
また、前記分離溝を形成する工程の後に、前記第一の酸化膜を除去する工程を有するとよい。
また、前記支持基板の裏面上に形成された前記耐酸化膜を除去する工程を有し、
前記半導体層表面に熱酸化膜を形成する工程と、支持基板裏面の前記耐酸化膜を除去した箇所に熱酸化膜を形成するとよい。
【００２７】
【発明の実施の形態】
図１から図９は、この発明の第１の実施例の半導体装置の製造方法で、工程順に示した要部製造工程断面図である。
支持基板１上に第１の絶縁層２を介して形成した半導体層３で構成されるＳＯＩウエハにエッチングマスク層４ａ、４ｂを形成し、エッチングマスク層４ａのトレンチ形成領域５をフォトリソグラフ法を用いて選択的に開口する。ＳＯＩウエハの各層の構成は支持基板１が厚さ６２０μｍの単結晶シリコン、第１の絶縁層２が厚さ１．０μｍの酸化シリコン、半導体層３が厚さ１０μｍの単結晶シリコンである。ＳＯＩウエハの直径は１５０ｍｍのものを用いた。製造工程投入前の支持基板１の表面（ＳＯＩウエハの裏面）にあらかじめ形成される酸化シリコン膜は有無を問わない。本実施例では前記酸化シリコン膜がないＳＯＩウエハを用いており、製造工程投入前の反り量はおよそ６０μｍである。エッチングマスク層４ａ、４ｂは熱酸化法により形成した１μｍ厚の酸化シリコン膜である。このとき、支持基板１の表面（ＳＯＩウエハの裏面）にも同じ膜厚のエッチングマスク層４ｂが形成される。トレンチ形成領域５の開口幅は１．２μｍであり、フォトレジストをマスクとしてフッ素系の混合ガスを用いたドライエッチング法で開口する（図１）。
【００２８】
つぎに、このエッチングマスク層４ａ、４ｂをマスクとして半導体層３の表面から第１の絶縁層２に到達するトレンチ６を形成する。エッチングマスク層４ｂはＳＯＩウエハの裏面をマスクする。このトレンチエッチングは臭化水素、酸素を含む混合ガスを用いたＲＩＥ（ＲｅａｃｔｉｖｅＩｏｎＥｔｃｈｉｎｇ）法を用いている（図２）。
【００２９】
つぎに、エッチングマスク層４ａ、４ｂをフッ化水素酸溶液を用いて除去し、素子間を分離する第２の絶縁層７ａ（このとき、ＳＯＩウエハの裏面に第２の絶縁層７ｂも同時に形成される）を形成し、さらに充填材をトレンチ６に充填した後（このとき、ＳＯＩウエハの裏面にも充填材が形成される）、トレンチ６内に充填材を残して、また、ＳＯＩウエハの裏面の充填材も残し、半導体層３上に形成された充填材を除去する。このとき、トレンチ６内に充填された充填材は充填層８ａとなり、支持基板１の表面（ＳＯＩウエハの裏面）に残留した充填材は充填層８ｂとなる。エッチングマスク層４ａを除去する際、ＳＯＩウエハ裏面に形成されているエッチングマスク層４ｂも同時に除去され、充填層８ｂは露出する。第２の絶縁層７ａ、７ｂは熱酸化法により形成された厚さ６００ｎｍの酸化シリコン膜であり、トレンチ６表面および半導体層３の表面に形成される第２の絶縁層７ａと同時に支持基板１表面（ＳＯＩウエハの裏面）に第２の絶縁層７ｂが形成される。充填材８ａ、８ｂには減圧ＣＶＤ（ＣｈｅｍｉｃａｌＶａｐｏｒＤｅｐｏｓｉｔｉｏｎ）法により形成される多結晶シリコン膜を用いた。多結晶シリコン膜は、第２の絶縁層７ａで被覆されたトレンチ６の内側を十分埋め込む膜厚で成膜する。本実施例では、充填層８ａ、８ｂの膜厚は１．０μｍとした。また、多結晶シリコン膜は、第２の絶縁層７ｂが形成されたＳＯＩウエハの裏面にも１．０μｍ成膜され、充填層８ｂとなる。半導体層３の表面側に成膜された充填層８ａはフッ素系の混合ガスを用いたドライエッチング法により除去する。ＳＯＩウエハの裏面（支持基板側１）の充填層８ｂは除去しない（図３）。
【００３０】
つぎに、半導体層３上に形成された第２の絶縁層７ａをフォトリソグラフ法を用いて選択的に除去し、前記トレンチ６により区画され、第２の絶縁層７ａが除去された半導体層３のｐ型ＭＯＳＦＥＴ形成領域１０１、ｎ型ＭＯＳＦＥＴ形成領域１０２および高耐圧デバイス形成領域１０３に、イオン注入時の犠牲酸化膜となる第４の絶縁層１０ａを形成し、この第４の絶縁層１０ａを介してイオン注入法および熱拡散法により拡散層を形成する（ウエル領域やベース領域やバッファ領域の形成）。この第４の絶縁層１０ａを形成するとき、同時に、充填層８ａ上にも第４の絶縁層１０ａ' が形成され、ＳＯＩウエハの裏面にも第４の絶縁層１０ｂが形成される。半導体層３上の第２の絶縁層７ａの除去には選択的に開口されたレジスト膜をマスクとして希釈されたフッ化水素酸溶液を用いた（図４）。
【００３１】
つぎに、第４の絶縁層１０ａ、１０ａ' 、１０ｂを希釈されたフッ化水素酸溶液で除去した後、第５の絶縁層１１ａ、１１ａ' 、１１ｂおよび耐酸化層１２ａ、１２ｂを形成する。第５の絶縁層１１ａ、１１ａ' 、１１ｂは熱酸化法により形成された厚さ３５ｎｍの酸化シリコン膜であり、耐酸化層１２ａ、１２ｂは減圧ＣＶＤ法により形成した厚さ１５０ｎｍの窒化シリコン膜である。第５の絶縁層１１ａ、１１ａ' と耐酸化層１２ａは半導体層３上とトレンチ６上（充填層８ａ上）に形成され、第５の絶縁層１１ｂ、耐酸化層１２ｂはＳＯＩウエハの裏面（支持基板１側）の充填層８ｂ上にも形成される（図５）。
【００３２】
つぎに、半導体層３側の耐酸化膜１２ａの表面に、図示しないレジスト層を形成して保護し、ＳＯＩウエハの裏面（支持基板１側）の耐酸化膜１２ｂを除去する。この耐酸化膜１２ｂを除去することで、図８の工程で裏面に形成された充填材８ｂが酸化され、体積膨張（酸化されたポリシリコンの体積が倍以上となる）してＳＯＩ基板の反りを補正する働きをする（図６）。
【００３３】
つぎに、図示しないレジスト層を除去した後、フォトリソグラフ法を用いてｐ型ＭＯＳＦＥＴ形成領域１０１、ｎ型ＭＯＳＦＥＴ形成領域１０２および高耐圧デバイス領域１０３の活性領域上に耐酸化層１２ａを残し、充填層８ａ上に耐酸化層１３ａを残す。この耐酸化層１３ａは、充填層８ａ上に残留した耐酸化層１２ａである。また、充填層８ａが露出する幅より広く耐酸化層１３ａを残す。こうすることで、充填層８ａが酸化されることを確実に防止できる（図７）。
【００３４】
つぎに、この耐酸化層１３ａをマスクとして選択的に第６の絶縁層１４ａ、１４ｂを熱酸化法で８００ｎｍ形成する（ＬＯＣＯＳ（選択酸化）工程）。このとき耐酸化膜１２ａが被覆した拡散層（半導体素子の活性領域）表面およびトレンチ６上の耐酸化膜１３ａで保護される充填層８ａ表面を除く表面に、第６の絶縁層１４ａが形成されるとともに、ＳＯＩウエハの裏面（支持基板１側）の充填層８ｂにも第６の絶縁膜１４ｂが形成される。充填層８ａ、８ｂとして用いる多結晶シリコンは単結晶シリコンに比べ熱酸化法による酸化速度が大きいため、半導体層３側に形成される第６の絶縁層１４ａ（ＬＯＣＯＳ酸化膜）に比べＳＯＩウエハの裏面（支持基板１側）の充填層８ｂ上に形成される第６の絶縁層１４ｂの方が厚くなる。ＳＯＩウエハの裏面（支持基板１側）の充填層８ｂ上に形成された第６の絶縁層１４ｂが残存している後工程では、ＳＯＩウエハの反りは小さく抑えられる（図８）。
【００３５】
つぎに、耐酸化層１２ａ、１３ａを除去した後、ゲート絶縁膜である第７の絶縁層１５ａ、１５ａ' 、ゲート電極１６ａ（ゲート電極１６ｂはゲート電極１６ａ形成時に工程上、同時にＳＯＩウエハの裏面に形成される多結晶シリコン層である）、ソース領域、ドレイン領域、金属電極１８、保護膜１９などを形成して、半導体チップとなる素子ユニットが多数内蔵されたＳＯＩウエハが出来上がる（図９）。
【００３６】
これらの工程を経たＳＯＩウエハの最終的な反りについて説明する。後述の図２４のＡに示すとおり、１４個のＳＯＩウエハの反り量の平均値は０μｍ程度となり、反り量のばらつきは１０μｍ程度となる。反り量のばらつきは、充填層８ａの空洞の大きさに依存するが、充填層８ａ上に耐酸化層１３ａを被覆することで、空洞の有無に係わらず充填層８ａの酸化を防止するため、反り量のばらつきは小さくなる。勿論、反り量自体も小さくなる。また、後述する図２５のＡに各工程での反り量の推移を示す。各工程で、反り量は１５０μｍ以下となっている。
【００３７】
この第１実施例において、図６に示すＳＯＩウエハの裏面（支持基板１側）の耐酸化膜１２ｂを除去する工程と、図７に示すｐ型ＭＯＳＦＥＴ形成領域１０１、ｎ型ＭＯＳＦＥＴ形成領域１０２および高耐圧デバイス領域１０３の活性領域および各トレンチ６上の充填層８ａが露出する幅より広く耐酸化層１３ａを残す工程とを同時に実施しすることにより、より少ない工程数で同じ効果が得られる。
【００３８】
尚、前記の第１の絶縁層２および第２の絶縁層７ａ、７ｂは、熱酸化法以外にＣＶＤ法による絶縁膜を適用しても構わない。
図１０から図１７は、この発明の第２実施例の半導体装置の製造方法で、工程順に示した要部製造工程断面図である。
第１実施例の図３の工程まで同様の工程を経た後、減圧ＣＶＤ法により第３の絶縁層９ａ、９ｂ（同一の絶縁膜）を厚さ０．４μｍ形成する（図１０）。
【００３９】
つぎに、フォトリソグラフ法と希釈フッ化水素酸溶液を用いてトレンチ６上の第２の絶縁層７ａと第３の絶縁層９ａを除いて他の箇所の第２の絶縁層７ａとＳＯＩウエハの裏面の第３の絶縁層９ｂを除去する（図１１）。
本実施例では第２の絶縁層７ａが熱酸化層で第３の絶縁層はＣＶＤ酸化膜である。同じ酸化膜であるため同一工程で除去できる。
【００４０】
つぎに、第４の絶縁層１０ａを形成し、前記した図４の工程と同様に半導体装置の拡散層を形成する。この工程では、充填層８ａ上に第３の絶縁層９ａが形成されているため、充填層８ａの酸化は、第３の絶縁層９ａで阻止され、ＳＯＩウエハの反りは抑制される。また、ＳＯＩウエハの裏面にも第４の絶縁膜１０ｂが形成される（図１２）。
【００４１】
つぎに、第４の絶縁層１０ａ、１０ｂを除去し、第５の絶縁層１１ａ、１１ｂと耐酸化層１２ａ、１２ｂを形成する（図１３）。
つぎに、ＳＯＩウエハの裏面（支持基板１側）の耐酸化層１２ｂを除去する。これによって、図１６の工程でＳＯＩウエハの裏面の充填層８ｂが酸化されやすくなる（図１４）。
【００４２】
つぎに、半導体装置の活性領域上に耐酸化層１２ａとトレンチ６上に耐酸化膜１３ａを残す（図１５）。
つぎに、耐酸化層１２ａ、１３ａをマスクとして選択的に第６の絶縁層１４ａ、１４ｂを半導体層３の表面およびＳＯＩウエハの裏面（支持基板１側）の充填層８ｂ上にそれぞれ形成する（ＬＯＣＯＳ工程）。この第６の絶縁層１４ｂは、充填層８ｂを酸化して形成されるため、充填層８ｂが体積膨張を起こして、ＳＯＩウエハの反りは抑制される（図１６）。
【００４３】
つぎに、耐酸化層１２ａ、１３ａを除去した後、ゲート絶縁膜である第７の絶縁層１５ａ、１５ａ' 、ゲート電極１６ａ（ゲート電極１６ｂはゲート電極１６ａ形成時に工程上、同時にＳＯＩウエハの裏面に形成される多結晶シリコン層である）、ソース領域、ドレイン領域、金属電極１８、保護膜１９などを形成して、半導体チップとなる素子ユニットが多数内蔵されたＳＯＩウエハが出来上がる（図１７）。
【００４４】
図１２の工程の第４の絶縁膜１０ａを形成する過程で、充填層８ａ上が第３の絶縁層９ａで被覆されており、この過程での充填層８ａの酸化は抑制される。そのため、第１実施例の場合に比べて、図１２の工程後のＳＯＩウエハの反りは小さくなる。また、最終的なＳＯＩウエハの反り量および反り量のばらつきは第１実施例とほぼ同じである（図２５を参照のこと）。
【００４５】
図１８から図２０は、この発明の第３実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。
図１８までの工程は、第１実施例の図５までの工程と同じであるが、それに続く図１９では、図７のようにＳＯＩウエハの裏面の耐酸化層１２ｂを除去することをせずに残留させる。また、図２０以降の工程は従来の図３７以降の工程と同じである。そのため、ＳＯＩウエハの裏面は、最終工程では従来方法の図４０の裏面と同じになる。この点が第１実施例と異なる。図２０では図８のように、耐酸化層１２ａ、１３ａをマスクとして選択的に第６の絶縁層１４ａ、１４ｂを熱酸化法で８００ｎｍ形成する。このとき、充填層８ａは耐酸化層１３ａで被覆されているので、酸化されず、体積膨張が起こらないので、ＳＯＩウエハの反りは抑制される。しかし、ＳＯＩウエハの裏面の充填層８ｂは酸化されないため、体積膨張が起こらずＳＯＩウエハの反りは第１実施例のようには抑制されない。
【００４６】
そのため、１４個のＳＯＩウエハの反り量の平均値は、第１実施例と比べて１００μｍ程度と大きくなるが、１５０μｍよりは小さい。また、ウエハ間のばらつきは１０μｍと小さいために、ＳＯＩウエハの搬送には支障がでない。
図２１から図２３は、この発明の第４実施例の半導体装置の製造方法であり、工程順に示した要部製造工程断面図である。
【００４７】
図２１までの工程は、第２実施例の図１３までの工程と同じであるが、それに続く図２２では、図１５のようにＳＯＩウエハの裏面の耐酸化層１２ｂを除去することをせずに残留させる。また、図２３以降の工程は従来の図３７以降の工程と同じである。そのため、ＳＯＩウエハの裏面は、最終工程では従来方法の図４０の裏面と同じになる。この点が第２実施例と異なる。図２３では図１６のように、耐酸化層１２ａ、１３ａをマスクとして選択的に第６の絶縁層１４ａ、１４ｂを熱酸化法で８００ｎｍ形成する。このとき、充填層８ａは耐酸化層１３ａで被覆されているので、酸化されず、体積膨張が起こらないので、ＳＯＩウエハの反りは抑制される。しかし、ＳＯＩウエハの裏面の充填層８ｂは酸化されないため、体積膨張が起こらずＳＯＩウエハの反りは第２実施例のようには抑制されない。
【００４８】
そのため、１４個のＳＯＩウエハの反り量の平均値は、第２実施例と比べて１００μｍ程度と大きくなるが、１５０μｍよりは小さい。また、ウエハ間のばらつきは１０μｍと小さいために、ＳＯＩウエハの搬送には支障がでない。
図２４は、第１実施例と第３実施例と従来のＳＯＩウエハの最終工程での反り量を示す図である。ＳＯＩウエハの枚数は各１４枚である。反り量は製造工程完了後の値を示している。図中のＡは、第１実施例の図１０工程後の反り量である。Ｃは、第３実施例で、第１実施例の図９に相当する工程後の反り量である。従来は、従来方法の場合で、充填材８ａを酸化した場合で図４０の工程後の反り量である。従来方法ではＳＯＩウエハの反り量は１３０〜１９０μｍ前後でありウエハ間のばらつきも６０μｍと大きい。また、従来方法のＳＯＩウエハ番号８は、ＬＯＣＯＳ工程（第６の絶縁層１４ａ、１４ｂを形成する工程）で４００μｍ程度の反りが発生し、後工程へのＳＯＩウエハの搬送が困難となったものである。また、Ｃの場合、ＳＯＩウエハの裏面の充填層８ｂを酸化しないようにしたため、反り量は平均で１００μｍと大きいが、反り量のばらつきは１０μｍ程度で小さい。Ａの場合、ＳＯＩウエハの裏面の充填層８ｂを酸化し、トレンチ６の充填層８ａの酸化を防止することにより、反り量はほぼ０μｍとなり、反り量のばらつきも１０μｍと小さい。第１実施例および第３実施例のいずれの場合も反り量は１５０μｍ以下となり、搬送のトラブルは発生しない。
【００４９】
尚、第２実施例および第４実施例の反り量は、図示しないが、第１実施例および第３実施例とそれぞれほぼ同じである。
図２５は、各工程と反り量の関係を示す図である。工程Ｎｏの説明は図４１に示す。Ａ、Ｃは図２４のＡ、Ｃのウエハ番号１０の反り量であり、Ｂは、第２実施例の場合である。Ｎｏ３の工程で、第１実施例（Ａ）に比べて第２実施例（Ｂ）の反り量が小さくなっているのは、図１２の工程で、充填層８ａ上に形成された第３の絶縁膜９ａが充填層８ａの酸化を防止しているためである。
【００５０】
Ｎｏ４のＬＯＣＯＳ工程（第６の絶縁層１４ａを形成する工程）で、その前のＮｏ３の拡散層形成（ウエル領域形成）工程での反り量１４０μｍ程度と比べて、Ａの場合では反り量は０μｍ程度となり、Ｃの場合でも１００μｍ程度となり、いずれの場合も反り量は減少している。これは、従来の方法で、反り量が１８０μｍ程度に増大するのに比べて、大幅に反り量が改善されていることが分かる。
【００５１】
図２６から図２８は、この発明の第５実施例の半導体装置の製造方法で、工程順に示した要部製造工程断面図である。
図２６までの工程は、第１実施例の図５までの工程と同じであるが、それに続く図２７では、図７のようにトレンチ６上の耐酸化層１３ａを残すのではなく、除去する。この点が第１実施例と異なる。図２８では図８のように、耐酸化層１２ａをマスクとして選択的に第６の絶縁層１４ａ、１４ｂを熱酸化法で８００ｎｍ程度形成する。このとき、充填層８ａは耐酸化層１３ａで被覆されていないので、酸化して体積膨張を起こし、ＳＯＩウエハの反りが増長される。しかし、ＳＯＩウエハの裏面の充填層８ｂが酸化されるため、体積膨張が起こり、ＳＯＩウエハの反りは抑制され、前記の増長された以上に抑制されて、反り量は小さくなる。その結果、搬送トラブルは発生しなくなる。
【００５２】
【発明の効果】
この発明によると、トレンチ内に形成された充填層の酸化を防止することで、ＳＯＩウエハの反り量と反り量のばらつきを小さくする。
また、ＳＯＩウエハの裏面に形成された充填層を酸化させることで、ＳＯＩウエハの反り量を小さくする。
【００５３】
反り量が小さくなることで、ＳＯＩウエハの工程間での搬送トラブルが解決できる。
【図面の簡単な説明】
【図１】この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２】図１に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図３】図２に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図４】図３に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図５】図４に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図６】図５に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図７】図６に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図８】図７に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図９】図８に続く、この発明の第１の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１０】この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１１】図１０に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１２】図１１に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１３】図１２に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１４】図１３に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１５】図１４に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１６】図１５に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１７】図１６に続く、この発明の第２の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１８】この発明の第３の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図１９】図１８に続く、この発明の第３の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２０】図１９に続く、この発明の第３の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２１】この発明の第４の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２２】図２１に続く、この発明の第４の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２３】図２２に続く、この発明の第４の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２４】ＳＯＩウエハと反り量の関係を示す図
【図２５】各工程と反り量の関係を示す図
【図２６】この発明の第５の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２７】図２６に続く、この発明の第５の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２８】図２７に続く、この発明の第５の実施例の半導体装置の製造方法を示す要部製造工程断面図
【図２９】従来の半導体装置の製造方法を示す要部製造工程断面図
【図３０】図２９に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３１】図３０に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３２】図３１に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３３】図３２に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３４】図３３に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３５】図３４に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３６】図３５に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３７】図３６に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３８】図３７に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図３９】図３８に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図４０】図３９に続く、従来の半導体装置の製造方法を示す要部製造工程断面図
【図４１】半導体装置の主要な製造工程を示す図
【図４２】従来の製造工程と反り量の関係を示す図
【図４３】トレンチ内に形成した充填層に形成された空洞を示す図
【図４４】第１の絶縁層の膜厚と反り量の関係を示す図
【図４５】多結晶シリコンの酸化膜厚と反り量の関係を示す図
【図４６】トレンチを充填する充填層の状態を示す図
【図４７】トレンチを充填する充填層の状態を示す図
【図４８】トレンチを充填する充填層に第６の絶縁層１４が形成した図
【図４９】充填層に形成された空洞の図
【図５０】空洞が露出した状態を示す図
【図５１】空洞が第６の絶縁層で酸化された状態を示す図
【符号の説明】
１支持基板
２第１の絶縁層
３半導体層
４ａ、４ｂエッチングマスク
５トレンチ形成領域
６トレンチ
７ａ、７ｂ第２の絶縁層
８ａ、８ｂ充填層
９ａ、９ｂ第３の絶縁層
１０ａ、１０ａ' １０ｂ第４の絶縁層
１１ａ、１１ｂ第５の絶縁層
１２ａ、１２ｂ耐酸化層
１３ａ耐酸化層
１４ａ、１４ａ' １４ｂ第６の絶縁層
１５第７の絶縁層
１６ゲート電極（多結晶シリコン膜）
１７層間絶縁膜
１８金属電極
１９保護膜
１０１ｐ形ＭＯＳＦＥＴ形成領域
１０２ｎ形ＭＯＳＦＥＴ形成領域
１０３高耐圧デバイス形成領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a dielectric isolation type semiconductor device manufactured using an SOI (Silicon on Insulator) substrate.
[0002]
[Prior art]
The dielectric isolation technology using an SOI substrate is a technology that can achieve high voltage isolation between elements in a narrow isolation region as compared with a junction isolation technology using a pn junction because elements are separated by an insulating film.
FIG. 29 to FIG. 40 are cross-sectional views of essential parts shown in the order of steps in a method for manufacturing a semiconductor device formed on an SOI substrate using a conventional dielectric separation technique.
[0003]
Etching mask layers 4a and 4b are formed on an SOI substrate (SOI wafer) composed of a semiconductor layer 3 formed on a support substrate 1 via a first insulating layer 2, and a trench formation region 5 of the etching mask layer 4a is formed. Are selectively opened using a general photolithographic method (photolithography) (FIG. 29).
A trench 6 is formed using the etching mask layers 4a and 4b as a mask. A thermal oxide film formed by a thermal oxidation method is used for the etching mask layers 4a and 4b (FIG. 30).
[0004]
Next, the etching mask layers 4a and 4b are removed using a hydrofluoric acid solution, and a second insulating layer 7a for separating elements is formed (at this time, the second insulating layer 7b is also formed on the back surface of the SOI wafer at the same time). And then filling the trench 6 with a filler (at this time, the filler is also formed on the back surface of the SOI wafer), leaving the filler in the trench 6 and the SOI wafer. The filler formed on the semiconductor layer 3 is removed while leaving the filler on the back surface. At this time, the filler filling layer 8a filled in the trench 6 is formed, and the filler remaining on the back surface of the SOI wafer (the surface of the support substrate 1) becomes the filling layer 8b. (Fig. 31)
Next, the second insulating layer 7a formed on the semiconductor layer 3 is selectively removed using a photolithographic method (FIG. 32).
[0005]
Next, an ion implantation method and thermal diffusion are applied to the p-type MOSFET formation region 101, the n-type MOSFET formation region 102, and the high breakdown voltage device formation region 103 of the semiconductor layer 3 partitioned by the trench 6 and from which the second insulating layer 7a is removed. A diffusion layer (well region, base region, buffer region, etc.) is formed by the method (FIG. 33).
Next, fifth insulating layers 11a, 11a ′ 11b and oxidation resistant layers 12a, 12b are formed (FIG. 34).
[0006]
Next, the oxidation resistant layer 12a is left in the active regions of the p-type MOSFET formation region 101, the n-type 1MOSFET formation region 102, and the high breakdown voltage device region 103 by using a photolithographic method, and the oxidation resistant layer 12b on the back surface of the SOI wafer is also formed. Leave (FIG. 35).
Next, sixth insulating layers 14a and 14a 'are selectively formed using the oxidation resistant layers 12a and 12b as masks (FIG. 36).
[0007]
Next, after removing the oxidation resistant layers 12a and 12b and the fifth insulating layers 11a and 11b, a seventh insulating layer 15a (a seventh insulating layer 15b is also formed on the back surface of the SOI wafer) and a gate electrode 16a (at the same time, a gate electrode 16b (polycrystalline silicon film) is also formed on the back surface of the SOI wafer) to form a high-concentration diffusion layer (FIG. 37).
[0008]
Next, an interlayer insulating film 17 is deposited (FIG. 38).
Next, contact holes are formed to form metal electrodes 18 (FIG. 39).
Next, an SOI wafer in which a large number of element units to be semiconductor chips are built is completed through the step of forming the final protective film 19 (FIG. 40).
[0009]
[Problems to be solved by the invention]
FIG. 41 is a diagram illustrating a manufacturing process of a semiconductor device. FIG. 42 is a diagram showing the warpage amount of the SOI wafer in each step of FIG. The SOI wafer warps so that the semiconductor layer side is convex. The warpage amount of the SOI wafer before the manufacturing process is input (initial state) is about 60 μm. The amount of warpage increases as the process progresses. In the LOCOS formation step of step No. 5 (step of forming the sixth insulating layer 14a in FIG. 36), the amount of warpage suddenly increases and becomes about 180 μm. If the amount of warpage exceeds 200 μm, it becomes difficult to vacuum-fix the wafer on a transfer jig for transferring the SOI wafer to the next process, and a trouble occurs that the SOI wafer falls from the transfer jig and breaks. To do. For this reason, there is a demand for reliably preventing a conveyance trouble by limiting the upper limit of the warping amount of the SOI wafer to 150 μm with a margin.
[0010]
The SOI wafer includes a support substrate 1, an insulating layer 2, and a semiconductor layer 3. Usually, the support substrate 1 and the semiconductor layer 3 are silicon, and the insulating layer 2 is silicon oxide. The thermal expansion coefficient of silicon and silicon oxide is 2.6 × 10^-60.5 × 10^-6(/ ° C.) and there is a five-fold difference. Therefore, when heat treatment is performed, stress is generated between the support substrate 1 and the semiconductor layer 3 and the first insulating layer 2, and the SOI wafer is in an initial state (process No. 1) before entering the manufacturing process, as shown in FIG. The semiconductor layer 3 has a convex warp. As a method for suppressing the warpage of the SOI wafer in the initial state, a method of forming a silicon oxide film on the back surface of the SOI wafer is disclosed in Japanese Patent Laid-Open Nos. 9-45882 and 3-250617.
[0011]
However, even when a silicon oxide film is formed on the back surface of the SOI wafer, if a trench is formed and the surface of the filling layer 8a made of polycrystalline silicon filling the trench is oxidized by a LOCOS process or the like, the filling layer Volume expansion occurs in 8a, and as described above, the warpage amount of the SOI wafer exceeds 150 μm. Further, as shown in FIG. 43, if there is a cavity whose surface is exposed in the polycrystalline silicon, the volume expansion of the filling layer 8a is increased by oxidation in the cavity, and like the wafer No. 8 in FIG. In some cases, the amount of warpage is as large as about 400 μm. A detailed description of the warpage of the SOI wafer due to the oxidation of the filling layer 8a of the trench will be described later.
[0012]
In addition, when an etching mask layer 4a, 4b is formed by a thermal oxidation method in a conventional manner on an SOI wafer to which the measures described in the above publication are applied, silicon oxide is already formed on the back surface of the SOI wafer, that is, on the surface of the support substrate 1. Since the film is formed, the oxidation of the back surface of the SOI wafer hardly proceeds. For this reason, when the etching mask layers 4a and 4b are removed after the trench 6 is formed, the etching mask layer 4b formed on the back surface (the surface of the support substrate 1) of the SOI wafer and the silicon oxide film formed initially are removed. It is impossible to prevent the warpage of the SOI wafer that occurs during the manufacturing process of the semiconductor device. Even if the initially formed silicon oxide film is left on the back surface of the SOI wafer, if the filling layer 8a formed in the trench 6 is oxidized in the LOCOS process, the SOI wafer is expanded by the volume expansion of the filling layer 8a. Will warp.
[0013]
In a dielectric isolation type semiconductor device using an SOI wafer, the warpage of the wafer depends on the thickness of the first insulating layer 2 but is also affected by the presence or absence of an element isolation region formed by the trench 6.
FIG. 44 is a diagram showing the relationship between the amount of warpage in the final process of a semiconductor device manufactured using an SOI wafer and the film thickness of the first insulating layer 2. The amount of warpage depends on the thickness of the first insulating layer 2 regardless of the presence or absence of the trench 6, and is about 50 to 80 μm larger than the amount of warpage when there is no warpage when the trench 6 is present.
[0014]
As a result of the detailed investigation, the increase in warpage due to the trench 6 is caused by structural factors, and the polycrystalline silicon used for the filling material of the filling layer 8a is formed in the LOCOS process (thermal oxidation process) shown in FIG. It has been clarified that the warpage is increased by oxidation (the warpage is increased by the formation of the sixth insulating layer 14a ′ in FIG. 36).
FIG. 45 is a diagram showing the relationship between the amount of oxidation and the amount of warpage of polycrystalline silicon. The amount of warpage increases as the thickness of the oxide film increases, and the amount of warpage increases by about 30 μm as compared with the case where the film thickness of 0.6 μm is not oxidized. Further, the variation in the amount of warpage is caused by variations in the shape of the trench 6, the embedding property of the filler 8, and the size of the cavity (gap) formed in the surface layer of the filler 8a shown in FIG.
[0015]
FIG. 46 is a top sectional view of the isolation region immediately after the trench 6 having a wider opening width than the bottom is filled with the second insulating layer 7a and the filling layer 8a. The filling layer 8 a grows from the end faces on both sides of the second insulating layer 7 a and fills the inside of the trench 6 by contacting at the center of the trench 6. Since the region in contact with the filling layer 8a is inferior in density to the grown region, the etching at the contact portion proceeds in the next step of removing the filling layer 8a on the surface and becomes larger than the depression of the filling layer 8a.
[0016]
The exposed contact portion (b) shown in FIG. 47 is oxidized in the LOCOS step (oxidation step) for forming the sixth insulating layer 14 as compared with the growth region of the semiconductor layer (single crystal silicon layer) not shown. Proceed fast (FIG. 48). Since the wedge-shaped oxidation proceeds with respect to the packed bed 8a, a stress is generated in the horizontal direction due to volume expansion to increase warpage.
On the other hand, when the shape of the trench 6 is vertical or wider at the bottom than the top, a cavity is generated at the center of the trench 6 due to the shape of the trench 6 as shown in FIG. In this case, since the cavity is opened in the next removal step (FIG. 50), the oxidation further proceeds to the inside of the filling layer 8a than usual (FIG. 51). Accordingly, the stress becomes larger and the amount of warpage is further increased.
[0017]
As described above, variations in the amount of warpage of the SOI wafer occur due to variations in the shape of the trench 6 and variations in the implantation of polycrystalline silicon.
An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-described problems and can reduce the amount of warpage of the SOI wafer and the variation in the amount of warpage during the manufacturing process.
[0025]
[Means for Solving the Problems]
In order to achieve the above object, a first oxide film is formed on the entire surface of an SOI substrate in which a semiconductor layer is formed on a support substrate via a first insulating layer, and the first oxide film is selectively opened. Forming a separation groove reaching the first insulating layer from the surface of the semiconductor layer;
  Forming a second oxide film on the entire surface of the SOI substrate, and forming a second oxide film on the inner wall of the separation groove and the back surface of the support substrate;
  A polycrystalline semiconductor film is formed on the entire surface of the SOI substrate, filling the inside of the separation groove covered with the second oxide film, and a polycrystalline semiconductor film is formed on the second oxide film on the back surface of the support substrate. And removing the polycrystalline semiconductor film formed on the semiconductor layer surface;
  Forming a CVD oxide film on the entire surface of the SOI substrate;
  Removing the CVD oxide film formed on the semiconductor layer while leaving the polycrystalline semiconductor film filled in the separation groove;
  An oxidation step of forming a sacrificial oxide film during ion implantation on the entire surface of the SOI substrate;
  In the semiconductor layer surface layer separated by the separation grooveBy the ion implantation and thermal diffusionForming a diffusion layer;
  Forming an oxidation resistant film on the entire surface of the SOI substrate;
  A step of selectively removing the oxidation-resistant film formed on the semiconductor layer while leaving an upper part of the polycrystalline semiconductor film filled in the separation groove;
  Forming a thermal oxide film on the surface of the semiconductor layer by thermal oxidation;
  It is good to set it as the manufacturing method which has these and performs these processes in this order.
[0026]
In addition, after the step of forming the separation groove,A step of removing the first oxide film;Good.
A step of removing the oxidation-resistant film formed on the back surface of the support substrate;
A step of forming a thermal oxide film on the surface of the semiconductor layer, and a step of forming a thermal oxide film at a location where the oxidation resistant film on the back surface of the support substrate is removed.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 to 9 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.
Etching mask layers 4a and 4b are formed on an SOI wafer composed of a semiconductor layer 3 formed on a support substrate 1 with a first insulating layer 2 interposed therebetween, and a trench formation region 5 of the etching mask layer 4a is formed by photolithography. Use to selectively open. The structure of each layer of the SOI wafer is such that the support substrate 1 is single crystal silicon having a thickness of 620 μm, the first insulating layer 2 is silicon oxide having a thickness of 1.0 μm, and the semiconductor layer 3 is single crystal silicon having a thickness of 10 μm. An SOI wafer having a diameter of 150 mm was used. It does not matter whether or not there is a silicon oxide film formed in advance on the front surface (back surface of the SOI wafer) of the support substrate 1 before the manufacturing process is input. In this embodiment, an SOI wafer without the silicon oxide film is used, and the warpage amount before the manufacturing process is about 60 μm. The etching mask layers 4a and 4b are 1 μm thick silicon oxide films formed by a thermal oxidation method. At this time, an etching mask layer 4b having the same thickness is also formed on the front surface of the support substrate 1 (the back surface of the SOI wafer). The trench formation region 5 has an opening width of 1.2 μm, and is opened by a dry etching method using a fluorine-based mixed gas using a photoresist as a mask (FIG. 1).
[0028]
Next, trenches 6 reaching the first insulating layer 2 from the surface of the semiconductor layer 3 are formed using the etching mask layers 4a and 4b as masks. The etching mask layer 4b masks the back surface of the SOI wafer. This trench etching uses RIE (Reactive Ion Etching) method using a mixed gas containing hydrogen bromide and oxygen (FIG. 2).
[0029]
Next, the etching mask layers 4a and 4b are removed using a hydrofluoric acid solution, and a second insulating layer 7a for separating elements is formed (at this time, the second insulating layer 7b is also formed on the back surface of the SOI wafer at the same time). And then filling the trench 6 with a filler (at this time, the filler is also formed on the back surface of the SOI wafer), leaving the filler in the trench 6 and the SOI wafer. The filler formed on the semiconductor layer 3 is removed while leaving the filler on the back surface. At this time, the filling material filled in the trench 6 becomes the filling layer 8a, and the filling material remaining on the surface of the support substrate 1 (the back surface of the SOI wafer) becomes the filling layer 8b. When removing the etching mask layer 4a, the etching mask layer 4b formed on the back surface of the SOI wafer is also removed at the same time, and the filling layer 8b is exposed. The second insulating layers 7a and 7b are silicon oxide films having a thickness of 600 nm formed by a thermal oxidation method, and the support substrate 1 simultaneously with the second insulating layer 7a formed on the surface of the trench 6 and the surface of the semiconductor layer 3. A second insulating layer 7b is formed on the front surface (the back surface of the SOI wafer). Polycrystalline silicon films formed by low pressure CVD (Chemical Vapor Deposition) are used as the fillers 8a and 8b. The polycrystalline silicon film is formed with a film thickness sufficiently filling the inside of the trench 6 covered with the second insulating layer 7a. In this example, the thickness of the filling layers 8a and 8b was 1.0 μm. The polycrystalline silicon film is also formed on the back surface of the SOI wafer on which the second insulating layer 7b is formed to have a thickness of 1.0 μm and becomes the filling layer 8b. The filling layer 8a formed on the surface side of the semiconductor layer 3 is removed by a dry etching method using a fluorine-based mixed gas. The filling layer 8b on the back surface (support substrate side 1) of the SOI wafer is not removed (FIG. 3).
[0030]
Next, the second insulating layer 7a formed on the semiconductor layer 3 is selectively removed using a photolithographic method, and the semiconductor layer 3 is partitioned by the trench 6 and the second insulating layer 7a is removed. In the p-type MOSFET formation region 101, the n-type MOSFET formation region 102, and the high breakdown voltage device formation region 103, a fourth insulating layer 10a serving as a sacrificial oxide film during ion implantation is formed, and this fourth insulating layer 10a is formed. Then, a diffusion layer is formed by ion implantation and thermal diffusion (formation of a well region, a base region, and a buffer region). When the fourth insulating layer 10a is formed, a fourth insulating layer 10a 'is also formed on the filling layer 8a, and a fourth insulating layer 10b is also formed on the back surface of the SOI wafer. For the removal of the second insulating layer 7a on the semiconductor layer 3, a diluted hydrofluoric acid solution was used with a resist film selectively opened as a mask (FIG. 4).
[0031]
Next, after removing the fourth insulating layers 10a, 10a 'and 10b with a diluted hydrofluoric acid solution, fifth insulating layers 11a, 11a' and 11b and oxidation resistant layers 12a and 12b are formed. The fifth insulating layers 11a, 11a ′ and 11b are silicon oxide films with a thickness of 35 nm formed by a thermal oxidation method, and the oxidation resistant layers 12a and 12b are silicon nitride films with a thickness of 150 nm formed by a low pressure CVD method. is there. The fifth insulating layers 11a and 11a ′ and the oxidation resistant layer 12a are formed on the semiconductor layer 3 and the trench 6 (on the filling layer 8a), and the fifth insulating layer 11b and the oxidation resistant layer 12b are formed on the back surface of the SOI wafer ( It is also formed on the filling layer 8b on the support substrate 1 side (FIG. 5).
[0032]
Next, a resist layer (not shown) is formed and protected on the surface of the oxidation resistant film 12a on the semiconductor layer 3 side, and the oxidation resistant film 12b on the back surface (support substrate 1 side) of the SOI wafer is removed. By removing the oxidation-resistant film 12b, the filler 8b formed on the back surface in the step of FIG. 8 is oxidized, and volume expansion (the volume of the oxidized polysilicon becomes twice or more) causes warping of the SOI substrate. It works to correct (Fig. 6).
[0033]
Next, after removing a resist layer (not shown), an oxidation resistant layer 12a is left on the active regions of the p-type MOSFET formation region 101, the n-type MOSFET formation region 102, and the high breakdown voltage device region 103 by using a photolithographic method. The oxidation resistant layer 13a is left on the layer 8a. The oxidation resistant layer 13a is the oxidation resistant layer 12a remaining on the filling layer 8a. Further, the oxidation-resistant layer 13a is left wider than the width where the filling layer 8a is exposed. By doing so, it is possible to reliably prevent the packed bed 8a from being oxidized (FIG. 7).
[0034]
Next, the sixth insulating layers 14a and 14b are selectively formed to 800 nm by a thermal oxidation method using the oxidation resistant layer 13a as a mask (LOCOS (selective oxidation) step). At this time, a sixth insulating layer 14a is formed on the surface excluding the surface of the diffusion layer (active region of the semiconductor element) covered with the oxidation resistant film 12a and the surface of the filling layer 8a protected by the oxidation resistant film 13a on the trench 6. In addition, a sixth insulating film 14b is also formed on the filling layer 8b on the back surface (support substrate 1 side) of the SOI wafer. Polycrystalline silicon used as the filling layers 8a and 8b has a higher oxidation rate by thermal oxidation than that of single crystal silicon. The sixth insulating layer 14b formed on the filling layer 8b on the back surface (supporting substrate 1 side) is thicker. In the post-process in which the sixth insulating layer 14b formed on the filling layer 8b on the back surface (support substrate 1 side) of the SOI wafer remains, warping of the SOI wafer is suppressed to a small level (FIG. 8).
[0035]
Next, after removing the oxidation-resistant layers 12a and 13a, the seventh insulating layers 15a and 15a ′, which are gate insulating films, and the gate electrode 16a (the gate electrode 16b is formed on the back surface of the SOI wafer at the same time when forming the gate electrode 16a. The source region, the drain region, the metal electrode 18, the protective film 19 and the like are formed, and an SOI wafer having a large number of element units serving as semiconductor chips is completed (FIG. 9). .
[0036]
The final warpage of the SOI wafer that has undergone these steps will be described. As shown in FIG. 24A to be described later, the average value of the warpage amount of the 14 SOI wafers is about 0 μm, and the variation of the warpage amount is about 10 μm. The variation in the amount of warpage depends on the size of the cavity of the filling layer 8a, but by covering the filling layer 8a with the oxidation resistant layer 13a, the oxidation of the filling layer 8a is prevented regardless of the presence or absence of the cavity. The variation in the amount of warpage is reduced. Of course, the warping amount itself is also reduced. Moreover, transition of the curvature amount in each process is shown to A of FIG. 25 mentioned later. In each step, the warpage amount is 150 μm or less.
[0037]
In the first embodiment, the step of removing the oxidation-resistant film 12b on the back surface (support substrate 1 side) of the SOI wafer shown in FIG. 6, the p-type MOSFET formation region 101, the n-type MOSFET formation region 102 shown in FIG. The same effect can be obtained with a smaller number of steps by simultaneously carrying out the active region of the high breakdown voltage device region 103 and the step of leaving the oxidation resistant layer 13a wider than the width in which the filling layer 8a on each trench 6 is exposed.
[0038]
The first insulating layer 2 and the second insulating layers 7a and 7b may be an insulating film formed by a CVD method other than the thermal oxidation method.
FIGS. 10 to 17 are cross-sectional views of the main part manufacturing process shown in the order of steps in the method of manufacturing the semiconductor device according to the second embodiment of the present invention.
After going through the same steps up to the step of FIG. 3 of the first embodiment, the third insulating layers 9a and 9b (the same insulating film) are formed to a thickness of 0.4 μm by the low pressure CVD method (FIG. 10).
[0039]
Next, using the photolithographic method and diluted hydrofluoric acid solution, except for the second insulating layer 7a and the third insulating layer 9a on the trench 6, the second insulating layer 7a at other locations and the SOI wafer The third insulating layer 9b on the back surface is removed (FIG. 11).
In this embodiment, the second insulating layer 7a is a thermal oxide layer, and the third insulating layer is a CVD oxide film. Since they are the same oxide film, they can be removed in the same process.
[0040]
Next, a fourth insulating layer 10a is formed, and a diffusion layer of the semiconductor device is formed in the same manner as in the process of FIG. In this step, since the third insulating layer 9a is formed on the filling layer 8a, the oxidation of the filling layer 8a is blocked by the third insulating layer 9a, and the warpage of the SOI wafer is suppressed. A fourth insulating film 10b is also formed on the back surface of the SOI wafer (FIG. 12).
[0041]
Next, the fourth insulating layers 10a and 10b are removed, and fifth insulating layers 11a and 11b and oxidation resistant layers 12a and 12b are formed (FIG. 13).
Next, the oxidation resistant layer 12b on the back surface (support substrate 1 side) of the SOI wafer is removed. Thereby, the filling layer 8b on the back surface of the SOI wafer is easily oxidized in the step of FIG. 16 (FIG. 14).
[0042]
Next, an oxidation resistant layer 12a is left on the active region of the semiconductor device and an oxidation resistant film 13a is left on the trench 6 (FIG. 15).
Next, the sixth insulating layers 14a and 14b are selectively formed on the filling layer 8b on the front surface of the semiconductor layer 3 and the back surface (support substrate 1 side) of the SOI wafer by using the oxidation resistant layers 12a and 13a as masks (see FIG. LOCOS process). Since the sixth insulating layer 14b is formed by oxidizing the filling layer 8b, the filling layer 8b undergoes volume expansion, and warping of the SOI wafer is suppressed (FIG. 16).
[0043]
Next, after removing the oxidation-resistant layers 12a and 13a, the seventh insulating layers 15a and 15a ′, which are gate insulating films, and the gate electrode 16a (the gate electrode 16b is formed on the back surface of the SOI wafer at the same time when forming the gate electrode 16a. The source region, the drain region, the metal electrode 18, the protective film 19 and the like are formed, and an SOI wafer having a large number of element units serving as semiconductor chips is completed (FIG. 17). .
[0044]
In the process of forming the fourth insulating film 10a in the process of FIG. 12, the filling layer 8a is covered with the third insulating layer 9a, and the oxidation of the filling layer 8a in this process is suppressed. Therefore, the warpage of the SOI wafer after the process of FIG. 12 is smaller than in the case of the first embodiment. Further, the warp amount of the final SOI wafer and the variation in the warp amount are almost the same as those in the first embodiment (see FIG. 25).
[0045]
FIGS. 18 to 20 are cross-sectional views of the main part manufacturing process shown in the order of the steps in the semiconductor device manufacturing method according to the third embodiment of the present invention.
The steps up to FIG. 18 are the same as the steps up to FIG. 5 of the first embodiment. However, in FIG. 19, the oxidation resistant layer 12b on the back surface of the SOI wafer is not removed as shown in FIG. To remain. 20 and the subsequent steps are the same as the conventional steps after FIG. Therefore, the back surface of the SOI wafer becomes the same as the back surface of the conventional method in FIG. 40 in the final process. This is different from the first embodiment. In FIG. 20, as shown in FIG. 8, the sixth insulating layers 14a and 14b are selectively formed by thermal oxidation with a thickness of 800 nm using the oxidation resistant layers 12a and 13a as a mask. At this time, since the filling layer 8a is covered with the oxidation resistant layer 13a, it is not oxidized and volume expansion does not occur, so that warpage of the SOI wafer is suppressed. However, since the filling layer 8b on the back surface of the SOI wafer is not oxidized, the volume expansion does not occur and the warpage of the SOI wafer is not suppressed as in the first embodiment.
[0046]
Therefore, the average value of the amount of warpage of the 14 SOI wafers is as large as about 100 μm as compared with the first embodiment, but is smaller than 150 μm. Further, since the variation between the wafers is as small as 10 μm, there is no problem in transporting the SOI wafer.
FIG. 21 to FIG. 23 are cross-sectional views of main part manufacturing steps shown in the order of steps in the semiconductor device manufacturing method according to the fourth embodiment of the present invention.
[0047]
The steps up to FIG. 21 are the same as the steps up to FIG. 13 of the second embodiment. However, in FIG. 22, the oxidation resistant layer 12b on the back surface of the SOI wafer is not removed as shown in FIG. To remain. Also, the steps after FIG. 23 are the same as the conventional steps after FIG. Therefore, the back surface of the SOI wafer becomes the same as the back surface of the conventional method in FIG. 40 in the final process. This is different from the second embodiment. In FIG. 23, as shown in FIG. 16, the sixth insulating layers 14a and 14b are selectively formed by thermal oxidation at 800 nm using the oxidation resistant layers 12a and 13a as a mask. At this time, since the filling layer 8a is covered with the oxidation resistant layer 13a, it is not oxidized and volume expansion does not occur, so that warpage of the SOI wafer is suppressed. However, since the filling layer 8b on the back surface of the SOI wafer is not oxidized, the volume expansion does not occur and the warpage of the SOI wafer is not suppressed as in the second embodiment.
[0048]
Therefore, the average value of the amount of warpage of the 14 SOI wafers is as large as about 100 μm as compared with the second embodiment, but is smaller than 150 μm. Further, since the variation between the wafers is as small as 10 μm, there is no problem in transporting the SOI wafer.
FIG. 24 is a diagram showing the warpage amount in the final process of the first and third embodiments and the conventional SOI wafer. The number of SOI wafers is 14 each. The amount of warpage indicates the value after completion of the manufacturing process. A in the figure is the amount of warpage after the step of FIG. 10 of the first embodiment. C is the amount of warpage after the step corresponding to FIG. 9 of the first embodiment in the third embodiment. Conventionally, in the case of the conventional method, the amount of warpage after the process of FIG. 40 is obtained when the filler 8a is oxidized. In the conventional method, the warpage amount of the SOI wafer is about 130 to 190 μm, and the variation between the wafers is as large as 60 μm. Also, SOI wafer No. 8 of the conventional method has a warp of about 400 μm in the LOCOS process (process for forming the sixth insulating layers 14a and 14b), making it difficult to carry the SOI wafer to the subsequent process. It is. In the case of C, since the filling layer 8b on the back surface of the SOI wafer is not oxidized, the amount of warpage is as large as 100 μm on average, but the variation in the amount of warpage is as small as about 10 μm. In the case of A, by oxidizing the filling layer 8b on the back surface of the SOI wafer and preventing the filling layer 8a of the trench 6 from being oxidized, the warping amount becomes almost 0 μm, and the variation of the warping amount is as small as 10 μm. In both cases of the first embodiment and the third embodiment, the amount of warpage is 150 μm or less, and no conveyance trouble occurs.
[0049]
Although not shown, the warpage amounts of the second and fourth embodiments are substantially the same as those of the first and third embodiments.
FIG. 25 is a diagram showing the relationship between each process and the warpage amount. The description of the process No is shown in FIG. A and C are the warpage amounts of wafer number 10 of A and C in FIG. 24, and B is the case of the second embodiment. In the process of No3, the warpage amount of the second example (B) is smaller than that of the first example (A) in the third process formed on the filling layer 8a in the process of FIG. This is because the insulating film 9a prevents the filling layer 8a from being oxidized.
[0050]
In the case of A, the amount of warpage is 0 μm in the No. 4 LOCOS step (step of forming the sixth insulating layer 14a), compared to the amount of warpage of about 140 μm in the previous No. 3 diffusion layer formation (well region formation) step. Even in the case of C, it is about 100 μm, and in either case, the amount of warpage is reduced. This shows that the amount of warpage is significantly improved in the conventional method as compared with the case where the amount of warpage is increased to about 180 μm.
[0051]
26 to 28 are sectional views of the principal part manufacturing steps shown in the order of the steps in the semiconductor device manufacturing method according to the fifth embodiment of the present invention.
The steps up to FIG. 26 are the same as the steps up to FIG. 5 of the first embodiment, but in FIG. 27 that follows, the oxidation-resistant layer 13a on the trench 6 is not left but removed as shown in FIG. . This is different from the first embodiment. In FIG. 28, as shown in FIG. 8, the sixth insulating layers 14a and 14b are selectively formed by a thermal oxidation method to about 800 nm using the oxidation resistant layer 12a as a mask. At this time, since the filling layer 8a is not covered with the oxidation resistant layer 13a, the filling layer 8a is oxidized to cause volume expansion, and the warpage of the SOI wafer is increased. However, since the filling layer 8b on the back surface of the SOI wafer is oxidized, volume expansion occurs, warping of the SOI wafer is suppressed, and the amount of warpage is reduced by suppressing more than the increase. As a result, no conveyance trouble occurs.
[0052]
【The invention's effect】
According to the present invention, the variation of the warpage amount and the warpage amount of the SOI wafer is reduced by preventing the filling layer formed in the trench from being oxidized.
Moreover, the amount of warpage of the SOI wafer is reduced by oxidizing the filling layer formed on the back surface of the SOI wafer.
[0053]
By reducing the amount of warpage, it is possible to solve a conveyance trouble between processes of an SOI wafer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a main part manufacturing process showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention;
2 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 1, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
3 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 2, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
4 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 3;
5 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the invention, following FIG. 4;
6 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 5, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
7 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 6, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 8 is a cross-sectional view showing the main part manufacturing process continued from FIG. 7 and shows the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
9 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 8, illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;
FIG. 10 is a cross-sectional view of a main part manufacturing process showing a method of manufacturing a semiconductor device according to a second embodiment of the invention.
FIG. 11 is a cross-sectional view showing the main part manufacturing process continued from FIG. 10 and shows the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 12 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 11, showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 13 is a cross-sectional view of the essential part manufacturing process, subsequent to FIG. 12, showing the method of manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 14 is a cross-sectional view of the essential part manufacturing process showing the method for manufacturing the semiconductor device according to the second embodiment of the invention, following FIG. 13;
FIG. 15 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 14, showing the method for manufacturing the semiconductor device according to the second embodiment of the invention;
FIG. 16 is a cross-sectional view showing the main part manufacturing process continued from FIG. 15 and shows the method for manufacturing the semiconductor device according to the second embodiment of the present invention;
FIG. 17 is a cross-sectional view of the essential part manufacturing process, which shows the manufacturing method of the semiconductor device according to the second embodiment of the invention, following FIG. 16;
FIG. 18 is a cross-sectional view of main part manufacturing steps showing a method for manufacturing a semiconductor device according to a third embodiment of the present invention;
FIG. 19 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 18, showing the method for manufacturing the semiconductor device according to the third embodiment of the present invention;
20 is a cross-sectional view of main part manufacturing steps, subsequent to FIG. 19, illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 21 is a cross-sectional view of main part manufacturing steps showing a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention;
FIG. 22 is a cross-sectional view of the essential part manufacturing process, which shows the manufacturing method of the semiconductor device according to the fourth embodiment of the invention, following FIG. 21;
FIG. 23 is a cross-sectional view showing the main part manufacturing process continued from FIG. 22 and showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;
FIG. 24 is a diagram showing the relationship between the SOI wafer and the warpage amount;
FIG. 25 is a diagram showing the relationship between each process and the amount of warpage.
FIG. 26 is a fragmentary manufacturing step sectional view showing the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention;
FIG. 27 is a cross-sectional view showing the main part manufacturing process continued from FIG. 26 and showing the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention;
FIG. 28 is a cross-sectional view of the essential part manufacturing step showing the method for manufacturing the semiconductor device according to the fifth embodiment of the invention, following FIG. 27;
FIG. 29 is a cross-sectional view of main part manufacturing steps showing a conventional method of manufacturing a semiconductor device.
FIG. 30 is a cross-sectional view of main part manufacturing steps, illustrating the conventional method for manufacturing a semiconductor device, following FIG. 29;
FIG. 31 is a principal part manufacturing step sectional view showing the conventional method of manufacturing the semiconductor device, following FIG. 30;
FIG. 32 is a cross-sectional view of main part manufacturing steps, illustrating the conventional method for manufacturing a semiconductor device, following FIG. 31;
FIG. 33 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing the semiconductor device, following FIG. 32;
FIG. 34 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing a semiconductor device, following FIG. 33;
FIG. 35 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing the semiconductor device, following FIG. 34;
FIG. 36 is a cross-sectional view of essential part manufacturing step, showing the conventional method for manufacturing a semiconductor device, following FIG. 35;
FIG. 37 is a principal part manufacturing step sectional view showing the conventional method of manufacturing the semiconductor device, following FIG. 36;
FIG. 38 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing the semiconductor device, following FIG. 37;
FIG. 39 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing the semiconductor device, following FIG. 38;
40 is a cross-sectional view of main part manufacturing steps, showing the conventional method for manufacturing the semiconductor device, continued from FIG. 39;
41 is a diagram showing main manufacturing steps of a semiconductor device; FIG.
FIG. 42 is a diagram showing a relationship between a conventional manufacturing process and a warpage amount.
FIG. 43 is a diagram showing a cavity formed in a filling layer formed in a trench;
FIG. 44 is a diagram showing the relationship between the thickness of the first insulating layer and the amount of warpage.
FIG. 45 is a diagram showing the relationship between the oxide film thickness and the amount of warpage of polycrystalline silicon.
FIG. 46 is a diagram showing the state of the filling layer filling the trench.
FIG. 47 is a view showing a state of a filling layer filling a trench.
FIG. 48 is a diagram in which a sixth insulating layer 14 is formed in the filling layer filling the trench.
FIG. 49 is a diagram of a cavity formed in a filling layer.
FIG. 50 is a diagram showing a state in which a cavity is exposed.
FIG. 51 is a diagram showing a state in which the cavity is oxidized by the sixth insulating layer;
[Explanation of symbols]
1 Support substrate
2 First insulating layer
3 Semiconductor layer
4a, 4b Etching mask
5 Trench formation region
6 Trench
7a, 7b Second insulating layer
8a, 8b packed bed
9a, 9b Third insulating layer
10a, 10a ′ 10b Fourth insulating layer
11a, 11b Fifth insulating layer
12a, 12b Oxidation resistant layer
13a Oxidation resistant layer
14a, 14a ′ 14b Sixth insulating layer
15 Seventh insulating layer
16 Gate electrode (polycrystalline silicon film)
17 Interlayer insulation film
18 Metal electrode
19 Protective film
101 p-type MOSFET formation region
102 n-type MOSFET formation region
103 High breakdown voltage device formation region

Claims

A first oxide film is formed on the entire surface of the SOI substrate on which the semiconductor layer is formed on the support substrate via the first insulating layer, the first oxide film is selectively opened, and the first oxide film is opened from the surface of the semiconductor layer. Forming a separation groove reaching the insulating layer of
Forming a second oxide film on the entire surface of the SOI substrate, and forming a second oxide film on the inner wall of the separation groove and the back surface of the support substrate;
A polycrystalline semiconductor film is formed on the entire surface of the SOI substrate, filling the inside of the separation groove covered with the second oxide film, and a polycrystalline semiconductor film is formed on the second oxide film on the back surface of the support substrate. And removing the polycrystalline semiconductor film formed on the semiconductor layer surface;
Forming a CVD oxide film on the entire surface of the SOI substrate;
Removing the CVD oxide film formed on the semiconductor layer while leaving the polycrystalline semiconductor film filled in the separation groove;
An oxidation step of forming a sacrificial oxide film during ion implantation on the entire surface of the SOI substrate;
Forming a diffusion layer in the semiconductor layer surface layer separated by the separation groove by the ion implantation and thermal diffusion ;
Forming an oxidation resistant film on the entire surface of the SOI substrate;
A step of selectively removing the oxidation-resistant film formed on the semiconductor layer while leaving an upper part of the polycrystalline semiconductor film filled in the separation groove;
Forming a thermal oxide film on the surface of the semiconductor layer by thermal oxidation;
A method for manufacturing a semiconductor device, characterized in that these steps are performed in this order.

Wherein after the step of forming the isolation trench, the method of manufacturing a semiconductor device according to claim 1, characterized in that it comprises a step of removing the first oxide film.

Removing the oxidation-resistant film formed on the back surface of the support substrate;
The process of forming a thermal oxide film on the surface of the semiconductor layer, and forming a thermal oxide film at a location where the oxidation-resistant film on the back surface of the support substrate is removed. Semiconductor device manufacturing method.