JP4377946B1 - Demodulator - Google Patents

Abstract

A highly sensitive demodulator is provided.
An ASK demodulator operates in synchronization with a clock signal CLK. The input signal from the external device received by the antenna 10 is sent to the rectifier circuit 11. The rectifier circuit 11 rectifies the input signal. The input signal rectified by the rectifier circuit 11 is compared with a threshold value by the clocked comparator 12 and binarized. The clocked comparator 12 operates with a phase different from the phase of the clock signal CLK.
[Selection] Figure 1

Description

  The present invention relates to an amplitude shift keying (hereinafter, abbreviated as ASK) demodulator.

  An ASK demodulator that demodulates an ASK-modulated input signal usually includes a rectifier circuit and a comparator. The rectifier circuit rectifies and detects a signal received by the antenna to obtain a demodulated signal. The demodulated signal is compared with a threshold value by a comparator, greatly amplified to a logical level, and converted into a binary signal. In many cases, a comparator has a hysteresis function to suppress malfunction caused by noise. However, if a hysteresis function is provided, it is more resistant to noise, but it is difficult to improve reception sensitivity.

  In general, a rectifier circuit cannot rectify with an input signal power smaller than a threshold voltage (about 0.7 V) of a diode, so that reception sensitivity is low. The high gain rectifier circuit described in Patent Document 1 is composed of an NMOS transistor, and the threshold voltage is set to approximately 0 V by applying a voltage corresponding to the threshold voltage of the MNOS transistor between the gate and the source. With this configuration, it is possible to rectify a minute AC signal having an effective value equal to or lower than the threshold voltage. That is, the reception sensitivity of the rectifier circuit is improved.

  In order to improve the reception sensitivity of the comparator, it is necessary to eliminate the hysteresis and set the threshold value low. In this case, it is necessary to consider the DC offset voltage due to variations in elements constituting the comparator. When the DC offset voltage varies greatly on the positive side, the reception sensitivity decreases. When the DC offset voltage varies greatly on the negative side, the output logic level becomes “1” even when the input voltage is 0V. (Malfunction). In order to prevent malfunction, the threshold value of the comparator needs to be set high in consideration of variations in the DC offset voltage. For this reason, it is difficult to improve the reception sensitivity of the comparator. Further, in order to reduce the DC offset voltage due to the element variation, it is necessary to increase the size of the element, which increases the cost.

Moreover, since the high gain rectifier circuit described in Patent Document 1 supplies a bias voltage to the rectifier circuit using a clock signal, noise synchronized with the clock signal appears at the output of the rectifier circuit. In order to suppress noise synchronized with the clock signal, it is necessary to increase the time constant of the output of the rectifier circuit, and it becomes difficult to improve the data rate.
JP 2006-34085 A (paragraph 0014, FIG. 1)

  The ASK demodulator circuit described above cannot simultaneously satisfy the prevention of malfunction due to noise and the improvement of reception sensitivity. Even if a high-gain rectifier circuit to which a bias voltage synchronized with the clock signal is applied is used, noise due to the clock signal appears at the output of the rectifier circuit. Further, even if it is attempted to eliminate the hysteresis of the comparator and improve the reception sensitivity, it is difficult due to the influence of the DC offset due to variations in the elements of the comparator.

  The present invention has been made in view of the above problems, and an object thereof is to provide a highly sensitive demodulator.

An amplitude shift keying demodulator according to an embodiment of the present invention includes a bias circuit that outputs a DC voltage, a first MOS transistor to which only the DC voltage is applied between a gate terminal and a source terminal, and a gate terminal A second MOS transistor in which only the DC voltage is applied between the first MOS transistor and the drain terminal is connected to the source terminal of the first MOS transistor, and one end of which is the source terminal of the first MOS transistor. A rectifier circuit having a coupling capacitor connected to the other end to which an AC signal is input from the other end, the rectifier circuit supplying the bias voltage at a predetermined timing, and the input signal rectified by the rectifier circuit A clocked comparator that outputs a binary signal by comparing with a threshold at a timing different from the timing of .

  In the amplitude shift keying demodulator according to an embodiment of the present invention, the rectifier circuit supplies a bias voltage at a predetermined timing, and the clocked comparator compares the input signal rectified by the rectifier circuit with a threshold value to obtain a binary signal. Is output. The clocked comparator operates at a timing different from the predetermined timing. Since the clock noise generated at a predetermined timing that appears in the output of the rectifier circuit is different from the operation timing of the comparator, the influence of the clock noise can be reduced and a highly sensitive demodulator can be realized.

  Hereinafter, an embodiment of an ASK demodulator according to the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a diagram showing a configuration of an ASK (Amplitude Shift Keying) demodulating circuit according to a first embodiment of the present invention.

  A signal from the antenna 10 is supplied to the clocked comparator 12 via the rectifier circuit 11. The output of the clocked comparator 12 is output via a noise removal circuit 16. The predetermined bias voltage set in the rectifier circuit 11 is supplied in synchronization with the clock pulse φ1. The clock pulse φ1 is output from the pulse width adjustment circuit 13 to which the clock signal CLK is supplied, and the clock signal CLK is also supplied to the clocked comparator 12 and the threshold correction circuit 14. The threshold correction circuit 14 receives the output Vout of the clocked comparator 12 and supplies a threshold correction signal VREF, which is an n-bit digital signal, to the clocked comparator 12. The input terminal of the clocked comparator 12 is grounded to the reference voltage via the switch 15. The correction signal CAL, which is a control signal for the switch 15, is also supplied to the threshold correction circuit 14, and the operation (state transition) of the threshold correction circuit 14 is controlled.

  The antenna 10 is an antenna that receives a radio signal transmitted from the outside. The antenna 10 is used, for example, to perform wireless communication with a non-contact type wireless device or to receive a control signal from a remote controller.

  The rectifier circuit 11 is a circuit that converts a radio frequency into a direct current. The rectifier circuit 11 rectifies and detects the input signal received by the antenna 10 to obtain a demodulated signal. A predetermined threshold voltage V1 (about 0.7V) is set in the rectifier circuit 11, and it is detected whether or not a signal having an intensity equal to or higher than the threshold voltage V1 is received. The rectifier circuit 11 according to the present embodiment is a high gain rectifier circuit in which a bias voltage V2 is applied in advance to a diode in the rectifier circuit 11 for high sensitivity. Even if the intensity D of the signal received by the antenna 10 is small by this bias voltage V2, it can be detected as long as the sum of the signal intensity D and the bias voltage V2 exceeds the threshold voltage V1 of the transistor. Can be realized. For example, when V1 = 0.7V and V2 = 0.6V, a signal of 0.1V or higher can be detected. Therefore, reception is possible even if the input signal detected by the antenna 10 is weak.

  A circuit diagram of the rectifier circuit 11 is shown in FIG. The rectifier circuit 11 is less than a threshold voltage (for example, 0.7 V) required for the MOS transistor to exhibit rectification characteristics between the source and the gate of the diode-connected MOS transistor, and preferably the threshold voltage. By applying a nearby constant voltage, it is possible to rectify a minute AC signal having an effective value equal to or lower than the threshold voltage.

  In FIG. 2, the NMOS transistor M1 has a back gate terminal and a source terminal connected, and a drain terminal connected to the plus terminal T1. Further, a bias circuit 10a capable of generating a predetermined voltage is connected between the gate terminal and the source terminal. With this connection, the NMOS transistor M1 functions as a diode element using the drain side PN junction. Further, the bias circuit 10a applies the predetermined voltage described above between the gate terminal and the source terminal of the NMOS transistor M1. The bias circuit 10a can generate a voltage lower than a threshold voltage (hereinafter referred to as a diode bias voltage) necessary for the NMOS transistor M1 to exhibit rectification characteristics as a predetermined voltage. The diode bias voltage is, for example, in the range of 0 V to 1.0 V, but is preferably a value near the threshold voltage (for example, 0.6 V). In other words, the NMOS transistor M1 is biased between the gate terminal and the source terminal with a diode bias voltage so that an AC signal having an effective value equal to or lower than the threshold voltage can be rectified.

  For example, this diode circuit can rectify an AC signal having an effective value of about 100 mV when the diode bias voltage is 0.6V.

  Similarly, in the NMOS transistor M2, the back gate terminal and the source terminal are connected, and the source terminal is connected to the minus terminal T2. A bias circuit 10b is connected between the gate terminal and the source terminal. The NMOS transistor M2 also functions in the same manner as the NMOS transistor M1, and the bias circuit 10b biases the gate terminal and the source terminal with a diode bias voltage.

  The source terminal of the NMOS transistor M1 and the drain terminal of the NMOS transistor M2 are connected to each other, and one end of the capacitor C1 is connected to the connection line. The other end of the capacitor C1 is connected to the signal input terminal TA. This capacitor C1 functions as a coupling capacitance.

  A capacitor C2 is connected between the drain terminal of the NMOS transistor M1 and the source terminal of the NMOS transistor M2. The signal half-wave rectified by the NMOS transistors M1 and M2 is smoothed by the capacitor C2. By this smoothing, a DC voltage can be taken out from both ends of the capacitor C2, that is, between the plus terminal T1 and the minus terminal T2.

  The NMOS transistors M1 and M2 are formed in a triple well structure and are isolated from the substrate. Therefore, each source terminal is connected to the P well below the NMOS transistor, each drain terminal is connected to the N well, and the diode element is formed by a PN junction inside the MOS transistor.

  FIG. 3 is a circuit diagram showing a configuration example of the bias circuits 10a and 10b shown in FIG. In FIG. 3, the bias circuit 100 corresponds to the bias circuit 10a or 10b, and the NMOS transistor M10 corresponds to the NMOS transistor M1 or M2. The bias circuit 100 includes two NMOS transistors M11 and M12 connected in series. These NMOS transistors M11 and M12 each function as a transfer gate and are disposed on the plus line L1. Similarly, the bias circuit 100 includes two NMOS transistors M21 and M22 connected in series on the minus line L2 and functioning as transfer gates. The gate terminal of the NMOS transistor M11 and the gate terminal of the NMOS transistor M21 are connected to each other, and the gate terminal of the NMOS transistor M12 and the gate terminal of the NMOS transistor M22 are also connected to each other. A capacitor C11 is connected between a line connecting the drain terminal of the NMOS transistor M11 and the source terminal of the NMOS transistor M12 and a line connecting the drain terminal of the NMOS transistor M21 and the source terminal of the NMOS transistor M22. Yes. Further, a capacitor C12 is connected between the drain terminal of the NMOS transistor M12 and the drain terminal of the NMOS transistor M22.

  To the bias circuit 100, a DC generation circuit 110, an inverter INV1, and an inverter INV2 are connected as peripheral circuits. The DC generation circuit 110 generates a DC voltage corresponding to the above-described diode bias voltage from the main power supply of the device on which the rectifier circuit according to the present embodiment is mounted. The DC voltage generated by the DC generation circuit 110 is applied between the plus line L1 and the minus line L2 of the bias circuit 100. The NMOS transistor M10 is representative of the NMOS transistors M1 and M2 shown in FIG. 2, but since the NMOS transistor M10 operates at a high frequency of GHz, it is necessary to make the parasitic capacitance as small as possible. The DC generation circuit 110 has a large capacity in order to stably generate a DC voltage. For this reason, the bias circuit 100 as shown in FIG. 3 is provided without directly applying the diode bias voltage obtained from the DC generation circuit 110 in parallel between the gate and the source of the NMOS transistor M10.

  The input terminal of the inverter INV1 is connected to the clock input terminal TC, and a clock pulse (φ1) having a constant frequency is input. This clock pulse is generated by, for example, a pulse width adjustment circuit 13 described later. The output terminal of the inverter INV1 is connected to the gates of the NMOS transistors M11 and M21, and is also connected to the input terminal of the inverter INV2. The output terminal of the inverter INV2 is connected to the gates of the NMOS transistors M12 and M22.

  When the clock pulse input from the clock input terminal TC is the logic level “0”, the inverter INV1 outputs the logic level “1”, and the inverter INV2 outputs the logic level “0”. Therefore, the NMOS transistors M11 and M21 are turned on, and the capacitor C11 is charged by the DC voltage supplied from the DC generation circuit 110. Further, the NMOS transistors M12 and M22 are turned off, and no DC voltage is applied to the capacitor C12.

  On the other hand, when the clock pulse input from the clock input terminal TC is the logic level “1”, the inverter INV1 outputs the logic level “0”, and the inverter INV2 outputs the logic level “1”. Therefore, the NMOS transistors M11 and M21 are turned off and the NMOS transistors M12 and M22 are turned on, so that the charge charged in the capacitor C11 is supplied to the capacitor C12. Since both ends of the capacitor C12 are connected to the output terminal of the bias circuit 100, the voltage across the capacitor C12 is used as a diode bias voltage between the gate terminal and the source terminal of the diode-connected NMOS transistor M10. Applied.

  Ultimately, the voltage across the capacitor C12 only needs to be the diode bias voltage of the NMOS transistor M10, and the DC voltage supplied by the DC generation circuit 110 need not be the same as the diode bias voltage. For example, the voltage of the capacitor C12 can be fixed to an arbitrary value by performing the switching operation of the NMOS transistors M11, M12, M21, and M22 by PWM (Pulse Wide Modulation) control. In this case, the DC power generation circuit 110 may be eliminated and a main power source may be connected between the plus line L1 and the minus line L2.

  The detected demodulated signal is output from the rectifier circuit 11 to the clocked comparator 12. The clocked comparator 12 also has a predetermined threshold voltage different from that of the rectifier circuit 11, and converts the received demodulated signal Vin into a binary signal of “1” or “0” at the timing of the clock pulse φ1. . If the intensity of the demodulated signal Vin output from the rectifier circuit 11 is equal to or higher than the threshold voltage, the clocked comparator 12 outputs “1”, and if the demodulated signal Vin is smaller than the threshold voltage, outputs “0”. The threshold correction circuit 14 is a circuit for correcting the threshold voltage of the clocked comparator 12. Therefore, the clocked comparator 12 compares the demodulated signal output from the rectifier circuit 11 with the threshold value corresponding to the threshold correction signal VREF of the n-bit digital output corrected by the threshold correction circuit 14.

  The rectifier circuit 11 uses a clock pulse (φ1) supplied to the clock input terminal TC to apply a bias voltage, and the pulse width adjustment circuit 13 adjusts the clock width of the clock signal CLK to τ. The pulse φ1 is output. The rising edges of the clock signal CLK and the clock pulse φ1 are synchronized. Therefore, as shown in FIG. 4, noise (clock noise) synchronized with the clock pulse φ1 appears in the output from the rectifier circuit 11. If the time constant of the output of the rectifier circuit 11 is increased, clock noise synchronized with the clock pulse φ1 can be suppressed, but in this case, it is difficult to improve the data rate.

  In addition, when clock noise is generated in the output from the rectifier circuit 11, if the threshold voltage V <b> 3 of the random noise level smaller than the clock noise is set as the threshold voltage of the clocked comparator 12, the clocked comparator 12. May erroneously output “1” with respect to clock noise even when the input signal is 0V. Therefore, in order to correctly convert the output from the rectifier circuit 11, it is conceivable to set a threshold voltage V4 that is greater than the clock noise. However, when the threshold voltage is increased, the reception sensitivity is lowered.

  In order to prevent such a decrease in reception sensitivity, the clocked comparator 12 of this embodiment operates in synchronization with the falling edge of the clock signal CLK, as shown in FIG. By doing so, the clock noise synchronized with the clock pulse φ1 generated at the output from the rectifier circuit 11 and the operating phase of the clocked comparator 12 can be shifted. For this reason, it is not necessary to increase the threshold voltage beyond the clock noise, and the reception sensitivity can be improved without lowering the data rate.

  The reception sensitivity of the clocked comparator 12 is reduced by a DC offset voltage due to variations in elements in the clocked comparator 12. When the DC offset voltage greatly varies on the negative side, “1” may be output even if the input signal is 0 V (malfunction). For this reason, it is necessary to set the threshold voltage high in consideration of variations in the DC offset voltage. However, increasing the threshold voltage causes a decrease in reception sensitivity. Further, in order to reduce the DC offset voltage due to element variation, it is necessary to increase the element size, but the cost for increasing the element size increases.

  The threshold correction circuit 14 is a digital circuit for correcting the frequency of reception sensitivity degradation, malfunction due to the DC offset voltage of the clocked comparator 12, and malfunction due to noise by adjusting the threshold.

  FIG. 5 is a diagram showing an outline of the transition of the operation state of the threshold correction circuit 14. When the threshold voltage is corrected, the switch 15 is turned on to ground the input voltage Vin of the clocked comparator 12 to GND (ground).

  When the correction signal CAL = 1 is input in the initial state (S0), the state transits to the DC offset voltage correction state (S1).

  In the state (S1), the DC offset voltage of the clocked comparator 12 is searched. Since the input voltage Vin is grounded, the expected value of the output from the clocked comparator 12 is “0”. However, since the DC offset voltage varies in a normal distribution, it is not necessarily “0”. "May be output. Therefore, in the state (S1), first, a threshold correction signal VREF for setting the threshold voltage to an arbitrary voltage higher than the DC offset voltage is supplied to the clocked comparator 12.

  The DC offset voltage of the clocked comparator 12 is searched by the following linear search, for example. When the output from the clocked comparator 12 is “1”, the output VREF of the threshold correction circuit 14 (given as a threshold voltage to the clocked comparator 12) is increased, and the clocked comparator output is changed from “1” to “0”. The output VREF at the time when “” is reached is set as a correction threshold voltage. On the other hand, when the expected value of the output from the clocked comparator 12 is “1” (when the input voltage Vin is not grounded), when the output of the clocked comparator 12 is “0”, the threshold correction circuit 14 The output VREF is decreased, it is determined that the clocked comparator output has fallen below the threshold voltage at the time of switching from “0” to “1”, and the output VREF immediately before the switching is set as the correction threshold voltage. The correction threshold voltage may be set by searching for the DC offset voltage using another search algorithm.

  If the threshold voltage of the clocked comparator 12 is corrected to a voltage slightly higher than the DC offset voltage in the state (S1) for high sensitivity, the clocked comparator 12 may malfunction due to noise. There is. For this reason, the correction threshold voltage VREF is set so that the frequency of occurrence of malfunction due to noise (the output of the clocked comparator 12 is “1”) is equal to or lower than the predetermined frequency R by transitioning to the noise error correction state (S2). To do. It can be arbitrarily determined in advance how much malfunction is allowed to occur.

  In the state (S2), the output from the clocked comparator 12 is integrated for N samples, for example. The expected value of the output of the clocked comparator 12 is “0”, and “1” is output when a malfunction occurs. For this reason, the output integral value indicates the number M of times that malfunction occurred. Therefore, the malfunction occurrence frequency R1 generated in the output from the clocked comparator 12 is represented by R1 = M / N. If the malfunction occurrence frequency R1 is greater than the predetermined frequency R, the output VREF of the threshold correction circuit 14 is increased, and a larger threshold voltage is applied to the clocked comparator 12. On the other hand, if the malfunction occurrence frequency R1 is equal to or less than the predetermined occurrence frequency R, the output VREF of the threshold correction circuit 14 is held. That is, the output VREF of the threshold correction circuit 14 is increased until the occurrence frequency R1 = M / N of the malfunction becomes equal to or less than the arbitrarily set occurrence frequency R, and a larger threshold voltage is given to the cross comparator 12.

  When the DC offset voltage correction (S1) and the noise malfunction correction (S2) are completed, the correction signal CAL = 0 and the state transitions to the correction result holding state (S3). In the correction result holding state (S3), the threshold correction signal VREF is fixed, and the threshold voltage of the clocked comparator 12 appropriately corrected by the threshold correction by the threshold correction circuit 14 is held. The clocked comparator 12 compares the output from the rectifier circuit 11 with the held correction threshold voltage.

  While in the correction result holding state (S3), the corrected threshold voltage is held, but the threshold voltage and the DC offset voltage vary depending on the power supply voltage and temperature. For this reason, it is necessary to re-correct the threshold voltage according to changes in the surrounding environment. That is, the correction signal CAL = 1 is input in accordance with the environmental change, and the state transitions from the correction result holding state (S3) to the DC offset voltage correction (S1). In the DC offset voltage correction (S1), the appropriate threshold value is corrected again.

  In FIG. 1, a switch 15 is provided at the output of the rectifier circuit 11. However, when correction is performed in a state where the output from the rectifier circuit 11 includes noise, the switch 15 is provided at the input of the rectifier circuit 11. Further, when correction is performed in a state where the output includes noise from the antenna 10 and the rectifier circuit 11, the switch 15 may remain off.

  Thus, since the DC offset voltage of the clocked comparator 12 can be corrected by the threshold correction circuit 14, the threshold voltage is lower than the clock noise and close to random noise (threshold voltage V3 shown in FIG. 4). Therefore, it is possible to realize a highly sensitive and stable ASK demodulation circuit.

  FIG. 6 is a diagram illustrating an example of a circuit configuration of the clocked comparator 12. The clocked comparator 12 includes a dynamic latch 20 and a set reset latch (hereinafter abbreviated as SR latch) 30. The dynamic latch 20 consumes current only during clock operation. For this reason, there is a merit that power consumption when waiting for a radio signal is reduced.

  FIG. 7 is a diagram illustrating an example of a circuit configuration of the dynamic latch 20 according to the present embodiment. In FIG. 7, the output of the rectifier circuit 11 is connected to Vin.

  The dynamic latch 20 can also operate with a ground level input voltage. The dynamic latch 20 reduces power consumption by precharging the outputs Voutp and Voutn to GND (ground) while the clock signal CLK is “1”.

  The dynamic latch 20 includes a differential pair composed of MOS transistors M1 and M2, a latch circuit composed of MOS transistors M3 to M6, and MOS switches M7 to M9. When the value of the clock pulse CLK is 1, the MOS switches M7 and M8 are turned on and the MOS switch M9 is turned off. Therefore, no current flows, and the outputs Voutp and Voutn are precharged to GND.

  When the value of the clock pulse CLK becomes 0, the MOS switches M7 and M8 are turned off, and the outputs Voutp and Voutn are separated from GND. At the same time, since the MOS switch M9 is turned on, a current starts to flow.

  If the input voltage Vin is larger than the GND voltage, the current flowing in the left path including the MOS transistors M1, M3, and M5 becomes larger than the current flowing in the right path including the MOS transistors M2, M4, and M6, and Voutp, A potential difference is generated between Voutn. The positive feedback amplifier circuit composed of the MOS transistors M3 to M6 amplifies the output potential difference thus generated, and Voutp is set to VDD (power supply voltage) and Voutn is set to the GND voltage. This state is called a latch mode.

  As shown in FIG. 8, the dynamic latch 20 performs a comparison operation while switching between precharge and latch mode every half cycle. The SR latch 30 can be realized by a NAND SR latch, and performs the operations shown in the truth table of FIG. That is, when S (= Voutp) = 0 and R (= Voutn) = 1, “0” is output, and when S (= Voutp) = 1 and R (= Voutn) = 0, “1” is output. "Is output.

  The DC offset voltage of the dynamic latch 20 includes the MOS transistors M1 and M2, the MOS transistors M3 and M4, the MOS transistors M5 and M6, the MOS switches M7 and M8, and the load capacitances CL1 and CL2 of the outputs Voutp and Voutn that constitute the differential pair. Due to mismatch. As shown in FIG. 7, by making the value of the load capacitance CVER variable according to the n-bit threshold correction signal VREF input, the DC offset voltage can be adjusted and set to an arbitrary threshold. In FIG. 7, the threshold voltage increases when the variable capacitor CVER is increased with respect to the load capacitor CREF, and the threshold voltage decreases when the variable capacitor CVER decreases with respect to the load capacitor CREF.

  When it is desired to increase the reception sensitivity but it is not desired to transmit a malfunction due to noise to the subsequent stage, the noise is removed by the noise removal circuit 16 provided at the subsequent stage of the comparator 12. The noise removal circuit 16 determines that “0” is received when N bits are continuously input as “0” reception state, and “1” is received when N bits are continuously input as “1”. Further, a signal having a pulse width of N−1 bits or less is determined as noise and is not transmitted to the subsequent stage. It is assumed that the value of N can be set arbitrarily.

  FIG. 10 is a diagram illustrating an example of the operation of the noise removal circuit 16 when N = 2. As shown in FIG. 10, a pulse having a pulse width of N−1 = 1 bit is not output after being subjected to noise discrimination, and is not propagated to the subsequent stage. Therefore, even if “0” having a pulse width of 1 bit is input, it is determined as noise, and “1” is propagated to the subsequent stage. Conversely, even if “1” having a pulse width of 1 bit is input, it is determined as noise and “0” is propagated to the subsequent stage. An output signal having a pulse width of 2 bits or more is directly transmitted to the subsequent stage.

  As described above, in this embodiment, the clocked comparator 12 operates in synchronization with the falling edge of the clock signal CLK. Therefore, the phase of the clock noise generated by the rectifier circuit in synchronization with the rising edge of the clock signal CLK and the phase of the operation of the clocked comparator 12 can be shifted. Therefore, the influence of clock noise can be removed.

  In this embodiment, the threshold voltage of the clocked comparator 12 is corrected by the threshold correction circuit 14. By correcting the threshold voltage, the influence of the DC offset of the clocked comparator 12 can be removed. It is also possible to correct the threshold voltage of the clocked comparator 12 so that the allowable frequency of occurrence of malfunction is determined in advance and the occurrence of malfunction is less than the allowable frequency.

  Further, in the present embodiment, the noise removal circuit 16 provided at the subsequent stage of the clocked comparator 12 prevents the pulse narrower than the predetermined pulse width from being propagated to the subsequent stage as noise. Thereby, noise can be removed more accurately.

  In the future, as the miniaturization of semiconductors progresses, the overhead of digital circuits will be further reduced. For this reason, as shown in this embodiment, the merit of digitally correcting the threshold voltage is great.

Second Embodiment Hereinafter, a second embodiment of the ASK demodulation circuit according to the present invention will be described. In the description of the second embodiment, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 11 is a diagram showing a configuration of an ASK (Amplitude Shift Keying) demodulation circuit according to the second embodiment of the present invention.

  The ASK demodulator circuit shown in FIG. 11 includes a rectifier circuit 11, a clocked comparator 12, a pulse width adjustment circuit 13, a threshold correction circuit 14, a switch 15, and a noise removal circuit 16, as in FIG. The ASK demodulation circuit according to the present embodiment further includes a digital-analog conversion circuit (DAC) 17. A correction signal VREF which is a digital output of the threshold correction circuit 14 is supplied to the clocked comparator 12 as an analog correction voltage Vref via the DAC 17.

  FIG. 12 is a diagram illustrating an example of a circuit configuration of the dynamic latch 20 according to the second embodiment. In the first embodiment, the threshold voltage is set by the difference between the load capacitances CREF and CVER. However, in this embodiment, the analog correction voltage Vref from the DAC 17 corresponding to the threshold correction by the threshold correction circuit 14 is the dynamic latch. It is connected to the gate of 20 transistors M2. Based on the correction voltage Vref, the DC offset voltage of the clocked comparator 12 is corrected. When a capacitor array type DAC is used as the DAC 17, it is possible to reduce power consumption when waiting for a radio signal. However, other types of DACs may be used.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a diagram showing an example of the configuration of an ASK demodulator circuit according to a first embodiment of the present invention. The figure which shows an example of a structure of the rectifier circuit used for the ASK demodulator circuit of FIG. The figure which shows an example of a structure of the bias circuit used for the rectifier circuit of FIG. The figure which shows an example of the timing chart of an ASK demodulation circuit. The figure which shows an example of the outline of the operation state transition of a threshold value correction circuit. The figure which shows an example of the circuit structure of a clocked comparator. FIG. 3 is a diagram illustrating an example of a circuit configuration of a dynamic latch according to the first embodiment. The figure which shows an example of operation | movement of a clocked comparator. Truth table of SR latch. The figure which shows an example of operation | movement of a noise removal circuit. 6 shows an example of the configuration of an ASK demodulation circuit according to a second embodiment of the present invention. The figure which shows an example of the circuit structure of the dynamic latch which concerns on 2nd Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Antenna, 11 ... Rectifier circuit, 12 ... Clocked comparator, 13 ... Pulse width adjustment circuit, 14 ... Threshold correction circuit, 15 ... Switch, 16 ... Noise removal circuit

Claims (8)

Only the DC voltage is applied between the gate terminal and the source terminal, the bias circuit for outputting the DC voltage, the first MOS transistor to which only the DC voltage is applied between the gate terminal and the source terminal, and the first MOS transistor. And a second MOS transistor having a drain terminal connected to the source terminal of the first MOS transistor, a coupling capacitor having one end connected to the source terminal of the first MOS transistor and an AC signal input from the other end. A rectifier circuit that supplies the bias voltage at a predetermined timing;
A clocked comparator that compares the input signal rectified by the rectifier circuit with a threshold at a timing different from the predetermined timing and outputs a binary signal;
An amplitude shift keying demodulator comprising:   The amplitude shift keying demodulator according to claim 1, wherein the rectifier circuit operates in synchronization with a rising edge of a clock signal, and the comparator operates in synchronization with a falling edge of the clock pulse.   The amplitude shift keying demodulator according to claim 1, wherein the clocked comparator includes a dynamic latch and a set-reset latch.   The dynamic latch includes an input transistor unit to which an input signal and a threshold value are input, a positive feedback unit that operates according to the clock, and a load capacitor unit, and the load capacitor unit includes a fixed capacitor and a variable capacitor, The amplitude shift keying demodulator according to claim 3, wherein a threshold of the clocked comparator is adjusted by changing the variable capacitor.   The amplitude shift keying demodulator according to claim 1, further comprising threshold control means for detecting a DC offset voltage of the clocked comparator and setting the DC offset voltage as a threshold of the clocked comparator.   6. The amplitude shift keying demodulator according to claim 5, further comprising analog conversion means for converting the output from the threshold control means to analog and providing the result of analog conversion to the clocked comparator.   The amplitude shift keying demodulator according to claim 1, wherein a predetermined bias voltage is applied to the rectifier circuit. Only the DC voltage is applied between the gate terminal and the source terminal, the bias circuit for outputting the DC voltage, the first MOS transistor to which only the DC voltage is applied between the gate terminal and the source terminal, and the first MOS transistor. And a second MOS transistor having a drain terminal connected to the source terminal of the first MOS transistor, a coupling capacitor having one end connected to the source terminal of the first MOS transistor and an AC signal input from the other end. A rectifier circuit comprising: the bias voltage is supplied at a predetermined timing;
A comparator that compares the input signal rectified by the rectifier circuit with a threshold and outputs a binary signal is operated at a timing different from the predetermined timing;
Amplitude shift keying demodulation method.

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