JP4369820B2 - Switched capacitor amplifier circuit - Google Patents

Description

  The present invention relates to an offset cancel type switched capacitor amplifier circuit.

  A conventional offset cancel type switched capacitor amplifier circuit is configured so that an offset voltage is not generated in an output by storing an offset voltage of an operational amplifier in a capacitor (see, for example, Patent Document 1).

  An example of the circuit configuration of a conventional offset cancel type switched capacitor amplifier circuit is shown in FIG. In the reset phase Φ1, the switch circuits 123, 124, 125, 128, 129, 132 are closed. At this time, the capacitors 101, 102, 103, and 104 are discharged through the switch circuits 123, 124, 125, and 129. After a certain time, the switch circuits 123, 124, 125, 128, 129, 132 are opened, and the reset phase Φ1 ends.

Next, the process proceeds to the sampling phase Φ2. The switch circuits 121, 122, 126, 130, 128, 132 are closed. The voltage at the input terminal 141 is stored as a charge in the capacitor 101, and the voltage at the input terminal 142 is stored as a charge in the capacitor 102. The charge of the capacitor 103 changes by an amount equal to the change in the charge of the capacitor 101. At the same time, the charge in the capacitor 104 changes by an amount equal to the change in the charge in the capacitor 102. As a result, the voltage at the output terminal 151 changes.
The voltage at the output terminal 151 is given by the following equation.
Vout = − (C1 / C2) × (Vin1-Vin2)

The input offset voltage of the operational amplifier is stored in the capacitors 101 and 102 in the reset phase Φ1. The change in potential between both ends of the capacitor 101 during the sampling phase Φ 2 is the difference between the voltage at the input terminal 141 and the reference voltage applied to the switch 123. Similarly, the change in potential across the capacitor 102 during the sampling phase Φ2 is the difference between the voltage at the input terminal 142 and the reference voltage applied to the switch 124. Therefore, the change in the voltage stored between both ends of the capacitors 101 and 102 is the difference between the input voltage and the reference voltage, and does not include the offset voltage. For this reason, the offset voltage of the operational amplifier is not amplified and canceled.
US Pat. No. 4,543,534 “Offset compensated switched capacitor circuits”

  However, the conventional switched capacitor amplifier circuit can cancel the offset voltage of the operational amplifier, but when the input voltage itself has an offset voltage or offset temperature characteristic, the offset voltage is amplified and output. It was.

The present invention solves such a problem. A voltage applied to a sampling capacitor that feeds back an output voltage to an operational amplifier is set as a first reference voltage and a second reference voltage different from the reference voltage, A configuration that can be controlled separately, such as having temperature characteristics.
Further, the voltage applied to the capacitor connected to the terminal opposite to the output terminal of the operational amplifier at the time of single-end output is set as a third reference voltage different from the reference voltage.

  The switched capacitor amplifying circuit of the present invention can amplify only the signal component by canceling the offset voltage and temperature characteristics of the input voltage with low noise by adopting the above configuration.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an example of a configuration diagram of a switched capacitor amplifier circuit according to the present invention. In the reset phase Φ1, the switch circuit 123 is closed, the capacitor 101 is connected to the node 111, the switch circuit 124 is closed, the capacitor 102 is connected to the node 112, the switch circuit 125 is closed, and the capacitor 103 is connected to Vref1. 129 is closed and the capacitor 104 is connected to Vref2. After a certain time, the switch circuits 123, 124, 125, 129 are opened, and the reset phase Φ1 ends. During the reset phase Φ1, the charge stored in the capacitor 101 is
q = C1 × VREF
The charge stored in the capacitor 102 is
q = C1 × (VREF−VOFF)
The charge stored in the capacitor 103 is
q = C2 × Vref1
The charge stored in the capacitor 104 is
q = C2 × Vref2
It becomes.

Next, the process proceeds to the sampling phase Φ2. The switch circuits 121, 122, 126, 130, 128, 132 are closed. The voltage at the input terminal 141 is stored as a charge in the capacitor 101, and the voltage at the input terminal 142 is stored as a charge in the capacitor 102. The charge of the capacitor 103 changes by an amount equal to the change in the charge of the capacitor 101. At the same time, the charge in the capacitor 104 changes by an amount equal to the change in the charge in the capacitor 102. As a result, the voltage at the output terminal 151 changes. The charge stored in the capacitor 101 in the sampling phase Φ2 is
q = C1 × Vin1
The charge stored in the capacitor 102 is
q = C1 × Vin2
It becomes.

Therefore, the amount of change in the charge amount of the capacitor 101 after the change from the reset phase Φ1 to the sampling phase Φ2 is
Δq = C1 × (Vin1−VREF)
The change in the amount of charge in the capacitor 102 is
Δq = C1 × (Vin2− (VREF−VOFF))
The change in the amount of charge in the capacitor 103 is
Δq = C2 × (VOUT−Vref1)
The change in the amount of charge in the capacitor 104 is
Δq = C2 × (VREF−Vref2)
It becomes.

When the voltage Vin1 at the input terminal 141 consists of the signal voltage Vinp and the offset voltage Vos, and the voltage Vin2 at the input terminal 142 consists only of the signal voltage Vinn,
The voltage Vout of the output terminal 151 is
Vout = − (C1 / C2) × ((Vin1−Vin2) − (VREF− (VREF−VOFF))) + (Vref1−Vref2 + VREF)
= − (C1 / C2) × ((Vinp + Vos −Vinn) −VOFF)) + (Vref1−Vref2 + VREF)
= − (C1 / C2) × ((Vinp−Vinn) + (Vos−VOFF)) + (Vref1−Vref2 + VREF)
Given in.

  That is, by adjusting VOFF = Vos, the offset voltage of the input voltage can be canceled with low noise, and even when Vos = VOFF does not hold, fine adjustment can be performed with Vref1-Vref2. Also, it can be seen that Vref1 and Vref2 have a large noise but are not amplified, and thus have little influence on the output voltage.

  Furthermore, it is possible to cancel the temperature dependence of the offset voltage of the input voltage by providing one of Vref1 and Vref2 with temperature characteristics. For example, Vref1 is a reference voltage having no temperature characteristic, and Vref2 is temperature characteristic. By doing so, it becomes possible to cancel the temperature dependence of the offset voltage of the input voltage using Vref2 having temperature dependence, and to adjust the absolute value of the offset voltage of the input voltage using Vref1.

  By switching the node that provides Vref1 and Vref2 with a switch, it becomes possible to provide temperature correction with a polarity opposite to the temperature-dependent polarity.

  Thus, in the circuit system of the present invention, the offset voltage and temperature dependency of the input voltage can be canceled with low noise, and only the signal component can be amplified.

  It is obvious that the present invention can also be implemented in a fully differential circuit having two inputs and two outputs. By taking a fully differential circuit configuration, an effect of further reducing common-mode noise can be obtained.

  The circuit shown in this embodiment is an example of a switched capacitor amplifier circuit, and it is obvious that the circuit can be implemented in other types of switched capacitor amplifier circuits.

  The value of the offset voltage included in the input voltage is known in advance, and the fixed voltage value may be a fixed resistor, but if the value of the offset voltage included in the input voltage is unknown, the voltage value is set to the offset voltage. By using a variable voltage that can be adjusted in accordance with the offset voltage, it is possible to adjust the offset voltage while observing the output voltage.

It is a circuit diagram of the switched capacitor amplifier circuit of the present invention. It is a circuit diagram of the conventional switched capacitor amplifier circuit.

Explanation of symbols

100 operational amplifier
101, 102, 103, 104, 105, 106 capacity
111, 112 Reference voltage
121, 122, 123, 124, 125, 126, 127, 128, 129,
130, 131, 132, 133, 134 Switch circuit
141, 142 input terminals
151, 152 output terminals

Claims (2)

In a switched capacitor amplifier circuit,
An operational amplifier,
Provided between the first input terminal of the switched capacitor amplifier circuit and the first input terminal of the operational amplifier, and a voltage obtained by subtracting the first reference voltage from the voltage of the first input terminal of the switched capacitor amplifier circuit during a predetermined period. Based on the first capacity, the amount of charge changes,
A voltage provided between the second input terminal of the switched capacitor amplifier circuit and the second input terminal of the operational amplifier, and a voltage obtained by subtracting a second reference voltage from the voltage of the second input terminal of the switched capacitor amplifier circuit during the predetermined period Based on the second capacity, the charge amount changes,
A third amount is provided between the first input terminal of the operational amplifier and the output terminal of the operational amplifier, and the charge amount changes based on a voltage obtained by subtracting the first reference voltage from the voltage of the output terminal of the operational amplifier during the predetermined period. Capacity,
The charge amount is changed based on a voltage obtained by subtracting the second reference voltage from the first reference voltage in the predetermined period, provided between the second input terminal of the operational amplifier and the terminal to which the first reference voltage is applied. With a fourth capacity to
A switched capacitor amplifier circuit comprising:   2. The switched capacitor amplifier circuit according to claim 1, wherein one of the first reference voltage and the second reference voltage has a temperature characteristic.

Images