JP4343198B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including an MIM capacitor and a manufacturing method thereof.

  In a conventional semiconductor device, aluminum (Al) wiring is generally used as a metal wiring for electrically connecting elements formed on a Si wafer. The Al film formed on the insulating film is patterned by photolithography and anisotropic etching. However, with the miniaturization of integrated circuit elements and wiring, it is becoming difficult to form a low-resistance wiring, and it is also difficult to form a wiring by anisotropic etching and embed an insulating film in a space between wirings. Therefore, in recent years, copper (Cu) wiring by a damascene process has been used as metal wiring instead of Al wiring.

On the other hand, a capacitor is usually indispensable in an LSI mounting an analog circuit. As the analog circuit capacitor, an MIM (Metal-Insulator-Metal) capacitor that can stably obtain a large capacitance is used. Since the MIM capacitor uses metal for the upper and lower electrodes, a part of the process of forming the Cu multilayer wiring by the damascene process and the process of forming the MIM capacitor can be shared. Various process technologies for coexisting MIM capacitors and Cu damascene wiring have been proposed (see, for example, Patent Document 1).
JP2002-270769

  When the analog circuit using the MIM capacitor is a high-frequency circuit, in order to prevent the transmitted signal from deteriorating and realize high speed performance, the capacitance between the multilayer wirings must be reduced. It is desirable to use an insulating film having a low dielectric constant. However, in general, a low dielectric constant insulating film has poor step coverage. As a method for improving the coverage of the insulating film on the side wall of the MIM capacitor, a film forming method using a high-density plasma (HDP) type plasma CVD apparatus can be considered, but the insulating film formed by this method generally has high hygroscopicity. Also, heat shrinkage is large. For this reason, adhesiveness with other films such as metal is deteriorated, and metal corrosion and film peeling due to moisture absorption are likely to occur.

  Therefore, it is difficult to obtain high reliability of the MIM capacitor in the semiconductor device having the MIM capacitor and the Cu multilayer wiring by the damascene process.

  An object of the present invention is to provide a semiconductor device with improved reliability of the MIM capacitor and a manufacturing method thereof.

A semiconductor device according to an aspect of the present invention includes a semiconductor substrate, a first wiring formed on the semiconductor substrate via a first insulating film, and an MIM capacitor formed on the first insulating film. A second insulating film formed to cover the MIM capacitor; a second wiring formed to be embedded in the second insulating film; and the second insulating film so as to surround the MIM capacitor. And a guard ring embedded so as to pass through .

A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first wiring on a semiconductor substrate via a first insulating film, and a step of forming an MIM capacitor on the first insulating film. A step of forming a second insulating film so as to cover the MIM capacitor; a second wiring embedded in the second insulating film; and a guard surrounding the MIM capacitor in the second insulating film Embedding the ring so as to penetrate the second insulating film .

  As described above, according to the present invention, it is possible to provide a semiconductor device in which the reliability of the MIM capacitor is improved and a manufacturing method thereof.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a plan view showing an integrated structure of a Cu multilayer wiring and an MIM capacitor in a semiconductor device according to an embodiment, and FIG. 2 is a cross-sectional view taken along the line I-I ′ of FIG. Although not shown, transistors and the like are formed on the silicon substrate 1. A first wiring 3 is formed on the first interlayer insulating film 2 formed on the silicon substrate 1. The interlayer insulating film 2 is a silicon oxide film, and its surface is flattened. The first wiring 3 is a Cu film having a barrier metal made of, for example, tantalum (Ta) and / or tantalum nitride (TaN) embedded in the insulating film 2 by a damascene process. Although not shown in the figure, the first wiring 3 is connected to an element formed on the silicon substrate 1 through a contact hole using a dual damascene process.

  A block insulating film 4 made of a silicon nitride film (SiN film) that covers the first wiring 3 is formed on the interlayer insulating film 2 on which the first wiring 3 is formed. An MIM capacitor 5 is formed on the block insulating film 4. The MIM capacitor 5 has a laminated structure of a lower electrode 5a, a dielectric film 5b, and an upper electrode 5c. The lower electrode 5a and the upper electrode 5c are, for example, titanium nitride (TiN) films, and the dielectric film 5b is, for example, a silicon nitride (SiN) film.

  The MIM capacitor 5 is covered with a second interlayer insulating film 6, and the surface thereof is flattened. The interlayer insulating film 6 is a film having a dielectric constant lower than that of a normal dTEOS-SiO2 film (a silicon oxide film made of TEOS by a dual plasma CVD process), preferably a low dielectric constant having a relative dielectric constant (k) of 3.5 or less. It is a rate film. Specifically, the interlayer insulating film 6 includes an FSG (Fluoro-Silicate Glass) film that is a silicon oxide film containing fluorine (F), a silicon oxide film containing carbon (C), and porous silicon in which pores are introduced. It is a kind selected from oxide films.

  A second wiring 7 is formed in the interlayer insulating film 6 by a dual damascene process. The second wiring 7 is a Cu film having a barrier metal made of, for example, tantalum (Ta) and / or tantalum nitride (TaN) as a base, which is buried and planarized on the upper surface of the interlayer insulating film 6. The second wiring 7 is connected to the first wiring 3 through the wiring via hole 8. The interlayer insulating film 6 is also a contact plug that contacts the lower electrode 5a and the upper electrode 5b of the MIM capacitor 5 formed by embedding the same material as the second wiring 7 in a hole formed simultaneously with the wiring via hole 8. 10 is embedded.

  Further, a guard ring 9 is embedded in the interlayer insulating film 6 so as to surround the MIM capacitor 5. The guard ring 9 is not connected to the MIM capacitor 5 or the wiring. The guard ring 9 is preferably a metal ring formed of the same material as the second wiring 7 so as to penetrate the interlayer insulating film 6 at the same time. The width of the guard ring 9 can be selected in the range of 0.1 μm to 1 μm, but preferably about 1 μm. The guard ring 9 functions as a barrier that suppresses cracks from spreading from the periphery of the MIM capacitor 5 into the interlayer insulating film 6 due to insufficient step coverage of the interlayer insulating film 6, and from the side surface of the chip. It also functions as a barrier that prevents the diffusion of moisture entering the MIM capacitor 5.

  On the interlayer insulating film 6 on which the second wiring 7, the contact plug 10 and the metal ring 9 are formed, a block insulating film 14 made of a silicon nitride film (SiN film) and an interlayer made of a TEOS-SiO2 film are formed. The insulating film 11 is formed sequentially. A third wiring 12 that electrically connects the second wiring 7 and the MIM capacitor 5 is formed on the interlayer insulating film 11 by a dual damascene process. The third wiring 12 is a Cu film having a barrier metal made of, for example, tantalum (Ta) and / or tantalum nitride (TaN), which is buried and planarized in the upper surface of the interlayer insulating film 11. The third wiring 12 is connected to the second wiring 7 and the contact plug 10 through the via hole 13. Accordingly, the third wiring 12 electrically connects the MIM capacitor 5 and the second wiring 7. Alternatively, the third wiring 12 may electrically connect the first wiring 3 and the MIM capacitor 5.

  A specific manufacturing process will be described with reference to FIGS. 3 to 9 correspond to the cross section of FIG. As shown in FIG. 3, a SiO 2 film is deposited as a first interlayer insulating film 2 on a silicon substrate 1 on which elements are formed, and is flattened. A first wiring 3 is flatly embedded in the upper surface of the interlayer insulating film 2 by a damascene process. The process of forming the first wiring 3 will be specifically described as follows.

  First, a wiring trench 21 is formed in the interlayer insulating film 2 by lithography and RIE (Reactive Ion Etching). Next, a TaN (and / or Ta) film as a barrier metal and a Cu film as a wiring material are sequentially formed by a PVD (Physical Vapor Deposition) method. A Cu film is embedded in the wiring trench 21 by electroplating using the obtained TaN / Cu film as an electrode. Subsequently, the TaN / Cu film is planarized by a CMP (Chemical Mechanical Polishing) process. Thereby, the TaN / Cu film in the region other than the wiring trench 21 is removed, and the first wiring 3 is embedded only in the wiring trench 21. In order to connect the first wiring 3 to the diffusion layer of the silicon substrate, a wiring groove and a wiring contact hole may be formed by a dual damascene process.

  Next, as shown in FIG. 4, after depositing a SiN film of about 0.1 μm as a block insulating film 4 covering the wiring 3, an MIM capacitor 5 is formed thereon. Specifically, a laminated film of a TiN film to be the lower electrode 5a, a SiN film to be the dielectric film 5b, and a TiN film to be the upper electrode 5c is sequentially formed. The thickness of the lower electrode 5a is 0.3 μm, and the total thickness of the capacitor insulating film 5b and the upper electrode 5c is 0.1 μm. About this TiN / SiN / TiN laminated film, the upper electrode 5c is patterned by lithography and RIE using Cl-based gas. Subsequently, the dielectric film 5b is patterned by lithography and RIE using a CF-based gas. Finally, the lower electrode 5a is patterned again by lithography and RIE using a Cl-based gas.

  Next, as shown in FIG. 5, a second interlayer insulating film 6 covering the MIM capacitor 5 is deposited and planarized by CMP. The interlayer insulating film 6 is an FSG film, a silicon oxide film to which C is added, or a porous silicon oxide film. In order to facilitate planarization by CMP, a normal TEOS-SiO2 film may be further laminated on the surface of these low dielectric constant films.

  The method of forming these interlayer insulating films 6 is as follows. The FSG film is preferably formed by using a parallel plate type plasma CVD apparatus and supplying a gas containing F containing SiH4 as a main material. By this film formation method, an FSG film with good adhesion and no film peeling is formed. In the case of a silicon oxide film containing C, a film is formed by a CVD method using Black-diamond (trade name of Applied Materials, Inc.) as a raw material. In the case of a porous silicon oxide film, an organic SOG (Spin-on-Glass) film is formed and formed into a porous film by a forming reaction by heating or irradiation with an energy beam.

  Next, a second wiring 7, a metal ring 9, and a contact plug 10 are formed in the interlayer insulating film 6 by a dual damascene process. Specifically, as shown in FIG. 6, the wiring via hole 8, the electrode contact hole 32, and the guard ring groove 33 are formed in the interlayer insulating film 6 by lithography and RIE. The guard ring groove 33 is formed so that the bottom surface thereof is located below the bottom surface of the MIM capacitor 5 and the underlying interlayer insulating film 2 is exposed. The via hole 8 and the contact hole 32 have a diameter of 0.2 μm, and the guard ring groove 33 has a width of 1 μm. Subsequently, a wiring groove 34 continuous with the wiring via hole 8 is formed by lithography and an RIE method using a CF-based gas.

  Next, a TaN (and / or Ta) film as a barrier metal and a Cu film as a wiring material are sequentially formed by a PVD method. By using the obtained TaN / Cu film as an electrode, a Cu film is embedded in the wiring groove 34, the via hole 8, the contact hole 32, and the guard ring groove 33 by electroplating. Subsequently, the TaN / Cu film is planarized by CMP. As a result, as shown in FIG. 7, simultaneously with the second wiring 7, the contact plug 10 of the MIM capacitor 5 and the metal ring 9 surrounding the MIM capacitor 5 are embedded in the interlayer insulating film 6 flatly.

  As described above, in this embodiment, the wiring connection to the MIM capacitor 5 is not performed in the step of forming the embedded wiring in the interlayer insulating film 6 covering the MIM capacitor 5. In the region of the MIM capacitor 5, only the contact plug 10 is embedded. Electrical connection to the MIM capacitor 5 is performed by the following third wiring. Accordingly, a state where the interlayer insulating film 6 is thin and the bottom surface position of the second wiring 7 embedded in the interlayer insulating film 6 is lower than the top surface of the MIM capacitor 5 is allowed.

  Next, as shown in FIG. 8, an SiN film is deposited as the block insulating film 14, and a TEOS-SiO 2 film is deposited as the third interlayer insulating film 11. A third wiring for electrically connecting at least one of the second wiring 7 and the first wiring 3 and the MIM capacitor 5 is formed on the interlayer insulating film 11 by a dual damascene process. More specifically, as shown in FIG. 8, the wiring via hole 13 is formed in the interlayer insulating film 11 by RIE, and the wiring groove 43 continuing to these is formed. A via hole is not formed on the metal ring 9, and the metal ring 9 is brought into an electrically floating state.

  Then, in the same process as the embedding of the second wiring 7, as shown in FIG. 9, the third wiring 12 made of a TaN / Cu film is embedded in the via hole 13 and the wiring groove 43. The third wiring 12 is connected to the upper and lower electrodes of the MIM capacitor 5 through the contact plug 10 previously embedded in the interlayer insulating film 6 in the step of forming the second wiring 7. Even when the third wiring 12 electrically connects the first wiring 3 and the MIM capacitor 5, the third wiring 12 can be formed by the same process.

  Thereafter, although not shown, a laminated film of a SiO2 film and a SiN film by plasma CVD is deposited as a passivation film. The passivation film is subjected to sinter annealing for 60 minutes in an H 2 atmosphere at 400 ° C. Finally, a pad is formed.

  As described above, according to this embodiment, the reliability of the MIM capacitor is increased by embedding the guard ring so as to surround the MIM capacitor in the interlayer insulating film covering the MIM capacitor. The reason will be specifically described. In order to reduce the inter-wiring capacitance, it is preferable that the interlayer insulating film covering the MIM capacitor is a low dielectric constant film as described above. However, the low dielectric constant insulating film has poor step coverage and low mechanical strength. Therefore, the low dielectric constant insulating film is easily peeled off due to external stress or cracks are easily generated.

  FIG. 10 shows a state in which the Cu multilayer wiring and the MIM capacitor 5 are formed under the same conditions as in the above embodiment except that the guard ring 9 is not provided, corresponding to FIG. When the step coverage of the interlayer insulating film 6 covering the MIM capacitor 5 is insufficient, a seam 51 is formed at the side wall step portion of the MIM capacitor 5 as shown in FIG. If stress is applied to the interlayer insulating film 6 due to contraction of the electrodes of the MIM capacitor 5 in a later heat process, cracks 52 are likely to be generated in the lateral direction in the interlayer insulating film 6 from the seam 51 as illustrated.

  If the seam 51 and the crack 52 reach the wiring 7 and the via hole 8, the barrier metal under the wiring is cracked, and Cu diffuses into the seam 51 and the crack 52. This causes a short circuit and insulation failure between the wiring 7 and the MIM capacitor 5. Furthermore, since the low dielectric constant insulating film has a low film density, moisture and the like are likely to penetrate from the outside. Therefore, after dicing the semiconductor chip, water may diffuse from the side surface of the chip through the low dielectric constant interlayer insulating film 6 to the inside. The MIM capacitor 5 is usually subject to a high electric field. Therefore, when water enters the MIM capacitor 5 through the interlayer insulating film 6, the breakdown voltage and reliability of the capacitor deteriorate.

  According to this embodiment, even if a seam is formed from the side wall portion of the MIM capacitor 5 in the interlayer insulating film 6, the guard ring 9 cuts it. Thereby, generation | occurrence | production of a crack is prevented in a subsequent heat process. Accordingly, it is possible to prevent a short circuit or insulation failure between the MIM capacitor and the wiring. The guard ring also serves as a barrier that prevents diffusion of moisture entering from the side surface of the chip into the region of the MIM capacitor 5. Thereby, deterioration with time of the MIM capacitor is also suppressed.

  Furthermore, in this embodiment, since the guard ring is embedded in the same material and in the same process as the wiring, it is not necessary to add a special process for forming the guard ring.

  In the above embodiment, the guard ring embedded in the interlayer insulating film covering the MIM capacitor is the Cu layer formed at the same time as the Cu wiring by the damascene process. Other materials that can prevent this can be used. For example, tungsten (W) or aluminum (Al) can be used for a conductive material, and USG (Undoped Silicate Glass) using TEOS-SiO2 or an HDP type plasma CVD apparatus can be used for an insulating material. Can do. Of course, in order to form the guard ring with these materials different from the wiring material, a process different from the wiring forming process is required.

  In the following, some experimental examples and reference examples for comparison are described. In the test wafers of the following experimental examples and reference examples, 100 M × 10 μm 2 square MIM capacitors are arranged in each chip area, 10 vertically and 10 by 2 μm space, to form the above-described three-layer Cu wiring. did.

[Experiment 1]
In the test wafer of Experimental Example 1, a 0.6 μm FSG film formed by a parallel plate type plasma CVD apparatus was used as the second interlayer insulating film 6. Each MIM capacitor is surrounded by the metal ring 9 formed simultaneously with the second wiring as described above. The test chip diced from this wafer had good initial characteristics, and there was no short circuit or open failure. As a result of the pressure resistance test, no defect was found up to 50V. As a result of a TDDB (Time Dependent Dielectric Breakdown) test in which a voltage of 20 V was applied to the MIM capacitor, a lifetime of 10 years or more was confirmed.

[Experimental example 2]
As the second interlayer insulating film 6, a test chip is diced on a test wafer having the same conditions as in Experimental Example 1 except that a film using Black-diamond as a raw material and a TEOS-SiO 2 film are used. Tested. In the pressure resistance test and the TDDB test, good results similar to those of Experimental Example 1 were obtained. In addition, as a result of performing a high humidity test at 30 ° C. and a humidity of 90% or more, no change in the characteristics of the MIM capacitor was observed after 500 hours.

[Reference Example 1]
A test wafer prepared under the same conditions as in Experimental Example 1 except that the metal ring 9 was not provided was diced into chips and subjected to the same test. As with the case of Experimental Example 1, the initial characteristics were not problematic. In the withstand voltage test, a withstand voltage failure occurred from around 10V. As a result of analyzing the defective portion, a seam was generated in the direction of 45 ° from the lower portion of the side wall of the MIM capacitor, and further cracks were observed from the seam. As a result of analysis by EDX, diffusion of Cu was recognized in the crack.

In the upper defective portion, seam was observed in the observation immediately after the formation of the FSG film, but no crack was observed. It was confirmed that the crack was generated by sintering annealing after forming the passivation film.
As a result of the TDDB test, it was confirmed that the lifetime of one digit was shorter than that of the chip of Experimental Example 1.

[Reference Example 2]
A test wafer made under the same conditions as in Experimental Example 2 except that there was no metal ring 9 was tested by dicing the chip. The initial characteristics were not problematic as in Experimental Example 2. As a result of the withstand voltage test, a withstand voltage failure occurred at 50 V or less. As a result of performing a high humidity test at 30 ° C. and a humidity of 90% or more, a change in characteristics of the MIM capacitor was observed within 500 hours.

[Reference Example 3]
A test wafer was manufactured under the same manufacturing conditions as in Experimental Example 1 except that the FSG film formation conditions were different. Specifically, the FSG film was formed by using an HDP type plasma CVD apparatus using SiOF as a raw material. Although the relative dielectric constant (k) of the FSG film was 3.5 or less, the FSG film peeled off during the CMP process after the formation of the FSG film, and it was not possible to proceed to the subsequent steps.

1 is a plan view of a semiconductor device according to an embodiment of the present invention. It is I-I 'sectional drawing of FIG. FIG. 10 is a cross-sectional view showing a step of forming a first wiring on the first interlayer insulating film in the same embodiment. It is sectional drawing which shows the process of forming a MIM capacitor on the interlayer insulation film in which the 1st wiring was formed. It is sectional drawing which shows the process of forming the 2nd interlayer insulation film which covers a MIM capacitor. It is sectional drawing which shows the process of forming a via hole, a contact hole, a guard ring groove | channel, and a wiring groove | channel in the 2nd interlayer insulation film. It is sectional drawing which shows the process of embedding a metal in a via hole, a contact hole, a guard ring groove | channel, and a wiring groove | channel, respectively. It is sectional drawing which shows the process of forming the 3rd interlayer insulation film which covers 2nd wiring, and forming a via hole and a wiring groove | channel in this. It is sectional drawing which shows the process of forming 3rd wiring. It is sectional drawing of the semiconductor device of a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... 1st interlayer insulation film, 3 ... 1st wiring, 4 ... Block insulation film, 5 ... MIM capacitor, 5a ... Lower electrode, 5b ... Dielectric film, 5c ... Upper electrode, 6 ... 2nd interlayer insulation film, 7 ... 2nd wiring, 8 ... Via hole, 9 ... Guard ring (metal ring), 10 ... Contact plug, 11 ... 3rd interlayer insulation film, 12 ... 3rd wiring, 13 ... via hole, 21 ... wiring groove, 32 ... contact hole, 33 ... guard ring groove, 34, 43 ... wiring groove.

Claims (20)

A semiconductor substrate;
A first wiring formed on the semiconductor substrate via a first insulating film;
An MIM capacitor formed on the first insulating film;
A second insulating film formed over the MIM capacitor;
A second wiring formed embedded in the second insulating film;
A guard ring embedded so as to penetrate the second insulating film so as to surround the MIM capacitor;
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the second wiring is connected to the first wiring through a hole formed in the second insulating film. The semiconductor device according to claim 2, wherein the guard ring is a metal ring embedded through the second insulating film with the same material as the second wiring. 4. The semiconductor device according to claim 3, wherein the second wiring and the metal ring are a Cu layer having a barrier metal as a base. The semiconductor device according to claim 1, wherein the second insulating film has a relative dielectric constant of 3.5 or less. 6. The semiconductor device according to claim 5, wherein the second insulating film is a silicon oxide film containing fluorine. 6. The semiconductor device according to claim 5, wherein the second insulating film is a silicon oxide film containing carbon. 6. The semiconductor device according to claim 5, wherein the second insulating film is a porous silicon oxide film. The semiconductor device according to claim 1, further comprising a block insulating film that covers the first wiring between the first insulating film and the second insulating film. A contact plug embedded in the second insulating film with the same material as the second wiring and contacting the upper and lower electrodes of the MIM capacitor;
A third insulating film formed on the second insulating film so as to cover the second wiring;
2. A third wiring formed on the surface of the third insulating film and electrically connecting at least one of the first and second wirings and the MIM capacitor. Semiconductor device. Forming a first wiring through a first insulating film formed on a semiconductor substrate;
Forming a MIM capacitor on the first insulating film;
Forming a second insulating film so as to cover the MIM capacitor;
Embedding and forming a second wiring in the second insulating film and embedding a guard ring surrounding the MIM capacitor in the second insulating film so as to penetrate the second insulating film ;
A method for manufacturing a semiconductor device, comprising: The second wiring and the guard ring are formed with a via hole, a wiring groove continuous with the via hole, and a guard ring groove surrounding the MIM capacitor formed in the second insulating film, and then the via hole, the wiring groove, 12. The method of manufacturing a semiconductor device according to claim 11, wherein the semiconductor device is formed simultaneously by embedding a wiring material in the guard ring groove. Forming a third insulating film on the second insulating film so as to cover the second wiring;
Forming a third wiring for electrically connecting at least one of the first and second wirings and the MIM capacitor on the third insulating film by a dual damascene process. A method for manufacturing a semiconductor device according to claim 11. 4. The semiconductor device according to claim 3, wherein the metal ring is in an electrically floating state. 2. The semiconductor device according to claim 1, wherein the guard ring is formed so as to cut a seam formed from around the MIM capacitor in the second insulating film. 2. The semiconductor device according to claim 1, wherein a width of the guard ring is in a range of 0.1 [mu] m to 1 [mu] m. The third wiring semiconductor device according to claim 10, wherein it is connected to the MIM capacitor via the contact plug. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the second wiring and the metal ring are a Cu layer having a barrier metal as a base. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the second insulating film has a relative dielectric constant of 3.5 or less. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the guard ring is formed so as to cut a seam formed around the MIM capacitor in the second insulating film. .

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