JP4224430B2 - 情報処理装置 - Google Patents
情報処理装置 Download PDFInfo
- Publication number
- JP4224430B2 JP4224430B2 JP2004165435A JP2004165435A JP4224430B2 JP 4224430 B2 JP4224430 B2 JP 4224430B2 JP 2004165435 A JP2004165435 A JP 2004165435A JP 2004165435 A JP2004165435 A JP 2004165435A JP 4224430 B2 JP4224430 B2 JP 4224430B2
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- data
- coprocessor
- accelerator
- main processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000010365 information processing Effects 0.000 title claims abstract description 26
- 238000012546 transfer Methods 0.000 claims abstract description 39
- 238000012545 processing Methods 0.000 abstract description 108
- 238000007667 floating Methods 0.000 description 90
- 230000006870 function Effects 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 230000007704 transition Effects 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 10
- 238000004364 calculation method Methods 0.000 description 8
- 102100026693 FAS-associated death domain protein Human genes 0.000 description 7
- 101000911074 Homo sapiens FAS-associated death domain protein Proteins 0.000 description 7
- 101150071111 FADD gene Proteins 0.000 description 5
- 230000004913 activation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000004044 response Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- NGGRGTWYSXYVDK-RRKCRQDMSA-N 4-amino-5-chloro-1-[(2r,4s,5r)-4-hydroxy-5-(hydroxymethyl)oxolan-2-yl]pyrimidin-2-one Chemical compound C1=C(Cl)C(N)=NC(=O)N1[C@@H]1O[C@H](CO)[C@@H](O)C1 NGGRGTWYSXYVDK-RRKCRQDMSA-N 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
- G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Devices For Executing Special Programs (AREA)
Description
ステータスレジスタをコプロセッサ搭載モードに設定し、通常モードに復帰する。このとき、復帰先のアドレスが起動命令なので、該バイトコードからバイトコードアクセラレータは復帰できる。バイトコードのアドレス(JavaPC)は起動命令の引数のレジスタ値として与えればよい。
3 メモリ(MEM)
2 キャッシュ(CACHE)
4 中央処理装置(CPU)
10 命令フェッチ部(FETc)
12、20 デコード部(DECc、DECf)
13、21 実行部(EXEc、EXEf)
14、22、33 制御部(CTLc、CTLf、CTL)
15 CPUレジスタファイル(GREG_FILE)
23 FPUレジスタファイル(FREG_FILE)
6 バイトコードアクセラレータ(BCA)
30 変換テーブル部(TRS_TBL)
31 データチェック部(DATA_CHK)
32 模擬パイプライン部(PL_SIM)
50 ソフト仮想マシン(SOFT_VM)
51 初期化ルーチン部(INITIALIZE)
52 起動部(HOOKUP)
53 ディスパッチテーブル部(DISPACTH TABLE)
54 インタプリタ部(INTERPRETER)
ACTIVE 起動
DEACT 停止
UNSUPPORT BCODE 非サポートバイトコード検出
IDGET 命令受理信号
E1GO 命令発行信号
BTCNCL、IDCNCL、E1CNCL、E2CNCL キャンセル信号
EXP_BUS 外部バス
PC プログラムカウンタ
SPC 例外保存用プログラムカウンタ
PR サブルーチン保存用プログラムカウンタ
Rjp 汎用レジスタの一つ
Claims (6)
- メインプロセッサと、メインプロセッサにデータバスで接続されたコプロセッサと、前記メインプロセッサが実行可能なネイティブ命令と異なる命令セットに含まれる仮想マシン命令をネイティブ命令に変換可能なアクセラレータとを有し、
前記アクセラレータは、コプロセッサを利用してデータ演算を行う仮想マシン命令を前記コプロセッサが実行する演算用のネイティブ命令とメインプロセッサが実行するレジスタ間転送用のネイティブ命令に変換し、
前記メインプロセッサは、前記コプロセッサが前記演算用のネイティブ命令を実行する前に前記レジスタ間転送用のネイティブ命令を実行し、
前記メインプロセッサは、前記演算用のネイティブ命令に前記コプロセッサが取り扱えないデータが含まれていることが検出された場合は、前記コプロセッサが前記演算用のネイティブ命令を実行する前に、前記コプロセッサの演算を抑止するための信号を前記コプロセッサに送信し、
前記演算用のネイティブ命令に前記コプロセッサが取り扱えないデータが含まれていることの検出は、前記レジスタ間転送用のネイティブ命令によるデータ転送を行っている間に前記アクセラレータが行うことを特徴とする情報処理装置。 - 前記レジスタ間転送用のネイティブ命令は、メインプロセッサのレジスタファイルからコプロセッサのレジスタファイルに前記データバスを介してデータを転送するデータ転送命令であることを特徴とする請求項1記載の情報処理装置。
- アクセラレータは、メインプロセッサの汎用レジスタをオペランドスタックのキャッシュとして扱い、前記コプロセッサの演算レジスタをオペランドスタックのキャッシュとして扱わないことを特徴とする請求項1又は2記載の情報処理装置。
- 前記コプロセッサの演算レジスタは、前記オペランドスタックの一時的使用のために用いられることを特徴とする請求項3記載の情報処理装置。
- 前記メインプロセッサに接続されるメモリを更に具備し、
前記メインプロセッサは、前記メモリから前記仮想マシン命令及び前記ネイティブ命令を取り込むための命令フェッチ部と、前記ネイティブ命令をデコードするためのデコーダ部と、前記命令フェッチ部に取り込まれた命令が前記仮想マシン命令である場合に前記アクセラレータの出力を選択し前記命令フェッチ部に取り込まれた命令が前記ネイティブ命令である場合に前記命令フェッチ部の出力を選択する選択回路とを有することを特徴とする請求項1に記載の情報処理装置。 - 前記仮想マシン命令は、Javaバイトコードであることを特徴とする請求項1に記載の情報処理装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004165435A JP4224430B2 (ja) | 2003-07-07 | 2004-06-03 | 情報処理装置 |
US10/883,758 US7788469B2 (en) | 2003-07-07 | 2004-07-06 | Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003192600 | 2003-07-07 | ||
JP2004165435A JP4224430B2 (ja) | 2003-07-07 | 2004-06-03 | 情報処理装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008193209A Division JP2009032263A (ja) | 2003-07-07 | 2008-07-28 | 情報処理装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005044336A JP2005044336A (ja) | 2005-02-17 |
JP4224430B2 true JP4224430B2 (ja) | 2009-02-12 |
Family
ID=34106835
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004165435A Expired - Fee Related JP4224430B2 (ja) | 2003-07-07 | 2004-06-03 | 情報処理装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7788469B2 (ja) |
JP (1) | JP4224430B2 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7293159B2 (en) * | 2004-01-15 | 2007-11-06 | International Business Machines Corporation | Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder |
JP4602047B2 (ja) * | 2004-10-29 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 情報処理装置 |
US7571312B2 (en) * | 2005-05-13 | 2009-08-04 | Intel Corporation | Methods and apparatus for generating endorsement credentials for software-based security coprocessors |
US20080208402A1 (en) * | 2007-02-23 | 2008-08-28 | Vhasure Shashikant G | Processor health check utilizing intelligent peripheral |
JP5265886B2 (ja) * | 2007-06-19 | 2013-08-14 | 晃 西田 | 演算処理システム、演算処理方法、プログラム、およびプログラムを記録したコンピュータ読み取り可能な記録媒体 |
US8103858B2 (en) * | 2008-06-30 | 2012-01-24 | Intel Corporation | Efficient parallel floating point exception handling in a processor |
US8959277B2 (en) * | 2008-12-12 | 2015-02-17 | Oracle America, Inc. | Facilitating gated stores without data bypass |
US20120173923A1 (en) * | 2010-12-31 | 2012-07-05 | International Business Machines Corporation | Accelerating the performance of mathematical functions in high performance computer systems |
US9836316B2 (en) * | 2012-09-28 | 2017-12-05 | Intel Corporation | Flexible acceleration of code execution |
CN102903001B (zh) * | 2012-09-29 | 2015-09-30 | 上海复旦微电子集团股份有限公司 | 指令的处理方法和智能卡 |
US9785444B2 (en) | 2013-08-16 | 2017-10-10 | Analog Devices Global | Hardware accelerator configuration by a translation of configuration data |
US9542211B2 (en) * | 2014-03-26 | 2017-01-10 | Intel Corporation | Co-designed dynamic language accelerator for a processor |
JP2018101256A (ja) * | 2016-12-20 | 2018-06-28 | ルネサスエレクトロニクス株式会社 | データ処理システム及びデータ処理方法 |
CN108932406B (zh) * | 2017-05-18 | 2021-12-17 | 北京梆梆安全科技有限公司 | 虚拟化软件保护方法和装置 |
US10795718B2 (en) * | 2019-02-08 | 2020-10-06 | Microsoft Technology Licensing, Llc | Updating hardware with reduced virtual machine downtime |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69229657T2 (de) * | 1991-06-19 | 1999-12-02 | Hewlett-Packard Co., Palo Alto | Co-Prozessor unterstützende Architektur für einen Prozessor, der keine Zusatzprozessorfähigkeit hat |
US6085307A (en) * | 1996-11-27 | 2000-07-04 | Vlsi Technology, Inc. | Multiple native instruction set master/slave processor arrangement and method thereof |
US6505290B1 (en) * | 1997-09-05 | 2003-01-07 | Motorola, Inc. | Method and apparatus for interfacing a processor to a coprocessor |
EP1359501A3 (en) * | 1997-10-02 | 2007-11-21 | Koninklijke Philips Electronics N.V. | A processing device for executing virtual machine instructions |
US6480952B2 (en) * | 1998-05-26 | 2002-11-12 | Advanced Micro Devices, Inc. | Emulation coprocessor |
US6163835A (en) * | 1998-07-06 | 2000-12-19 | Motorola, Inc. | Method and apparatus for transferring data over a processor interface bus |
US6347344B1 (en) * | 1998-10-14 | 2002-02-12 | Hitachi, Ltd. | Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor |
US6332215B1 (en) | 1998-12-08 | 2001-12-18 | Nazomi Communications, Inc. | Java virtual machine hardware for RISC and CISC processors |
JP2001092662A (ja) | 1999-09-22 | 2001-04-06 | Toshiba Corp | プロセッサコア及びこれを用いたプロセッサ |
US20020069402A1 (en) * | 2000-10-05 | 2002-06-06 | Nevill Edward Colles | Scheduling control within a system having mixed hardware and software based instruction execution |
US6754804B1 (en) * | 2000-12-29 | 2004-06-22 | Mips Technologies, Inc. | Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions |
US7210022B2 (en) * | 2001-05-15 | 2007-04-24 | Cloudshield Technologies, Inc. | Apparatus and method for interconnecting a processor to co-processors using a shared memory as the communication interface |
GB2376099B (en) | 2001-05-31 | 2005-11-16 | Advanced Risc Mach Ltd | Program instruction interpretation |
GB2376100B (en) | 2001-05-31 | 2005-03-09 | Advanced Risc Mach Ltd | Data processing using multiple instruction sets |
GB0215033D0 (en) * | 2002-06-28 | 2002-08-07 | Critical Blue Ltd | Instruction set translation method |
-
2004
- 2004-06-03 JP JP2004165435A patent/JP4224430B2/ja not_active Expired - Fee Related
- 2004-07-06 US US10/883,758 patent/US7788469B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005044336A (ja) | 2005-02-17 |
US20050027965A1 (en) | 2005-02-03 |
US7788469B2 (en) | 2010-08-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4224430B2 (ja) | 情報処理装置 | |
TWI567646B (zh) | 容許一架構之編碼模組使用另一架構之程式庫模組的架構間相容性模組 | |
US9003422B2 (en) | Microprocessor architecture having extendible logic | |
KR910000364B1 (ko) | 이뮬레이션 시스템 및 그 방법 | |
US7827390B2 (en) | Microprocessor with private microcode RAM | |
US6457115B1 (en) | Apparatus and method for generating 64 bit addresses using a 32 bit adder | |
JP4485198B2 (ja) | Javaアクセラレータを備えたプロセッサシステム | |
EP1447742A1 (en) | Method and apparatus for translating instructions of an ARM-type processor into instructions for a LX-type processor | |
JP4602047B2 (ja) | 情報処理装置 | |
US20220206809A1 (en) | Method and system for executing new instructions | |
JP2001195250A (ja) | 命令トランスレータ、トランスレータ付命令メモリおよびそれらを用いたデータ処理装置 | |
CN106687972A (zh) | 针对有效gadget控制转移的攻击保护 | |
WO2010004242A2 (en) | Data processing apparatus, for example using vector pointers | |
US10740280B2 (en) | Low energy accelerator processor architecture with short parallel instruction word | |
JP3193650B2 (ja) | オペレーティング・システムに影響を与えないエミュレーション・コンテキストの保管と復元を行う方法およびシステム | |
TWI724065B (zh) | 包含用於控制流向終止的模式特定結束分支之處理器及系統 | |
US7124283B2 (en) | Hardware accelerator for a platform-independent code | |
CN112631657A (zh) | 用于字符串处理的字节比较方法以及指令处理装置 | |
US7613903B2 (en) | Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor | |
JP2000284973A (ja) | 二重割込みベクトル・マッピング装置とその操作方法 | |
US6405300B1 (en) | Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor | |
JP2009032263A (ja) | 情報処理装置 | |
US6463517B1 (en) | Apparatus and method for generating virtual addresses for different memory models | |
GB2461850A (en) | Memory management unit with address translation for a range defined by upper and lower limits | |
JP2004522236A (ja) | 中間言語アクセラレータチップ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061207 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080520 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080527 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080728 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080826 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081027 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20081118 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20081121 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111128 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111128 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111128 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111128 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121128 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131128 Year of fee payment: 5 |
|
LAPS | Cancellation because of no payment of annual fees |