JP4216075B2 - Fractional N-Frequency Synthesizer using Fractional Compensation Method (Fractional-NFREQUENCYSYNTHESIZER) - Google Patents

Abstract

A phase-locked loop (PLL) frequency synthesizer (Fig. 3) incorporates fractional spur compensation circuitry. This fractional spur compensation circuitry dynamically compensates charge pump ripple whenever a charge pump operates. It can utilize a programmable divider (336), two phase detectors (314 and 324) each using a charge pump stage pumps. A fractional accumulator stage (340) determines the number of charge pumps that operate during a phase comparison. The PLL frequency synthesizer avoids the need for compensation current trimming. Also, fractional compensation is accomplished dynamically and in a manner that is robust to environmental changes. A phase-locked loop (PLL) fractional-N type frequency synthesizer can incorporate a sample-and-hold circuit. The synthesizer can reduce circuit size by eliminating a loop filter. The synthesizer or fractional-N type PLL can use a divider and at least two phase detectors coupled to a sample-and-hold circuit. A lock detecting circuit can initially determine a reference voltage for the sample-and-hold circuit.

Description

  The apparatus and method of the present invention is a sample and hold type used in systems that require fractional resolution of a reference frequency, particularly in modern wireless or wired communication systems. type) It can be used for systems related to PLL-based frequency synthesizers, including fractional N synthesizers.

Frequency synthesizers are typically used in modern wireless communication systems to obtain the desired output at both the receiver and transmitter. There are various phase lock loop (PLL) based frequency synthesizers, among which the fractional N frequency synthesizer is suitable for communication systems with small channel spacing. The fractional-N architecture enables a frequency resolution that is a fractional part of the reference frequency F _REF , where F is the fractional resolution of the device with respect to the reference frequency, and the relationship between the output frequency signal F _OUT and the reference frequency F _REF is It is defined by the formula F _OUT = F _REF (N + K / F). In the fractional N architecture approach, it is necessary to generate a frequency divider that is a fraction rather than an integer. This is done by dynamically changing the divider in the loop between the values N and N + 1. If the division by N + 1 is executed K times from the F cycles and the division by N is executed F−K times, the average division ratio becomes N + K / F.

The advantage of the fractional N architecture is that the reference frequency F _REF is not constrained by channel spacing and can increase the loop bandwidth. Therefore, the phase noise is reduced and the lock time is shortened. However, with a small number of switches, spurious signals are generated in the configured output frequency signal F _OUT . These subharmonic spurs, also called fractional spurs, must be kept below some maximum allowable limit.

  We try to reduce unnecessary spurious signals by using fractional compensation circuits based on related technology. For proper fractional compensation, the area of the compensation pulse must be equal to the area of the main charge pump fractional N ripple (main charge pump fractional-N ripple). However, in a related art fractional compensation circuit, the magnitude of the compensation current is statically fixed. Therefore, cancellation of spurious signals cannot follow dynamic changes in spurious signals due to time, process, and temperature.

  In a fractional compensation circuit according to another related technique, usually called a fractional-N synthesizer, a division ratio is controlled by using a sigma-delta (ΣΔ) modulator. A modulus divider receives the output signal from the ΣΔ modulator. Fractional spurious frequency or phase noise is distributed over the entire frequency spectrum by the operation of the sigma-delta modulator. However, the absolute noise level may exceed an acceptable level. There is a need for a more robust and reliable fractional compensation scheme that does not degrade spectral purity.

  In frequency synthesizers used in modern wireless communication systems, it is common to use a phase-locked loop (PLL). A PLL typically includes a voltage controlled oscillator (VCO), a phase detector (PD), and a loop filter (LF). When integrating a PLL into a single integrated circuit, the required capacitance in the loop filter (LF) is often only a few microfarads, so a large LF capacitor used to stabilize the PLL is the majority of the circuit chip area. Occupy. Since recent wireless systems attempt to integrate the entire receiver and transmitter (including PLL) on a single chip, the required capacity of the LF capacitor is an important issue.

  One related art approach to reducing LF capacitance uses a sample and hold circuit as a phase detector or comparator. The capacitor in the sample and hold circuit is considerably smaller than the capacitance in a normal loop filter. Another advantage of the sample and hold phase detector is that the output does not contain high frequency harmonics of the input frequency. When the phase is constant, the output voltage is also constant. Therefore, the sample and hold PD can be applied to a frequency synthesizer.

  A sample and hold large PLL frequency synthesizer is disclosed that does not require a large LF capacitor. (See, for example, Patent Document 1) The sample and hold PLL frequency synthesizer of Patent Document 1 uses an integer N architecture to generate an output frequency that is an integer multiple of a reference frequency. However, in the integer N architecture, the loop bandwidth is limited because the input reference frequency must be equal to the channel spacing. Therefore, the phase noise of the oscillator is reduced only within the bandwidth of the loop, thus limiting the phase noise at close range. The disadvantage of the integer N architecture is that the lock time is long because the lock time of the PLL also depends on the loop bandwidth.

To increase the loop bandwidth, a fractional N architecture has been used for frequency synthesizers. FIG. 1 shows a related art frequency synthesizer that uses a sample and hold circuit. As shown in FIG. 1, the reference frequency divider 104 divides the input reference frequency 102 and outputs a divided reference signal 106. A phase detector (PD) 110 receives the divided reference signal 106 and the output 108 of the integer divider 128 and generates an output signal 112 that is responsive to the comparison. The sample and hold circuit 114 receives the output 112 of the PD 110. The voltage controlled oscillator 118 receives the output 116 of the sample and hold circuit 114. The output 120 of the voltage controlled oscillator 118 is an output signal F _OUT of the frequency synthesizer circuit and is further input to the integer frequency divider 128.

In operation, the VCO output signal 120 is divided by N in the integer divider 128 and compared with the divided reference signal 106 from the reference divider 104. The phase detector PD and the sample and hold circuit 130 generate a control signal that depends on the detected phase difference. A control signal is applied to a voltage controlled oscillator (VCO) to generate an output frequency F _OUT .

FIG. 2 a is a diagram of a related art phase detector and sample and hold circuit 130. As shown in FIG. 2 a, the charge pump 206 receives the output 204 of the phase detector 202. The output 214 of the charge pump 206 enters the node sample and hold circuit 114 at the first node n1. In the sample and hold circuit 114, the reference voltage V _REF 210 is connected to the first node n1 through the first switch 212. The sample capacitor 220 is connected between the ground reference voltage 222 and the first node n1. The second switch 224 is connected between the first node n1 and the second node n2 connected to the output terminal 234. The hold capacitor 230 is connected between the ground reference voltage and the second node n2. The capacities of the sample capacitor 220 and the hold capacitor 230 are much smaller than those of a normal loop filter. Before the phase comparison is performed by the phase detector 202, the switch SW1 is closed and the sample capacitor is charged to the reference voltage V _REF . The charge pump 206 after the phase detector 202 increases or decreases the voltage of the sample capacitor 220 from the reference voltage V _REF according to the detected phase difference as a result of the phase comparison. When the phase comparison is completed, the charge in the sample capacitor 220 is moved to the hold capacitor 230 via the second switch SW2.

FIG. 2b is a timing diagram of the lock state of the related art sample-and-hold integer N frequency synthesizer. As shown in FIG. 2b, there is a relationship between the reference frequency signal and the divider output (ie, the divided VCO output) when the phases are aligned in a normal loop filter type PLL. Therefore, the phase difference T is constant. Therefore, the sample-and-hold type PLL is not suitable for application as a clock or data recovery when the phase must be aligned between the input reference signal and the VCO output. The phase detector output and sample capacitor voltage are also shown in FIG. 2b. However, in the integer N frequency synthesizer, phase matching is not a necessary condition, and the sample-and-hold type PLL can be applied as long as the phase noise characteristics are satisfied. As shown in FIG. 2b, the phase of the reference frequency signal is advanced by a time T from the phase of the divider output, and the phase detector generates a UP (HIGH) signal for each phase comparison, and the sample capacitor The voltage of (Vsample) is increased from the reference voltage (V _ref ) at a constant rate. Therefore, the voltage of the hold capacitor (Vhold) and the output frequency of the voltage controlled oscillator are kept constant.

  However, as described above, the integer N frequency synthesizer has a narrower loop bandwidth than the fractional N frequency synthesizer. In order to make the loop bandwidth higher than the channel spacing, the fractional-N synthesizer includes a variable modulus programmable divider that is controlled by an accumulator. The accumulator changes the frequency division ratio of the variable modulus programmable frequency divider to generate a desired fractional resolution ratio. Therefore, the control voltage of the VCO in the fractional N frequency synthesizer is not constant, but the time average value of the control voltage is meaningful. Therefore, in the related art fractional-N architecture, the sample and hold circuit cannot be used to replace the loop filter.

  FIG. 2c is a timing diagram illustrating the problems and disadvantages of the sample and hold circuit in the related art fractional N synthesizer. As shown in FIG. 2c, the reference frequency and the divider output have a phase detector output, sample & no constant phase difference as shown in the phase detector output of FIG. 2b. The output voltage of the hold circuit and the state of the fractional accumulator are also shown. In FIG. 2c, the fractional ratio is assumed to be 3/8 (K = 3 N = 8), where N is the divisor. The state of the fractional accumulator changes according to the fractional ratio. Accordingly, the phase of the frequency divider output with respect to the width of the reference frequency signal and the UP pulse of the phase detector also changes. The voltage change amount of the sample capacitor (Vsample) is not fixed, and the voltage of the hold capacitor (Vhold) exhibits a fractional ripple that lowers the spectral purity of the synthesized frequency.

  The above references are incorporated herein by reference as far as appropriate with respect to additional or other details, features, and / or appropriate teachings of the technical background.

US Pat. No. 6,137,372

  The object of the present invention is to solve at least the above-mentioned problems and / or drawbacks and to present at least the advantages described below.

  Another object of the present invention is to present a phase-locked loop based fractional N synthesizer.

  Another object of the present invention is to provide a fractional compensation circuit and method incorporating two phase detectors.

  Another object of the present invention is to incorporate a fractional spurious compensation circuit that dynamically corrects for fractional spurs or charge pump ripple whenever the charge pump is operating.

  It is another object of the present invention to provide a phase locked loop based fractional N synthesizer and method that uses multiple phase detectors to dynamically cancel spurious signals.

  Another object of the present invention is to provide a phase-locked loop-based fractional N synthesizer that causes various lengths of delay for at least one output of a plurality of phase detectors to reduce fractional spurs.

  Another object of the present invention is to provide a fractional compensation circuit that uses a charge pump stage consisting of N charge pumps and in which the number N of charge pumps operating during phase comparison is determined by the fractional accumulator stage. is there.

  Another object of the present invention is to provide a fractional compensation circuit and method that incorporates a sample and hold circuit within a loop filter.

  Another object of the present invention is to provide a phase locked loop based fractional N synthesizer and method that dynamically cancels spurious signals using multiple phase detectors and uses a sample and hold circuit.

  Another object of the present invention is to use a charge pump stage consisting of N charge pumps coupled to a sample and hold circuit in a loop filter, where the number N of charge pumps operating during phase comparison depends on the fractional accumulator stage. It is to present a fractional compensation circuit as determined.

  An advantage of the fractional-N architecture and method according to the present invention is that the reference frequency is not subject to channel spacing constraints and the loop bandwidth can be increased.

  Another advantage of the fractional-N architecture and method according to the present invention is that sub-harmonic spurs or fractional spurs can be kept low.

  Another advantage of the fractional-N architecture and method according to the present invention is that spurious signal cancellation can be performed dynamically.

  Another advantage of the fractional N architecture and method according to the present invention is that compensation current trimming is not required.

  Another advantage of the fractional-N architecture and method according to the present invention is that it is less sensitive to environmental changes.

  Another advantage of the fractional-N architecture and method according to the present invention is that the circuit size can be reduced.

  Another advantage of the fractional-N architecture and method according to the present invention is that large loop filter capacitors are not required.

  An advantage of the fractional N architecture and method according to the present invention is that a sample and hold circuit can be implemented in the PLL to provide a stable voltage.

  In order to achieve all or part of the above objectives as shown and broadly described in the embodiments in accordance with the objectives of the present invention, the phase-locked loop comprises an input signal and a first divided signal. A first phase detector for receiving and outputting a first comparison signal; a second phase detector for receiving an input signal and a second divided signal and outputting a second comparison signal; A circuit that receives a comparison signal and generates an output signal that is a response to the comparison signal, a voltage-controlled oscillator that receives an output signal from the circuit and generates a signal of a predetermined frequency, and receives a signal of a predetermined frequency and has a predetermined phase relationship A programmable modulus divider is provided for generating first and second divided signals.

  In addition, in order to achieve all or part of the above objectives as shown and broadly described in the embodiments in accordance with the objectives of the present invention, a fractional N frequency synthesizer for a mobile terminal receives a reference signal. A first phase detector comprising a first input port, a second input port, a third input port, and an output port coupled together, and a first input coupled to receive a reference signal A second phase detector comprising a port, a second input port, a third input port, and an output port, a first input port and an output coupled to the output ports of the first and second phase detectors A circuit comprising a port, an input port coupled to an output port of the circuit, a voltage controlled oscillator for transmitting a signal of a predetermined frequency from the output port, a first divided signal A first output port coupled to the second input port of the first phase detector for transmitting, a second of the second phase detector for transmitting the second divided signal Programmable modulus divider comprising a second output port coupled to the input port, a first input port coupled to the output port of the voltage controlled oscillator, and a second input port, and a programmable modulus divider And an accumulator comprising a second output port coupled to the third input port of the phase detector and a first output port coupled to the second input port of the phase detector.

  Other advantages, objects, and features of the present invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art after reviewing the description and in accordance with the invention. You can also learn by implementing The objects and advantages of the invention will be realized and realized as particularly pointed out in the appended claims.

  The present invention will be described in detail with reference to the figures, wherein like reference numerals refer to like elements.

  FIG. 3 is a schematic diagram illustrating a preferred embodiment of a fractional compensation circuit according to the present invention. As shown in FIG. 3, the frequency synthesizer 300 is a programmable coupled to a phase locked loop (PLL) comprising a phase detector circuit 342, a loop filter 328, a voltage controlled oscillator (VCO) 330, and an accumulator 340. A modulus divider 336 is provided. In the frequency synthesizer 300, the reference frequency 302 is supplied to the reference frequency divider 304. The output of the reference frequency divider 304 is split into two phase detector feeds 306 and 308. The two phase detector feeds 306 and 308 are input to the phase detectors 314 and 324 of the phase detector circuit 342, respectively. Outputs 316 and 322 of phase detectors 314 and 324 are coupled to an input 320 of a loop filter (LF) 328. The output 329 of the loop filter 328 is supplied to a voltage controlled oscillator (VCO) 330. The phase detector circuit 342 preferably includes two phase detectors 314 and 324 comprising two charge pump blocks (not shown). The terms “charge pump”, “charge pump block”, and “CP” refer to the same type of circuit and may be used interchangeably herein. CP1 and CP2 are sometimes used when multiple charge pumps are referenced.

The programmable modulus divider 336 divides the output frequency signal F _OUT 332 of the VCO 330 by switching N and N + 1 according to the control signal 338 from the accumulator 340, respectively. Two of the divided value VCO signals F _DIV1 and F _DIV2 from the modulus programmable divider are used as the second inputs 310 and 312 of the phase detectors 314 and 324, respectively. The two divided VCO signals F _DIV1 and F _DIV2 310 and 312 output by the modulus programmable divider 336 may be the same as the frequency and phase difference, which is the VCO period (1 / F _OUT ). is there. N equal charge pumps (not shown) are preferably coupled to phase detectors 314 and 324, respectively. The accumulator 340 determines the number of charge pumps that should be enabled before performing a phase comparison of the phase detectors 314 and 324 between the input reference frequency (F _REF ) and the _divided VCO clocks (F _DIV1 , F _DIV2 ). To control. Thus, the output of accumulator 340 enables signals 318 and 326 to phase detectors 314 and 324, respectively.

FIG. 4 is a diagram illustrating a preferred embodiment of a programmable modulus divider 400, for example, dividing an input signal by N + 1 or N and two divided VCO outputs F _DIV1 and F _DIV2 416 and 422. Is output. The programmable modulus divider 400 can be used as the programmable modulus divider 336 of FIG. The programmable modulus divider 400 can include three flip-flops 412, 420, 434 and two logic gates 402, 428. Since the three flip-flops 412, 420, and 434 preferably use the same output signal 436 as a clock signal, and since this is preferably the output frequency signal F _OUT 336, F _DIV1 and F _DIV2 , The phase difference between 416 and 422 is the period of the VCO frequency (T _VCO = 1 / F _OUT ).

As shown in FIG. 4, the first “OR” gate 402 receives an input 404 from a third flip-flop 434 and an input 406 from a second flip-flop 420. The first flip-flop 412 receives and processes the output 408 of the first “OR” gate 402 in accordance with the F _OUT signal 436. The second flip-flop 420 receives and processes the output 414 of the first flip-flop 412 according to the F _OUT signal 436. In addition to input 406 from second flip-flop 420, second “OR” gate 428 receives a modulus control signal as input 426. The third flip-flop 434 receives and processes the output 430 of the second “OR” gate 428 in accordance with the F _OUT signal 436. The output signals 414 and 406 of the first and second flip-flops 412 and ₄₂₀ are preferably the _divided VCO signals D _FDIV1 416 and F _DIV2 422 from the programmable modulus divider 400.

  FIG. 5 is a diagram illustrating another preferred embodiment of a phase detector and charge pump circuit 500. As shown in FIG. 5, for example, using phase detector and charge pump circuit 500 as one of phase detectors 314, 324 in phase detector circuit 342 shown in FIG. Can do. The charge or discharge current supplied to each LF (not shown) from each charge pump is preferably determined by I / N, where I is the current of a typical fractional N frequency synthesizer. The enable signal (EN) 515 is generated by a corresponding accumulator (not shown) such as the accumulator 340 according to the state of the fractional accumulator, and the enable / disable of the charge pump 534 is controlled. As shown in FIG. 5, there are preferably N charge pumps 534 coupled to a phase detector 506 that receives the enable signal from the accumulator.

As shown in FIG. 5, the phase detector 506 compares the F _REF input 502 and the F _DIV input 504 as the divided reference signals, and each charge pump circuit 534 receives 2 in response to the comparison. Two outputs 508 and 510 are generated. The first “AND” gate 518 of the charge pump 534 receives an “UP” signal 512 and an “EN” signal 515. The second “AND” gate 520 receives a “DN” signal 514 and an “EN” signal 515. The output signal 508 is preferably an “UP” signal 512 and the output signal 510 is preferably a “DN” signal 514. The first switch 526 and the first current source 522 are coupled in series between the power supply voltage and the output terminal 530. The state of the first switch 526 (eg, open or closed) is controlled by the output signal 540 from the first “AND” gate 518 and the enable signal EN for the comparison result in the corresponding phase detector. A second switch 528 and a second current source 524 are coupled in series between the output terminal 530 and the ground reference voltage. The state of the second switch 528 is preferably controlled by the output signal 542 from the second “AND” gate 520. Accordingly, the first current source 522 and the second current source 524 can be selectively coupled to the single output terminal 530 of the charge pump 534. The outputs 532 of the N charge pumps 534 of the phase detector and charge pump circuit 500 enter a loop filter (not shown). The output terminals 530 of the N charge pumps 534 are coupled to provide an output 532 to the loop filter. However, the present invention is not intended to be so limited.

  The control timing relationship of the charge pump block is illustrated in FIG. 6, and the fraction is assumed to be 3/8 (K = 3, N = 8). Therefore, the modulus divider divides 5 times by 8 (N) and 3 times by 9 (N + 1) out of 8 cycles. The timing relationship diagram shown in FIG. 6 can be used for the charge pump block associated with each phase detector 314, 324 of FIG. Thus, for example, the phase detector circuit 342 may comprise 2 (N = 8) or 16 charge pump stages 534.

  The waveforms shown in FIG. 6 are the divided reference frequency voltage 602 and the voltages at the outputs of the modulus programmable dividers 604 and 606 (eg, 310, 312). The number of charge pumps enabled for CP1 and CP2 (eg, in PD 314 and PD 324) is indicated by 608 and the state of the fractional accumulator is indicated by 610. The state of the synthesizer divider is indicated by 612. As shown in FIG. 6, the number of charge pumps (CP 1 and CP 2) enabled during phase comparison is determined by the accumulator state 610. The total number of enabled charge pumps is always fixed as a divisor N.

  Another preferred embodiment of a phase detector circuit comprising a charge block pump with N charge pumps is shown in FIG. As shown in FIG. 7, charge pump block 700 includes switches 726, 728, 730,. . . The output 706 of the first phase detector PD1 used as the first input string to 732 is received. The output 708 of the second phase detector PD2 is a switch 726, 728, 730,. . . Used as the second input string to 732. Switch outputs 734, 736, 738,. . . 740 includes charge pumps 742, 744, 746,. . . Used as input to 748. Preferably N charge pumps 742, 744, 746,. . . 748 outputs 750, 752, 754,. . . 756 is coupled to an output signal 758 that is connected to a loop filter (not shown). In the charge pump block 700, the accumulator turns the phase detectors PD1 and PDF2 into charge pumps 726, 728, 730,. . . When controlling the work connected to 732, the number of charge pumps is reduced to N compared to the total number of 2N charge pumps in FIG.

The phase relationship between the divided reference frequency and the divided VCO frequency is shown in FIGS. 8a and 8b. FIG. 8a shows the relative phase lag of the divided reference signal and FIG. 8b shows the relative phase advance of the divided reference signal. For example, FIGS. 8a and 8b can show the phase relationship between the divided reference frequency 306 and the divided VCO frequencies 310, 312 of the frequency synthesizer 300 of FIG. As shown in FIGS. 8 a and 8 b, this relative voltage waveform includes a reference frequency 802, Divider Output ₁ 804, Divider Output ₂ 806, PD1 output 808, and PD2 output 810. The number of enabled charge pumps 812 and 816 and the fractional accumulator state 814, which is always a divisor N, are also shown for those waveforms.

In FIG. 8a, as a response to the phase lag of the _divided reference frequency F _REF 802, both phase detector outputs 808 and 810 cause all charge pumps to discharge the loop filter (eg, the “DOWN” signal). To reduce the VCO output frequency. Conversely, in FIG. 8b, due to the phase advance of the divided reference frequency, the phase detector outputs 808 and 810 discharge all charge pumps (eg, generate an “UP” signal), and the VCO Increase the output frequency. In the locked state, the phase of the divided reference frequency (F _REF ) is placed between the two divided VCO frequencies F _DIV1 and F _DIV2 , 804 and 806, which is one of the phase detectors. This means that (PD1) generates a “DOWN” signal and the other (PD2) generates an “UP” signal. Thus, in the locked state, the charge pump connected to PD1 discharges the loop filter, and the charge pump connected to PD2 charges the loop filter, preferably keeping the loop filter voltage constant.

FIG. 9 is a timing diagram illustrating fractional compensation according to a preferred embodiment of the present invention. For example, FIG. 9 may show the phase relationship between the divided reference frequency 306 and the divided VCO frequencies 310, 312 of the frequency synthesizer 300 of FIG. In FIG. 9, this fraction is assumed to be 3/8 (K = 3, N = 8) as described above for FIG. As shown in FIG. 9, the divided reference frequency 902 relative voltage waveform, Divider Output ₁ 904, Divider Output ₂ 906, PD1 output 908, PD2 output 910, and control voltage 918 are shown. . For clarity, the amplitude 920, 922, and 924 sections of the control voltage 918 are shown enlarged in FIG. The number of charge pumps 912 and 916 enabled and the fractional accumulator state 914 are also shown for those waveforms.

  In the locked state of the frequency synthesizer as shown in FIG. 9, the charge pump (CP1) connected to PD1 always sinks current from the loop filter, but the charge pump connected to PD2 ( CP2) always sources current into the loop filter. The amount of discharge current due to CP1 is given by the following equation:

Q _discharge = I _discharge * T _discharge = {(N−K) * (I / N)} * {(K / N) * T _VCO } (Formula 1)

K represents the state of the accumulator. Similar to Equation 1, the charging current amount by CP2 is given by the following equation.

Q _charge = I _charge * T _charge = {K * (I / N)} * [{(N−K) / N} * T _VCO ] (Formula 2)

From (Equation 1) and (Equation 2), Q _charge and Q _discharge are always the same. Therefore, the charging current and the discharging current compensate each other, and the output voltage of the loop filter is kept constant in the locked state. It is preferable that the PLL loop characteristics maintain the phase relationship and satisfy the above formula, and the loop filter voltage is preferably kept constant regardless of environmental changes such as temperature. Thus, fractal spurs are dynamically compensated. Furthermore, compensation current trimming is not required. Furthermore, since the perturbation of the loop filter voltage at the time of phase comparison in FIG. 9 is small, the average level of the control voltage is not changed, and it occurs in a very short period of the VCO frequency period, so that fractal spurious and phase noise are generated. It can be seen that it is negligibly small compared to the related art fractal N architecture.

  However, the preferred embodiment according to the present invention is not limited to the above case and is not intended to be so limited. For example, other combinations for performing fractal compensation of the reference signal according to the present invention are possible by changing the phase difference between the divided signals and the number of charge pumps used.

  Another embodiment of a frequency synthesizer comprising a phase locked loop according to the present invention is shown in FIG. As shown in FIG. 10, the frequency synthesizer 1000 receives a reference frequency 1002 that is input to first and second phase detectors 1010 and 1012, respectively. The first phase detector 1010 further receives a first divided VCO frequency 1004 and the second phase detector 1012 further receives a second divided VCO frequency 1008. At delay 1018, the output 1014 of the first phase detector 1010 is received and preferably output after the specified delay. The first charge pump 1022 receives the output 1020 of the delay block 1018 and the second charge pump 1024 directly receives the output 1016 of the second phase detector 1012. The output 1026 of the first charge pump 1022 and the output 1028 of the second charge pump 1024 are combined and used as an input 1030 to a loop filter, such as the loop filter 328. VCO 330, modulus programmable divider 336, and accumulator 340 are preferably coupled to loop filter 328 and phase detector circuit 1050. In the preferred embodiment of FIG. 10, perturbations in the loop filter voltage 1030 are further reduced by delaying the output of one of the first and second phase detectors 1010 and 1012. As shown in FIG. 10, the output 1014 of the first phase detector 1010 is delayed to reduce or minimize loop filter voltage perturbations. However, the present invention is not intended to be so limited.

  For example, if a delay block 1018 as shown in FIG. 10 is placed in front of the first phase detector 1010, the same effect as described above can be obtained with favorable results. As shown in FIG. 11, in another preferred embodiment of a frequency synthesizer phase detector circuit 1100, a first delay block 1106 that receives a reference frequency input 1002 and a first divided VCO frequency 1004 are provided. A second delay block 1108 for receiving is provided. The first phase detector 1010 receives and processes the output 1110 of the first delay block 1106 and the output 1112 of the second delay block 1108. The second phase detector 1012 and the second charge pump 1024 operate as described above. However, the first charge pump 1022 receives the output 1114 directly from the first phase detector 1010. The output 1126 from the first charge pump 1022 and the output 1128 from the second charge pump 1024 are combined and used as an input 1130 to a loop filter (not shown).

  The operation and effect of the delay as occurs in the preferred embodiment shown in FIGS. As shown in FIG. 12, the voltage output of the first phase detector is represented by waveform 1202, the delayed output of the first phase detector is represented by waveform 1204, and the second phase detector Is represented by a waveform 1206. The voltage control signal is represented by waveform 1208, and the amplitude shown in the figure is exaggerated in sections 1212, 1214, and 1216 for clarity. Further, the state of the fractional accumulator is indicated at 1210.

  As shown in FIG. 12, the “DOWN” signal of PD1 and the “UP” signal of PD2 overlap. Thus, the charge current and discharge current are simultaneously applied to the loop filter and compensate each other to reduce or minimize the maximum amplitude variation of the loop filter voltage. As long as the delayed PD1 signal 1204 and PD2 signal 1206 overlap, the operation of the preferred embodiment of FIGS. 10-11 has the effect of reducing the voltage of the loop filter. However, preferred embodiments of the present invention are not intended to be so limited. For example, the delay can occur in the PD2 signal or in both the PD1 and PD2 signals. Furthermore, an optimal or predetermined delay depending on the frequency division ratio can be set, for example, by a control accumulator.

  13 and 14 are diagrams showing examples of delay control circuits. FIG. 13 shows a digital control circuit 1300 where delay taps 1304, 1312, 1320, and 1328 coupled in series are coupled between an input terminal 1302 and an output terminal 1340. The number of delay taps 1304, 1312, 1320, and 1328 that are switched into the circuit determines the predetermined delay between the input signal IN and the output signal OUT. The digital delay control circuit 1300 receives a delayed signal as the input signal IN of the input terminal 1302. For example, an inverter can be considered as the delay tap. The plurality of switches 1332, 1334, 1336, 1338 are connected between the outputs of the delay taps 1304, 1312, 1320, and 1328 and the output terminal 1340, respectively. The on / off state of switches 1332, 1334, 1336, and 1338 is preferably determined by control signal 1350. Accordingly, the total delay of digital delay control circuit 1300 is controlled by the state of switches 1332, 1334, 1336, and 1338.

  FIG. 14 shows an example of an analog delay control circuit in which the delay of each delay cell and the total delay of the circuit are controlled by the control voltage. As shown in FIG. 14, the analog delay control circuit 1400 receives an input signal IN at an input terminal 1402 that is coupled to the first delay cell 1404. Delay cells 1412, 1416, and 1422 are connected in series between first delay cell 1404 and output terminal 1426. Each of the delay cells 1404, 1412, 1416, and 1422 is supplied with a control voltage CONTROL 1428, and this control voltage controls a delay generated in each delay cell. Therefore, the control voltage 1428 controls the input signal IN and the output signal OUT. A predetermined cumulative delay between is determined. As described above, the delay circuit example can be configured with a few delay taps or delay cells.

  As mentioned above, the preferred embodiment of the frequency synthesizer has various advantages. A frequency synthesizer comprising a phase locked loop (PLL) according to a preferred embodiment incorporates a fractional spurious compensation circuit to dynamically correct for charge pump ripple as the charge pump operates. In a preferred embodiment, the programmable divider is two output signals that are preferably divided signals from a voltage controlled oscillator (VCO) that uses the same divider ratio for the inputs to the two phase detectors of the PLL. Is output. Therefore, the phase difference of the divided VCO signal is preferably the VCO output period. In the locked state of the frequency synthesizer, the phase of the corresponding reference signal is generated between these divider signals. In the preferred embodiment, two phase detectors (PD) are used, each with its input terminal connected to receive one of the two divided VCO signals of the divider. The second input terminal of each phase detector is connected to receive a reference signal. Therefore, in the locked state, one PD outputs an “UP” signal and the other outputs a “DOWN” signal.

  The charge pump block may comprise N equal charge pump stages and is connected to each phase detector output terminal. The output terminals of each charge pump are coupled in a loop filter. The number of charge pumps operating during phase comparison is determined by the fractional accumulator stage. In the locked state, the amount of charge current and discharge current is always the same and compensates for each other. Therefore, no fractional ripple occurs. Thus, the preferred embodiment according to the present invention eliminates or reduces the need for compensation current trimming. Fractional compensation is dynamic and is not susceptible to environmental changes such as circuit age, process, and temperature. Thus, the preferred embodiment of the frequency synthesizer can be implemented by changing the phase difference of the divided signal of the programmable divider and the number of activated charge pumps.

FIG. 15 is a diagram illustrating a preferred embodiment of a sample and hold circuit 1500 in which a plurality of phase detectors are each coupled to a sample capacitor. As shown in FIG. 15, the first charge pump 1506 receives input from the first phase detector PD1, and the second charge pump 1508 receives input from the second phase detector PD2. The output 1510 of the first charge pump 1506 and the output 1512 of the second charge pump 1508 are coupled together to the input 1514 of the sample and hold circuit 1536 that is coupled to the first node n1. In the sample and hold circuit 1536, the reference voltage V _ref 1516 is coupled through the first switch 1518 to the first node n1. A sample capacitor, the first capacitor 1520, is coupled between the ground reference voltage 1522 and the first node n1. The second switch 1524 is coupled between the first node n1 and a second node n2 that is coupled to the output terminal 1534. A hold capacitor, which is the second capacitor 1530, is coupled between the ground reference voltage 1522 and the second node n2. The capacitances of the sample capacitor 1520 and the hold capacitor 1530 are much smaller than the capacitance of a normal loop filter capacitor. Before phase comparison is performed at phase detectors PD1 and PD2, first switch 1518 is closed and sample capacitor 1520 is charged to reference voltage V _ref 1516. The charge pump blocks 1506 and 1508 after the phase detectors PD1 and PD2, respectively, increase or decrease the voltage of the sample capacitor 1520 from the reference voltage V _ref 1516 according to the detected phase difference as a result of the phase comparison. When the phase comparison is complete, the charge in the sample capacitor 1520 is preferably transferred to the hold capacitor 1530 via the second switch 1524.

FIG. 16 is a timing diagram showing a fractional compensation method of the sample-and-hold type fractional N frequency synthesizer according to the present invention. For example, FIG. 16 may show the phase relationship between the divided reference frequency 306 and the divided VCO frequencies 310 and 312 of the frequency synthesizer 300 of FIG. 3 replacing lo with a sample and hold circuit. In FIG. 16, this fraction is assumed to be 3/8 (K = 3, N = 8). The number of charge pumps operating during phase comparison is determined by the state K of the fractional accumulator. For example, (N−K) charge pumps of PD1 and K charge pumps of PD2 are enabled. The total number of charge pumps enabled is always N. FIG. 16 shows a relative voltage waveform of the divided reference frequency 1602, Divider Output ₁ 1604, Divider Output ₂ 1606, PD1 output 1608, PD2 output 1610, and control voltage 1612. The number of charge pumps 1616 and 1618 enabled and the fractional accumulator state 1614 are also shown with respect to their waveforms. In FIG. 16, the phase advance of the divided reference signal 1602 is uniformly corrected by changing the number of enabled charge pumps corresponding to PD1 and PD2, so the reference from PD1 and PD2 A consistent value is obtained by increasing the charge from the voltage (Vmaple) to the control voltage (Vhold).

  As described above with respect to FIG. 7, a total of N charge pumps are implemented and the number of charge pumps connected to PD1 and PD2 is determined by a switch controlled by an accumulator. As shown in FIG. 16, the amount of charge sourced from the charge pump in all phase comparisons is given by:

Q _TOTAL = I _CP1 * T _CP1 + I _CP2 * T _CP2
= [{(N−K) * (I / N)} * {T1− (K / N) * T _VCO }] + [K * (I / N) * {(T ₁ − (K / N) * T _VCO ) + T _VCO }]
= I * T ₁ = constant (Formula 3)

Therefore, the voltage change of the control voltage or the sample capacitor is constant, and the voltage of the hold capacitor is also kept constant. Therefore, the synthesized output shows good spectral purity. When the frequency division ratio changes and different frequencies are generated, the phase difference T ₁ between the reference signal and the divided output changes, thereby determining the control voltage. Further, as shown in FIG. 16, the reference signal goes ahead of the divided signals 1604 and 1606. However, the present invention is not intended to be so limited. When the phase of the reference signal is delayed from the divided output, the voltage of the sample capacitor can be lowered from the reference voltage _Vref . Furthermore, the preferred embodiment according to the present invention can be implemented in various ways by changing the phase difference between the two divider output signals and the number of charge pumps in each phase detector.

  Another embodiment of a sample and hold fractional N frequency synthesizer with a phase locked loop according to the present invention is shown in FIG. As shown in FIG. 17, frequency synthesizer 1700 receives a reference frequency 1702 that is input to first and second phase detectors 1710 and 1712, respectively. The first phase detector 1710 further receives a first divided VCO frequency 1704 and the second phase detector 1712 further receives a second divided VCO frequency 1708. Lock detector 1718 and first charge pump block 1722 receive output 1714 of first phase detector 1710. Lock detector 1718 and second charge pump 1724 receive output 1716 of second phase detector 1712. The output 1726 of the first charge pump 1722 and the output 1728 of the second charge pump 1724 are coupled together and used as the input 1730 of a sample and hold circuit 1740 such as the sample and hold circuit 1536. VCO 330, modulus programmable divider 336, accumulator 340, etc. are preferably coupled to sample and hold circuit 1740 and phase detectors 1710 and 1712.

In the preferred embodiment of FIG. 17, a digital to analog converter (DAC) 1732 receives input 1720 from lock detector 1718 and generates an output 1734 that enters sample and hold circuit 1740. The output 1734 is preferably a reference voltage V _ref that is used to initialize the sample capacitor.

In the sample-and-hold type PLL, if the initially set reference voltage is too far from the lock control voltage, the loop cannot generate the target frequency. The frequency synthesizer 1700 according to the present invention includes a lock detector and generates a target frequency even if the initially set reference voltage is too far from the lock control voltage. As shown in FIG. 17, the detector circuit 1750 may comprise a lock detector 1718 and a DAC 1732. Lock detector 1718 preferably monitors the output of each phase detector 1710 and 1712, respectively. For example, if both PD1 and PD2 outputs are increased voltage signals (eg, an “UP” signal), the reference signal 1702 goes ahead of the divided signals 1704 and 1708. In this case, the DAC 1732 increases the reference voltage 1734 (eg, V _ref ), minimizing the voltage difference between the reference voltage and the target voltage. If the outputs of both PD1 and PD2 are reduced voltage signals (eg, “DOWN” signal), the reference signal 1702 is delayed from the divided signals 1704 and 1708. In this case, the reference voltage 1734 is lowered by the DAC 1732. If one phase detector generates an increase signal and the other phase detector generates a decrease signal (eg, PD1 generates a DOWN signal and PD2 generates an UP signal), the reference voltage 1734 is The value is very close to the control voltage. However, the present invention is not intended to be so limited.

FIG. 18 shows a system for setting a reference voltage according to another embodiment of the present invention. As shown in FIG. 18, another preferred embodiment of detector circuit 1850 includes an analog-to-digital circuit (ADC) 1820 and a digital-to-analog circuit (DAC) 1830. First phase detector 1710, second phase detector 1712, first charge pump 1722, second charge pump 1724, and sample and hold circuit 1740 have been described above. Therefore, the description is omitted here. The output 1810 of the sample and hold circuit 1740 is sent to a VCO (not shown) and an analog to digital converter 1820. The output 1822 of the analog to digital converter 1820 enters the digital to analog converter 1830. The ADC 1820 determines a control voltage for comparison with a predetermined voltage, and preferably sets a reference voltage 1840 (eg, V _ref ) through the DAC 1830. However, the present invention is not intended to be so limited. For example, the detector circuit 1850 can be replaced by a detector circuit 1750, and a DAC 1732 output until it can be compared to a predetermined control voltage using a lock detector 1718 that receives the output voltage 1810 from the sample and hold circuit 1740. To control.

FIG. 19 is a timing diagram showing a fractional compensation method of the sample-and-hold type fractional N frequency synthesizer when the reference voltage in the sample-and-hold circuit matches the target control voltage. For example, FIG. 19 may show the phase relationship between the divided reference frequency 306 and the divided VCO frequencies 310, 312 of the frequency synthesizer 300 of FIG. In FIG. 19, as described above, this fraction is assumed to be 3/8 (K = 3, N = 8). The relative voltage waveform is the divided reference frequency 1902, which shows Divider Output ₁ 1904, Divider Output ₂ 1906, PD1 output 1908, PD2 output 1910, and control voltage 1918. The number of charge pumps 1912 and 1916 enabled and the fractional accumulator state 1614 are also shown with respect to their waveforms.

  As shown in FIG. 19, the reference signal is between the divided signals. Thus, the charge pump (CP1) coupled to PD1 always sinks current from the sample and hold circuit, and the charge pump (CP2) coupled to PD2 always sources current to the sample and hold of the frequency synthesizer. The amount of charge and discharge is exactly matched through Equation 3 and the control voltage is kept constant. According to Equation 3, the amount of discharge current due to CP1 is given by:

Q _discharge = I _discharge * T _discharge = {(N−K) * (I / N)} * {(K / N) * T _VCO } (Formula 1)

K represents the state of the accumulator. Similar to Equation 1, the charging current amount by CP2 is given by the following equation.

Q _charge = I _charge * T _charge = {K * (I / N)} * [{(N−K) / N} * T _VCO ] (Formula 2)

From (Equation 1) and (Equation 2), Q _charge and Q _discharge are always the same.

  As mentioned above, the preferred embodiment of the frequency synthesizer according to the present invention has various advantages. A preferred embodiment of a phase locked loop (PLL) frequency synthesizer incorporates a sample and hold circuit within the fractional N-type frequency synthesizer. In the preferred embodiment, the sample and hold circuit replaces the related art loop filter capacitor in the fractional-N frequency synthesizer, thereby reducing circuit size and power requirements. A frequency synthesizer comprising a phase locked loop (PLL) according to a preferred embodiment further incorporates a fractional spurious compensation circuit to dynamically compensate for charge pump ripple as the charge pump operates. In a preferred embodiment, the programmable divider generates two output signals that are preferably divided signals from a voltage controlled oscillator (VCO) whose phase difference is the period of the VCO output. In the locked state of the frequency synthesizer, the corresponding reference signal phase is generated between these two divider signals. In a preferred embodiment, two phase detectors (PD) are used, each receiving one of a reference signal and two divided VCO signals, and outputting a voltage increase signal at one phase detector, The other phase detector can output a voltage decrease signal in the locked state.

  The charge pump block comprises N equal charge pump stages and can be coupled to one or both phase detector output terminals, and the output of each charge pump is coupled in a sample and hold circuit. In the locked state, the amount of charge current and discharge current substantially compensate each other. Therefore, no fractional ripple occurs. As such, fractional compensation is dynamic and less susceptible to environmental changes such as circuit age, process, and temperature in preferred embodiments according to the present invention. A preferred embodiment of the frequency synthesizer can be implemented by providing a uniform and stable VCO control voltage using a plurality of phase detectors with sample and hold circuits.

  The foregoing embodiments and advantages are merely exemplary and should not be construed as limiting the invention. The teachings of the present invention can be readily applied to other types of devices. The description of the present invention is for purposes of understanding and is not intended to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means and functions clauses are intended to cover not only the structural and structural equivalents described as performing the functions described herein, but also equivalent structures. ing.

FIG. 2 is a diagram of an embodiment according to the related art of an integer N frequency synthesizer using a sample and hold circuit. FIG. 2 is a diagram of the phase detector and sample and hold circuit of FIG. 1. It is a timing diagram of the lock state of the sample & hold type | mold integer N frequency synthesizer of related technology. FIG. 5 is a timing diagram of a sample and hold circuit in a related art fractional-N synthesizer. 1 is a schematic diagram illustrating a preferred embodiment of a frequency synthesizer comprising a phase locked loop (PLL) according to the present invention. FIG. 4 illustrates a preferred embodiment of the programmable modulus divider of FIG. FIG. 5 shows a phase detector circuit comprising a charge pump block with a charge pump stage after the phase detector. FIG. 6 is a diagram showing a control timing chart of the charge pump block of FIG. 5. FIG. 6 is a diagram illustrating another embodiment of a phase detector circuit including a charge pump block in which the number of charge pumps is reduced to N as compared to a total of 2N charge pumps of FIG. 5. FIG. 5 is a timing diagram of phase delay and phase advance of a divided reference frequency and a divided VCO frequency, respectively. FIG. 5 is a timing diagram of phase delay and phase advance of a divided reference frequency and a divided VCO frequency, respectively. FIG. 6 is a timing diagram of a compensation scheme according to a preferred embodiment of the present invention. FIG. 5 shows another preferred embodiment of a frequency synthesizer with a PLL that introduces a delay in the phase detector circuit. FIG. 6 illustrates another preferred embodiment of a phase detector circuit with delay. FIG. 6 is a timing diagram showing the effect when a delay enters the phase detector circuit. It is a figure which shows the example of a digital control circuit by which a delay is determined by the delay tap switched in a circuit. It is a figure which shows the analog circuit example by which the delay of each delay cell and the total delay of a circuit are controlled by a control voltage. FIG. 5 shows a sample and hold circuit in which each charge pump output is coupled to one sample capacitor. FIG. 5 is a timing diagram illustrating a preferred embodiment of a method for operating a sample and hold fractional N frequency synthesizer according to the present invention. FIG. 6 shows another preferred embodiment of a sample and hold fractional N frequency synthesizer comprising a detector circuit for setting a reference voltage according to the present invention. FIG. 6 shows a portion of another preferred embodiment of a fractional N frequency synthesizer comprising a detector circuit for setting a reference voltage according to the present invention. FIG. 6 is a timing diagram illustrating another preferred embodiment of a method for operating a sample-and-hold fractional N frequency synthesizer when a reference voltage according to the present invention matches a target control voltage.

Claims (19)

A phase-locked loop,
A first phase detector that receives an input signal and a first divided signal and outputs a first comparison signal;
A second phase detector that receives the input signal and a second divided signal and outputs a second comparison signal;
A circuit for receiving the first and second comparison signals and generating an output signal responsive to the comparison signals;
A voltage controlled oscillator that receives the output signal from the circuit and generates a predetermined frequency signal;
Receiving said predetermined frequency signal, e Bei a programmable modulus divider for generating said first and second divided signal having a predetermined phase relationship, said first and second phase detector Respectively,
A phase detector portion having a first output port;
A charge pump portion having N (N is an integer greater than or equal to 2) charge pumps coupled to the phase detector portion;
With
The number of charge pumps enabled during phase comparison in each of the first and second phase detectors is determined by the state of an accumulator coupled to the programmable modulus divider. . The sum of the number of charge pumps enabled is N;
The charge pump portions of the first and second phase detectors are identical;
Further comprising a plurality of parallel switches operated by a control line, each of said parallel switch, depending on the position of its, the the N of the charge pump corresponding one of said first and second comparison signals The phase-locked loop of claim 1, wherein the phase-locked loop is coupled to a selected signal. 3. The phase locked loop of claim 2, wherein each of the N charge pumps performs one of sourcing and sinking a predetermined amount of current to the circuit. . The phase-locked loop of claim 1, wherein the first and second phase detectors operate in a locked state . Each of the phase detector portions of the first and second phase detectors further comprises a second output port;
Each of the N charge pumps of the first and second phase detectors is:
A first current source and a first switch coupled in series between a first predetermined voltage and a charge pump output terminal;
A second current source and a second switch coupled in series between a second predetermined voltage and the charge pump output terminal;
A first input terminal is coupled to said first output port, receives a control signal for the second input terminal to control the number of charge pumps to the valid from the accumulator, the output terminal is the first A first logic gate coupled to one switch;
A first input terminal is coupled to the second output port, a second input terminal receives a control signal for controlling the number of enabled charge pumps from the accumulator , and an output terminal is the first output terminal . The phase-locked loop of claim 1 , comprising a second logic gate coupled to the two switches.   The first and second logic gates are AND gates, and one of the first and second switches is selected by an output of the first and second AND gates to set the charge pump output terminal to the The phase locked loop of claim 5, wherein the phase locked loop is coupled to one of the first and second current sources.   And a signal delay device coupled to delay one of the first and second comparison signal outputs from each of the first and second phase detectors. Item 2. A phase-locked loop according to Item 1. Comprising further the first and second one Oite to one of the phase detector, a signal delay device coupled to the input port or between said phase detector portion of the charge pump and the phase detector portion The phase-locked loop according to claim 1.   9. The phase-locked loop of claim 8, wherein the signal delay device is one of a digital delay control circuit and an analog delay control circuit.   The phase-locked loop of claim 1, wherein the first and second divided signals have the same frequency. The programmable modulus divider is
A first logic gate;
A second logic gate for receiving a modulus control signal;
A first flip-flop coupled to receive an output signal of the first logic gate and a predetermined frequency signal from an output port of the voltage controlled oscillator;
A second flip-flop coupled to receive the output signal of the first flip-flop, wherein the first and second logic gates receive the output signal of the second flip-flop. A second flip-flop,
A third flip-flop coupled to receive an output signal from the second logic gate, wherein the first, second, and third flip-flops receive a predetermined frequency signal as a clock signal; The output signal of the third flip-flop enters the first logic gate, and the output signals of the first and second flip-flops are the first and second divided signals, respectively. The phase-locked loop according to claim 1, further comprising a third flip-flop that is characterized. The phase-locked loop according to claim 11, wherein the first and second frequency-divided signals are different in phase by one period of the predetermined frequency signal.   The phase locked loop of claim 1, further comprising a detection circuit coupled to adjust a reference voltage of the circuit. The circuit is a sample and hold circuit,
First predetermined reference voltage, the first switch, and a first capacitor, and a second predetermined reference voltage is coupled in series,
The first switch and the first capacitor are coupled to form a first node;
The first node is coupled to receive first and second comparison signals ;
A second capacitor Ru Tei coupled between said second reference voltage and the second node, and a second switch coupled between said first node and said second node The phase locked loop according to claim 1, further comprising:   The phase-locked loop according to claim 14, further comprising a detection circuit that sets the first predetermined reference voltage. The detection circuit includes:
A lock detector that receives the first and second comparison signals from the first and second phase detectors;
The phase-locked loop of claim 15, comprising a digital-to-analog converter that adjusts a voltage level of the first predetermined reference voltage responsive to a control signal from the lock detector. The detection circuit includes:
An analog-to-digital converter that receives the output of the sample and hold circuit;
16. The phase-locked loop of claim 15, further comprising a digital-to-analog converter that adjusts a voltage level of the first predetermined reference voltage responsive to a control signal from the analog-to-digital converter. The detection circuit includes:
A lock detector for receiving the output signal from the sample and hold circuit;
The phase-locked loop of claim 15, comprising a digital-to-analog converter that adjusts a voltage level of the first predetermined reference voltage responsive to a control signal from the lock detector. The first and second frequency-divided signals have the same frequency, and the first and second frequency-divided signals differ in phase by one period of the predetermined frequency signal, and the first phase The phase-locked loop of claim 1, wherein the detector and the second phase detector are of the same design.

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