JP4206385B2 - Slot machine - Google Patents

Description

  The present invention relates to a slot machine capable of generating a predetermined prize according to a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable, and in particular, is constituted by a microcomputer, The present invention relates to a slot machine including control means for performing control.

  Conventionally, as this type of slot machine, every time one game is finished, data that does not need to be carried over to the next game among the stored data in the RAM mounted on the microcomputer that controls the game (for example, the next game) It has been proposed to initialize a winning game winning flag that is not carried over, the number of medals inserted, etc., and to shift to the next game (see, for example, Patent Document 1).

  Also in the pachinko machine, the variable display device that controls the variable display device has a storage area for storing data corresponding to each display area constituting the variable display device, and at the end of the variable display (from the game control means) It has been proposed to initialize the data stored in the storage area described above (when a confirmation command is received) (see, for example, Patent Document 2).

  On the other hand, in this type of slot machine, the control of the game (game) and the control of the effect performed in connection with the game are performed by one control means (microcomputer). There is a certain limit to the processing capacity, and it is extremely difficult to diversify the game and the accompanying effects, so a sub-control means is provided separately from the main control means for controlling the game. There has been proposed a slot machine in which the sub-control means controls the effects related to the game based on the command transmitted from the main control means.

  Also, the contents of the RAM provided in the main control means and the contents of the RAM provided in the sub-control means, that is, the control contents of the main control means and the sub-control means are backed up even in the event of a power failure. A slot machine that can return to the state has been proposed. This type of slot machine is provided with a power interruption detection means for monitoring a supply voltage and detecting a power interruption. When a power interruption is detected by this power interruption detection means, the main control means and sub Execute power failure processing to set data (for example, parity, checksum, etc.) to determine whether the control contents of the control means are backed up normally, and control the main control means and sub-control means at the time of recovery There has been proposed one that can confirm whether or not the content backup is normal (see, for example, Patent Document 3).

JP 2001-79157 A JP 2002-35318 A JP 2001-87459 A

  In the slot machine described in Patent Document 1 described above, every time one game is completed, data stored in the RAM that is not required to be carried over to the next game is initialized. A storage area in use (a storage area that is not used at all by design or an unused area in a stack) is not periodically initialized. For this reason, by making an illegal program resident in these unused areas of the RAM, the original program (stored in the ROM) at some opportunity (for example, an operation is performed with a procedure that is unlikely to be performed normally). There is a risk of fraud such as causing the gaming machine to perform an operation different from that of the program.

  On the other hand, in a slot machine generally described in Patent Document 3, a plurality of basic processes that constitute game control (for example, BET process, lottery process, reel rotation process, reel stop process, winning determination process, etc.) Are executed step by step, and interrupt processing for detecting switches, counting time, sending commands, etc. is interrupted in the basic processing described above and executed periodically. From such a configuration, it is conceivable that the power failure processing is interrupted by other processing by NMI (interrupt that cannot be prohibited) at the time of power failure. However, in this case, the power outage process can be performed promptly after the occurrence of the power outage, but if a power outage occurs during the above-mentioned periodic interrupt processing, double interruptions occur. There is a risk that not only the control load increases but also the consistency of control cannot be achieved. As a method for performing power failure processing without performing double interrupts, for example, it is conceivable to perform power failure processing during regularly executed interrupt processing, but in this case, interrupting after the occurrence of power failure Since the power failure process is not performed until the process is executed, there is a possibility that a necessary power source cannot be secured until the power failure process is performed, and there is a problem that the power failure process cannot be surely performed.

  The present invention has been made paying attention to such problems, and can prevent illegal programs from staying in the unused area of the memory means of the microcomputer that controls the game and generate multiple interrupts. It is an object of the present invention to provide a slot machine capable of performing a power failure process at an early stage as much as possible.

In order to solve the above-described problem, a slot machine according to claim 1 of the present invention provides:
A game can be started by setting a predetermined number of bets for one game, and a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable can be derived and displayed. 1 is a slot machine in which one game is completed and a winning can be generated according to the display result of the variable display device,
A main control means for controlling a game, comprising a microcomputer having an interrupt input terminal for generating an external interrupt when a signal is input;
Sub-control means for controlling production based on reception of control information transmitted from the main control means;
A power interruption detection means for monitoring a state of a predetermined power used in the slot machine and outputting a power interruption signal when a power interruption condition relating to the interruption of power supply is established;
With
The power interruption detection means outputs the power interruption signal to the interrupt input terminal of a microcomputer constituting the main control means,
The main control means includes
A storage means for storing data in a readable and writable manner and capable of holding data stored in the storage area even when power supply is stopped; A work area for storing data for operation of the microcomputer constituting the means, a stack area capable of temporarily storing data, and the microcomputer constituting the main control means for operation An unused area in which no data is read or written, and at least a main data storage means allocated;
Initialization means for initializing the unused area other than the stack area in the storage area of the main data storage means for each game;
Timer interrupt processing execution means for interrupting a process being executed every predetermined unit time and executing a timer interrupt process;
Branch counter updating means for updating a branch counter value for identifying a process to be executed in the timer interrupt process according to the execution of the timer interrupt process;
A plurality of types of processing executed in the timer interrupt processing, including processing for monitoring the input state of the operation detecting means for detecting the player's operation and storing the input information indicating the input state in the main data storage means A process selection means for selecting a process corresponding to the branch counter value as a process to be executed in the timer interrupt process,
Control before power supply stops the control state of the main control means when power supply is started in response to the occurrence of an external interrupt based on the input of the power interruption signal to the interrupt input terminal Power interruption interruption processing execution means for executing power interruption interruption processing for storing information necessary for returning to the state in the storage area of the main data storage means ;
Multiple interrupt prohibiting means for prohibiting the other interrupt process during the execution of either the timer interrupt process or the power interruption interrupt process,
The input information stored in the timer interrupt process is read, and a basic process for controlling one game is executed by gradually shifting a plurality of control states according to the progress of the game based on the read input information. Basic processing execution means to
Control information storage means that is a storage area assigned to the work area of the main data storage means and can store a plurality of the control information;
Control information generating means for generating the control information in accordance with the progress of the game in the basic processing and storing the control information in the control information storing means;
Control information transmission processing means for performing control information transmission processing for transmitting control information stored in the control information storage means to the sub-control means in the timer interrupt processing;
Including
The power interruption interrupt processing execution means waits for completion of the timer interruption processing being executed when the external interruption occurs during execution of the timer interruption processing. Run
The control information transmission processing means performs the control information transmission processing only once when the branching counter value indicates a specific value in the timer interrupt processing, and the control information storage means includes a plurality of the control information. If stored, only the control information generated at the earliest time among the plurality of control information stored in the control information storage means in the control information transmission process is transmitted.
According to this feature, since an unused area other than the stack area in the main data storage means is initialized for each game , an unused program other than the stack area in the main data storage means is used to store the malicious program. However, it is possible to prevent the unauthorized program from being resident.
In addition, the interruption of the other interrupt process is prohibited during the execution of either the interrupt process during power interruption or the timer interrupt process. Even when the signal is detected, it is possible to prevent double interruptions from occurring and prevent the control load of the main control means from increasing or data consistency from being lost. In particular, the transmission can be normally completed before the main control means stops without causing an external interruption due to the detection of the power interruption signal during the transmission of the control information and thereby preventing the transmission of the control information. Also, if a power interruption signal is detected during the execution of the timer interruption process, the interruption interruption process is executed after the timer interruption process is completed. Since the power interruption process is performed as early as possible while preventing the power failure, the power interruption process can be reliably performed before the main control means stops.
Moreover, even when transmitting a plurality of control information continuously, it is possible to secure time for the sub-control means to reliably receive the control information.
Note that the predetermined number of bets is at least one bet number, and a game can be started by setting a bet number of two or more or setting a maximum bet number. good.
The main data storage means may be built in a microcomputer constituting the main control means or may be provided outside the microcomputer.
The initialization unit may be any unit that initializes an unused area other than the stack area in the main data storage unit for each game (for example, at the start or end of a game). It is sufficient to initialize an unused area other than the stack area in the main data storage means at least once at the time of execution of a process that is always executed for each game.
In addition, the state of the predetermined power used in the slot machine is monitored, and when the power interruption condition related to the interruption of power supply is satisfied, for example, the DC voltage is monitored and the voltage is When the voltage falls below the threshold set for judging disconnection, when the period continues for a certain period, when the AC voltage is monitored and disturbance of the AC voltage waveform is detected, or when that period is a certain period Other conditions may be used as long as the power failure can be detected.

  Examples of the present invention will be described below.

  An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. A slot machine 1 according to the present embodiment is rotatable to a housing (not shown) whose front surface is open and a side end of the housing. It consists of a pivoted front door.

  Inside the casing of the slot machine 1 of this embodiment, reels 2L, 2C, 2R (hereinafter also referred to as a left reel, a middle reel, and a right reel) in which a plurality of types of symbols are arranged on the outer periphery are arranged in parallel in the horizontal direction. As shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, and 2R are arranged so as to be seen from the see-through window 3 provided on the front door.

  As shown in FIG. 2, “red 7” (black 7 in the drawing), “blue 7” (shaded 7 in the drawing), “white 7”, A plurality of types of mutually distinguishable symbols such as “BAR”, “JAC”, “watermelon”, “cherry”, and “bell” are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3, respectively.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and are rotated by reel motors 32L, 32C, and 32R (see FIG. 2), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Further, on the front door, a medal insertion portion 4 capable of inserting medals, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value) are used for one medal. The maximum bet number determined according to the gaming state within the range using the single BET switch 5 and credits operated when setting the betting number (in this embodiment, a normal gaming state and a small role described later) The MAXBET switch 6 is operated when setting 3 in the game, and 1) in the regular bonus described later, and is operated when the number of medals stored as credits is settled (medals for credits are returned). Checkout switch 10, start switch 7 operated when starting the game, operated when stopping the rotation of reels 2L, 2C, 2R, respectively Top switch 8L, 8C, 8R are provided.

  The front door also displays a credit indicator 11 for displaying the number of medals stored as credits, the number of medals acquired in a big bonus, which will be described later, and an error code indicating the contents when an error occurs. An auxiliary indicator 12 and a payout indicator 13 for displaying the number of medals paid out due to the occurrence of a prize are provided.

  Also, on the front door, 1 BET LED 14 that notifies that the bet number is set by 1 is turned on, 2 BET LED 15 that notifies that the bet number is set 2 is turned on, and that the bet number is set to 3 is turned on 3BETLED 16 to notify, the insertion request LED 17 to notify that the medal can be inserted by lighting, the start effective LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, and the weight (previous game) A waiting LED 19 that lights up to indicate that the game is in progress because a certain period of time has not elapsed since the start, and a replaying LED 20 that lights up to indicate that a replay game is in progress, which will be described later. Is provided.

  Further, inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 3) for notifying by lighting that the betting number setting operation by the operation of the 1BET switch 5 and the MAXBET switch 6 is valid. Inside the stop switches 8L, 8C, and 8R, left, middle, and right stop effective LEDs 22L, 22C, and 22R for informing that the reel stop operation by the corresponding stop switches 8L, 8C, and 8R is effective by lighting (FIG. 3) is provided.

  Further, inside the front door, a reset switch 23 for detecting a reset operation for canceling an error state excluding a RAM abnormality error described later by a predetermined key operation, changing a set value described later or confirming a set value A set value display 24 for displaying the set value at that time, a flow path of medals inserted from the medal insertion unit 4, a hopper tank (not shown) side or a medal payout opening provided later in the casing A flow path switching solenoid 30 for selectively switching to any one of the 9 side and a throw medal sensor 31 for detecting a medal thrown from the medal throwing section 4 and flowing down to the hopper tank side are provided.

  Inside the casing, a reel unit (not shown) including the reels 2L, 2C, and 2R, reel motors 32L, 32C, and 32R, and reel sensors 33 that can detect the reference positions of the reels 2L, 2C, and 2R, respectively. A hopper tank (not shown) for storing medals inserted from the medal insertion unit 4, a hopper motor 34 for paying out medals stored in the hopper tank from the medal payout opening 9, and the hopper motor 34 being paid out. A payout sensor 35 for detecting medals and a power supply box (not shown) are provided.

  On the front of the power supply box is a stop switch for selecting whether to enable / disable a stop function for controlling the stop state (a state in which the progress of the game is restricted until a reset operation is performed) at the end of a big bonus, which will be described later 36, a setting key switch 37 for switching to the setting change mode at the time of startup, and functioning as a reset switch for canceling an error state and a stop state except for a RAM abnormality error in a normal state. There are provided a reset / setting switch 38 functioning as a setting switch for changing the setting value of the winning probability (out-run rate) of the lottery, and a power switch 39 operated when turning on / off the power.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or the bet number is set using credits. In order to use credits, the single BET switch 5 or the MAX BET switch 6 may be operated. When a predetermined number of bets are set, the pay lines L1 to L5 (see FIG. 1) are valid, and the operation of the start switch 7 is valid, that is, the game can be started. In this embodiment, the predetermined number of bets is three, which is the maximum number of bets that can be set in one game in the normal gaming state and the small bonus game in the big bonus, which will be described later. Is one sheet which is the minimum unit.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a predetermined symbol combination on each of the activated pay lines L1-L5 is a reel 2L, 2C, 2R. When the display result is stopped, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit number (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 3 is a block diagram showing the configuration of the slot machine 1. As shown in FIG. 3, the slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 100. The game state is controlled by the game control board 40, and the game state is controlled by the effect control board 90. The power supply board 100 generates drive power for the electrical components constituting the slot machine 1 and supplies the drive power to each unit.

  The power supply board 100 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected via the. Further, the above-described hopper motor 34, payout sensor 35, stop switch 36, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply substrate 100.

  Connected to the game control board 40 are the above-described one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, insertion medal sensor 31, and reel sensor 33. In addition, the above-described payout sensor 35, stop switch 36, setting key switch 37, and reset / setting switch 38 are connected via the power supply substrate 100, and detection signals of these connected switches are input. It is like that.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 10, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected to each other, and are described above via the power supply board 100. The hopper motor 34 is connected, and these electric components are driven based on control of a main control unit 41 described later mounted on the game control board 40.

  The game control board 40 is composed of a microcomputer having a CPU 41a, ROM 41b, RAM 41c, and I / O port 41d. The main control unit 41 for controlling the game, random numbers in a predetermined range (0 to 16383 in this embodiment) are used. A random number generation circuit 42 for generating, a sampling circuit 43 for acquiring a random number from the random number generation circuit, and a switch detection circuit 44 for detecting a detection signal input from switches connected to the game control board 40 directly or via the power supply board 100 , A motor driving circuit 45 that controls the driving of the reel motors 32L, 32C, and 32R, a solenoid driving circuit 46 that controls the driving of the flow path switching solenoid 30, and a driving control of various displays and LEDs connected to the game control board 40. The power supply voltage supplied to the LED drive circuit 47 and the slot machine 1 to be monitored is monitored. An interruption detection circuit 48 that outputs a voltage drop signal indicating that to the main control unit 41 when a drop is detected. When the power is turned on or when an initialization command from the CPU 41a is not inputted, a reset signal is sent to the CPU 41a. A reset circuit 49 to be applied and other various devices and circuits are mounted.

  The CPU 41a has an interrupt function (including an interrupt prohibition function) such as a timekeeping function and a timer interrupt, and executes a program (described later) stored in the ROM 41b to perform processing related to the progress of the game. Each part of the control circuit mounted on the control board 41 is controlled directly or indirectly. The ROM 41b stores fixed data such as programs executed by the CPU 41a and various tables. The RAM 41c is used as a work area when the CPU 41a executes a program. The I / O port 41d inputs / outputs a control signal to / from each circuit connected via a signal input / output terminal included in the main control unit 41.

  The main control unit 41 includes a signal input terminal DATA, and detection states of various switches connected to the game control board 40 are input to the input port via the signal input terminal DATA. The input states of these signal input terminals DATA are monitored by the CPU 41a, and the CPU 41a executes a basic process that shifts in stages according to the input states of the signal input terminals DATA, that is, the detection states of various switches.

  In addition, the CPU 41a has an interrupt function as described above, and can execute an interrupt process by interrupting the basic process when an interrupt occurs. In this embodiment, four types of interrupts of interrupts 1 to 4 can be executed. For each interrupt, a counter mode (signal input from a trigger terminal CLK / TRG provided separately from the signal input terminal DATA) is provided. Can be selected and set in either an interrupt mode for generating an external interrupt in accordance with the timer mode or an interrupt mode for generating an internal interrupt in accordance with the number of clock inputs to the CPU 41a.

  In this embodiment, among the interrupts 1 to 4, interrupt 2 is set to the counter mode, interrupt 3 is set to the timer mode, and interrupts 1 and 4 are unused. The trigger terminal CLK / TRG is connected to the above-described power failure detection circuit 48, and the CPU 41a generates an interrupt 2 in response to the input of the voltage drop signal output from the power failure detection circuit 48, and the power failure described later. Execute interrupt processing. Further, the CPU 41a executes a timer interrupt process to be described later by generating an interrupt 3 every time the number of clock inputs reaches a certain number, that is, every certain interval. Moreover, although the interrupts 1 and 4 are set to unused, the interrupts 1 and 4 may generate | occur | produce by noise etc. For this reason, when interrupts 1 and 4 occur, the CPU 41a executes an unused interrupt process that immediately returns to the original process.

  The CPU 41a is set to prohibit other interrupts during execution of interrupt processing based on the occurrence of any one of interrupts 1 to 4, and a plurality of interrupts occurred simultaneously. In this case, interrupts to be executed with priority in the order of interrupts 2, 3, 1, 4 are set. That is, when interrupt 2 and other interrupts occur simultaneously, priority is given to interrupt 2 and when interrupt 3 and interrupt 1 or 4 occur simultaneously, priority is given to interrupt 3. To run.

  Further, the CPU 41a temporarily stores data in use stored in the register in a later-described stack area provided in the RAM 41c at the start of interrupt processing based on the occurrence of any of the interrupts 1 to 4. The data saved in the stack area at the end of the interrupt process is returned to the register.

  As the RAM 41c, a DRAM (Dynamic RAM) is used, and a refresh operation is required to maintain the stored data contents. The CPU 41a is provided with a refresh register 41R (see FIG. 42) for performing this refresh operation. The refresh register 41R is composed of 8 bits, and the lower 7 bits are automatically incremented every time the CPU 41a fetches an instruction from the ROM 41b. The value is updated every execution time of one instruction. Is called.

  The main control unit 41 is also supplied with backup power even during a power failure, and while the backup power is being supplied, the CPU 41a performs a refresh operation to hold the data stored in the RAM 41c. It is like that.

  The random number generation circuit 42 is configured by a counter that counts up and updates the value every time a predetermined number of pulses are generated, as will be described later, and the sampling circuit 43 acquires the numerical value counted by the random number generation circuit 42. . The random number generation circuit 42 defines a range of numerical values to be counted for each type of random number. In this embodiment, 0 to 16383 is defined as the range. The CPU 41a sends an instruction to the sampling circuit 43 in accordance with the processing to acquire the numerical value indicated by the random number generation circuit 42 as a random number (this function is hereinafter referred to as a hardware random number function). Random numbers for internal lottery, which will be described later, are not used as they are, but are processed and used by software. The details will be described in detail. The CPU 41a also has a function of updating the numerical value of the specific address in the RAM 41c by the above-described timer interrupt processing and acquiring the updated numerical value as a random number (hereinafter, this function is referred to as a software random number function).

  The CPU 41a transmits various commands to the effect control board 90 via the I / O port 41d. A command transmitted from the game control board 40 to the effect control board 90 is sent in only one direction, and no command is sent from the effect control board 90 to the game control board 40. The transmission line of the command transmitted from the game control board 40 to the effect control board 90 is composed of a strobe (INT) signal line, a data transmission line, and a ground line, and is connected via the effect relay board 80. The game control board 40 and the effect control board 90 are not directly connected.

  The production control board 90 is connected to electrical components such as a liquid crystal display 51 (see FIG. 1), production effect LEDs 52, speakers 53 and 54, and reel LEDs arranged on the front door of the slot machine 1. The components are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  Similar to the main control unit 41, the effect control board 90 includes a microcomputer having a CPU 91a, ROM 91b, RAM 91c, and I / O port 91d. The effect control board 90 includes a sub control unit 91 for effect control and an effect control board 90. A liquid crystal driving circuit 92 that controls the driving of the connected liquid crystal display 51, a lamp driving circuit 93 that controls the driving of the effect LED 52, an audio output circuit 94 that controls audio output from the speakers 53 and 54, A reset circuit 95 that gives a reset signal to the CPU 91a when the initialization command from the CPU 91a is not input, and other circuits are mounted. The CPU 91a receives a command transmitted from the game control board 40 and produces an effect. While performing various controls to perform, each control circuit mounted on the production control board 90 The directly or indirectly controlled.

  Similar to the CPU 41a of the main control unit 41, the CPU 91a has an interrupt function (including an interrupt prohibition function) such as a timer interrupt. An interrupt terminal (not shown) of the sub-control unit 91 is connected to a strobe (INT) signal line that is output when the main control unit 41 transmits a command among command transmission lines. An interrupt is generated based on the input, and a command reception interrupt process to be described later is executed. The CPU 91a executes a timer interrupt process (sub) to be described later by generating an interrupt every time the number of clock inputs reaches a certain number, that is, every certain interval. Also, when an unused interrupt occurs in the CPU 91a, an unused interrupt process for immediately returning to the original process is executed.

  Further, unlike the CPU 41a, when an interrupt is generated based on the input of the strobe signal (INT), the CPU 91a interrupts the process even when an interrupt process based on another interrupt is being executed. The command reception interrupt process is executed at the top, and even if another interrupt occurs at the same time, the command reception interrupt process is executed with the highest priority.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and while the backup power is supplied, the CPU 91a performs a refresh operation so that the data stored in the RAM 91c is retained. It has become.

  4 is a circuit diagram for explaining the configuration of the power supply board 100, and FIG. 5A is a circuit diagram for explaining the configuration around the main control unit 41 in the game control board 40. (B) is a circuit diagram for explaining a configuration around the sub-control unit 91 in the effect control board 90.

  As shown in FIG. 4, a rectifier circuit 302, a transformer 304, and voltage generation circuits 303, 305 to 308 are mounted on the power supply substrate 100. The rectifier circuit 302 converts an AC 100V AC voltage supplied from the outside into a DC voltage, and the transformer 304 transmits the DC voltage converted by the rectifier circuit 302 to an internal circuit. Then, the voltage generation circuit 303 generates + 25V DC voltage from the DC voltage transmitted through the transformer 304 and outputs it to the connector 301 and the voltage generation circuits 305, 306, 307, and 308, respectively. The voltage generation circuits 305, 306, 307, and 308 generate +24 V, +12 V (VCC), +12 V, and +5 V DC voltages from the +25 V DC voltage generated by the voltage generation circuit 303 and output them to the connector 301. . The connector 301 is connected to the game control board 40 or the like, and the DC voltage generated by the voltage generation circuits 305, 306, 307, and 308 is a device mounted on the game control board 40 or the effect control board 90, the game control board 40, It is supplied as a power source for driving various electrical components connected to the effect control board 90. That is, the + 25V DC voltage generated by the voltage generation circuit 303 drives various devices mounted on the game control board 40 and the effect control board 90, and various electrical components connected to the game control board 40 and the effect control board 90. It is a generation source of power.

  Among the DC voltages supplied from the power supply board 100, + 24V DC voltage is used as a driving power source for the hopper motor 34 directly connected to the power supply board 100, and is supplied to the game control board 40, thereby playing the game control board 40. It is also used as a drive power source for electrical components such as the reel motors 32L, 32C, 32R and the flow path switching solenoid 30 connected to the. Also, a + 12V (VCC) DC voltage is supplied to the effect control board 90 via the game control board 40, which will be described later, which is a drive power source for devices mounted on the effect control board 90 such as the sub-control unit 91. It is used as a power source for +5 V (VCC), or as a driving power source for electrical components such as the liquid crystal display 51, LEDs, and speakers connected to the effect control board 90. Further, the + 12V DC voltage is supplied to the game control board 40 and is connected to the game control board 40 via the power supply board 100 and other electrical components such as LEDs, indicators, sensors, and switches. It is used as a drive power source for electric switches (including electrical parts such as switches). The + 5V DC voltage is supplied to the game control board 40 and used as a drive power source for devices mounted on the game control board 40 such as the main control unit 41.

  Further, the + 5V DC voltage supply line in the game control board 40 branches on the game control board 40 to form a + 5V (VBB) DC voltage supply line, as shown in FIG. The + 5V (VBB) DC voltage supply line is connected to the backup power supply input terminal VBB via a backflow prevention diode 312 and, as shown in FIG. A large-capacitance capacitor 310 is provided between them. As a result, a DC voltage of + 5V (VBB) can be stored in the capacitor 310, and even during a power failure, the voltage stored in the capacitor 310 can be supplied as a backup power source over the period until the voltage is completely discharged. It has become.

  In addition, among the DC voltages output from the power supply substrate 100, a DC voltage of + 25V, that is, a DC voltage serving as a source for generating + 24V, + 12V (VCC), + 12V, and + 5V DC voltages is 5 ( As shown in a), the pressure is reduced by the resistor 311 (about 6.6% in this embodiment), and is input to the monitoring voltage input terminal VSB provided in the power interruption detection circuit 48. The power interruption detection circuit 48 outputs a voltage drop signal from the voltage drop signal output terminal RESET when the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level (+1.2 V in this embodiment) or less. It is configured to output. The voltage drop signal output terminal RESET is connected to the trigger terminal CLK / TRG of the main control unit 41 as described above, and when the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level or less. The voltage drop signal is input to the trigger terminal CLK / TRG of the main control unit 41. That is, the CPU 41 a of the main control unit 41 can detect the occurrence of power interruption based on the input of the voltage drop signal from the power interruption detection circuit 48 and can execute a power interruption interrupt process to be described later. In this embodiment, when the + 25V DC voltage becomes about + 18V or less, the voltage reduced by the resistor 311 becomes + 1.2V or less and a voltage drop signal is output. Therefore, the CPU 41a is based on the input of the voltage drop signal. Thus, the occurrence of power interruption can be detected when the + 25V DC voltage becomes + 18V or less.

  Further, the voltage drop signal output terminal RESET branches in the middle and is also connected to the signal input terminal DATA of the main control unit 41, so that the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level or less. Sometimes, the voltage drop signal is input to the signal input terminal DATA in addition to the trigger terminal CLK / TRG of the main control unit 41. In addition, the power interruption detection circuit 48 becomes inoperable or the voltage is not supplied after the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level (+1.2 V) or less. The voltage drop signal is continuously output until it exceeds a predetermined magnitude (+1.2 V). Therefore, the CPU 41a can monitor the input state of the voltage drop signal even during the power interruption interrupt process based on the input of the voltage drop signal from the power interruption detection circuit 48.

  As described above, in this embodiment, the main control unit 41 and the power interruption detection circuit 48 are driven by the + 5V DC voltage generated by the voltage generation circuit 308, and the power interruption detection circuit 48 is connected to the voltage generation circuit 303. When the + 25V DC voltage generated by the above becomes + 18V or less, which is higher than + 5V for driving these devices, the occurrence of power interruption is detected and a voltage drop signal is output. Since the DC voltage of + 5V is supplied to the main control unit 41 for a while after the CPU 41a detects the occurrence of the power interruption, it is necessary for the CPU 41a to perform the power interruption interrupt process based on the input of the voltage drop signal. Enough time can be secured.

  In the present embodiment, the power interruption detection circuit 48 monitors the drop of + 25V DC voltage generated by the voltage generation circuit 303 and is connected to the power supply board 100, the game control board 40 and the effect control board 90. The power supply voltage for driving the electrical components is generated by the voltage generation circuits 305, 306, and 307 provided separately from the voltage generation circuit 303 that generates the + 25V DC voltage monitored by the power interruption detection circuit 48. Since a stable voltage is monitored by the power interruption detection circuit 48 in comparison with a power supply voltage that tends to decrease depending on the driving state of these electric components, the occurrence of power interruption occurs due to a temporary voltage drop. Can be detected, and malfunction such as power interruption interrupt processing can be prevented.

  Further, as shown in FIG. 4, a capacitor 309 is provided on a + 25V DC voltage line input to the voltage generation circuit 306 in the power supply substrate 100, and is supplied to the voltage generation circuit 306 from the + 25V DC voltage. Even when the voltage can be stored and the supply of voltage from the voltage generation circuit 303 is interrupted, +12 V (VCC) is generated for the voltage generation circuit 306 over the period until the voltage stored in the capacitor 309 is discharged. The voltage required to do this is supplied. Therefore, the voltage generation circuit 306 is a source of power for devices such as the sub-control unit 91 mounted on the effect control board 90 for a certain period of time even when the supply of voltage from the voltage generation circuit 303 is interrupted during a power failure. The + 12V (VCC) DC voltage supply can be maintained, and the devices mounted on the production control board 90, in particular the sub-control unit 91, can be replaced by the devices mounted on the game control board 40 during a power failure. It can be driven for a long time. In this embodiment, the sub-control is performed for at least 20 ms from the time when the power interruption detection circuit 48 outputs a voltage drop signal at the time of a power failure as the capacitor 309, that is, from the time when the + 25V DC voltage becomes + 18V or less. A capacitor having a capacity capable of maintaining the drive of the unit 91 is used.

  Further, in the effect control board 90, as shown in FIG. 5B, voltage generation for generating + 5V (VCC) from a + 12V (VCC) DC voltage supplied from the power supply board 100 via the game control board 40 is performed. The circuit 313 is provided, and the + 5V (VCC) DC voltage generated by the voltage generation circuit is supplied to various devices mounted on the effect control board 90, such as the sub-control unit 91, and is used as a drive power source for these devices. used.

  The supply line of the + 5V (VCC) DC voltage to the sub-control unit 91 is connected to the backup power supply input terminal VBB of the sub-control unit 91 via the backflow prevention diode 314 and to the ground level. A large-capacity capacitor 315 is provided between them. As a result, a DC voltage of +5 V (VCC) can be stored in the capacitor, and even during a power failure, the voltage stored in the capacitor 315 can be supplied as a backup power source for a period until the voltage is completely discharged. ing.

  In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value, and the winning probability of the internal lottery described later is determined according to the set value. Hereinafter, the setting value changing operation will be described.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the power is turned on with the setting key switch 37 in the ON state, 1 is displayed as the initial value of the setting value on the setting value display 24, and the setting change mode in which the setting value can be changed by operating the reset / setting switch 38 is set. Transition. When the reset / setting switch 38 is operated in the setting change mode, the setting value displayed on the setting value display 24 is updated one by one (when the operation is further performed from the setting 6, the setting is returned to the setting 1). . When the start switch 7 is operated, the set value is confirmed, and the confirmed set value is stored in the RAM 41c of the main control unit 41. Then, when the setting key switch 37 is turned off, the state shifts to a state in which the game can proceed.

  In the slot machine 1 of the present embodiment, when the CPU 41a of the main control unit 41 detects a voltage drop signal, a power interruption interrupt process is executed. In the power interruption processing, the RAM 41c of the main control unit 41 stores destructive diagnosis data (5A (H) in this embodiment) in which any bit is 1, and is stored in all areas of the RAM 41c. The RAM parity adjustment data is calculated so that the RAM parity based on the data becomes 0, and stored in the RAM 41c. The RAM parity is a value calculated as an exclusive OR of values stored in each bit of the corresponding area (all areas in this embodiment) of the RAM 41c. Therefore, if the RAM parity based on the data stored in all areas of the RAM 41c is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 41c is 1. In this case, the RAM parity adjustment data is 1.

  The CPU 41a calculates the RAM parity based on the data stored in all areas of the RAM 41c at the time of activation, confirms the value of the destructive diagnosis data, the RAM parity is 0, and the destructive diagnosis On the condition that the data value is also correct, the processing state of the CPU 41a is restored to the state before the power interruption based on the data stored in the RAM 41c, but when the RAM parity is not 0 (in the case of 1) or for destructive diagnosis If the data value is not correct, it is determined that the RAM is abnormal, and a RAM abnormal error code is set and controlled to a RAM abnormal error state to disable the progress of the game. Unlike the other error states, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the setting change mode described above. It will not be released until

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, and 2R are stopped, if a combination of symbols called “combinations” is arranged on the activated winning line (hereinafter referred to as an effective line), Become. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition of the game state. In order for each winning combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag for the winning combination.

  FIG. 6A is a diagram showing a winning combination table by gaming state. The gaming state winning combination table is stored in advance in the ROM 41b of the main control unit 41 and is used to determine the combination determined to be winning in the internal lottery. The combination determined according to the game state is shown. The role in this slot machine 1 is JAC, Cherry, Watermelon, Bell as a small role, Replay as a replaying role, Big bonus (1), Big bonus (2), Big bonus (3), Regular bonus as special roles (1), regular bonus (2), and JACIN are defined.

  In the regular bonus game state, JAC, cherry, watermelon, and bell, which are small roles, are determined as winning roles, and are subject to lottery in the internal lottery in the regular bonus. In the small bonus game, which will be described later of the big bonus, cherry, watermelon and bell, which are small roles, and regular bonus (2), which is a special role, and JACIN are determined as winning roles. It is targeted. In the normal gaming state, the small role cherry, watermelon and bell, replay role replay, special role big bonus (1), big bonus (2), big bonus (3), regular bonus (1) It is determined as a winning combination and is subject to lottery in the internal lottery in the normal gaming state.

  In this embodiment, in the regular bonus game state, in addition to cherry, watermelon and bell, JAC is defined as a small role for winning. However, in the regular bonus game state, a small role game or a normal game is also provided. Similarly to the state, only cherry, watermelon and bell may be determined as winning small prizes.

  JAC is awarded when the combination of “Bell-JAC-JAC” is aligned on the active line in the regular bonus. However, in the gaming state other than the regular bonus, even if this combination is aligned, JAC is not awarded. Cherry is awarded when the symbol “cherry” is derived to any of the active lines for the left reel 2L in any gaming state. A watermelon is awarded when a combination of “watermelon-watermelon-watermelon” is aligned on any of the active lines in any gaming state. A bell is awarded when a combination of “bell-bell-bell” is arranged on any of the active lines in any gaming state. The payout of medals when these small roles are won will be described later.

  Replay is awarded when a combination of “JAC-JAC-JAC” is available on any of the active lines in the normal gaming state, but this combination is used for regular bonuses and big bonuses (small-games and regular bonuses). Even if it is complete, it will not be a replay prize. When a replay is won, the medals will not be paid out, but the next game can be started without setting the number of bets again, so the number of bets no longer required to be set in the next game (the regular bonus will not be replayed and will always be 3) This is substantially the same as when the corresponding three medals are paid out.

  The big bonus is a combination of “red 7-red 7-red 7”, a combination of “white 7-white 7-white 7”, or “blue 7-blue 7-blue 7” in any of the active lines in the normal gaming state. ”Will be awarded when the combination is complete. When the big bonus is won, the gaming state shifts to the big bonus. In the big bonus, a game called a small role game can be played. While the game state is the big bonus, the big bonus medium flag is set in the RAM 41c. The big bonus ends when the total number of medals paid out to the player in the big bonus reaches 465.

  When it is necessary to distinguish between a big bonus by “Red 7-Red 7-Red 7”, a big bonus by “White 7-White 7-White 7”, and “Blue 7-Blue 7-Blue 7” These are referred to as big bonus (1), big bonus (2), and big bonus (3), respectively. The big bonuses (1) to (3) are further subdivided according to the order in which the winning is determined in the internal lottery. When these are distinguished, the big bonus (1) -A Big Bonus (1) -B, Big Bonus (1) -C, Big Bonus (2) -A, Big Bonus (2) -B, Big Bonus (2) -C, Big Bonus (3) -A, Big The bonus (3) -B and the big bonus (3) -C shall be called.

  The regular bonus is awarded when a combination of “BAR-BAR-BAR” is arranged on any of the active lines in the small role game and the normal gaming state. When the regular bonus is won, the gaming state shifts from the small role game or the normal gaming state to the regular bonus. The regular bonus ends when 12 games are consumed, or when 8 games are won (any kind of combination is possible), whichever comes first. While the game state is in the regular bonus, the regular bonus medium flag is set in the RAM 41c. In particular, when a regular bonus is won in the small role game, a regular bonus is provided during the big bonus, and the regular bonus medium flag is also set in the RAM 41c in addition to the big bonus medium flag. When the total number of medals paid out to the player in the big bonus reaches 465 with the regular bonus in the big bonus, the regular bonus is terminated together with the big bonus.

  In addition, when it is necessary to distinguish between the regular bonus due to “BAR-BAR-BAR” in the normal gaming state and the regular bonus due to “BAR-BAR-BAR” in the small role game in the big bonus, the regular bonus (1) respectively. This is called regular bonus (2). In addition, the aforementioned big bonus (1), big bonus (2) and big bonus (3), regular bonus (1) and regular bonus (2) may be collectively referred to as “bonus”. To do.

  JACIN wins when a combination of “Watermelon-JAC-JAC” is available on any of the active lines in the small role game, but in a gaming state other than the small role game, even if this combination is available, JACIN wins. Not. When winning JACIN, the above-mentioned regular bonus is provided during the big bonus, and the regular bonus medium flag is also set in the RAM of the main control unit 41 in addition to the big bonus medium flag. When the total number of medals paid out to the player in the big bonus reaches 465 with the regular bonus in the big bonus, the regular bonus is terminated together with the big bonus.

  Hereinafter, the internal lottery will be described. The internal lottery decides whether or not the winning of each winning combination is allowed before the display results of all the reels 2L, 2C and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random number for internal lottery (an integer from 0 to 16383) is acquired as described later. Then, for each combination determined according to the gaming state, the acquired internal lottery random number, the bet number set by the player, and the set value set by the reset / setting switch 38 It is performed according to the number of judgment values for the combination. In this embodiment, since the lottery of the small role, the re-playing role and the special role is performed separately in the normal gaming state, the winning in the internal lottery is not exclusive, Special roles may be won at the same time.

  In the regular bonus and the small bonus game in the big bonus, the reference of the combination according to the gaming state is performed according to the winning combination table according to the gaming state shown in FIG. 6 (a). It is performed according to both the winning combination table according to gaming state shown in FIG. 6 (a) and the special role combination table described later shown in FIG. 6 (c).

  When the gaming state is a regular bonus (including the case where it is provided during the big bonus), JAC, cherry, watermelon, and bell are sequentially read out as the internal lottery target roles, and the small state game in which the gaming state is in the big bonus , Cherry, watermelon, bell, regular bonus (2), and JACIN are sequentially read out as the internal lottery target roles. However, when the regular bonus winning flag (2) is set in the game before the previous time and the game is carried over without winning based on the flag, the regular bonus (2) and JACIN are not eligible for internal lottery.

  When in the normal gaming state, first, a lottery of a small combination and a re-playing combination is performed, and then a lottery of a special combination is performed. In the lottery for the small role and the re-playing role, refer to the winning role-specific winning table, and in the normal gaming state, the target small role and the re-playing role, i.e., cherry, watermelon, bell, and replay are sequentially selected as the internal drawing. Read out.

  In the lottery of special roles, refer to the winning status table for each gaming state and the special role table for the special role. It is read in the order registered in another table.

  In addition, in the lottery for special roles, it is determined whether or not the special role is lost while winning is determined for a plurality of special roles. The roles and special roles are registered in the order in which they are judged. For this reason, in the special role lottery, the special combination and the special combination losing are read out in the order registered in the special-function-specific table.

  As shown in FIG. 6 (c), in the special role-specific table, the big bonus (1) -A, the big bonus (2) -A, and the big bonus are shown as special bonuses to be selected in the normal gaming state. (3) -A, big bonus (1) -B, big bonus (2) -B, big bonus (3) -B, big bonus (1) -C, big bonus (2) -C, big bonus (3 ) -C, regular bonus (1) is registered, and between big bonus (3) -A and big bonus big bonus (1) -B, big bonus (3) -B and big bonus (1)- Loss-A and Loss-B are registered between C, respectively, so in the special role drawing, big bonus (1) -A, big bonus (2) -A, big bonus (3) -A, Losing A, Big Bonus (1) -B, Big Bonus (2) -B, Big Bonus (3) -B, Loss-B, Big Bonus (1) -C, Big Bonus (2) -C, Big Bonus (3 ) -C and regular bonus (1).

  However, the regular bonus winning flag (1), the big bonus winning flag (1), the big bonus winning flag (2) or the big bonus winning flag (3) is set in the game before the previous time, and no winning based on the flag is generated. Since the regular bonus (1) and the big bonuses (1) to (3) are not subject to the internal lottery, the special bonus lottery is not performed.

  In the internal lottery, the number of determination values determined for the internal lottery target combination is sequentially added to the internal lottery random number, and when the addition result overflows, it is determined that the winning combination is won. When the winning is determined, the winning flag of the combination is set in the RAM 41c of the main control unit 41. The determination value number is read according to the storage address of the determination value number registered in the role-specific table stored in advance in the ROM of the main control unit 41.

  Also, especially in the normal gaming state, when the number of judgment values determined for the small role and the re-playing role that are the target in the normal gaming state is sequentially added to the random number for internal lottery, and the result of the addition overflows It is determined that the winning combination has been won, and the winning flag of the winning combination is set.

  Furthermore, regardless of whether or not the result of the addition of the random numbers for internal lottery overflowed, the number of judgment values determined for the special role that is the target in the normal gaming state (the judgment value that was determined in response to the special role lost) Is added to the random number for internal lottery (the first acquired random number) before addition, and when the result of addition overflows, it is determined that the winning combination is won, and the winning flag of the winning combination is determined. Is set (this is not the case when the result of adding the number of judgment values determined corresponding to the special role loses overflows). That is, in the normal gaming state, both the lottery for the small combination and the re-game combination and the lottery for the special combination are performed based on the same random number for internal lottery.

  As described above, the regular bonus winning flag (1), the big bonus winning flag (1), the big bonus winning flag (2) or the big bonus winning flag (3) is carried over from the previous game to the previous game. If it is, the special role will not be drawn.

  FIG. 6B is a diagram illustrating an example of a role-specific table for a small role and a re-playing role, and FIG. 6C is a diagram illustrating an example of a role-specific table for a special role (and lose). is there. The number of determination values may be 256 or more, and cannot be stored for one word. Therefore, each determination value is registered using a storage area for two words.

  The number of determination values for each combination (and lose) is registered corresponding to the number of bets (BET) set by the player in the game. This is because even with the same combination, the winning probability in the regular bonus may differ from other combinations. In addition, the number of determination values corresponding to the number of bets for each combination (and lose) is common regardless of the set value, and is different depending on the set value. If the number of determination values is common regardless of the set value, a common flag is set (value is set to “1”).

  In the role-specific table for the small role and the replaying role, as shown in FIG. 6B, the storage addresses of the JAC, cherry, watermelon, bell, and replay determination value numbers are registered in the order of reference. .

  The JAC is a role that is subject to internal lottery only with the regular bonus, and the storage address of the number of determination values corresponding to the bet number 1 with the regular bonus is registered. The common flag for this combination is 1, and a common storage address for the number of determination values is registered regardless of the set value.

  Cherry, watermelon, and bell are the targets that are subject to internal lottery in any gaming state, and the storage address of the number of judgment values corresponding to the bet number 1 in the regular bonus and the betting in the normal gaming state or small role game A storage address of the number of determination values corresponding to Equation 3 is registered. For cherry and watermelon, the common flag is 1, and a storage address for the common number of determination values is registered corresponding to the number of bets regardless of the set value. For the bell, the common flag is 0, and the storage address of the number of determination values is individually registered according to the set value corresponding to each bet number.

  Replay is a role that is subject to internal lottery only in the normal gaming state, and a storage address for the number of determination values corresponding to the bet number 3 in the normal gaming state is registered. The common flag for this combination is 1, and a common storage address for the number of determination values is registered regardless of the set value.

  As shown in FIG. 6 (c), the special role (and lose) role-specific table includes a big bonus (1) -A, a big bonus (2) -A, a big bonus (3) -A, and a loser. A, Big Bonus (1) -B, Big Bonus (2) -B, Big Bonus (3) -B, Loss-B, Big Bonus (1) -C, Big Bonus (2) -C, Big Bonus (3 ) -C, regular bonus (1), regular bonus (2), and JACIN are stored in the order of the storage values for the number of judgment values for each combination.

  Big Bonus (1) -A, Big Bonus (2) -A, Big Bonus (3) -A, Loss-A, Big Bonus (1) -B, Big Bonus (2) -B, Big Bonus (3)- B is a role that is an object of the internal lottery only in the normal gaming state, and the storage addresses of the number of determination values corresponding to the number 3 of bets in the normal gaming state are respectively registered. For these combinations, the value of the common flag is 1, and the storage address of the common determination value number is registered regardless of the set value.

  Loss-B, Big Bonus (1) -C, Big Bonus (2) -C, Big Bonus (3) -C, Regular Bonus (1) are roles that are subject to internal lottery only in the normal gaming state, The storage addresses for the number of determination values corresponding to the bet number 3 in the normal gaming state are registered. For these combinations, the value of the common flag is 0, and the storage address of the number of determination values is individually registered according to the set value.

  Regular bonus (2) and JACIN are internal lottery targets only in the small bonus game in the big bonus, and the storage address of the number of judgment values corresponding to the bet number 3 in the small bonus game is registered. . The value of the common flag for this role is 1, and a storage address for a common number of determination values is registered regardless of the set value.

  In addition, the number of medals to be paid out when winning each winning combination is also registered in the role-specific table. However, only the JACs, cherries, watermelons, and bells, which are small roles, are the targets for paying out medals when winning a prize. Cherry, watermelon and bell can be awarded when the bet number is 1 (regular bonus) or 3 (game state other than the regular bonus), but for the bell, when the bet number is 1, That is, when the gaming state is a regular bonus, 15 medals that are more than the other 8 are paid out.

  Big Bonus (1), Big Bonus (2), Big Bonus (3), Regular Bonus (1), Regular Bonus (2), and JACIN winnings are accompanied by a transition of the gaming state, and medals are paid out. It will not be. Replay does not involve the payout of medals. However, since it is not necessary to insert medals used for setting the number of bets in the next game, it is substantially the same as paying out 3 medals. Of course, losing special roles are not eligible for medal payout.

  FIG. 7 is a diagram illustrating a storage area for the number of determination values acquired based on addresses registered in the role-specific table. The storage area for the number of determination values is provided in the RAM 41c of the main control unit 41 in the development model, and in the address area allocated to the ROM 41b in the main control unit 41 in the mass production model.

  For example, the addresses ADD, ADD + 36, ADD + 36, ADD + 38, ADD + 40, ADD + 42, ADD + 44, ADD + 46, ADD + 48, ADD + 110, and ADD + 112 are subject to internal lottery in JAC, replay, big bonus (1) -A, big bonus (2)- Set when A, Big Bonus (3) -A, Loss-A, Big Bonus (1) -B, Big Bonus (2) -B, Big Bonus (3) -B, Regular Bonus (2), JACIN The addresses are referenced regardless of the value, and 27, 2245, 3, 3, 3, 260, 3, 3, 3, 32, and 4311 are acquired as the number of determination values, respectively, regardless of the set value.

  ADD + 98 is an address that is referred to when the target character of the internal lottery is a regular bonus (1) and the set value is 1. At this time, 31 that is a value stored here is acquired as the number of determination values. The Addresses ADD + 100, ADD + 102, ADD + 104, ADD + 106, and ADD + 108 are addresses that are referenced when the internal lottery is a regular bonus (1) and the set value is 2-6. As for regular bonus (1), the number of judgment values is individually stored according to the set value, but since the same number of judgment values is stored, the winning of regular bonus (1) at any set value Probabilities are the same.

  Addresses ADD + 50, ADD + 52, ADD + 54, ADD + 56, ADD + 58, and ADD + 60 are addresses that are referred to when the target combination of the internal lottery is Lost-B and the set value is 1 to 6, respectively. Addresses ADD + 62, ADD + 64, ADD + 66, ADD + 68, ADD + 70, and ADD + 72 are addresses that are referenced when the internal lottery target role is the big bonus (1) -C and the set value is 1-6. Addresses ADD + 74, ADD + 76, ADD + 78, ADD + 80, ADD + 82, and ADD + 84 are addresses that are referenced when the internal lottery target role is the big bonus (2) -C and the set value is 1-6. Addresses ADD + 86, ADD + 88, ADD + 90, ADD + 92, ADD + 94, and ADD + 96 are addresses that are referenced when the internal lottery target is a big bonus (3) -C and the set value is 1-6. For lose-B, big bonus (1) -C, (2) -C, (3) -C, the number of determination values is stored individually according to the set value, and different numbers of determination values are stored. Therefore, the winning (special role losing) probabilities of the loss-B, big bonus (1) -C, (2) -C, and (3) -C will differ depending on the set value.

  The address ADD + 2 is an address that is referred to regardless of the set value when the bet number is 1, that is, in the regular bonus, the target combination of the internal lottery is cherry. The address ADD + 4 is an address that is referred to regardless of the set value when the number of bets is 3, that is, in the normal gaming state or in the small role game, when the target character of the internal lottery is cherry. The number of determination values for cherry is registered according to the number of bets, but since the same value is registered, the winning probability of cherry is the same in any gaming state. For the watermelon, the number of determination values is registered in the same manner at addresses ADD + 6 and ADD + 8.

  Addresses ADD + 10, ADD + 12, ADD + 14, ADD + 16, ADD + 18, and ADD + 20 are addresses that are referenced when the bet number is 1, that is, when the target character of the internal lottery is a bell and the set value is 1 to 6 in the regular bonus. is there. Since the same value is registered in each of the addresses ADD + 10 and ADD + 12, ADD + 14 and ADD + 16, and ADD + 18 and ADD + 20, the set value 1 and the set value 2, the set value 3 and the set value 4, and the set value are set at the regular bonus time. With 5 and the set value 6, the winning probability of the bell is the same.

  Addresses ADD + 22, ADD + 24, ADD + 26, ADD + 28, ADD + 30, and ADD + 32 are each when the number of bets is 3, that is, when the target lot of the internal lottery is a bell and the set value is 1 to 6 in the normal game state or the small role game The address to be referenced. Since different values are registered in the addresses ADD + 22, ADD + 24, ADD + 26, ADD + 28, ADD + 30, and ADD + 32, the winning probability of the bell differs depending on the set value in the normal game state or the small role game.

  FIGS. 8A, 8B, 9, 10A, and 10B are diagrams showing examples of the relationship between the value of the random number for internal lottery and the number of determination values of each combination and the winning combination. . 8 (a), (b) and FIG. 9 show an example of a normal game state, FIG. 10 (a) shows a small role game, and FIG. 10 (b) shows an example of a regular bonus. Yes. FIGS. 8A, 8B, 9, and 10A, 10B show examples where the set value is 6, and FIGS. 8B and 9 are regular. An example in which neither a bonus winning flag nor a big bonus winning flag is set is shown.

  In the normal gaming state, the roles that are subject to the internal lottery are regular bonus (1), big bonus (1), big bonus (2), big bonus (3), cherry, watermelon, bell, and replay. In the normal gaming state as described above, the lottery for the small role and the replaying role and the lottery for the special role are performed separately for the same random number for the internal lottery. Random values for internal lottery and the number of judgment values for each role and the winning combination, random values for internal lottery in special lottery and the relationship between the number of judgment values for each role and the winning role, both lotteries The random number value for internal lottery and the relationship between the number of determination values for each combination and the winning combination will be described.

  For example, as shown in FIG. 8 (a), the winning roles in the lottery of the small role and the replaying role in the normal gaming state are cherry, watermelon, bell, and replay. The number of values is 269, 68, 3582, 2245. When the cherry that is the target of the lottery of the small combination and the re-playing combination is added as the random number for internal lottery 16115-16383, the addition result overflows by adding 31 judgment values Will be won.

  Next, the watermelon that is the target of the lottery of the small combination and the re-playing combination adds 337 that is the sum of the determination value number 269 of cherry and the determination value 68 of watermelon, and the addition result overflows 16047 When ˜16114 is acquired as a random number for internal lottery, it is won. Similarly, when 12465 to 16046 are acquired as random numbers for internal lottery, the replay is determined to be winning when 10220 to 12464 are acquired as random numbers for internal lottery.

  The approximate winning probabilities of the small role and the replaying role calculated based on the number of judgment values are 1 / 60.9, 1 / 240.9, 1/4 for cherry, watermelon, bell, and replay, respectively. .6, 1 / 7.3. In addition, when 0-10219 is acquired as a random number for internal lottery, all the small combinations and re-playing combinations are lost.

  On the other hand, as shown in FIG. 8 (b), the winning combinations in the special winning lottery in the normal gaming state are big bonus (1) -A, big bonus (2) -A, big bonus (3) -A. , Loss-A, Big Bonus (1) -B, Big Bonus (2) -B, Big Bonus (3) -B, Loss-B, Big Bonus (1) -C, Big Bonus (2) -C, Big Bonus (3) -C, regular bonus (1). With the set value 6, the number of determination values is 3, 3, 3, 260, 3, 3, 3, 5886, 14, 14, 14, Therefore, 16381 to 16383, 16047 to 16380, 16375 to 16377, 16115 to 16674, 16112 to 16114, 16109 to 16111, 16106 to 16108, 10 When the 20～16105,10206～10219,10192～10205,10178～10191,10147～10777 has been acquired as a random number for the internal lottery, it is determined to win (loss of the special role). In addition, the approximate winning probabilities of the respective roles are 1 / 5461.3, 1 / 5461.3, 1 / 5461.3, 1 / 63.0, 1 / 5461.3, 1 / 5461.3, 1/546, 5461.3, 1 / 2.8, 1 / 11170.3, 1 / 11170.3, 1 / 11170.3, 1 / 528.5. When 0-10146 is acquired as a random number for internal lottery, all special roles are lost.

  Then, a random number range (16115 to 16383) for internal lottery in which cherries are determined to be won in the lottery of the small role and replaying role, and big bonus (1) -A, big bonus (2)- A, Big Bonus (3)-A random number range (16381 to 16383, 16047 to 16380, 16375 to 16377) for internal lottery in which A is determined to be winning overlaps, so the values in these overlapping ranges are for internal lottery Are obtained as the random numbers, it is determined that the big bonus (1) and cherry, the big bonus (2) and cherry, and the big bonus (3) and cherry are won simultaneously. Similarly, a random number range (16047 to 16114) for internal lottery in which watermelons are determined to be winning in the lottery of the small role and replaying role, and big bonus (1) -B and big bonus (2) in the lottery of special role -B, Big Bonus (3)-Since the range of random numbers for internal lottery (16112 to 16114, 16109 to 16111, and 16106 to 16108) in which B is determined to be won, respectively, the values of these overlapping ranges are When obtained as random numbers for internal lottery, it is determined that the big bonus (1) and watermelon, the big bonus (2) and watermelon, and the big bonus (3) and watermelon are won at the same time.

  Therefore, in the normal gaming state, as shown in FIG. 9, when 16381-16383, 16047-16380, 16375-16377 are acquired as random numbers for internal lottery, big bonus (1), cherry, big bonus, respectively (2) and cherry, big bonus (3) and cherry are determined to be won at the same time, and when 16115 to 16374 are acquired as random numbers for internal lottery, it is determined that only cherry is won alone, and 16112 to When 16114, 16109-16111, 16106-16108 were acquired as random numbers for internal lottery, Big Bonus (1) and Watermelon, Big Bonus (2) and Watermelon, Big Bonus (3) and Watermelon were won simultaneously. It is determined that 16047-16105 is a random for internal lottery It is determined that only the watermelon has been won alone, and when 12465 to 16046 is acquired as a random number for internal lottery, it is determined that only the bell has been won alone, and 10220 to 12464 are internal. When it was acquired as a random number for lottery, it was determined that only replay was won alone, and when 10206-10219 was acquired as a random number for internal lottery, only the big bonus (1) was won alone It is determined that when 10192 to 10205 are acquired as random numbers for internal lottery, it is determined that only the big bonus (2) has been won alone, and when 10178 to 10191 is acquired as random numbers for internal lottery, Only the big bonus (3) is determined to be won alone, and 10147 to 10177 are acquired as random numbers for internal lottery When it is, and only the regular bonus (1) is determined to have elected alone. And the approximate probability of winning both Big Bonus (1) and Cherry, Big Bonus (2) and Cherry, Big Bonus (3) and Cherry will be 1 / 5461.3 respectively, and the approximate probability that Cherry will win alone is The probabilities of winning the big bonus (1) and watermelon, the big bonus (2) and watermelon, and the big bonus (3) and watermelon are 1 / 5461.3 respectively. The approximate probability of winning will be 1 / 277.7, and the approximate probability that the bell, replay, big bonus (1), big bonus (2), big bonus (3), regular bonus (1) will win independently 1 / 4.6, 1 / 7.3, 1 / 11170.3, 1 / 11170.3, 1 / 11170.3, 1/528 5 to become. When 0-10146 is acquired as a random number for internal lottery, all combinations are lost.

  In the normal gaming state, if either the regular bonus winning flag or the big bonus winning flag is already set, that is, if these winning flags are set and carried over in the previous game, the small Since only the lottery and the re-playing role are drawn, the random number value determined for each winning combination and the winning probability of each winning combination are as shown in FIG.

  In addition, as shown in FIG. 10A, in the small role game, cherry, watermelon, bell, regular bonus (2), and JACIN are subject to internal lottery, and the number of determination values is 269, 68, 3582, 32, 4311. Therefore, when 16115-16383, 16047-16114, 12465-16046, 12433-12464, and 8122-12432 are acquired as random numbers for internal lottery, it is determined that the winner is won. In addition, the approximate winning probabilities of each combination are 1 / 60.9, 1 / 240.9, 1 / 4.6, 1/512, and 1 / 3.8. When 0 to 8121 are acquired as random numbers for internal lottery, all combinations are lost.

  Also, as shown in FIG. 10B, in the regular bonus, JAC, cherry, watermelon, and bell are subject to internal lottery, and the number of determination values is 27, 269, 68, 15919. When 16383, 16088 to 16356, 16020 to 16087, and 101 to 16019 are acquired as random numbers for internal lottery, it is determined that the winner is won. In addition, the approximate winning probabilities of each combination are 1 / 606.8, 1 / 60.9, 1 / 240.9, and 1 / 1.03. When 0 to 100 are acquired as random numbers for internal lottery, all combinations are lost.

  Next, acquisition of random numbers for internal lottery will be described in detail with reference to FIG. The random numbers for the internal lottery are acquired by extracting random numbers from the random number generation circuit 42 by the hardware random number function and processing them by software by the CPU 41a. It is assumed that the least significant bit of the random number extracted from the random number generation circuit 42 or the processed random number is called the 0th bit, and the most significant bit is called the 15th bit.

  FIG. 11A is a block diagram showing the configuration of the random number generation circuit 42 in detail. As shown in the figure, the random number generation circuit 42 includes a pulse generation circuit 42a, a lower counter 42b, and an upper counter 42c. The lower counter 42b and the upper counter 42c are both 8-bit (1 byte) counters, the lower counter 42b is the 0th to 7th bits, and the upper counter 42c is a total of 16 bits from the 8th to 15th bits. The data signal is output.

  The pulse generation circuit 42a outputs a pulse signal at a frequency that is higher than the frequency of the operation clock of the CPU 41a and is not an integral multiple thereof (preferably relatively prime). The pulse signal output from the pulse generation circuit 42a is clocked into the lower counter 42b.

  The lower counter 42b alternately inverts the 0th bit data signal between the H level and the L level every time a pulse signal is input from the pulse generation circuit 42a. Assuming that positive logic is applied, a logical value of H level corresponds to 1 and a logical value of L level corresponds to 0. In the case of negative logic, a logic value of 1 may be read as L level, and a logic value of 0 may be read as H level. When the level of the 0th bit data signal is inverted from H level to L level, that is, whenever the logic value of the 0th bit data signal changes from 1 to 0, the level of the 1st bit data signal is changed to H level. Inverted alternately with L level.

  Similarly, when the level of the (m−1) th bit data signal is inverted from the H level to the L level, that is, whenever the logic value of the (m−1) th bit data signal changes from 1 to 0, the mth bit data The signal level is alternately inverted between the H level and the L level. A carry signal is output every time the level of the seventh bit data signal changes from H level, that is, the logical value of the seventh bit data signal changes from 1 to 0. The carry signal output from the lower counter 42b is clocked into the upper counter 42c.

  The upper counter 42c alternately inverts the eighth bit data signal between the H level and the L level every time a carry signal is input from the lower counter 42b. Each time the level of the 9th bit data signal is inverted from H level to L level, the level of the 9th bit data signal is alternately inverted between H level and L level. Similarly, every time the level of the m−1th bit data signal is inverted from the H level to the L level, the level of the mth bit data signal is alternately inverted between the H level and the L level.

  The logic value of a 16-bit data signal in which the data signal of the lower counter 42b is the lower 8 bits and the data signal of the upper counter 42c is the upper 8 bits is 0 (0000h) every time the pulse generation circuit 42a outputs the pulse signal. ) → 1 (0001h) → 2 (0002h) →... → 65535 (FFFFh) The values are updated so as to be continuous every update, and the maximum value 65535 (FFFFh) is next to the initial value 0 (0000h). The value circulates and is output from the random number generation circuit 42.

  The sampling circuit 43 includes a latch circuit, and latches and latches a 16-bit data signal output from the random number generation circuit 42 at that time based on a sampling command (when the start switch 7 is operated) from the CPU 41a. Output the data signal. The CPU 41a extracts numerical data corresponding to the data signal input from the sampling circuit 43 via the I / O port 41d as a random number generated by the random number generation circuit. In the following description, the data signal output from the random number generation circuit 42 is described as a random number corresponding to the logical value.

  FIG. 11B is an explanatory diagram until the CPU 41a processes the random number extracted from the random number generation circuit 42 into a random number for internal lottery by software. The random number extracted from the random number generation circuit 42 is stored in a 16-bit general-purpose register 41GR included in the CPU 41a.

  When the random number extracted from the random number generation circuit 42 is stored in the general-purpose register 41GR, the CPU 41a uses the other general-purpose register or the work area of the RAM 41c to lower-order the bytes of the general-purpose register 41GR (value extracted from the lower-order counter 42b). And the value of the upper byte (the value extracted from the upper counter 42c) are exchanged.

  Next, the CPU 41a performs an OR operation with the value 8080h of the random number in which the upper byte and the lower byte are replaced with respect to the extracted random number. Since the processing word of the CPU 41a is 1 byte, the logical sum operation is actually performed sequentially on the upper byte and the lower byte. By this OR operation, the 15th bit and the 7th bit are always 1. Furthermore, the CPU 41a shifts the upper 1 byte (8th bit to 15th bit) to the lower bit by bit, and inserts 1 into the empty 15th bit.

  The CPU 41a acquires the value stored in the general-purpose register 41GR at this time as a random number for internal lottery, stores it in a predetermined area of the RAM 41c, and sequentially adds the number of determination values of each combination to this It becomes. Since the 15th and 14th bits of the random number for internal lottery are always 1, the random number for internal lottery is a random number having a size of 14 bits (16384), which is substantially 0 to 16383. It takes a value.

  Note that interrupts to the CPU 41a are prohibited from the extraction of random numbers from the random number generation circuit 42 to the end of processing. This is to prevent the contents of the general-purpose register 41GR from being rewritten in the interrupt processing routine when an interrupt is generated to the CPU 41a.

  Next, the arrangement of symbols on the reels 2L, 2C, and 2R and stop control will be described. As described above, the rotation of the reels 2L, 2C, and 2R is stopped within a drawing range within 4 frames from when the stop switches 8L, 8C, and 8R are operated. The symbols to be stopped are selected according to the setting status of the winning flag, and the symbols of the winning combination in the drawing range of 4 frames on the active line set in each game are stopped. If you can, stop them all together. Symbols that have not been won will be stopped within the 4-frame pull-in range.

  Here, as shown in FIG. 2, “watermelon”, “bell”, and “JAC” are arranged at intervals of 5 frames or less on each of the reels 2L, 2C, and 2R, and the drawing range of 4 frames is shown. Thus, the variable display device 2 can always be stopped at any position. That is, when the winning flags of watermelon, bell, replay, JAC, and JACIN are set, regardless of the operation timing of the stop switches 8L, 8C, and 8R by the player, the combination must be used. You can win a prize.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The RAM 41c of the main control unit 41 has a 512-byte storage area. As shown in FIG. 12, addresses of 7E00 (H) to 7FFF (H) are assigned to each byte, as well as important work. , General work, special work, set value work, unsaved work, unused area, stack area.

  The important work is an area of 40 bytes from 7E00 (H) to 7E27 (H), and it is a big bonus such as various display and LED display data, I / O port 41d input / output data, game time counter, etc. This work stores data that is inconvenient if it is initialized at the end.

  The general work is a 178-byte area of 7E28 (H) to 7E8E (H), 7EBA (H) to 7F04 (H). This work stores data that can be initialized at the end of the big bonus, such as the total number of payouts.

  The special work is a 39-byte area from 7E8F (H) to 7EB5 (H), and data for transmitting commands to the effect control board 90, various software random numbers, etc., are initialized only before the start of setting. The work to be stored.

  The set value work is a 1-byte area of 7EB6 (H) and is a work in which the set value is stored. After 0 is stored in the initialization before the setting is started (before the transition to the setting change mode), It is corrected to 1, and the set value newly set at the end of the setting (at the end of the setting change mode) is stored.

  The unsaved work is a 3-byte area from 7EB7 (H) to 7EB9 (H), and is a work that maintains the state of various switches as the stop switch 36. When the power is turned on, the data in the RAM 41c is destroyed. The value is always set regardless of whether or not it is set.

  The unused area is a 205-byte area from 7F05 (H) to 7FD1 (H) and is an unused area in the storage area of the RAM 41c, and any one of a plurality of initialization conditions to be described later is satisfied. Then it will be initialized.

  The stack area is a 45-byte area from 7FD2 (H) to 7FFF (H), and the area from 7FD2 (H) to stack pointer-1 is an unused stack area in the stack area. The area of the stack pointer to 7FFF (H) is an in-use stack area in which data saved from the register of the CPU 41a is stored. Of these, the unused stack area is initialized if any one of a plurality of initialization conditions to be described later is satisfied, as in the case of the unused area. Therefore, it is not initialized.

  In this embodiment, as shown in FIG. 13A, the CPU 41a of the main control unit 41 destroys the data in the RAM 41c before starting the setting (before shifting to the setting change mode), at the end of the big bonus, and at the time of turning on the power. When there is not, when four initialization conditions at the end of one game are satisfied, four types of initializations with different areas initialized according to each initialization condition are performed.

  Initialization 1 is an initialization that is performed before the setting key switch 37 is turned on when the power is turned on and shifts to the setting change mode. Initialization 1 includes the storage area of the RAM 41c. All the areas (including the unused area and the unused stack area) except the in-use stack area are initialized. Initialization 2 is initialization performed at the end of the big bonus. In initialization 2, the general work, the unused area, and the unused stack area are initialized in the storage area of the RAM 41c. Initialization 3 is an initialization performed when the setting key switch 37 is in an OFF state when the power is turned on, and the data in the RAM 41c is not destroyed. In the initialization 3, the unsaved work, the unused area, Unused stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  In the ROM 41b, the start address of the area to be initialized and the initialization size indicating the size of the area to be initialized are registered corresponding to each of initializations 1 to 4, and when the CPU 41a initializes the RAM 41c. Refers to the initialization table, acquires the start address and initialization size corresponding to any of initializations 1 to 4 according to the initialization condition, sets a pointer to the start address, and sets the initialization size . If the initialization size includes the size of the unused stack area, the size of the unused stack area (stack pointer-7FD2 (H)) is calculated and the initialization size is set. Then, the area of the address corresponding to each byte from the initialization address where the pointer is set is cleared to 0, and each time the byte is cleared, the initialization size is decremented by 1 and the pointer is advanced by 1. Run until zero. That is, when the CPU 41a initializes the RAM 41c, it does not initialize each area according to the initialization condition, but initializes an area of a specified size from a specified address.

  FIG. 13B is a diagram showing an initialization table. In the initialization table, the start address and the initialization size are registered corresponding to the initializations 1 to 4 as described above.

  In initialization 1, 7E00 (H) is registered as the start address, and 1D3 (H) + M (size of unused stack area: (stack pointer−7FD2)) bytes are registered as the initialization size. 7E00 (H) to 1D3 (H) + M bytes are initialized. Then, as shown in FIG. 12, important work, general work, special work, set value work, unsaved work, general work, unused area, and unused stack area are allocated to address areas that are continuous from 7E00 (H). The sum of the sizes of these areas is 1D3 (H) + M bytes. Therefore, in initialization 1, 7D00 (H) is initialized to 1D3 (H) + M bytes, so that These areas are initialized in the order of general work, special work, set value work, non-saved work, general work, unused area, and unused stack area.

  In initialization 2, two start addresses and initialization sizes for each address are registered. This is because the general work initialized in the initialization 2 is allocated to two separate address areas. In initialization 2, 7E28 (H) is registered as the start address of the area to be initialized first, 67 (H) bytes are registered as the initialization size, and 7EB7 (H) is set as the start address of the area to be initialized next. Since 118 (H) + M bytes are registered as the conversion size, in initialization 2, an area for 7E28 (H) to 67 (H) bytes and an area for 7EB7 (H) to 118 (H) + M bytes Is initialized. The size of general workpieces 7E28 (H) to 7E8E (H) is 67 (H) bytes. As shown in FIG. 12, the remaining general workpiece area, unused area, and unused stack area are 7EB7 ( H) are allocated to consecutive address areas, and the total size of these areas is 118 (H) + M bytes. Therefore, in initialization 2, 7E28 (H) to 67 (H) bytes are initialized, By initializing 7EB7 (H) to 118 (H) + M bytes, these areas are initialized in the order of general work, unused area, and unused stack area.

  Also in the initialization 3, two start addresses and initialization sizes for each address are registered. This is because the non-saved work initialized in the initialization 3 and the unused area and the unused stack area are allocated to two separate address areas. In initialization 3, 7EB7 (H) is registered as the start address of the area to be initialized first, 3 (H) bytes are registered as the initialization size, and 7F05 (H) is set as the start address of the area to be initialized next. Since CD (H) + M bytes are respectively registered as the conversion size, in initialization 3, an area from 7EB7 (H) to 3 (H) bytes and an area from 7F05 (H) to CD (H) + M bytes Is initialized. Then, as shown in FIG. 12, the unsaved work is an area for 3 bytes from 7EB7 (H), and the unused area and the unused stack area are allocated to address areas that are continuous from 7F05 (H). Since the total size of these areas is CD (H) + M bytes, in initialization 3, 7EB7 (H) to 3 (H) bytes are initialized, and 7F05 (H) to CD (H) + M bytes. When the minutes are initialized, these areas are initialized in the order of the non-saved work, the unused area, and the unused stack area.

  In initialization 4, 7F05 (H) is registered as the start address and CD (H) + M bytes are registered as the initialization size. Therefore, in initialization 4, an area from 7F05 (H) to CD (H) + M bytes is registered. Is initialized. As shown in FIG. 12, the unused area and the unused stack area are allocated to address areas that continue from 7F05 (H), and the total size of these areas is CD (H) + M bytes. Therefore, in initialization 4, the CD (H) + M bytes from 7F05 (H) are initialized, so that these areas are initialized in the order of the unused area and the unused stack area. .

  In addition, initializations 1 and 3 among initializations 1 to 4 are processes performed after the CPU 41a is started and before an interrupt is permitted. On the other hand, the initializations 2 and 4 are processes performed in a state where interrupts are permitted, but interrupts are prohibited during the execution of these initializations 2 and 4. That is, interrupts are always prohibited during the initializations 1-4.

  Next, control when the CPU 41a of the main control unit 41 transmits a command to the effect control board 90 will be described.

  FIG. 14 is a diagram illustrating an example of a command transmitted from the main control unit 41 to the effect control board 90.

  The BET command is a command that can specify the number of medals inserted, that is, the number of medals used to set the bet number. When a medal is inserted, the one-BET switch 5 or the MAX BET switch 6 is operated to set the bet number. Sent when

  The internal winning command is a command that can specify the winning status of the internal winning flag and the type of the internal winning flag that has been established, and is transmitted when the start switch 7 is operated to start the game.

  The reel rotation start command is a command for notifying the start of reel rotation, and is transmitted when rotation of the reels 2L, 2C, and 2R is started.

  The reel stop command is a command that can specify whether the reel to be stopped is the left reel, the middle reel, or the right reel, or the symbol to stop on the corresponding reel, and every time the reel is controlled to stop. Sent.

  The winning determination command is a command that can specify the presence / absence of winning, the type of winning, and the number of medals to be paid out at the time of winning, and is transmitted after all the reels are stopped and the winning determination is performed.

  The payout start command is a command for notifying the start of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is started. The payout end command is a command for notifying the end of payout of medals, and is transmitted when the payout of medals by winning and winning a credit is completed.

  The gaming state command is a command that can specify the gaming state of the next game (whether it is a normal gaming state, a big bonus, a regular bonus, etc.), and is transmitted at the end of the game.

  The standby command is a command indicating a transition to the standby state, and is transmitted when the transition to the standby state is made after a certain time has elapsed without setting the bet amount after the end of one game.

  The initialization command is a command indicating that the gaming state has been initialized, and is transmitted when the setting ends, that is, when the setting change mode ends.

  Of these commands, commands other than the initialization command are generated in accordance with the progress of the game in the game processing described later, temporarily stored in a command queue provided in the special work of the RAM 41c, and transmitted in the timer interrupt processing described above. Is done. The initialization command is temporarily stored in the command queue at the end of the setting change mode, and transmitted in the timer interrupt process described above.

  FIG. 15 is a diagram showing the configuration of the command queue described above. The command queue is provided with an area capable of storing a maximum of 16 commands so that a plurality of commands can be accumulated. In addition, in the area for storing each command, a numerical value (0 to 15) indicating an area number is set in association with each storage area. Further, a transmission pointer indicating the area number of the area where the command to be transmitted next is stored and a storage pointer indicating the area number of the area where the command is to be stored next are set in the command queue. The transmission pointer is incremented by 1 every time an unsent command stored in the command queue is transmitted, and the storage pointer is incremented by 1 when storing the command. The area number indicated by the transmission pointer and the area number of the storage pointer are the same number when transmitted and when all areas of the command queue are full due to an untransmitted command. If an unsent command is stored, the unsent flag is set. Therefore, if the area number indicated by the send pointer is the same as the area number of the stored pointer, the unsent flag is set. If it is, the command queue is shown to be full of unsent commands, and if the unsent flag is not set, it is shown that the unsent commands are empty.

  In this embodiment, the CPU 41a generates an interrupt 3 at an interval of 0.56 ms, and executes a timer interrupt process when the interrupt 3 occurs, so that the timer interrupt process is executed every 0.56 ms. It becomes. Further, as shown in FIG. 16, in the timer interrupt process, timer interrupts 1 to 4 are repeatedly performed, and the processes unique to the timer interrupts 1 to 4 are performed at intervals of 2.24 ms. Will be. Since the command transmission process for transmitting the command stored in the command queue is executed by the timer interrupt 2, the command transmission process is also executed at an interval of 2.24 ms.

  On the other hand, as will be described later, the sub control unit 91 acquires the buffered command in the timer interrupt process (sub) in which the command is executed at intervals of 1.12 ms. For this reason, every time the CPU 41a executes the timer interrupt process, that is, when the command transmission process is performed at an interval of 0.56 ms, there is a possibility that the sub-control unit 91 cannot receive the command normally.

  However, in this embodiment, as described above, the CPU 41a executes the command transmission process at a rate of once every four timer interruption processes, that is, at an interval of 2.24 ms, so that two commands are transmitted continuously. Even in such a case, the commands are transmitted at intervals of at least 2.24 ms, and the commands transmitted continuously can be reliably acquired on the sub-control unit 91 side.

  FIGS. 17A and 17B are timing charts showing an example of command transmission status in this embodiment.

  In this embodiment, as shown in FIG. 17A, a command is generated according to the progress of the game or at the end of the setting and stored in the command queue. When an unsent command stored in the command queue is detected in the command transmission process in timer interrupt 2, a delay time is set, and when the set delay time elapses, the unsent command stored in the command queue Command is sent.

  Specifically, when an unsent command stored in the command queue is detected in the command transmission process, the random number for delay set in the range of 0 to 15 is acquired, and the acquired value is corrected to 2 to 17 The range value (L) is set in the delay counter provided in the special work of the RAM 41c.

  At this time, in the command transmission process in which the delay counter value (L) is set and the command transmission process executed in the timer interrupt 2 thereafter, the delay counter value is decremented by 1, and the delay counter value becomes 0. At that time, the command stored in the command queue is transmitted.

  That is, the command detected in the command transmission process is a time corresponding to a multiple of the command transmission process execution interval (2.24 ms), more specifically, a value obtained by subtracting 1 from the delay counter value (L) acquired at that time ( (L-1) multiplied by the execution interval (2.24 ms) of command transmission processing {(L is a value of 2 to 17, so 2.24 to 35.84 ms} has passed, and then the transmission is performed. .

  Also, in this embodiment, an area capable of storing a plurality of commands is provided in the command queue, and a newly generated command is set in an empty area of the command queue without waiting for transmission of the command stored in the command queue. It is possible to store. That is, a plurality of commands can be accumulated. For this reason, it can be avoided that the progress of the game is stopped due to the delay of the command transmission. Note that this is not the case when the command queue is full of unsent commands.

  In the command storage process, when a plurality of commands are stored in the command queue, these commands are stored in the order of generation, and in the command transmission process, the commands are transmitted in the order stored in the command queue. That is, commands stored in the command queue are always transmitted in the order in which they are generated.

  In addition, when a plurality of unsent commands are stored in the command queue, after the first generated command is transmitted, the unsent commands are stored in the command queue again in the command transmission process to be executed next. If the command is stored, the delay time (delay counter value) of the command is set at that time, and the command is transmitted when the delay time has elapsed. Therefore, when a plurality of commands are stored in the command queue, even if each transmission interval is the shortest (when 2 is determined as the delay counter value), as shown in FIG. .48 ms (2.24 × 2 ms) are transmitted at intervals. In other words, transmission of a new command is prohibited until 4.48 ms elapses after the command is transmitted.

  In the slot machine 1 of the present embodiment, the number of symbols arranged on the reels 2L, 2C, and 2R is 21, and the rotation speed is 750 ms and the rotation is 1 rotation (80 rotations per minute). The time required for each reel 2L, 2C, 2R to move one symbol is 35.7 ms (= 750/21 ms).

  Further, in order to prevent an effect that assists the presentation on the effect control board 90 side, when the CPU 41a transmits a command to the effect control board 90, the maximum delay time is set. It is necessary to set a time longer than the time required for the reels 2L, 2C, and 2R to move one symbol. That is, in this embodiment, it is necessary to set a time of 35.7 ms or more as the maximum delay time.

  On the other hand, in order to prevent a sense of discomfort caused by a large gap between the effect by the sub-control unit 91 mounted on the effect control board 90 and the control by the main control unit 41, the maximum delay time in the command transmission process It is preferable to make the value as short as possible. That is, in the case of the present embodiment, it is preferable that the maximum value of the delay time is set to 35.7 ms or more and as close as possible to 35.7 ms. In the present embodiment, as described above, the delay time in the command transmission process can be set only for a time corresponding to a multiple of the execution interval (2.24 ms) of the command transmission process. Since the minimum value among the values of 35.7 ms or more is 2.24 ms × 16 = 35.84 ms, the optimum maximum delay time is 35.84 ms in the slot machine 1 of the present embodiment.

  For this reason, it is only necessary to set 17 as the upper limit value of the delay counter value (L), and in this way, the maximum value of the delay time is prevented in order to prevent the effect of assisting in the present embodiment. It is possible to set the minimum value among the values that are equal to or greater than the maximum value of the minimum delay time required.

  Further, in this embodiment, as shown in FIG. 17B, a power failure occurs before the delay time {2.24 × (La-1) ms} set when an untransmitted command is detected. When a power interruption interrupt process described later is executed, the command stored in the command queue, the transmission pointer, the value of the stored pointer, the untransmitted flag, and the delay at that point The counter value La ′ is backed up. If untransmitted commands remain after the interruption of power is restored and the interrupt prohibition is canceled, the delay counter value La ′ set at that time becomes zero. Send a send command. That is, at the time of restoration of power interruption, subtraction is resumed from the value La ′ of the delay counter at the time of power interruption, and the delay time {2.24 × (La′−1) ms} has elapsed after the restoration of power interruption. By doing so, an unsent command is sent.

  Next, various control contents executed by the CPU 41a of the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When the reset signal is input from the reset circuit 49, the CPU 41a performs a startup process shown in the flowchart of FIG. Since the reset signal is a signal output when the power is turned on and when the operation of the main control unit 41 is stagnant, the activation process is performed when the CPU 41a is activated when the power is turned on and when the CPU 41a is activated due to a malfunction. This is a process to be performed.

  In the start-up process, first, the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa1), then the voltage drop signal detection data is acquired from the input port, and whether or not the voltage drop signal is input. That is, it is determined whether or not the voltage is stable (Sa2), and when the voltage drop signal is input, the process proceeds to a loop process in which no process is performed.

  If it is determined in step Sa2 that the voltage drop signal is not input, the values of the I register and IY register are initialized (Sa3). By the initialization of the I register and the IY register, the address of the interrupt table to be referred to when an interrupt occurs is set in the I register, and the reference address for referring to the storage area of the RAM 41c is set in the IY register. . These values are fixed values and are always initialized at startup.

  Next, access to the RAM 41c is permitted (Sa4), and it is determined whether or not the setting key switch 37 is in an ON state (Sa5). If the setting key switch 37 is not in the ON state in step Sa5, the RAM parity of all storage areas (including the unused area and the unused stack area) of the RAM 41c is calculated (Sa6). Is determined (Sa7). If the power interruption interrupt processing is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa7, the data stored in the RAM 41c is not normal. The process proceeds to the RAM abnormality error process shown in FIG.

  If the RAM parity is 0 in step Sa7, it is further determined whether or not the destructive diagnosis data is normal (Sa8). If power interruption interrupt processing is performed normally, the data for destruction diagnosis should be set. If the data for destruction diagnosis is not normal in step Sa8 (the data for destruction diagnosis is stored at the time of power interruption. In the case other than 5A (H), the data in the RAM 41c is not normal, and the routine proceeds to the RAM abnormality error processing shown in FIG.

  In the RAM abnormality error process, as shown in FIG. 19, after the RAM abnormality error code is displayed on the game auxiliary display 12 (Sb1), the process proceeds to a loop process in which no process is performed.

  If it is determined in step Sa8 that the destructive diagnosis data is normal, the data in the RAM 41c is normal. Therefore, initialization for initializing the non-saved work, the unused area, and the unused stack area in the RAM 41c is performed. After performing step 3 (Sa9), the destruction diagnosis data is cleared (Sa10). Next, each register is restored to the state before the power interruption (Sa11), the interrupt is permitted (Sa12), and the process executed at the end before the power interruption is returned to.

  If the setting key switch 37 is in the ON state in step Sa5, after executing initialization 1 for initializing all storage areas in the storage area of the RAM 41c except for the used stack area (Sa13), The value stored in the set value work (0 at this time) is corrected to 1 (Sa14). Next, interruption is permitted (Sa15), and the setting change process shown in FIG. 20, that is, the setting change mode is entered (Sa16). After the setting change process is completed, the process proceeds to the game process.

  In the setting change process, as shown in FIG. 20, the setting value stored in the setting value work of the RAM 41c (the value of the setting value work is corrected to 1 before shifting to the setting changing process. Is read out (Sb1).

  Thereafter, the operation enters a state of waiting for detection of the operation of the reset / setting switch 38 and the start switch 7 (Sb2, Sb3). When the operation of the reset / setting switch 38 is detected in the step Sb2, the set value read in the step Sb1. 1 is added (Sb4), and it is determined whether or not the set value after the addition is 7, that is, whether or not the settable range is exceeded (Sb5). If the set value after the addition is not 7, After returning to the state of waiting for detection of the operation of the reset / setting switch 38 and the start switch 7 in the steps Sb2 and Sb3 again, if the set value after addition is 7 in the step Sb5, the set value is corrected to 1 (Sb6 ), The process returns to the detection waiting state for the operation of the reset / setting switch 38 and the start switch 7 in the steps Sb2 and Sb3.

  When the operation of the start switch 7 is detected in step Sb3, the changed set value selected at that time is stored in the set value work of the RAM 41c and the set value is confirmed (Sb7). Wait until the setting key switch 37 is turned off (Sb8). If it is determined in step Sb8 that the setting key switch 37 is OFF, the process returns to the flowchart of FIG. 18, and the process proceeds to the game process.

  As described above, in the startup process, when the setting key switch 37 is not in the ON state, it is stored in the RAM 41c by determining whether or not the RAM parity is 0 and whether or not the destructive diagnosis data is normal. It is determined whether or not the stored data is normal. If the data in the RAM 41c is not normal, the process proceeds to a RAM abnormality error process. In the RAM abnormality error process, after the RAM abnormality error code is displayed on the game auxiliary display 12, the process proceeds to a loop process in which no process is performed, so that the progress of the game is disabled. If the data in the RAM 41c is not normal, the interrupt is not permitted. Therefore, once the process proceeds to the RAM abnormality error process, the setting key switch 37 is activated and the interrupt is permitted. Will not be interrupted even if it is interrupted. That is, the RAM adjustment data is not calculated and stored so that the RAM parity is newly set to 0 in the power interruption interrupt process, and the destruction diagnosis data is not newly set. Even if the game is started, the game cannot be resumed even if the CPU 41a is restarted except when the setting key switch 37 is turned on.

  Once the RAM abnormal error state is entered, the setting key switch 37 is activated and all areas except for the used stack area of the RAM 41c are initialized. The game cannot be progressed until a new set value is selected and set by operating the setting switch 38. In other words, in the state that has shifted to the RAM abnormal error state, the state where the game cannot be progressed is released and the game is resumed on condition that a new set value is selected and set by operating the reset / setting switch 38. Is possible.

  FIG. 21 is a flowchart showing the control contents of the game process executed by the CPU 41a.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a reel stop process (Sd4), a winning determination process (Sd5), a payout process (Sd6), and a game end process (Sd7) ) Are executed in order, and when the game end process is completed, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where the bet number can be set, sets a predetermined number of bets, and executes a process of determining the bet number when the start switch 7 is operated. Further, when a replay winning is generated in the previous game, the same bet number as in the previous game is set.

  In the internal lottery process in step Sd2, a random number for internal lottery is extracted simultaneously with the start of the game by the detection of the start switch 7 in step Sd1, and the winning of each above-described combination is permitted based on the extracted random number value. Process to determine whether or not. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results.

  In the reel rotation process in step Sd3, a process of rotating each reel 2L, 2C, 2R is executed. In this reel rotation process, the operation of the stop switches 8L, 8C, 8R is validated when all the reels 2L, 2C, 2R rotate at a constant speed.

  In the reel stop process in the step of Sd4, the player's operation of the stop switches 8L, 8C, 8R is detected, and the corresponding reels 2L, 2C, 2R corresponding to the fact that the stop condition of each reel 2L, 2C, 2R is satisfied. Execute the process to stop the rotation.

  In the winning determination process in step Sd5, when it is determined in step Sd4 that the rotation of all the reels 2L, 2C, and 2R has been stopped, a winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd6, when it is determined in step Sd5 that a winning has occurred, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd7, a process for setting a gaming state in preparation for the next game is executed. In addition, in the process at the end of the game, initialization 4 is performed to initialize the unused area and the unused stack area of the RAM 41c. In particular, at the end of the big bonus, in addition to the unused area and the unused stack area of the RAM 41c. Perform initialization 2 to initialize the general workpiece.

  22-24 is a flowchart which shows the control content of the internal lottery process which CPU41a performs in the step of Sd2.

  In the internal lottery process, first, a random number acquisition process whose details will be described later is performed (Se1). In this random number acquisition process, a random number value for internal lottery is acquired based on a random number generated by a random number generation circuit (not shown).

  Then, the set value stored in the RAM set value work is read (Se2), and whether or not the read set value is in the range of 1 to 6, that is, the set value stored in the set value work is an appropriate value. If the read set value is not a value in the range of 1 to 6, the process proceeds to the RAM abnormality error process shown in FIG.

  Further, if the set value read in the step of Se3 is in the range of 1 to 6, it is determined whether or not the current gaming state is the normal gaming state (Se4), and if it is the normal gaming state, the normal gaming state Correspondingly, a small combination and a re-playing combination are read out in the order registered in the winning combination table according to gaming state shown in FIG. 6A (Se5). The BET number (the number of bets) set in the step of Sd1 is read, and the common flag of the combination corresponding to the small combination and the re-playing combination in FIG. The setting status is acquired (Se6). As a result, it is determined whether or not a common flag is set for the combination and the BET number (Se7).

  If the common flag is set, the number of determination values stored at the address registered in the role-specific table for the small combination and replay combination in FIG. 6B is acquired for the combination and the number of BETs. (Se8). Then, the process proceeds to Se10. If the common flag is not set, the number of judgment values stored at the address registered in the role-specific table for the small combination and re-playing combination corresponding to the set value read for the combination and the BET number Obtain (Se9). Then, the process proceeds to Se10.

  In the step of Se10, the number of determination values acquired in the step of Se8 or Se9 is added to the random number value for internal lottery, and the result of the addition is used as a new random number value for internal lottery. Here, it is determined whether or not an overflow has occurred when the number of determination values is added to the random number value for internal lottery (Se11). If an overflow occurs, the winning flag for the combination is set in the RAM 41c (Se12). Then, the process proceeds to Se14 shown in FIG.

  If no overflow has occurred in the step of Se11, it is determined whether or not there is a combination that has not been processed yet among the small combination and re-playing combination defined for the normal gaming state (Se13). If there is a combination that has not yet been processed, the process returns to the process of Se5, and the processing continues with the next combination from the small combination and re-game combination determined for the normal gaming state as the processing target. If there is no combination not to be processed, the process proceeds to Se14 shown in FIG.

  In the step of Se14, it is determined whether the regular bonus winning flag or the big bonus winning flag is already set in the RAM 41c in the previous game or not, and it is carried over without winning based on the winning flag (Se14). If the regular bonus winning flag or the big bonus winning flag is already set, the internal lottery process is terminated and the process returns to the flowchart of FIG. If neither the regular bonus winning flag nor the big bonus winning flag is set, the random number for internal lottery is returned to the value before addition, that is, the value acquired in the random number acquisition process of Se1 (Se15).

  Next, with reference to the winning combination table according to gaming state shown in FIG. 6 (a) and the special role combination table shown in FIG. 6 (c), lottery of the normal gaming state registered in the winning combination table according to gaming state The target special combination is read out in the order registered in the special combination table for the special combination (Se16). At this time, if the special role lose is registered in the special role-specific table, the special role loses are also read in the registered order. Furthermore, the setting state of the common flag is acquired from the role-specific table for special roles in FIG. 6C (Se17). As a result, it is determined whether a common flag is set for the combination (Se18).

  If the common flag is set, the number of determination values stored in the address registered in the special role-specific table of FIG. 6C for the role is acquired (Se19). Then, the process proceeds to Se21. If the common flag is not set, the number of determination values stored at the address registered in the special role-specific table corresponding to the set value read for the corresponding role is acquired (Se20). Then, the process proceeds to Se21.

  In the step of Se21, the number of determination values acquired in the step of Se19 or Se20 is added to the random number value for internal lottery, and the result of the addition is used as a new random number value for internal lottery. Here, it is determined whether or not an overflow has occurred when the number of determination values is added to the random number value for internal lottery (Se22). If an overflow has occurred, it is determined whether or not the combination is a loss A or a loss B (Se23). If the winning combination is either lose-A or lose-B, the internal lottery process is terminated and the process returns to the flowchart of FIG. If the winning combination is neither Loss A nor Losing B, the winning flag for the winning combination is set in the RAM 41c (Se24). Then, the internal lottery process is terminated, and the process returns to the flowchart of FIG.

  If no overflow has occurred in the step of Se22, it is determined whether or not there is a combination that has not been processed yet among the special combination (including the special combination lost) determined for the normal gaming state (Se25). If there is a combination that has not yet been processed, the process returns to the processing of Se16, and the processing continues with the next combination from the special combination (including the special combination lost) defined for the normal gaming state as the processing target. If there is no combination not to be processed, the internal lottery process is terminated and the process returns to the flowchart of FIG.

  In the step of Se4, if the current gaming state is not the normal gaming state, it is determined whether or not it is a small role game (Se26). If it is a small role game, corresponding to the small role game, the roles registered in the winning state-specific winning combination table of FIG. 6A are sequentially read (Se27), and the process proceeds to Se29. If it is not a small role game in the step of Se26, it is a regular bonus. Therefore, in correspondence with the regular bonus, the roles registered in the winning combination table according to the gaming state in FIG. 6A are sequentially read (Se28), and Se29. Proceed to the process.

  In the step of Se29, it is determined whether or not the type of the combination read in the steps of Se27 and Se28 is regular bonus (2) or JACIN. In the case of regular bonus (2) or JACIN, it is determined whether the regular bonus (2) winning flag has already been set in the RAM 41c in the previous game or not, and it is carried over without winning based on the winning flag. (Se30). If the type of the read combination is neither regular bonus (2) nor JACIN, the process proceeds to Se31 as it is.

  If the regular bonus (2) winning flag has already been set, the internal lottery process is terminated and the process returns to the flowchart of FIG. 21 (regular bonus (2) and JACIN are the winning combinations by gaming state as described above) In this case, the internal lottery process will be completed because it is registered after the small role. Even if the type of the read combination is regular bonus (2) or JACIN, if the regular bonus (2) winning flag is not set, the process proceeds to Se31.

  In the step of Se31, the BET number (the number of bets) set in the step of Sd1 is further read, and the common flag from the combination table of FIGS. 6B and 6C for the combination and the combination corresponding to the read BET number is read. Get the setting status of. As a result, it is determined whether or not a common flag is set for the combination and the BET number (Se32).

  If the common flag is set, the determination value number stored in the address registered in the role-specific table of FIGS. 6B and 6C is acquired for the role and the BET number (Se33). Then, the process proceeds to Se35. If the common flag is not set, the number of determination values stored at the address registered in the role-specific table of FIGS. 6B and 6C corresponding to the setting value read for the role and the BET number Is acquired (Se34). Then, the process proceeds to Se35.

  In the step of Se35, the number of determination values acquired in the step of Se33 or Se34 is added to the random number value for internal lottery, and the result of addition is used as a new random number value for internal lottery. Here, it is determined whether or not an overflow has occurred when the number of determination values is added to the random number value for internal lottery (Se36). When an overflow occurs, the winning flag for the combination is set in the RAM 41c (Se37). Then, the internal lottery process is terminated, and the process returns to the flowchart of FIG.

  If no overflow has occurred in the step of Se36, it is determined whether or not there is a combination that has not been processed yet among the combinations determined for the gaming state (Se38). If there is a combination that has not yet been processed, the process returns to the processing of Se26, and the processing is continued with the next combination determined for the gaming state as the processing target. If there is no combination not to be processed, the internal lottery process is terminated and the process returns to the flowchart of FIG.

  As described above, in the internal lottery process, it is confirmed whether or not the set value stored in the set value work is an appropriate value. If the set value is not an appropriate value, the above-described RAM abnormality error process is performed. As in the case where it is determined that the data in the RAM 41c is not normal at the time of startup, the RAM abnormal error state is entered and the progress of the game is disabled.

  Also, in the normal gaming state, since the random number for the same internal lottery is drawn separately for the small role and the re-playing role and the special role, the random number to be won in the normal gaming state A small combination (cherry and watermelon in this embodiment) and a special combination (in this embodiment, big bonuses (1) to (3)) may be won simultaneously.

  Next, the random number acquisition process in the step of Se1 will be described in detail based on the flowchart of FIG. In the random number acquisition process, first, interrupts are prohibited (Sf1). Next, a sampling command is output to the sampling circuit 43, the random number generated by the random number generation circuit 42 is latched, and the value of the latched random number is input from the I / O port 41d and extracted. The random number value extracted from the random number generation circuit 42 is stored in the general-purpose register 41GR (Sf2).

  Next, the lower byte value and upper byte value of the random number stored in the general-purpose register 41GR are exchanged with each other using the work area of the RAM 41c (Sf3). Next, the value of the random number stored in the general-purpose register 41GR is ORed with 8080h (Sf4). Further, the upper byte (15th to 8th bits) is shifted downward by 1 bit, and 1 is inserted into the empty 15th bit. At this time, the value stored in the general-purpose register 41GR is acquired as a random number for internal lottery and stored in a predetermined area of the RAM 41c (Sf5). Then, after permitting the interrupt prohibited in the step of Sf1 (Sf6), the random number acquisition process is terminated and the process returns to the flowchart of FIG.

  Next, the control contents of initialization 1 to 4 executed by the CPU 41a in response to the establishment of the initialization condition will be described with reference to the flowcharts of FIGS.

  FIG. 26 is a flowchart showing the control contents of initialization 1 executed by the CPU 41a before the transition to the step of Sa13, ie, the setting change mode.

  In initialization 1, first, the initialization table of the ROM 41b is referred to, and the start address and initialization size registered corresponding to initialization 1 are read (Sg1). A pointer is set to the read start address (7E00 (H)) (Sg2). Next, the size of the unused stack area (M = stack pointer−7FD2 (H)) is calculated (Sg3), and the number of bytes (1DM (H) + M) of the area to be initialized is set (Sg4). Then, a RAM clear process for clearing data from the start address set in Sg2 to the number of bytes set in Sg4 is executed (Sg5). When the RAM clear process is completed, the initialization 1 is completed. Return to.

  FIG. 27 is a flowchart showing the control contents of the RAM clear process executed in step Sg5 of FIG.

  In the RAM clear process, the 1-byte data indicated by the address indicated by the pointer is cleared to 0 (Sh1), and the initialization byte number (the number of bytes set as the area to be initialized) is decremented by 1 (Sh2). Next, it is determined whether or not the number of initialized bytes after subtraction has become 0, that is, whether or not the initialization of all the specified number of bytes has been completed (Sh3). If the number of initialized bytes after subtraction is not 0, the pointer is advanced by 1 (Sh4), the process returns to Sh1, and the processes of Sh1 to 4 are repeated until the number of initialized bytes becomes 0. If the initialization byte count after subtraction is 0 in the step of Sh3, the initialization of all the specified byte counts is completed, so the RAM clear process is terminated and the process returns to the original process. .

  FIG. 28 is a flowchart showing the control content of initialization 2 executed by the CPU 41a at the end of the big bonus in the game end processing of Sd7.

  In the initialization 2, first, interrupts are prohibited (Si1), and then the start address and the initialization size registered corresponding to the initialization 2 are read with reference to the initialization table of the ROM 41b (Si2). In initialization 2, since two start addresses and initialization sizes corresponding to the two start addresses are registered, a pointer is set at the start address (7E28 (H)) of the area to be initialized first among the read start addresses. (Si3), the number of bytes (67 (H)) of the area to be initialized first is set (Si4), and the RAM clear process for clearing data from the start address set in Si3 over the number of bytes set in Si4 (See FIG. 27) is executed (Si5). When the RAM clear process is completed, a pointer is set to the start address (7EBA (H)) of the second area to be initialized among the read start addresses (Si6), and the size of the unused stack area (M = stack pointer− 7FD2 (H)) is calculated (Si7), and the number of bytes (118 (H) + M) of the second area to be initialized is set (Si8). Then, a RAM clear process (see FIG. 27) for clearing data from the start address set in Si6 to the number of bytes set in Si8 is executed (Si9). When the RAM clear process is completed, it is prohibited in the Si1 step. The interrupt that has been made is permitted (Si10), and the process returns to the original process even after the initialization 2 is completed.

  FIG. 29 is a flowchart showing the control contents of initialization 3 executed when the CPU 41a performs the step of Sa9, that is, when the data in the RAM 41c is normal at the time of activation.

  In initialization 3, first, the initialization table of the ROM 41b is referred to, and the start address and initialization size registered corresponding to initialization 3 are read (Sj1). Since two start addresses and initialization sizes corresponding to the two start addresses are registered in initialization 3, a pointer is set at the start address (7EB7 (H)) of the area to be initialized first among the read start addresses. (Sj2), the number of bytes (3 (H)) of the area to be initialized first is set (Sj3), and the RAM clear process for clearing data from the start address set in Sj2 over the number of bytes set in Sj3 (See FIG. 27) is executed (Sj4). When the RAM clear process is completed, a pointer is set to the start address (7F05 (H)) of the second area to be initialized among the read start addresses (Sj5), and the size of the unused stack area (M = stack pointer− 7FD2 (H)) is calculated (Sj6), and the number of bytes (CD (H) + M) of the second area to be initialized is set (Sj7). Then, a RAM clear process (see FIG. 27) for clearing data from the start address set in Sj5 to the number of bytes set in Sj7 is executed (Sj8). When the RAM clear process is completed, initialization 3 is ended. Return to the original process.

  FIG. 30 is a flowchart showing the control contents of initialization 4 executed for each game by the CPU 41a in the game end process of Sd7.

  In the initialization 4, first, interrupts are prohibited (Sk1), and then the start address and the initialization size registered corresponding to the initialization 4 are read with reference to the initialization table of the ROM 41b (Sk2). A pointer is set to the read start address (7F05 (H)) (Sk3). Next, the size of the unused stack area (M = stack pointer−7FD2 (H)) is calculated (Sk4), and the number of bytes (CD (H) + M) of the area to be initialized is set (Sk5). Then, a RAM clear process (see FIG. 27) for clearing data from the start address set in Sk3 over the number of bytes set in Sk5 is executed (Sk6). When the RAM clear process is completed, it is prohibited in the Sk1 step. The interrupt is permitted (Sk7), and the process returns to the original process even after the initialization 4 is completed.

  FIGS. 31 and 32 are flowcharts showing the control contents of the timer interrupt process executed by the CPU 41a by interrupting the setting change process or the game process in response to the occurrence of the interrupt 3, that is, at an interval of 0.56 ms.

  In the timer interrupt process, interrupts are first prohibited (Sm1). That is, the execution of another interrupt process during the execution of the timer interrupt process is prohibited. Then, the register in use is saved in the stack area (Sm2).

  Next, the branch counter for identifying the timer interrupt to be executed in the timer interrupt process is advanced by 1 from the four types of timer interrupts 1 to 4 (Sm3). In step Sm3, 1 is added when the branch counter value is 0 to 2, and is updated to 0 when the counter value is 3. That is, the branch counter value loops in the order of 0 → 1 → 2 → 3 → 0... Each time the timer interrupt process is executed.

  Next, referring to the counter value for branching, it is determined whether it is 2 or 3, ie, timer interrupt 3 or timer interrupt 4 (Sm4), and if it is not timer interrupt 3 or timer interrupt 4, that is, timer interrupt In the case of 1 or timer interrupt 2, it is checked whether the reel motors 32L, 32C, 32R are started or whether they are rotating at a constant speed, and whether the reel motors 32L, 32C, 32R are started or are rotating at a constant speed. For example, the motor phase signal output process for outputting the phase signal data changed in the motor step process of Sm8 described later and the phase signal data changed in the final stop process of Sm23 described later is executed (Sm5).

  Next, it is determined whether or not it is 1 (ie, timer interrupt 2) by referring to the minute counter value (Sm6). If it is not timer interrupt 2 (ie, timer interrupt 1), the reel motor Reel start processing (Sm7) for controlling the step time interval when starting 32L, 32C, 32R, motor step processing (Sm8) for changing phase signal data of the reel motors 32L, 32C, 32R, reel motors 32L, 32C After the stop of 32R, the motor phase signal standby process (Sm9) for changing the phase signal to one-phase excitation after a certain time has been sequentially executed, and then the register saved in the stack area in Sm2 is restored (Sm20). The interrupt prohibited in the step is permitted (Sm21), and the process returns to the state before the interrupt.

  In the case of timer interrupt 2 in step Sm6, LED dynamic display processing for dynamically lighting various indicators (Sm10), control signal output processing for outputting data such as lighting signals of various LEDs to an output port, etc. (Sm11), random number update process for updating various software random numbers (Sm12), time counter update process for updating various time counters (Sm13), command transmission for transmitting commands stored in the command queue to the effect control board 90 After sequentially executing the process (Sm14) and the external output signal update process (Sm15) for updating the external output signal, the register saved in the stack area in Sm2 is restored (Sm20), and the interrupt prohibited in the step of Sm1 is permitted. Then (Sm21), the process returns to the state before the interruption.

  If it is timer interrupt 3 or timer interrupt 4 in step Sm4, it is further determined whether it is 3 by referring to the counter value for wake-up, that is, timer interrupt 4 (Sm16). If it is not interrupt 4, that is, timer interrupt 3, port input processing (Sm17) for inputting detection data of various switches from the input port, passing the origin of reels 2L, 2C, 2R during constant speed rotation After the origin passing process (Sm18) to be checked and the switch input determination process (Sm19) for determining whether or not these various switches satisfy the detection condition based on the detection signals of the various switches, the stack is stacked in Sm2. The register saved in the area is restored (Sm20), the interrupt prohibited in the step of Sm1 is permitted (Sm21), and the process before the interruption is returned.

  If the timer interrupt is 4 in the step of Sm17, the stop position is determined when the detection of the effective stop switches 8L, 8C, and 8R is determined, and the number of steps after which the stop is calculated is calculated. The number of steps until the stop calculated in the switch process (Sm22) and the stop switch process is counted, and when it is time to stop, the stop process (Sm23) starts the brake by the two-phase excitation, and the brake is started in the stop process. After executing a final stop process (Sm24) for three-phase excitation after a certain period of time, the registers saved in the stack area in Sm2 are restored (Sm20), and the interrupts prohibited in the Sm1 step are permitted ( Sm21), the process returns to the state before the interruption.

  FIG. 33 is a flowchart showing the control content of the command storage process executed when the CPU 41a generates a command according to the progress of the game and stores it in the command queue.

  The command transmitted by the CPU 41a is composed of 2 bytes. The first byte represents MODE (command classification), and the second byte represents EXT (command content). Further, the form of the command shown in this embodiment is an example, and other data forms may be used. In this embodiment, the command is composed of a 2-byte signal, but these commands may be composed of a 1-byte signal or a 3-byte or more signal.

  In the command storing process, first, MODE and EXT composing a command to be transmitted are generated (Sn1). Then, after storing the generated command in the area of the area number indicated by the storage pointer, that is, in the empty area of the command queue (Sn2), 1 is added to the area number indicated by the storage pointer (Sn3). Since the area number is a numerical value in the range of 0 to 15, when the serial number indicated by the storage pointer is 15, 1 is added and updated to 0 when it becomes 16.

  Next, it is confirmed whether or not the untransmitted flag is set (Sn4). If the untransmitted flag is not set, the untransmitted flag is set (Sn5). Then, it is checked whether the area number indicated by the storage pointer matches the area number indicated by the transmission pointer, that is, whether all areas of the command queue are filled with unsent commands. In this case, an unsent command stored in the command queue is transmitted, and waits until the area number indicated by the storage pointer does not match the area number indicated by the transmission pointer, and the area number indicated by the storage pointer and the transmission pointer are waited. The command storing process is terminated when the area number indicated by (2) no longer matches, that is, when the command queue becomes empty (Sn6).

  FIG. 34 is a flowchart showing the control content of the command transmission process executed by the CPU 41a in the timer interrupt 2 of the timer interrupt process described above.

  In the command transmission process, first, it is determined whether or not the delay counter for setting the transmission delay time of the command is greater than 0, that is, whether or not the command is waiting for transmission of the command stored in the command queue (Sp1). ).

  If it is not waiting for transmission in Sp1, it is determined whether or not the above-mentioned untransmitted flag indicating that an untransmitted command is stored in the command queue is set (Sp2). If the untransmitted flag is not set in Sp2, the command to be transmitted is not stored because the command to be transmitted is not stored.

  Further, when the unsent flag is set in Sp2, that is, when an unsent command is stored in the command queue, a random number value randomly generated in the range of 0 to 15 is acquired from the random number counter ( Sp3), 2 is added to the obtained random number value to correct it to a value of 2 to 17, and set in the delay counter (Sp4).

  Next, 1 is subtracted from the delay counter value (Sp5), whether or not the delay counter value is larger than 0, that is, whether or not the transmission delay time of the command stored in the area indicated by the transmission pointer value of the command queue has elapsed, (Sp6), and if the delay counter value is greater than 0, that is, if the transmission delay time has not elapsed, the command transmission process is terminated.

  If the delay counter value is 0 in the step Sp6, that is, if the transmission delay time has elapsed, the command stored in the area indicated by the transmission pointer value in the command queue is transmitted to the effect control board 90 ( Sp7-Sp10). Specifically, first, MODE composing the command stored in the area indicated by the transmission pointer value of the command queue is output (Sp7), and a strobe signal for notifying the sub-control unit 91 that the command has been output is output for a predetermined time. (In this embodiment, 10 μs) is output (Sp8). Then, EXT constituting the command stored in the area indicated by the transmission pointer value is output (Sp9), and the strobe signal is output again for a predetermined time (Sp10).

  Next, 1 is added to the area number indicated by the transmission pointer (Sp11). Since the area number is a numerical value in the range of 0 to 15, when the area number indicated by the transmission pointer is 15, 1 is added and when it becomes 16, the area number is updated to 0.

  Next, it is confirmed whether or not the area number indicated by the transmission pointer matches the serial number indicated by the storage pointer, that is, whether or not the command to be transmitted is stored in the command queue (Sp12). Then, the non-transmission flag is cleared and the command transmission process is terminated (Sp13).

  If it is determined in Sp1 that the delay counter value is greater than 0, that is, it is in a transmission waiting state, the process proceeds to Sp5, and if the transmission delay time has elapsed, the command queue transmission pointer value indicates the area. The stored command is transmitted, and when an untransmitted command becomes empty, processing such as clearing an untransmitted flag is performed (Sp5 to Sp13), and the command transmission processing is terminated.

  FIG. 35 shows control of power interruption interrupt processing executed by the CPU 41a interrupting and executing setting change processing or game processing in response to the occurrence of interrupt 2, that is, when a voltage drop signal from the power interruption detection circuit 48 is input. It is a flowchart which shows the content.

  In the power interruption interruption process, first, interruption is prohibited (Sq1). That is, other interrupt processing is prohibited from being executed at the start of the power interruption interrupt processing. Next, all registers that may be in use are saved in the stack area (Sq2). Although the values of the I register and IY register described above are used, they are not stored here because the same fixed value is always set with the initialization at the time of power-on.

  Next, the detection data of the voltage drop signal is acquired from the input port, and it is determined whether or not the voltage drop signal is input (Sq3). At this time, if the voltage drop signal is not input, the register saved in the stack area in Sq2 is restored (Sq4), the interrupt prohibited in the step of Sq1 is permitted (Sq5), and the process before the interrupt is performed. Return.

  If a voltage drop signal is input in step Sq3, destruction diagnosis data (5A (H) in this embodiment) is set (Sq6), and all output ports are initialized (Sq7). . Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 41c becomes 0 (Sq8), and access to the RAM 41c is performed. It is prohibited (Sq9).

  Then, except for the determination of whether or not the voltage drop signal is input (Sq10, where Sq10 is the same processing as Sq3), the processing enters a loop processing in which no processing is performed. That is, when the voltage decreases as it is, the operation is stopped internally. Therefore, the CPU 41a reliably stops operation when the power is interrupted. Further, in this loop processing, when the voltage recovers and the voltage drop signal is not input, the above-described startup processing is executed, and if the RAM parity is 0 and the destructive diagnosis data is normal, the original processing is performed. It will return to.

  In this embodiment, after the access to the RAM 41c is prohibited, the output state of the voltage drop signal is monitored, and when the voltage drop signal is not input, it is determined that the voltage is restored, and the process proceeds to the startup process. However, no processing is performed in the loop processing, and the voltage is recovered while the loop processing is being performed, and the process proceeds to the start-up processing based on the input of the reset signal from the reset circuit 49. You may make it do.

  Next, various control contents executed by the CPU 91a of the sub-control unit 91 mounted on the effect control board 90 will be described based on the flowcharts of FIGS.

  When the reset signal is input from the reset circuit 95, the sub control unit 91 performs the startup process (sub) shown in FIG.

  In the startup process (sub), the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sr1), and then access to the RAM 91c is permitted (Sr2). Then, the RAM parity of all the storage areas of the RAM 91c is calculated (Sr3), and it is determined whether or not the RAM parity is 0 (Sr4). If the data in the RAM 91c is normal, the RAM parity should be 0. If the RAM parity is 0 in the Sr4 step, the data stored in the RAM 91c is normal. (Sr5), interrupt is permitted (Sr7), and the process proceeds to loop processing. That is, it returns to the control state at the time of power interruption. If the RAM parity is not 0 in step Sr4, the data stored in the RAM 91c is not normal. Therefore, after the RAM 91c is initialized (Sr6), interrupts are permitted (Sr7) and the loop processing is performed. Transition.

  FIG. 37 is a flowchart showing the control content of the command reception interrupt process executed by the CPU 91a by interrupting and executing another process based on the detection of the strobe signal output from the game control board 40. The strobe signal is a signal input to the interrupt terminal of the sub-control unit 91 at the time of command transmission.

  In the command reception interrupt process, first, interrupts are prohibited (Ss1), and the register is saved in the RAM 91c (Ss2). Then, the command transmission line detection data from the input port, that is, the MODE output from the game control board 40 is acquired (Ss3), and the process waits until the strobe signal is detected again (Ss4).

  Next, when the strobe signal is detected again, the detection data of the command transmission line from the input port, that is, the EXT output from the game control board 40 is acquired again (Ss5). Then, a command composed of MODE and EXT is stored in a buffer provided in the RAM 91c (Ss6). Then, the saved register is restored in Ss2 (Ss7), the interrupt prohibited in Ss1 is permitted (Ss8), and the state before the interruption is restored.

  FIG. 38 is a flowchart showing the control contents of timer interrupt processing (sub) executed by the CPU 91a at intervals of 1.12 ms based on the count of the internal clock.

  In the timer interrupt process (sub), first, it is determined whether or not a command is stored in the buffer (St1). If stored, the command is acquired from the buffer (St2), and it is determined whether or not the acquired command is an initialization command (St3). If the acquired command is an initialization command, the RAM 91c is initialized (St7), and then the process proceeds to St8.

  In addition, in St3, when it is determined that the acquired command is not an initialization command, an effect setting process for setting the control content of the peripheral device for effect according to the content of the command (St4), and the set control content Then, an effect control process for controlling the peripheral device for effects is performed (St5), an effect control according to the command is executed, a counter update process for updating various counters is performed (St6), and then the process proceeds to St8.

  In step St8, the RAM parity adjustment is performed so that the exclusive OR of all the storage areas of the RAM 91c becomes 0 so that it can be confirmed whether or not the content of the data backed up in the RAM 91c at the time of startup is normal. Data is calculated and set, and the timer interrupt process (sub) ends. That is, the CPU 91a does not set the RAM parity adjustment data when the power interruption is detected like the CPU 41a of the main control unit 41, but the RAM parity adjustment data for each timer interrupt process (sub) that is periodically executed. Even if the power is cut off, it is possible to determine whether or not the content of the data backed up in the RAM 91c at the time of recovery is normal.

  Next, operation states of the CPU 41a of the main control unit 41 and the CPU 91a of the sub control unit 91 during a power failure will be described based on the timing chart of FIG.

  First, the power interruption detection circuit 48 outputs a voltage drop signal to the main control unit 41 when a + 25V DC voltage (hereinafter referred to as a power supply monitoring voltage) becomes + 18V or less (ta1). If the CPU 41a is executing a setting change process or a game process when the voltage drop signal is input, the CPU 41a interrupts the game process to execute the power interruption interrupt process. When a voltage drop signal is input simultaneously with the request for timer interrupt processing (interrupt 3), the power interruption interrupt processing is executed with priority over the power interruption interrupt processing over the timer interrupt processing. Further, when the voltage drop signal is input while the CPU 41a is executing the timer interrupt process, the power interruption interrupt process is executed when the timer interrupt process being executed is completed (ta2). In this embodiment, the CPU 41a is driven after the power monitoring voltage becomes + 18V at which the voltage drop signal is output, rather than the sum of the maximum time required for the timer interrupt process and the maximum time required for the power interruption interrupt process. Since the time to drop to the voltage (+ 5V) (ta3) that can be generated is longer, even when the CPU 41a is executing the timer interrupt process at the time of a power failure, it guarantees the time when the power interrupt process can be performed reliably It has come to be.

  Further, + 12V (VCC), which is the source of the power supply voltage (+5 V (VCC)) of the sub-control unit 91, is delayed in voltage drop by the capacitor 309 mounted on the power supply board 100 even during a power failure. The CPU 91a is buffered until a time sufficient for buffering the command transmitted in the timer interrupt process at the time of the power failure and acquiring the buffered command in the subsequent timer interrupt process (sub) (ta4). Since the voltage (+ 7V) that can be driven is maintained, even when the command is buffered from the game control board 40 at the time of a power failure, the time for reliably acquiring the command and reflecting it as data to be backed up in the RAM 91c It has come to be secured. In this embodiment, a voltage that can drive the CPU 91a is maintained until a time of 20 ms or more has elapsed from the time when the power monitoring voltage becomes +18 V or less. It is only necessary to maintain a voltage capable of driving the CPU 91a over a time equal to or longer than the execution interval of the CPU 2 (a time sufficient for the CPU 91a to reliably acquire a command).

  As described above, in the slot machine 1 of the present embodiment, the unused area in the RAM 41c of the main control unit 41 is initialized for each game, so that the malicious program is stored using the unused area of the RAM 41c. However, it is possible to prevent the unauthorized program from being resident.

  Further, in this embodiment, the unused stack area in the stack area is initialized for each game in addition to the unused area in the RAM 41c, so that all the unused areas in the RAM 41c at that time are stored for each game. For example, even if it is attempted to store an illegal program using an unused stack area without using an unused area of the RAM 41c, there is no room for the illegal program to reside. Therefore, it is possible to more reliably prevent the unauthorized program from being resident, and for example, to add unauthorized data (such as an address specified by the unauthorized program) to the unused stack area, causing the microcomputer to malfunction when the data is restored. By rewriting the register to an illegal one, the original program Fraud can be prevented that would carry out the operation different from the. Further, by storing illegal data in the unused stack area, an area where the saved data should be stored can be compressed, the stack area overflows, and the micro that configures the main control unit 41 is stored. Problems such as the computer running away can be prevented.

  In this embodiment, the initialization area 4 for initializing the unused area and the unused stack area of the RAM 41c is executed every game at the end of the game, so that the unused area and the unused stack area of the RAM 41c are changed for each game. If the unused area and / or the unused stack area of the RAM 41c is initialized at least once per game, but the unused area and / or the unused stack area of the RAM 41c is initialized. The timing for performing the conversion may be any timing during one game. For example, the unused area and / or the unused stack area of the RAM 41c may be initialized at the start of the game or when a process that is always executed for each game is executed. It may be one that performs the conversion.

  Also, before the start of setting (before the transition to the setting change mode), at the end of the big bonus, when the data in the RAM 41c is not destroyed at the time of turning on the power, when the four initialization conditions at the end of one game are satisfied. In addition, four types of initializations 1 to 4 having different regions to be initialized are performed in accordance with each initialization condition, and an unused region in the RAM 41c is always used regardless of which of the four types of initialization conditions is satisfied. In addition, since the unused stack area in the stack area is initialized, it is possible to more reliably prevent the illegal program from being resident.

  The ROM 41b of the main control unit 41 registers the start address of the area to be initialized and the initialization size indicating the size of the area to be initialized, corresponding to the initializations 1 to 4, and the CPU 41a stores the RAM 41c. When initialization is performed, the initialization table is referred to, the start address and initialization size corresponding to any of initializations 1 to 4 are obtained according to the initialization condition, and a pointer is set to the start address. The initialization size is set (if the initialization size includes the size of the unused stack area, the size of the unused stack area (stack pointer-7FD2 (H)) is calculated and the initialization size is set. ). Then, the area of the address corresponding to each byte from the initialization address where the pointer is set is cleared to 0, and each time the byte is cleared, the initialization size is decremented by 1 and the pointer is advanced by 1. Run until zero. That is, when the CPU 41a initializes the RAM 41c, it does not initialize each area according to the initialization condition, but initializes an area of a specified size from a specified address.

  Therefore, by setting only the start address corresponding to the type of initialization condition and the size of the area initialized at that time in the initialization table of the ROM 41b, the initialization end corresponding to the type of initialization condition is completed. The area corresponding to the type of initialization condition can be initialized without individually setting addresses, and multiple types of initialization can be performed using a common process (RAM initialization process). The capacity of the program for performing multiple types of initialization can be reduced. Further, in the RAM initialization process, the end of the process is determined only by determining whether or not the initialization size is 0. Therefore, the end of the process is determined by comparing the address of the currently initialized byte with the end address. Compared to the case, the processing load can be greatly reduced.

  Further, interrupts are always prohibited during the initializations 1 to 4, and a voltage drop signal is output from the power interruption detection circuit 48 while the data stored in the RAM 41c is being initialized. Even if it is input, the power interruption interrupt process is not executed until the initialization is completed. For example, the power interruption interrupt process is performed at a stage before the initialization is completely completed. It is possible to prevent problems such as initialization data and non-initialization data mixed among power data, and a normal return to the control state before power interruption cannot be performed at the time of recovery.

  Further, in the power interruption processing, the RAM parity adjustment data is calculated and stored so that the RAM parity based on all data including the unused area and the unused stack area of the RAM 41c becomes 0, and at the time of recovery, the RAM 41c is restored. It is determined whether or not the RAM parity calculated based on the data stored in all the areas including the unused area and the unused stack area is 0. If the RAM parity is not 0, a RAM abnormal error Since the game is impossible until the initialization 1 for initializing all the areas except the used stack area of the RAM 41c is performed, the game is impossible. When an illegal program is stored in the unused area and / or unused stack area of the RAM 41c It can be initialized to discover the malware.

  In the present embodiment, when an abnormality occurs in the data stored in the RAM 41c, the RAM is controlled to an error error state, the game is disabled, and the RAM error error state is once controlled. If the setting change mode is entered and a setting value is not newly selected / set based on the setting change operation, the state where the progress of the game is disabled is not released. That is, even if an abnormality occurs in the data stored in the RAM 41c, it is not the setting value automatically set by the slot machine, but the setting value selected and set based on the setting change operation (generally, the setting change Since the operation is performed by an employee of the amusement store, it is ensured that the game is performed based on the setting value selected by the amusement store side), so that the fairness of the game can be achieved.

  Further, in this embodiment, when determining whether or not winning is allowed in the internal lottery process, the set value stored in the set value work of the RAM 41c is an appropriate value (a value in the range of 1 to 6). If not, it is not determined whether or not the winning is allowed with the probability based on the default setting value (for example, setting 1), but in this case as well, it is controlled to the RAM abnormal error state, and the progress of the game is progressed. If the game is disabled, the mode is changed to the setting change mode, and the setting value is not newly selected / set based on the setting change operation, the state where the progress of the game is disabled is not released. In other words, even when it is not possible to properly determine whether or not winning is allowed in the internal lottery process, the game may be played based on the setting value selected and set based on the setting change operation. Since it is secured, the fairness of the game can be achieved.

  Further, the data stored in the RAM 41c is abnormal in most cases when the control cannot be continued due to a malfunction such as a power failure or the CPU 41a running out of control. For this reason, in this embodiment, since it is determined whether or not the data is normal only when the CPU 41a is activated after recovering from these states, it is determined whether or not the data stored in the RAM 41c is normal. The determination can be made only in a situation where there is a high possibility that an abnormality has occurred in the data. That is, in a situation where there is a low possibility that an abnormality has occurred in the data, it is not necessary to perform the determination, and the load on the CPU 41a can be reduced.

  In the present embodiment, the RAM parity adjustment data is calculated and stored so that the RAM parity based on all the data in the RAM 41c becomes 0 in the power interruption processing, and is stored in all areas in the RAM 41c at the time of restoration. By determining whether or not the RAM parity calculated based on the stored data is 0, it is determined whether or not the data in the RAM 41c is normal. Therefore, the determination can be performed accurately and easily. .

  Further, in this embodiment, in the power interruption processing, before the RAM parity adjustment data is calculated, destructive diagnosis data (in this embodiment, 5A (H)) in which any bit is 1 is set to a predetermined value. At the time of recovery, in addition to determining whether or not the RAM parity is 0, it is also determined whether or not the data for destructive diagnosis is stored normally, and the RAM parity is 0 and the data is destroyed It is determined that the data in the RAM 41c is normal on the condition that the diagnostic data is also normal. Even if the data in the RAM 41c is not normal, if 00 (H) is stored in all the areas, it is determined as normal by the RAM parity determination at the time of startup. After storing the destructive diagnostic data with the bit set to 1, calculate and store the RAM parity adjustment data, and check the destructive diagnostic data in addition to determining the RAM parity at the time of recovery. Even when 00 (H) is stored in all areas at the time of recovery and the RAM parity is determined to be normal, the destruction diagnosis data does not match the value stored at the time of a power failure and is determined to be abnormal. Therefore, the abnormality of the RAM 41c can be determined more accurately.

  Further, in this embodiment, when an abnormality occurs in the data in the RAM 41c and the progress of the game is disabled, a setting value changing operation as a condition for canceling the disabled state of the game is effective. As a result of the transition to the setting change mode (setting change processing), all the areas except the used stack area of the RAM 41c are initialized, so that the initial data of the RAM 41c due to the occurrence of an abnormality And initialization of data associated with selection / setting of set values can be performed at once, and unnecessary processing can be omitted. Further, when the CPU 41a is activated, it is determined whether or not the setting key switch 37 is ON before determining whether the data in the RAM 41c is normal. At that time, the setting key switch 37 is ON. If it is determined that there is, the determination as to whether the data in the RAM 41c is normal is not performed, and the mode shifts to the setting change mode, where a new setting value is selected and set. It can be omitted.

  In this embodiment, initialization 1 for initializing all areas except the used stack area of the RAM 41c is performed before shifting to the setting change process. However, along with the shift to the setting change process. Initialization 1 may be performed, for example, after the setting change process is completed, or may be performed when the setting value is confirmed in the setting change process. In this case, since the inconvenience arises when the determined set value is changed, in initialization 1, all areas except the used stack area and the set value work of the RAM 41c are initialized. Become.

  Also, in this embodiment, once controlled to the RAM abnormal error state, the game is disabled until the setting change process is performed. The initialization is performed to initialize all areas except the used stack area of the RAM 41c, and the setting value is set to an initial value (for example, the setting value 1). May be resumed.

  Further, in this embodiment, when determining whether or not winning is allowed in the internal lottery process, the set value stored in the set value work of the RAM 41c is an appropriate value (a value in the range of 1 to 6). If not, the RAM abnormal error state is also controlled in this case, but the setting value stored in the setting value work of the RAM 41c is not an appropriate value (a value in the range of 1 to 6). In this case, it may be determined whether or not winning is allowed with a probability based on an initial value of the set value (for example, set value 1).

  In this embodiment, the CPU 41a transmits a command corresponding to the progress of the game to the effect control board 90, and the sub-control unit 91 mounted on the effect control board 90 receives the command transmitted from the game control board 40. Since the CPU 41a does not need to control the presentation only by sending a command, the processing load on the CPU 41a can be reduced and the presentation can be made various. .

  Further, a command transmission line for transmitting a command from the game control board 40 to the effect control board 90 is connected between the game control board 40 and the effect control board 90 via the effect relay board 80, and the game control board Since the production control board 90 is not directly connected to 40, it is possible to prevent an illegal signal from being input from the command transmission line to the CPU 41a from the outside and affecting the control of the game.

  The CPU 41a sets the value of the delay counter at random when transmitting the command, and transmits the command when the delay counter value becomes 0, and the transmission timing of the command is a predetermined time. In the range (2.24 to 35.84 ms), the effect control board 90 side performs an effect that assists the eye based on the reception timing of the command transmitted from the game control board 40. Can be prevented

  In this embodiment, the command transmission timing is delayed in the range of 2.24 to 35.84 ms. At least the symbol of the reels 2L, 2C, and 2R has a maximum delay time of 1 symbol. Anything that exceeds the time required for movement is sufficient.

  Even when a plurality of commands are transmitted continuously, these commands are stored in the command queue provided in the RAM 41c in the order in which they are generated, and each command is transmitted in its generation order, that is, the command is originally transmitted. Since it is transmitted in the order of power, the production control board 90 side can perform the production by grasping the control state of the CPU 41a in the exact order, and the player feels uncomfortable due to a discrepancy in the production order. Can be prevented.

  In addition, when a power failure occurs in a state where command transmission is delayed, that is, in a command transmission waiting state, and a power interruption interrupt process is performed, the command, transmission pointer, and storage pointer stored in the command queue All of the delay counter values are backed up in the RAM 41c, and at the time of recovery, command transmission control is performed in the state of the command, transmission pointer, storage pointer, and delay counter value stored in the command queue backed up in the RAM 41c. Thus, even if a power failure occurs while waiting for command transmission, the command transmission control can be resumed from the power failure state at the time of recovery, so that the control of the CPU 41a can be simplified.

  In this embodiment, when a power failure occurs while waiting for transmission of a command transmission command, and the power failure is restored, command transmission control is resumed from the state at the time of the power failure. When a power failure occurs while waiting for command transmission, the delay counter value is newly reset after the recovery, and the delay time based on the reset delay counter value has been reset. Sometimes it may be sent. In other words, if there is a command waiting to be transmitted at the time of recovery, the command may be transmitted when a newly set delay time elapses at the time of recovery. However, the command transmission timing can be changed reliably.

  Further, in this embodiment, when the voltage drop signal is input to the trigger terminal CLK / TRG, the CPU 41a interrupts the process being executed and executes the power interruption process. In the process including the process for setting the data for destructive diagnosis and the process for calculating and setting the data for adjusting the RAM parity, the process for making it possible to determine whether the data in the RAM 41c is normal at the time of recovery or the initial setting of the output port Before performing the conversion, it is determined whether or not a voltage drop signal is input to the signal input terminal DATA. If the voltage drop signal is also input to the signal input terminal DATA, the data in the RAM 41c is normal at the time of recovery. If the voltage drop signal is not input to the signal input terminal DATA, the original processing is performed. It is adapted to return.

  That is, the voltage drop signal is input to the two systems of the input unit to the main control unit 41, and the CPU 41a does not perform the power interruption interrupt process when the voltage drop signal is input to one of the input units. Before the process for enabling determination of whether the data in the RAM 41c is normal, the initialization of the output port, or the like is performed, it is determined again whether or not the voltage drop signal is input to the other input unit. These processes are executed only when a voltage drop signal is also input to the input section of this, and when power failure is detected by mistake, whether or not the data in the RAM 41c is normal at the time of recovery is detected. Since it is possible to prevent the process for enabling the determination and the process such as the initialization of the output port from being performed, the control of the CPU 41a may be interrupted for an unnecessarily long time due to erroneous detection of power interruption. More than necessary Possible to prevent the load is applied to.

  In the present embodiment, the voltage monitored by the power interruption detection circuit 48 and the power supply voltage for driving the electrical components connected to the power supply board 100, the game control board 40, and the effect control board 90 are separately provided. Since a stable voltage is monitored by the power interruption detection circuit 48 as compared with the power supply voltage that tends to drop depending on the driving conditions of these electrical components, It is possible to prevent a malfunction such as a voltage drop signal being output along with the voltage drop and an electric interruption interrupt process being performed.

  In addition, other interrupts are prohibited during power interruption interrupt processing and timer interrupt processing. For example, when a voltage drop signal is input during execution of timer interrupt processing. However, double interruptions do not occur, and it is possible to prevent the processing load of the CPU 41a from increasing and data consistency from being lost. In particular, even if a voltage drop signal is input during the transmission of a command, no interruption occurs and the transmission of the command is not hindered, and the transmission can be completed normally before the CPU 41a stops driving. .

  Also, if the interrupt timing for power interruption interrupt processing and the interrupt timing for timer interrupt processing are simultaneous, that is, if interrupt 2 and interrupt 3 occur simultaneously, priority is given to interrupt 2 In addition to executing the interruption interrupt process, if an interruption 2 occurs during the execution of the timer interruption process, the interruption interruption process is executed after the timer interruption process ends. Therefore, the power interruption interrupt process is performed as early as possible while preventing multiple interruptions, so that the power interruption interrupt process can be reliably performed before the driving of the CPU 41a is stopped.

  Further, the CPU 41a can execute four types of interrupts of interrupts 1 to 4, and when interrupts 1 and 4 that are set to unused are generated, the CPU 41a immediately returns to the original process. The unused interrupt processing to be executed is executed. For this reason, even if unused interrupts 1 and 4 occur, the process immediately returns to the process before the interrupt. Therefore, even if an unused interrupt occurs due to noise or the like, the CPU 41a runs out of control. It is possible to prevent such troubles.

  In this embodiment, the CPU 91a of the sub-control unit 91 calculates and sets the RAM parity adjustment data every time the timer interrupt process is executed. In other words, the process for making it possible to determine whether or not the content of the data backed up in the RAM 91c at the time of restoration is performed periodically without depending on the command transmitted from the game control board 40. Even when the command is transmitted with a delay, the CPU 91a does not stop before calculating and setting the RAM parity adjustment data due to the delayed transmission of the command. The CPU 91a can accurately determine whether the data backed up in the RAM 91c is normal.

  In this embodiment, after the CPU 41a transmits a command, the transmission of a new command is prohibited for at least 4.48 ms, and the CPU 91a of the sub-control unit 91 receives the command reliably. In addition, the time for backing up the received command to the RAM 91c can be secured. In this embodiment, 4.48 ms is applied as a time during which transmission of a new command is prohibited, but at least a time sufficient for the CPU 91a to receive the command and to back up the received command to the RAM 91c. If so, a time shorter than 4.48 ms (eg, 2.24 ms) may be applied.

  In this embodiment, +12 V (VCC), which is the source of the power supply voltage {+5 V (VCC)} of the sub-control unit 91, is delayed in voltage drop by the capacitor 309 mounted on the power supply board 100 even during a power failure. At least in the event of a power failure, the CPU 91a of the sub-control unit 91 can be driven until a sufficient time (20 ms in this embodiment) has passed for the CPU 91a to reliably receive the command transmitted in the timer interrupt process. Even if a power failure occurs during command transmission, the CPU 91a can reliably receive the command transmitted at the time of power failure before the drive stops, Longer than the interval at which the command received by the CPU 91a is backed up (timer interrupt processing (sub) execution interval), Since a voltage capable driving the PU91a (+ 7V) is maintained can be reliably back the received command to the RAM 91c.

  Further, in the slot machine 1 of the present embodiment, as a type of winning combination, a small role accompanied by paying out medals, a re-playing role that does not require consumption of medals for the number of bets in the next game, and a transition of the gaming state. A special role is provided. The special role is accompanied by a transition of the gaming state and depends on the gaming state at that time, so it cannot be said to be a basic role. The playability of slot machines is not just playing a game, but the player earns medals based on the game results, so the small role that involves paying out medals by winning a prize is the most basic role. It can be said. Here, there are JAC, cherry, watermelon, and bell as types of small roles, but in addition to JAC that wins with a small probability in the regular bonus, it is determined as the types of winning combinations in any gaming state. ing. In this way, by defining the basic small combination as a winning combination regardless of the gaming state, the gameability becomes easy for the player to understand.

  When a big bonus is won in the normal gaming state, the gaming state is shifted to a big bonus that wins JACIN with a transition to a regular bonus with a relatively high probability (winning because there is no missing). The big bonus is ended when the total number of medals paid out to the player in the big bonus reaches 465 regardless of the number of digest games. Here, in a game with a big bonus (including a small role game and a regular bonus), since replay is not defined as a target character for internal lottery, no replay is won. Replay does not reduce the number of medals held by the player, but does not accompany the payout of medals, and therefore does not affect the number of payout medals, which is a condition for ending the big bonus. In other words, even if you make a replay win during the big bonus, it will only increase the number of big bonus games unnecessarily, so by not defining the replay as a target for internal lottery in the big bonus, The game can be efficiently advanced without unnecessarily prolonging the state.

  In addition, in the regular bonus game state, a small role (especially a bell) is won with a high probability and a large number of medals can be obtained, so the player has high expectations for this. This regular bonus is transferred not only when winning a JACIN in a small role game but also when winning a regular bonus in a normal gaming state. For this reason, even when the player is in the normal gaming state, the player can be given a sense of expectation for the regular bonus, so that the interest of the game can be improved. Furthermore, in the regular bonus, in addition to cherry, watermelon, and bell, which are defined in the normal gaming state and small role game, JAC is also defined as a small role. Thereby, the player's sense of expectation in the regular bonus can be further increased, and the interest of the game can be improved.

  In addition, the display mode of JACIN for shifting the game state from the small role game to the regular bonus in the big bonus is configured by a combination of “watermelon-JAC-JAC” and is not used as a display mode of other roles. It is. In the regular bonus, in addition to cherry, watermelon, and bell small roles, the JAC display mode is also determined by a combination of “Bell-JAC-JAC” and is not used as a display mode for other roles. It is. For this reason, the relationship between the display mode derived as the display result of the reels 2L, 2C, and 2R and the winning combination is clarified, and the gameability becomes easy for the player to understand.

  The rotation of the reels 2L, 2C, and 2R is stopped within the range of the maximum stop delay time of 190 milliseconds after the operation of the stop switches 8L, 8C, and 8R is detected. Since it can be pulled in, the symbol to be stopped can be selected from a range of 5 frames. Here, the symbols “watermelon”, “bell”, and “JAC” are always arranged at intervals of 5 frames or less for each of the reels 2L, 2C, and 2R. Bell, Replay, JAC, and JACIN will not miss out when they are elected. In particular, the bells in the regular bonus will be won with a very high probability of approximately 1 / 1.03, but this will not be missed, so the player will effectively hold on to the regular bonus. It becomes unnecessary, and it becomes possible to advance the game easily.

  As described above, the types of winning combinations that are subject to internal lottery for each gaming state are registered in the winning combination table by gaming state, but the number of judgment values that determine the winning probability of each combination is referred to from the determining table. Stored in the address. In the role table, the number of medals when a winning of each role occurs is also registered.

  In the role-specific table, the number of medals is registered according to the number of wagers. When a winning of cherry, watermelon, or bell occurs, the number of medals is set according to the number of wagers (although for cherry and watermelon, the result is The same number of medals is set). Here, the bet number in the regular bonus is fixed at 1, but the bet number in the gaming state other than the regular bonus is fixed at 3. As a result, an appropriate number of medals can be paid out according to the gaming state simply by acquiring the payout number according to the number of bets. Further, since it is not necessary to determine the gaming state when setting the number of medals, the processing steps in the winning determination process are simplified. In addition, the number of bets 1 corresponding to the regular bonus has a higher number of medals at the time of winning the bell than the number 3 of bets, so the player's expectation in the regular bonus is further enhanced, and the interest of the game is enhanced. Can be improved.

  In the role-specific table, for cherry, watermelon, and bell defined as winning combinations in any gaming state, the storage address of the determination value number is registered for each bet number, and the determination value according to the bet number The number is acquired (although, in the case of cherry and watermelon, the same determination value number is acquired as a result). Here, the bet number in the regular bonus is fixed at 1, but the bet number in the gaming state other than the regular bonus is fixed at 3. Thereby, the internal lottery of cherry, watermelon, and bell can be performed with the winning probability corresponding to the gaming state only by acquiring the number of determination values according to the number of bets. In addition, since it is not necessary to determine the gaming state when acquiring the determination value number, the processing steps in the internal lottery are simplified. Moreover, since the bet number 1 corresponding to the regular bonus has a higher probability of winning the bell than when the bet number is 3, the player's expectation in the regular bonus is further increased, and the interest of the game is improved. Can do.

  In addition, the storage address of the judgment value number of each combination registered in the combination table may differ depending on the set value, but the winning probability is the same regardless of the set value. For the winning combination, the number of determination values is stored in common regardless of the set value. By storing the number of determination values in common in this way, the storage capacity required for that is reduced. However, in the role-specific table, even if the target number of the internal lottery is the same as the set bet number and the address storing the number of judgment values referenced according to the set value is different, it is stored at a different address. In some cases, the number of determination values is the same.

  In general, in the development stage, the simulation is performed while adjusting the number of determination values according to the set values for at least some of the combinations (that is, adjusting the winning probability of internal lottery). As the initial number of determination values, a different number of determination values is registered according to the set value. However, as a result of adjustment by simulation, the number of determination values when the set values are different may be the same. Although the same number of judgment values was registered as the initial number of judgment values according to the set value, the number of judgment values registered from the beginning may be used as it is depending on the result of simulation (result of simulation). The number of judgment values different from the initial value, that is, the number of judgment values may differ depending on the set value). Then, the number of determination values obtained with an appropriate result in the simulation in each case is selected as the number of determination values to be set for the mass production model.

  Here, even if the number of determination values adjusted by the simulation is the same regardless of the set value, the number of determination values is stored in the ROM 41b with the same address assignment as that in the development stage. It can be used as a model for mass production. For this reason, it is not necessary to change the method for storing the number of judgment values in the model for mass production from the model for development, so that development from the initial design stage to the model for mass production can be easily performed. Become.

  Further, the storage address of the judgment value number of each combination registered in the combination table is different depending on the number of bets (1 or 3), but is stored at different addresses such as cherry or watermelon, for example. In some cases, the same number of determination values is used.

  In the development model, it is normal to perform simulation while finely adjusting the judgment value data according to the number of bets (the same as when the initial number of judgment values is different) There may be cases). Here, even if the number of decision values adjusted by the simulation becomes the same regardless of the number of bets, the number of decision values is stored in the ROM 41b with the same address assignment as the address assignment in the development stage. It can be used as a model for mass production. For this reason, it is not necessary to change the method for storing the number of judgment values in the model for mass production from the model for development, so that development from the initial design stage to the model for mass production can be easily performed. Become.

  In addition, the internal lottery adds the number of judgment values of each role referred from the role-specific table to the acquired random number for internal lottery, and depending on whether or not the result of the addition overflows, Judgment is made on whether or not there is a win. For this reason, an internal lottery can be performed using the number of determination values of each combination as it is. In addition, when generating the winning determination table before the actual winning determination is performed, the loop processing is required twice. However, according to this embodiment, the loop processing in the lottery processing may be performed only once. Thus, the processing efficiency in the entire lottery process is high.

  Further, in the internal lottery in the normal gaming state, the lottery for the small combination and re-playing combination and the lottery for the special combination are separately performed based on the same random number for internal lottery. Then, after the special combination is established, that is, in a state where the special combination winning flag is carried over, only the small combination and the re-playing combination are drawn. For this reason, since the lottery of the small combination and the re-playing combination can be made common before and after the special combination is established, the internal lottery in the normal gaming state can be simplified.

  In addition, in the special role combination table to be referred to in the special lottery in the internal lottery in the normal gaming state, the special role determination value number, the range of random numbers determined to win the small role, and the special role Registered are an address that stores the number of determination values that overlap each other, and an address that stores the number of determination values that do not overlap. For this reason, in the internal lottery in the normal gaming state, the range of random numbers determined to win the special role partially overlaps the range of random numbers determined to win the small role. If the value of the range that is determined to be won is acquired as a random number for internal lottery, the special role and the small role will be won at the same time, and the value of the range in which only the special role is determined is determined as the internal lottery If it is obtained as a random number for use, only the special role will be won. As a result, even if a small role winning is generated as a result of the game, it is not denied that the occurrence of a special role having a higher advantage than the small role is allowed. A player's expectation can be maintained.

  The random number for internal lottery acquired by the random number acquisition process is not used as it is from the random number generation circuit 42 by the sampling circuit 43 but is used after being processed by software. The random number generation circuit 42 generates a random number by updating at a high speed at the frequency of the pulse signal of the pulse generation circuit 42a. However, in the random number for internal lottery after processing by software, the periodicity of the update is increased by the processing. It will be lost.

  On the other hand, in the internal lottery, since the number of determination values corresponding to each combination is sequentially added to the random value for internal lottery, each combination is determined to be a winning combination as shown in FIGS. The random number value for the internal lottery to be set will be hardened. On the other hand, it is possible to prevent the player from aiming as much as possible by losing the periodicity of the random numbers for internal lottery by processing by software and varying the values.

  Moreover, the frequency of the pulse signal generated by the pulse generation circuit 42a for updating the values of the counters 42b and 42c of the random number generation circuit 42 is higher than the frequency of the operation clock of the CPU 41a, and is not an integral multiple. For this reason, it becomes difficult for the update of the random number generated by the random number generation circuit 42 to be synchronized with the process performed by the CPU 41a. In addition, by increasing the frequency of the pulse signal of the pulse generation circuit 42a, the update speed of the random number generated by the random number generation circuit 42 can be made extremely fast.

  On the other hand, the processing of random numbers by software is performed by replacing the upper byte and lower byte of the random number extracted from the random number generation circuit 42 by the sampling circuit 43, masking the 15th and 7th bits, and then bit-shifting the upper byte. good. Therefore, even for a relatively large random number of 16 bits (actually masked 14 bits), the load required for processing necessary to lose periodicity is not so large, and can be easily obtained. Can do. Since a large random number can be acquired in this way, the probability setting in the internal lottery can be finely performed.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  For example, in the above-described embodiment, the determination value number storage area uses a 2-byte area to store the determination value number in each case. However, in a general slot machine, the number of determination values of a combination such as a big bonus and a regular bonus cannot be set to exceed 255 in any game situation. As described above, for those that do not need to set the number of determination values exceeding 255, the number of determination values may be stored using only a 1-byte area.

  Further, in the above-described embodiment, some of the determination values that are common regardless of the set value are stored in common for all of the set values 1 to 6, but the number of determination values is related to the set value. Even common items can be individually stored for each of the setting values 1 to 6. In addition, if the number of determination values is common regardless of the set value, all of them can be stored in common for all of the set values 1 to 6.

  Moreover, in the said Example, it was whether it memorize | stored in common with the whole setting value 1-6, or it memorize | stored separately with respect to each of the setting values 1-6 in the said Example. However, it is assumed that the number of determination values is not stored in common for all of the setting values 1 to 6 (the common flag for the setting value is not set). About 4-6, the number of judgment values can also be made common. The same applies to the number of determination values for the bet number. For example, the bet numbers 1 and 2 may be common and the bet number 3 may be individual.

  In the above-described embodiment, the number of determination values referred to according to the number of bets for the same combination at the same set value is stored at a different address for each of the bets (1 or 3). That is, for the same combination at the same set value, even if the number of judgment values referred to according to the number of bets is the same, it is stored separately, but the combination with the same winning probability regardless of the number of bets For the role that makes the determination value number storage address common, or for the role that makes the winning probability the same regardless of the setting value and the number of bets, the address of the determination value number storage address is made common In this way, by storing the number of determination values in common, it is possible to reduce the storage capacity required for that purpose.

  In the embodiment, the number of determination values acquired according to the set value or the like is sequentially added to the random number value for internal lottery, but from the value of random number for internal lottery that acquired the acquired determination value number, Subtraction may be performed sequentially, and the result of the subtraction may be used as a new random value for internal lottery. When the number of determination values is subtracted from the random number value for internal lottery, the 15th and 14th bits of the random number for internal lottery are set to “0”, and the subtraction result overflows (here, the subtraction result is negative) It can be determined whether or not

  In the embodiment, in the internal lottery, the number of determination values of each combination according to the game situation is sequentially added to the acquired random number for internal lottery, and when the addition result overflows, the winning combination is won. It was supposed to be judged. On the other hand, a winning determination table in which a determination value for determining each combination as winning is determined for each game in accordance with the number of determination values for each combination according to the game situation, and the internal random number for internal lottery acquired It is good also as what performs an internal lottery by comparing this value with the determination value of each combination.

  Further, in the above embodiment, the game can be started only by setting 3 as the bet number in the small role game in the normal gaming state and the big bonus. On the other hand, even in the small game in the normal gaming state and the big bonus, it is possible to start the game by setting 1 as the bet number, and further, by setting 2 as the bet number, You may be able to get started. As a result, when 1 or 2 is set as the bet number in the small game in the normal gaming state and the big bonus, the winning probability of the small role in the internal lottery is lower than when 3 is set as the bet number. In both cases, the number of medals to be paid out when winning a small role can be increased. For example, when 3 is set as the bet number in the small game in the normal gaming state and the big bonus, the winning probability of the bell is 1 / 4.6 and the payout number is 8, but the bet number is 1 or 2 Is set, the winning probability of the bell may be 1 / 240.9 and the payout number may be 15. Further, the winning probability of the bell and the number of payouts may be changed when 1 is set as the bet number and when 2 is set.

  In the embodiment, in the internal lottery in the normal gaming state, for the same random number for internal lottery, the lottery of the small role and the replaying role referring to the role-specific table for the small role and the replaying role, and the special role The special role lottery that refers to the role-specific table is separately performed. By registering the address that stores the number of judgment values that overlap with the range of random numbers that are determined to win the special role, the special role and the small role can be won simultaneously. The storage address of the judgment value number corresponding only to the special role, the storage address of the judgment value number corresponding to both the special role and the small role, the storage address of the judgment value number corresponding only to the small role, replay Storage destination address for the number of judgment values corresponding to only the role In the internal lottery, the number of determination values for each combination referenced from the role-specific table is added to the acquired random number for internal lottery, and the number of determination values corresponding to the special combination only If the result of the addition of the item overflows, the winning of only the special role is determined. If the addition result with the number of judgment values corresponding to both the special role and the small role overflows, both the special role and the small role are determined. If the result of adding to the number of judgment values corresponding to only the small role or replaying role overflows, the special role can be determined by determining the winning of only the small role or replaying role. It can also be configured that the small role can be won simultaneously.

  FIG. 40 is a diagram showing a modification of the role-specific table, and FIG. 41 is a flowchart showing a modification of the internal lottery process.

  The role-specific table shown in FIG. 40 includes big bonus (1), big bonus (2), big bonus (3), regular bonus (1), regular bonus (2), JACIN, JAC, cherry, big bonus (1 ) + Cherry, Big Bonus (2) + Cherry, Big Bonus (3) + Cherry, Watermelon, Big Bonus (1) + Watermelon, Big Bonus (2) + Watermelon, Big Bonus (3) + Watermelon, Bell, Replay The storage addresses for the number of judgment values are registered in the order in which they are referenced.

  The number of determination values for each combination is registered corresponding to the number of bets (BET) set by the player in the game. This is because even with the same combination, the winning probability in the regular bonus may differ from other combinations. In addition, the number of determination values according to the number of bets for each combination may be common regardless of the set value, or may be different depending on the set value. If the number of determination values is common regardless of the set value, a common flag is set (value is set to “1”).

  Big Bonus (1), Big Bonus (2), Big Bonus (3), Regular Bonus (1), Big Bonus (1) + Cherry, Big Bonus (2) + Cherry, Big Bonus (3) + Cherry, Big Bonus (1) + Watermelon, Big Bonus (2) + Watermelon, Big Bonus (3) + Watermelon is a role subject to internal lottery only in the normal gaming state, and a determination corresponding to the bet number 3 in the normal gaming state The storage address for the number of values is registered. Among these roles, the value of the common flag is 0 for the big bonus (1), the big bonus (2), the big bonus (3), and the regular bonus (1). The storage address for the number of judgment values is registered. Big Bonus (1) + Cherry, Big Bonus (2) + Cherry, Big Bonus (3) + Cherry, Big Bonus (1) + Watermelon, Big Bonus (2) + Watermelon, Big Bonus (3) + Watermelon The common flag value is 1, and the storage address of the common number of judgment values is registered regardless of the set value. Regular bonus (2) and JACIN are internal lottery targets only in the small bonus game in the big bonus, and the storage address of the number of judgment values corresponding to the bet number 3 in the small bonus game is registered. . The value of the common flag for this role is 1, and a storage address for a common number of determination values is registered regardless of the set value.

  The JAC is a role that is subject to internal lottery only with the regular bonus, and the storage address of the number of determination values corresponding to the bet number 1 with the regular bonus is registered. The common flag for this combination is 1, and a common storage address for the number of determination values is registered regardless of the set value. Replay is a role that is subject to internal lottery only in the normal gaming state, and a storage address for the number of determination values corresponding to the bet number 3 in the normal gaming state is registered. The common flag for this combination is 1, and a common storage address for the number of determination values is registered regardless of the set value.

  Cherry, bell, and watermelon are the targets for internal lottery in any gaming state, the storage address of the number of judgment values corresponding to the bet number 1 in the regular bonus, and in the normal gaming state or small role game A storage address of the number of determination values corresponding to the bet number 3 is registered. For cherry and watermelon, the common flag is 1, and a storage address for the common number of determination values is registered corresponding to the number of bets regardless of the set value. For the bell, the common flag is 0, and the storage address of the number of determination values is individually registered according to the set value corresponding to each bet number.

  Next, based on the flowchart shown in FIG. 41, the modified example of the internal lottery process which CPU41a performs is demonstrated.

  In this internal lottery process, a random number acquisition process is performed (Se101). In this random number acquisition process, a random number value for internal lottery is acquired based on the random number generated by the random number generation circuit 42.

  Then, the set value stored in the RAM set value work is read (Se102), and whether or not the read set value is in the range of 1 to 6, that is, the set value stored in the set value work is an appropriate value. If the read set value is not in the range of 1 to 6, the process proceeds to the RAM abnormality error process shown in FIG.

  If the setting value read in the step of Se103 is in the range of 1 to 6, the combinations registered in the combination table of FIG. 40 corresponding to the current gaming state are sequentially read (Se104). The types of roles read here are regular bonus (regular bonus (1), regular bonus (2)), big bonus (big bonus (1), big bonus (2), big bonus (3) (+ cherry, + watermelon) Is not included))) (Se105). If it is one of the regular bonus, big bonus or JACIN, the regular bonus winning flag or big bonus winning flag is already set in the RAM 41c in the previous game, and it is carried over without winning based on the winning flag. It is determined whether or not (Se106). If the type of the read combination is neither a regular bonus nor a regular bonus, the process proceeds to Se107 as it is.

  If the regular bonus winning flag or the big bonus winning flag has already been set, the process returns to the processing of Se104, and further, the next registered role in the winning state-specific winning table is read (regular bonus, big bonus and JACIN is first registered in the role-specific table, and this does not end the lottery process). Even if the type of the read combination is regular bonus, big bonus or JACIN, if neither the regular bonus winning flag nor the big bonus winning flag is set, the process proceeds to Se107.

  In Se107, the number of BETs set in step Sa2 is further read, and the setting status of the common flag is acquired from the role-specific table of FIG. 40 for the role and the role corresponding to the read BET number. As a result, it is determined whether or not a common flag is set for the combination and the BET number (Se108).

  If the common flag is set, the number of determination values stored in the address registered in the role-specific table of FIG. 40 for the role and the BET number is acquired (Se109). Then, the process proceeds to Se111. If the common flag is not set, the setting value set in the RAM 41c is read, and the determination stored in the address registered in the role-specific table corresponding to the setting value read for the role and the BET number The number of values is acquired (Se110). Then, the process proceeds to Se111.

  In the step of Se111, the number of determination values acquired in the step of Se109 or Se110 is added to the random number value for internal lottery, and the result of the addition is used as a new random number value for internal lottery. Here, it is determined whether or not an overflow has occurred when the number of determination values is added to the random number value for internal lottery (Se112). If an overflow occurs, the winning combination is Big Bonus (1) + Cherry, Big Bonus (2) + Cherry, Big Bonus (3) + Cherry, or Big Bonus (1) + Watermelon, Big Bonus (2) + It is determined whether or not it is watermelon, big bonus (3) + watermelon (Se113). Big Bonus (1) + Cherry, Big Bonus (2) + Cherry, Big Bonus (3) + Cherry, or Big Bonus (1) + Watermelon, Big Bonus (2) + Watermelon, Big Bonus (3) + If it is not a watermelon, the winning flag of the combination is set in the RAM 41c (Se114). Then, the internal lottery process is terminated, and the process returns to the flowchart of FIG.

  In the step of Se113, the role is a big bonus (1) + cherry, big bonus (2) + cherry, big bonus (3) + cherry, or big bonus (1) + watermelon, big bonus (2) + watermelon, big If it is bonus (3) + watermelon, it is determined whether the regular bonus winning flag or the big bonus winning flag is already set in the RAM 41c in the previous game, and it is carried over without winning based on the winning flag ( Se115). If neither the regular bonus winning flag nor the big bonus winning flag is set, the winning flag corresponding to the big bonus (1) to (3) and the winning flag for cherry or the corresponding winning of the big bonus (1) to (3) A flag and a winning flag for watermelon are set in the RAM 41c (Se116). Then, the internal lottery process is terminated, and the process returns to the flowchart of FIG.

  If the regular bonus winning flag or the big bonus winning flag is already set in the step of Se115, the cherry winning flag or the watermelon winning flag is set in the RAM 41c (Se117). Then, the internal lottery process is terminated, and the process returns to the flowchart of FIG.

  If no overflow has occurred in the step of Se112, it is determined whether there is a combination that has not yet been processed among the combinations determined for the gaming state (Se118). If there is a combination that has not yet been processed, the process returns to the process of Se104, and the process continues with the next combination registered in the winning combination table by gaming state as the processing target. If there is no combination not to be processed, the internal lottery process is terminated and the process returns to the flowchart of FIG.

  As described above, according to the modified example to which the role-specific table shown in FIG. 40 and the internal lottery process shown in FIG. 41 are applied, it is not necessary to register the number of determination values corresponding to the special role lose, so the capacity of the ROM 41b Can be saved, and the internal lottery process can be made common regardless of the gaming state, so that the program can be simplified.

  In the above embodiment, the entire high-order byte of the random number extracted from the random number generation circuit 42 is replaced with the low-order byte, and the entire low-order byte is replaced with the high-order byte. On the other hand, the data of a specific bit among the random number bits extracted from the random number generation circuit 42 is simply replaced with data of other bits (however, other than the masked seventh and fifteenth bits). Also good. Alternatively, the random number value extracted from the random number generation circuit 42 may be directly acquired as a random number for internal lottery. Further, it may be processed into a random number for internal lottery by a method different from the above embodiment.

  FIG. 42 is an explanatory diagram of a first modification of the processing until the CPU 41a processes the random number extracted from the random number generation circuit 42 into a random number for internal lottery by software. Also in the first modification, the random number extracted from the random number generation circuit 42 is stored in the 16-bit general-purpose register 41GR included in the CPU 41a.

  When the random number extracted from the random number generation circuit 42 is stored in the general-purpose register 41GR, the CPU 41a further extracts the value of the internal refresh register 41R as a processing random number. The CPU 41a adds the processing random number extracted from the refresh register 41R to the value of the upper byte of the general-purpose register 41GR (the value extracted from the upper counter 42c). The value of the lower byte of the general register 41GR (the value extracted from the lower counter 42b) is left as it is.

  Next, the CPU 41a performs an OR operation with the value of the general-purpose register 41GR, that is, a value obtained by adding a processing random number to the upper byte with 8080h. Furthermore, the CPU 41a shifts the upper 1 byte (8th bit to 15th bit) to the lower bit by bit, and inserts 1 into the empty 15th bit. The CPU 41a acquires the value stored in the general-purpose register 41GR at this time as a random number for internal lottery, and sequentially adds the number of determination values to this.

  FIG. 43 is an explanatory diagram of a second modification of the process until the CPU 41a processes the random number extracted from the random number generation circuit 42 into a random number for internal lottery by software. Also in this example, the random number extracted from the random number generation circuit 42 is stored in the 16-bit general-purpose register 41GR included in the CPU 41a.

  When the random number extracted from the random number generation circuit 42 is stored in the general-purpose register 41GR, the CPU 41a further extracts the value of the internal refresh register 41R as a processing random number. The CPU 41a adds the processing random number extracted from the refresh register 41R to the value of the upper byte of the general-purpose register 41GR (the value extracted from the upper counter 42c). The processing random number extracted from the refresh register 41R is also added to the lower byte value (the value extracted from the lower counter 42b) of the general-purpose register 41GR.

  Next, the CPU 41a performs a logical OR operation with the value of the general-purpose register 41GR, that is, the value obtained by adding the processing random numbers to the upper byte and the lower byte, respectively, with 8080h. Furthermore, the CPU 41a shifts the upper 1 byte (8th bit to 15th bit) to the lower bit by bit, and inserts 1 into the empty 15th bit. The CPU 41a acquires the value stored in the general-purpose register 41GR at this time as a random number for internal lottery, and sequentially adds the number of determination values to this.

  In the first and second modified examples described above, the value of the refresh register 41R is extracted as a random number for processing, and this is extracted from the high-order byte of the random number extracted from the random number generation circuit 42 (in the second modified example, further lower byte) ) To process random numbers. The random number processing applied here includes at least processing for adding a processing random number to the upper byte. Thereby, the variation of the random numbers for internal lottery can be increased, and the player can prevent the aiming as much as possible.

  Further, since the processing random numbers are extracted from the refresh register 41R, no special configuration is required as means for generating the processing random numbers. Moreover, the value of the refresh register 41R is updated every time the CPU 41a fetches an instruction, and the update interval is not constant. Therefore, a random number with high randomness can be extracted as a processing random number. And since the randomness of the processing random number is high, the randomness of the random number for internal lottery generated using the random number is also high.

  In the first and second modifications, the value extracted from the refresh register 41R is added to the upper byte (and the lower byte) of the random number extracted from the random number generation circuit 42. A value that is periodically updated by hardware or software may be added. Further, instead of adding a value extracted from the refresh register 41R (or a value replacing the refresh register 41R), a logical operation such as subtraction, logical sum, or logical product may be performed.

  Further, bit replacement such as replacement of the upper byte and the lower byte shown in the above embodiment may be used in combination with the first and second modifications. Also in the first and second modified examples, the interrupt to the CPU 41a is prevented in order to prevent the contents of the general-purpose register 41GR from being rewritten between the extraction of the random number from the random number generation circuit 42 and the end of the processing. It will be prohibited.

  Further, in the second modification, processing random numbers to be added to the upper and lower bytes of the random number extracted from the random number generation circuit 42 may be separately extracted from the refresh register 41R at different timings. Separately prepare the processing random number to be added to the upper byte and the processing random number to be updated to the lower byte. Means for extracting may be provided. In this case, one of the means for updating the processing random number for the upper byte and the means for updating the processing random number for the lower byte can be constituted by the refresh register 41R.

  In the above embodiment, the case where the present invention is applied to the case where the random number generated by the random number generation circuit 42, that is, the random number extracted by the hardware random number function is processed by software has been described. However, the random number processing by the software described above may be applied to random numbers that are periodically updated by software. For example, the CPU 41a sends an instruction to the second microcomputer to extract a random number periodically updated by a timer interrupt or the like in a second microcomputer different from the microcomputer constituting the main control unit 41, and I The data can be input to the CPU 41a via the / O port 41d and stored in the general-purpose register 41GR. The function of the second microcomputer may be included in the microcomputer that constitutes the main control unit 41. Also in this case, the random number value obtained after processing can be varied, and the effect of preventing the player from aiming can be achieved.

  In the embodiment, when the CPU 41a initializes the RAM 41c, the initialization table of the ROM 41b is referred to, and the start address and initialization size corresponding to any of initializations 1 to 4 are determined according to the initialization conditions. Acquire, set the pointer to the start address, set the initialization size, clear the area of the corresponding address by 1 byte from the initialization address where the pointer was set, and initialize the size every time 1 byte is cleared 1 is subtracted and the process of advancing the pointer by 1 is executed until the initialization size becomes 0, so that the area of the RAM 41c corresponding to the initialization condition is initialized. The addressed area is set as a continuous address area, and the initialization table corresponds to one of initialization 1 to 4 depending on the initialization condition The start address and the end address common to all of initializations 1 to 4 are registered, and when the CPU 41a initializes the RAM 41c, the initialization table is referred to and the initialization address is initialized according to the initialization condition. The start address corresponding to any one of 1 to 4 is acquired, the pointer is set to the start address, and the area of the corresponding address is cleared to 0 by 1 byte from the initialization address to which the pointer is set, and 1 byte is cleared. Each time the pointer is advanced, the area of the RAM 41c corresponding to the initialization condition may be initialized by executing the process of advancing the pointer until the end address area common to the initializations 1 to 4 is cleared. .

  In this case, each time 1 byte is cleared, it is determined whether the address indicated by the pointer is the end address. If the address is the end address, the initialization may be terminated. The initialization byte number from the start address to the common end address is calculated and set, and every time 1 byte is cleared from the start address, the initialization byte number is decremented by 1 and the pointer is advanced by 1. It is preferable that the process is executed until the number reaches zero, and it is determined that the end address area has been cleared when the number of initialization bytes reaches zero, and the initialization is terminated. This is because the process of determining whether the number of initialization bytes is 0 is higher than the process of comparing the address indicated by the pointer and the end address for each byte.

  44 (a) is a diagram showing a modification of the storage area of the RAM 41c, FIG. 44 (b) is a diagram showing a modification of the initialization table, and FIG. 45 is a modification of initialization 1. It is a flowchart to show.

  As shown in FIG. 44 (a), in this modification, the storage area of the RAM 41c is 7E00 (H), the set value work, special work, important work, non-saved work, general work, unused area, unused The stack area is allocated in the order of the stack area in use. For this reason, even if any of initialization 1, 2, and 4 is performed, the area | region initialized is a continuous address area | region. Specifically, the areas initialized in the initialization 1 are all areas except the in-use stack area, that is, set value work, special work, important work, unsaved work, general work, unused area, unused stack. These areas are continuous address areas from 7E00 (H) to the stack pointer. The areas initialized in the initialization 2 are general work, unused area, and unused stack area, and these areas are continuous address areas from 7E53 (H) to the stack pointer. The areas initialized in the initialization 4 are an unused area and an unused stack area. These areas are continuous address areas from 7F05 (H) to the stack pointer. In initialization 2, general work, unused area, and unused stack area are initialized. In initialization 3, non-saved work, unused area, and unused stack area are initialized. The unused area and the unused stack area that are initialized in the initialization 3 are continuous address areas, but the non-saved work is a non-continuous address area.

  As shown in FIG. 44A, in the initialization table applied in this modification, start addresses are registered corresponding to initializations 1 to 4, and end addresses common to initializations 1 to 4 are included. Is registered. In addition, since the initialization 3 is an address area where non-saved work is not continuous, the initialization size is registered corresponding to the start address of the non-saved work.

  Next, a modification of the initialization 1 executed by the CPU 41a will be described based on the flowchart shown in FIG.

  In this initialization 1, first, the initialization table of the ROM 41b is referred to, and the start address registered corresponding to the initialization 1 is read (Sg101). Then, a pointer is set to the read start address (7E00 (H)) (Sg102). Next, the initialization address common to the initializations 1 to 4 is read with reference to the initialization table of the ROM 41b (Sg103). Then, the number of bytes from the start address (7E00 (H)) read in Sg101 to the end address (stack pointer) read in Sg103 is calculated (Sg104), and the number of bytes in the area for initializing the calculated number of bytes is set. (Sg105). Then, a RAM clear process for clearing data from the start address set in Sg102 to the number of bytes set in Sg105 is executed (Sg106). When the RAM clear process is completed, the initialization 1 is completed. Return to.

  In addition, the initialization 2 and 4 are almost the same processing as the initialization 1 shown in FIG. 45, and the start address of initialization 2 or initialization 4 registered in the initialization table is acquired. Then, the number of bytes from the start address to the common end address is calculated, and the data is cleared over the calculated number of bytes from the start address. In the modification of initialization 3, first, the start address and initialization size of the non-saved work registered in the initialization table are acquired, and after the data is cleared from the start address over the number of bytes corresponding to the initialization size, Get the start address of the unused area and unused stack area registered in the initialization table, calculate the number of bytes from the start address to the common end address, and clear the data over the calculated number of bytes from the start address Perform the process.

  According to the modification of the initialization of the RAM 41c as described above, for a plurality of initialization conditions, only the start address corresponding to the initialization table and the end address common to the plurality of initialization conditions are set. Because it is possible to initialize areas corresponding to multiple initialization conditions without individually setting end addresses corresponding to multiple initialization conditions, the program capacity for performing multiple types of initialization Can be reduced.

  In the embodiment, the RAM parity adjustment data is stored so that the RAM parity of the RAM 41c becomes 0 in the power interruption processing, and it is determined whether or not the RAM parity of the RAM 41c is 0 at the time of restoration. Although it is determined whether or not the data in the RAM 41c is normal, of course, the RAM parity adjustment data is stored so that the RAM parity of the RAM 41c becomes 1 in the power interruption processing, and the RAM parity of the RAM 41c becomes 1 at the time of restoration. Whether or not the data in the RAM 41c is normal may be determined. Further, the checksum (exclusive OR of the data stored in the corresponding area) of all areas of the RAM 41c is calculated in the power interruption processing, and is stored in a specific area, and at the time of recovery, the RAM 41c is restored. The checksum of all the areas including the specific area where the checksum is stored is calculated. If the result is 00 (H), it is determined that the data in the RAM 41c is normal, and must be 00 (H). For example, it may be determined that the data in the RAM 41c is abnormal.

  If the checksum is stored normally in the power interruption processing, the checksum of the area excluding the specific area and the data stored in the specific area (the checksum calculated at the time of power interruption) ) Should take the same value, and if the checksum of the area excluding the specific area matches the data stored in the specific area, the result of calculating the exclusive OR of both data is Since the result of calculating the checksum of all the areas including the specific area where the checksum of the RAM 41c is stored is 00 (H), it is determined that the data of the RAM 41c is normal. This is because it can.

  In this case as well, in the power interruption interrupt processing, before the checksum is calculated, the destructive diagnosis data (for example, 5A (H)) in which any bit is 1 is stored at a predetermined address, and at the time of restoration In addition to determining whether or not the checksum is 00 (H), it is also determined whether or not the data for destructive diagnosis is normally stored. The checksum is 00 (H) and the destructive diagnosis is performed. It is preferable to determine that the data in the RAM 41c is normal on the condition that the business data is also normal. Even if the data in the RAM 41c is not normal, if 00 (H) is stored in all areas, it will be determined to be normal by the checksum determination at the time of startup. After storing the destructive diagnostic data with the bit set to 1, calculate the checksum, store it in a specific area, and check the destructive diagnostic data in addition to determining the checksum at the time of recovery, For example, even when 00 (H) is stored in all areas at the time of recovery and the checksum is 00 (H) and it is determined to be normal, the data for failure diagnosis matches the value stored at the time of power failure Therefore, the abnormality of the RAM 41c can be determined more accurately.

  In the above, the RAM parity or checksum of the RAM 41c is calculated in the power interruption processing and stored in the RAM 41c, and whether or not the RAM parity calculated based on all areas of the RAM 41c at the time of restoration is 0. Or whether the data in the RAM 41c is normal based on whether or not the checksum calculated based on all the areas of the RAM 41c is 00 (H). RAM parity or checksum of the RAM 41c is calculated and stored in a specific area, and the RAM parity or checksum excluding the specific area of the RAM 41c is calculated at the time of recovery, and the RAM parity or checksum stored in the specific area is calculated. The data in the RAM 41c depends on whether the comparison result matches It may be determined whether normal or not. In this case as well, as described above, before the RAM parity or checksum is calculated, the destructive diagnosis data in which any bit is 1 is stored at a predetermined address. In addition to determining whether or not the sums match, it is determined whether or not the data for destructive diagnosis is stored normally, the RAM parity and checksum match, and the destructive diagnostic data is also normal. It is preferable to determine that the data in the RAM 41c is normal under the above conditions.

  In the embodiment, the slot machine for setting bets using medals and credits is used. However, the present invention is not limited to this, and the slot machine for setting bets using game balls. Alternatively, it may be a complete credit type slot machine that uses only credits to set the number of bets.

  Each element in the embodiment corresponds to the present invention as follows.

The slot machine according to claim 1 of the present invention includes:
A game can be started by setting a predetermined number (1 or 3) of bets for one game, and a variable display device (reel 2L, 2C, 2R) is a slot machine 1 in which one game is ended by deriving and displaying a display result, and winning can be generated according to the display result of the variable display device,
Main control means (main control unit) configured by a microcomputer having an interrupt input terminal (trigger terminal CLK / TRG) for generating an external interrupt (interrupt 2) when a signal is input, and controlling a game 41),
Sub-control means (sub-control unit 91) for controlling the production based on reception of control information (command) transmitted from the main control means;
The state of a predetermined power (+ 25V) used in the slot machine is monitored, and a power interruption signal (voltage) when a power interruption condition related to the power supply being cut off is satisfied (when it becomes + 18V or less). Power interruption detection means (power interruption detection circuit 48) for outputting a lowering signal;
With
The power interruption detection means outputs the power interruption signal to the interrupt input terminal of a microcomputer constituting the main control means,
The main control means includes
A storage means for storing data in a readable and writable manner and capable of holding data stored in the storage area even when power supply is stopped; Work area (important work, general work, special work, set value work, unsaved work) in which data for operating the microcomputer constituting the means is stored, and data can be temporarily stored A main data storage means (RAM 41c) to which at least a stack area and an unused area in which data for operation of the microcomputer constituting the main control means is not read and written are assigned;
Initialization means (initialization of the RAM 41c by the CPU 41a) for initializing the unused area other than the stack area in the storage area of the main data storage means for each game (every game ends);
Timer interrupt process execution means (timer interrupt process by the CPU 41a) for interrupting a process being executed every predetermined unit time (0.56 ms) and executing a timer interrupt process;
Branch counter updating means for updating a branch counter value for identifying a process to be executed in the timer interrupt process according to the execution of the timer interrupt process;
The process executed in the timer interruption process is a process (port input process) for monitoring the input state of the operation detection means for detecting the player's operation and storing the input information indicating the input state in the main data storage means ) Including a process selection means (selection of timer interrupts 1 to 4 by the CPU 41a) that selects a process corresponding to the branch counter value as a process to be executed in the timer interrupt process.
The main control means when power supply is started in response to the occurrence of an external interrupt based on the input of the power interruption signal (voltage drop signal) to the interrupt input terminal (trigger terminal CLK / TRG) Interruption during power interruption to save information (RAM parity adjustment data, destruction diagnosis data) necessary for returning the control state to the control state before the power supply is stopped in the storage area of the main data storage means Power interruption interrupt processing execution means for executing the processing (power interruption interrupt processing by the CPU 41a),
Multiple interrupt prohibition means (interrupt prohibition during interrupt processing) for prohibiting the other interrupt processing during execution of one of the timer interrupt processing or the interrupt processing at power interruption,
The input information stored in the timer interrupt process is read, and a basic process for controlling one game is executed by gradually shifting a plurality of control states according to the progress of the game based on the read input information. Basic processing execution means (game processing by the CPU 41a),
A storage area allocated to the work area of the main data storage means, and a control information storage means (command queue) capable of storing a plurality of the control information;
Control information generation means (command storage processing by the CPU 41a) for generating the control information in accordance with the progress of the game in the basic processing and storing it in the control information storage means;
In the timer interrupt processing, control information transmission processing means (command transmission processing by the CPU 41a) for performing control information transmission processing for transmitting control information stored in the control information storage means to the sub-control means;
Including
The power interruption interrupt processing execution means waits for completion of the timer interruption processing being executed when the external interruption occurs during execution of the timer interruption processing. Run
The control information transmission processing means performs the control information transmission processing (command transmission processing) only once when the branching counter value indicates a specific value in the timer interrupt processing, and the control information storage means ( When a plurality of control information (commands) are stored in the command queue), a plurality of control information (commands) stored in the control information storage means (command queue) in the control information transmission processing (command transmission processing) ), Only the control information (command) generated at the earliest time is transmitted.

It is a front view of the slot machine of the Example to which this invention was applied. It is a figure which shows the symbol arrangement | sequence of a reel. It is a block diagram which shows the structure of a slot machine. It is a circuit diagram for demonstrating the structure of a power supply board. (A) is a circuit diagram for demonstrating the structure around the main control part in a game control board. (B) is a circuit diagram for explaining a configuration around a sub-control unit in the effect control board. (A) is a figure which shows the winning combination table according to gaming state. (B) is a figure which shows the classification table for a small combination and a re-game combination. (C) is a diagram showing a role-specific table for special roles. It is a figure which shows the memory area of the number of judgment values acquired based on the address registered into the table according to role. (A) (b) is a figure which shows the example of the value of the random number for internal lottery, the determination value number of each combination, and a winning combination. It is a figure which shows the example of the value of the random number for internal lottery, the number of judgment values of each combination, and a winning combination. (A) (b) is a figure which shows the example of the value of the random number for internal lottery, the determination value number of each combination, and a winning combination. (A) is a block diagram showing in detail the configuration of a random number generation circuit. (B) is explanatory drawing until a CPU processes the random number extracted from the random number generation circuit into the random number for internal lottery by software. It is a figure which shows the structure of the storage area of RAM of a main control part. (A) is a figure which shows the area | region initialized in initialization 1-4 performed by CPU of a main control part. (B) is a figure which shows the initialization table stored in ROM of the main control part. It is a figure which shows an example of the command transmitted with respect to an effect control board from a game control board. It is a figure which shows the structure of the command queue set to RAM of a main control part. It is a timing chart which shows the generation situation of timer interruption processing which CPU of a main control part performs. (A) (b) is a timing chart which shows an example of the transmission condition of the command by CPU of a main control part. It is a flowchart which shows the control content of the starting process which CPU of a main control part performs at the time of starting. It is a flowchart which shows the control content of the RAM abnormality error process performed when CPU of a main control part determines RAM abnormality. It is a flowchart which shows the control content of the setting change process which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the game process which CPU of a main control part performs after a starting process. It is a flowchart which shows the control content of the internal lottery process which CPU of a main control part performs in a game process. It is a flowchart which shows the control content of the internal lottery process which CPU of a main control part performs in a game process. It is a flowchart which shows the control content of the internal lottery process which CPU of a main control part performs in a game process. It is a flowchart which shows the control content of the random number acquisition process which CPU of a main control part performs in an internal lottery process. It is a flowchart which shows the control content of the initialization 1 which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the RAM clear process which CPU of the main control part performs in initialization 1-4. It is a flowchart which shows the control content of the initialization 2 which CPU of a main control part performs at the time of the end of a big bonus. It is a flowchart which shows the control content of the initialization 3 which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the initialization 4 which CPU of a main control part performs whenever one game is complete | finished. It is a flowchart which shows the control content of the timer interruption process periodically performed by CPU of a main control part. It is a flowchart which shows the control content of the timer interruption process periodically performed by CPU of a main control part. It is a flowchart which shows the control content of the command storage process performed when CPU of a main control part produces | generates a command and stores it in a command queue. It is a flowchart which shows the control content of the command transmission process which CPU of a main control part performs in a timer interruption process. It is a flowchart which shows the control content of the interruption interruption process performed when CPU of a main control part inputs a voltage drop signal from an interruption detection circuit. It is a flowchart which shows the control content of the starting process (sub) which CPU of a sub control part performs at the time of starting. It is a flowchart which shows the control content of the command reception interruption process performed when CPU of a sub-control part inputs a strobe (INT) signal from a game control board. It is a flowchart which shows the control content of the timer interruption process (sub) which CPU of a sub control part performs regularly. It is a timing chart which shows the fall state of each voltage at the time of a power failure, and the operation state of CPU of a main control part and a sub control part. It is a figure which shows the modification of a table classified by role. It is a figure which shows the modification of the internal lottery process which CPU of a main control part performs. It is explanatory drawing of the 1st modification of a process until CPU processes the random number extracted from the random number generation circuit into the random number for internal lottery by software. It is explanatory drawing of the 2nd modification of the process until CPU processes the random number extracted from the random number generation circuit into the random number for internal lottery by software. (A) is a figure which shows the modification of the storage area of RAM in a main control part. (B) is a figure which shows the modification of an initialization table. It is a figure which shows the modification of the initialization 1 which CPU of a main control part performs.

Explanation of symbols

1 slot machine 2L, 2C, 2R reel 40 game control board 41 main control unit 41a CPU
41b ROM
41c RAM
42 Random number generation circuit 43 Sampling circuit 48 Power interruption detection circuit 80 Production relay board 90 Production control board 91 Sub-control unit 91a CPU
91b ROM
91c RAM

Claims (1)

A game can be started by setting a predetermined number of bets for one game, and a display result of a variable display device capable of variably displaying a plurality of types of identification information each identifiable can be derived and displayed. 1 is a slot machine in which one game is completed and a winning can be generated according to the display result of the variable display device,
A main control means for controlling a game, comprising a microcomputer having an interrupt input terminal for generating an external interrupt when a signal is input;
Sub-control means for controlling production based on reception of control information transmitted from the main control means;
A power interruption detection means for monitoring a state of a predetermined power used in the slot machine and outputting a power interruption signal when a power interruption condition relating to the interruption of power supply is established;
With
The power interruption detection means outputs the power interruption signal to the interrupt input terminal of a microcomputer constituting the main control means,
The main control means includes
A storage means for storing data in a readable and writable manner and capable of holding data stored in the storage area even when power supply is stopped; A work area for storing data for operation of the microcomputer constituting the means, a stack area capable of temporarily storing data, and the microcomputer constituting the main control means for operation An unused area in which no data is read or written, and at least a main data storage means allocated;
Initialization means for initializing the unused area other than the stack area in the storage area of the main data storage means for each game;
Timer interrupt processing execution means for interrupting a process being executed every predetermined unit time and executing a timer interrupt process;
Branch counter updating means for updating a branch counter value for identifying a process to be executed in the timer interrupt process according to the execution of the timer interrupt process;
A plurality of types of processing executed in the timer interrupt processing, including processing for monitoring the input state of the operation detecting means for detecting the player's operation and storing the input information indicating the input state in the main data storage means A process selection means for selecting a process corresponding to the branch counter value as a process to be executed in the timer interrupt process,
Control before power supply stops the control state of the main control means when power supply is started in response to the occurrence of an external interrupt based on the input of the power interruption signal to the interrupt input terminal Power interruption interruption processing execution means for executing power interruption interruption processing for storing information necessary for returning to the state in the storage area of the main data storage means ;
Multiple interrupt prohibiting means for prohibiting the other interrupt process during the execution of either the timer interrupt process or the power interruption interrupt process,
The input information stored in the timer interrupt process is read, and a basic process for controlling one game is executed by gradually shifting a plurality of control states according to the progress of the game based on the read input information. Basic processing execution means to
Control information storage means that is a storage area assigned to the work area of the main data storage means and can store a plurality of the control information;
Control information generating means for generating the control information in accordance with the progress of the game in the basic processing and storing the control information in the control information storing means;
Control information transmission processing means for performing control information transmission processing for transmitting control information stored in the control information storage means to the sub-control means in the timer interrupt processing;
Including
The power interruption interrupt processing execution means waits for completion of the timer interruption processing being executed when the external interruption occurs during execution of the timer interruption processing. Run
The control information transmission processing means performs the control information transmission processing only once when the branching counter value indicates a specific value in the timer interrupt processing, and the control information storage means includes a plurality of the control information. A slot machine that, when stored, transmits only control information generated at the earliest time among the plurality of control information stored in the control information storage means in the control information transmission process.

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