JP4298009B2 - Method for manufacturing SOI substrate and method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing an SOI (Silicon on Insulator) substrate having a single crystal semiconductor thin film on a substrate having an insulating surface. The present invention also relates to a method for manufacturing a semiconductor device including a thin film transistor (hereinafter referred to as a TFT) formed using such an SOI substrate.
[0002]
Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Accordingly, an electro-optical device typified by a liquid crystal display device or a photoelectric conversion device, a semiconductor circuit in which TFTs are integrated, and an electronic device including such an electro-optical device or semiconductor circuit as a component are also semiconductor devices.
[0003]
[Prior art]
In recent years, an SOI (Silicon on Insulator) structure that realizes low power consumption has attracted attention as VLSI technology has made great progress. This technique is a technique in which the active region (channel formation region) of an FET that has been conventionally formed of bulk single crystal silicon is thin film single crystal silicon.
[0004]
In an SOI substrate, a buried oxide film made of silicon oxide exists on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods are known for manufacturing such an SOI substrate. Recently, a bonded SOI substrate has attracted attention. A bonded SOI substrate, as its name suggests, realizes an SOI structure by bonding two silicon substrates. By using this technique, a single crystal silicon thin film can be formed on a ceramic substrate or the like.
[0005]
Among the bonded SOI substrates, a technique called ELTRAN (registered trademark of Canon Inc.) has recently attracted particular attention. This technique is a method for manufacturing an SOI substrate using selective etching of a porous silicon layer. The detailed technique of the ELTRAN method is detailed in “T.Yonehara, K. Sakaguchi and T. Hamaguchi: Appl. Phys. Lett. 43 [3], 253 (1983)”.
[0006]
[Problems to be solved by the invention]
In the conventional ELTRAN method, a single crystal silicon layer epitaxially grown on a porous silicon layer is used for a semiconductor element. However, if the thickness of the epitaxial silicon layer is reduced to a level of less than 50 nm, it becomes difficult to ensure a uniform thickness and film quality.
[0007]
The present invention provides means for solving the above problems, and an object of the present invention is to provide means for forming an extremely thin single crystal semiconductor thin film of 5 to 30 nm. It is another object of the present invention to provide a method for manufacturing a semiconductor device using an SOI substrate having such an extremely thin single crystal semiconductor thin film.
[0008]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
Forming a porous semiconductor layer on the first single crystal semiconductor substrate;
Forming a single crystal semiconductor layer by closing the vicinity of the surface of the porous semiconductor layer by performing a first heat treatment in a reducing atmosphere;
Forming a first silicon oxide layer on a main surface of the single crystal semiconductor layer;
Forming a second silicon oxide layer on the main surface of the second substrate;
Bonding the first single crystal semiconductor substrate and the second substrate by bonding the first silicon oxide layer and the second silicon oxide layer;
Grinding the first single crystal semiconductor substrate from the back side to expose the porous semiconductor layer; and
Removing the exposed porous semiconductor layer and exposing the single crystal semiconductor layer;
It is characterized by having.
[0009]
The present invention is a technique for improving the conventional ELTRAN method, and is for forming an extremely thin single crystal semiconductor thin film of 5 to 30 nm (typically 5 to 10 nm). Note that the single crystal semiconductor thin film includes not only a single crystal silicon thin film but also a single crystal silicon germanium thin film.
[0010]
In the conventional ELTRAN method, after forming a porous silicon layer, heat treatment is performed in a hydrogen atmosphere to flatten the surface of the porous silicon layer. At this time, the natural oxide film is reduced and removed on the surface of the porous silicon layer, and accelerated surface diffusion of silicon atoms occurs with the driving ability to minimize the surface energy. As a result, surface holes (fine vacancies observed on the surface) disappear near the surface of the porous silicon layer.
[0011]
This means a state in which individual surface holes are blocked by silicon atoms in the vicinity of the surface of the porous silicon layer, and the surface holes are not observed. Therefore, the porous silicon layer remains as it is in a portion deeper than the vicinity of the surface.
[0012]
Conventionally, after that, the single crystal semiconductor layer is epitaxially grown thereafter to obtain a single crystal semiconductor thin film. However, in the present invention, an extremely thin single crystal semiconductor thin film formed by blocking the surface holes of the porous semiconductor layer is used as it is. It is characterized in that it is used as an active layer of a thin film transistor. That is, it differs greatly from the conventional ELTRAN method in that there is no step of epitaxially growing a semiconductor thin film.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described in detail with the examples described below.
[0014]
【Example】
Example 1
The configuration of the present invention will be described with reference to FIG. First, a single crystal silicon substrate 101 is prepared as a first substrate. Although a P-type substrate is used here, an N-type substrate may be used. Of course, a single crystal silicon germanium substrate can also be used.
[0015]
Next, the porous silicon layer 102 is formed by anodizing the main surface. The anodizing step may be performed in a mixed solution of hydrofluoric acid and ethanol. The porous silicon layer 102 is considered to be a single crystal silicon layer in which columnar surface holes are provided with a surface density of about 10 ¹¹ pieces / cm ³ , and inherits the crystal state (orientation, etc.) of the single crystal silicon substrate 101 as it is. Since the ELTRAN method itself is known, a detailed description is omitted here.
[0016]
When the porous silicon layer 102 is formed, a heat treatment step in a temperature range of 900 to 1200 ° C. (preferably 1000 to 1150 ° C.) is performed in a reducing atmosphere. Here, heat treatment is performed at 1050 ° C. for 2 hours in a hydrogen atmosphere. (Fig. 1 (A))
[0017]
The reducing atmosphere is preferably a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or hydrogen and argon), but the surface of the crystalline silicon film can be planarized even in an inert atmosphere. It is. However, it is preferable to reduce the natural oxide film by using the reducing action because many silicon atoms with high energy are generated and as a result, the planarization effect is enhanced.
[0018]
However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the hydrogen reduction reaction will not occur.
[0019]
At this time, in the vicinity of the surface of the porous silicon layer 102 (from the main surface to a depth of 5 to 30 nm, typically about 5 to 10 nm), the surface holes are blocked by the movement of silicon atoms, and as a result, an extremely thin single crystal A silicon layer 103 is formed.
[0020]
When the single crystal silicon layer 103 is formed, the vicinity of the surface is oxidized to form an extremely thin silicon oxide layer (first silicon oxide layer) 104. The silicon oxide layer 104 needs to be formed with care so that the single crystal silicon layer 103 is not lost. As a formation method, thermal oxidation, plasma oxidation, laser oxidation, or the like can be used, but microwave-excited plasma oxidation is suitable for forming an extremely thin silicon oxide layer. It is sufficient that the silicon oxide layer 104 has a thickness of 5 to 15 nm. (Fig. 1 (B))
[0021]
Next, a ceramic substrate 106 is prepared as a second substrate. Instead of ceramic substrate, quartz substrate, glass ceramic substrate, semiconductor substrate (including single crystal and polycrystal)
Then, a second silicon oxide layer 107 is formed on the main surface. As a method for forming the second silicon oxide layer 107, a vapor phase method such as a low pressure thermal CVD method, a sputtering method, a plasma CVD method or the like may be used. If the second substrate is a semiconductor substrate (for example, a silicon substrate), a thermal oxidation method is used. Alternatively, a plasma oxidation method may be used.
[0023]
When the preparation of the first substrate and the second substrate is thus completed, the two substrates are bonded together so that their main surfaces face each other. In this case, the first silicon oxide layer 104 and the second silicon oxide layer 107 are bonded. (Figure 1 (C))
[0024]
When the bonding is completed, a heat treatment step is then performed at a temperature of 1050 to 1150 ° C. to stabilize the bonding interface made of silicon oxides. In this embodiment, this heat treatment step is performed at 1100 ° C. for 2 hours. In addition, what is shown with the dotted line is the bonding interface completely bonded. Further, the buried insulating layer 108 composed of the first silicon oxide layer and the second silicon oxide layer finally functions as a buried insulating layer of the SOI substrate. (Figure 1 (D))
[0025]
Next, the single crystal silicon substrate 101 is ground from the back side by mechanical polishing such as CMP, and the grinding process is terminated when the porous silicon layer 102 is exposed. In this way, the state of FIG.
[0026]
Next, the porous silicon layer 102 is selectively removed by wet etching. The etchant used is preferably a mixed solution of a hydrofluoric acid aqueous solution and a hydrogen peroxide aqueous solution. It has been reported that a solution in which 49% HF and 30% H ₂ O ₂ are mixed at a ratio of 1: 5 has a selectivity ratio of 100,000 times or more between the single crystal silicon layer and the porous silicon layer.
[0027]
In this way, the state of FIG. In this state, a buried insulating layer 108 is provided on the ceramic substrate 106, and a single crystal silicon layer 109 is formed thereon.
[0028]
Although the SOI substrate is completed at this point, since there are minute irregularities on the surface of the single crystal silicon layer 109, it is desirable to perform planarization by performing a heat treatment step in a hydrogen atmosphere. As described above, this flattening phenomenon is due to accelerated surface diffusion of silicon atoms by reducing the natural oxide film.
[0030]
Thus, an extremely thin single crystal silicon thin film having a thickness of 5 to 30 nm (typically 5 to 10 nm) can be obtained. When forming a TFT, the thickness of the active layer can be reduced to reduce the off-current value (corresponding to the leakage current when the TFT is in the off state), but the semiconductor thin film of the present invention is sufficiently The effect can be demonstrated.
[0031]
(Example 2)
In this example, the case where a TFT is manufactured using an island-shaped semiconductor layer formed using the structure of Example 1 will be described with reference to FIGS.
[0032]
First, an SOI substrate is formed through the steps shown in the first embodiment. Reference numeral 301 denotes a substrate having an insulating surface, which actually has a structure in which a buried insulating layer is provided on a silicon substrate or a ceramic substrate. After the SOI substrate is obtained, the island-like silicon layer 302 is formed by patterning the single crystal silicon layer.
[0033]
Next, a thermal oxidation process is performed to form a silicon oxide film 303 having a thickness of 10 nm on the surface of the island-like silicon layer 302. This silicon oxide film 303 functions as a gate insulating film. After the gate insulating film 303 is formed, a conductive polysilicon film is formed thereon, and a gate wiring 304 is formed by patterning. (Fig. 3 (A))
[0034]
In this embodiment, a polysilicon film having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use a tantalum, a tantalum alloy, or a laminated film of tantalum and tantalum nitride to lower the resistance of the gate wiring. Furthermore, if a low resistance gate wiring is aimed, it is effective to use copper or a copper alloy.
[0035]
When the state of FIG. 3A is obtained, an impurity region 306 is formed by adding an impurity imparting N-type conductivity or P-type conductivity. The impurity concentration in the LDD region is determined later by the impurity concentration at this time. In this embodiment, arsenic is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ , but neither the impurity nor the concentration need be limited to this embodiment.
[0036]
Next, a thin silicon oxide film 307 of about 5 to 10 nm is formed on the surface of the gate wiring. This may be formed using a thermal oxidation method or a plasma oxidation method. The formation of the silicon oxide film 307 has the purpose of functioning as an etching stopper in the next sidewall formation step.
[0037]
After the silicon oxide film 307 serving as an etching stopper is formed, a silicon nitride film is formed and etched back to form sidewalls 308. In this way, the state of FIG.
[0038]
In this embodiment, a silicon nitride film is used as the sidewall, but a polysilicon film or an amorphous silicon film can also be used. Of course, if the material of the gate wiring changes, it goes without saying that the range of selection of materials that can be used as sidewalls also increases accordingly.
[0039]
Next, an impurity having the same conductivity type as before is added again. The impurity concentration added at this time is higher than that in the previous step. In this embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to be limited to this. By this impurity addition step, a source region 309, a drain region 310, an LDD region 311 and a channel formation region 312 are defined. (Figure 3 (C))
[0040]
When each impurity region is thus formed, the impurity is activated by means such as furnace annealing, laser annealing or lamp annealing.
[0041]
Next, the silicon oxide film formed on the surfaces of the gate wiring 304, the source region 309, and the drain region 310 is removed, and the surfaces thereof are exposed. Then, a cobalt film 313 having a thickness of about 5 nm is formed and a heat treatment process is performed. By this heat treatment, a reaction between cobalt and silicon occurs, and a silicide layer (cobalt silicide layer) 314 is formed. (Fig. 3 (D))
[0042]
This technique is a known salicide technique. Therefore, titanium or tungsten may be used instead of cobalt, and heat treatment conditions may be referred to known techniques. In this embodiment, the heat treatment process is performed using lamp annealing.
[0043]
When the silicide layer 314 is thus formed, the cobalt film 313 is removed. Thereafter, an interlayer insulating film 315 having a thickness of 1 μm is formed. As the interlayer insulating film 315, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film may be used. Further, these insulating films may be stacked.
[0044]
Next, contact holes are formed in the interlayer insulating film 315 to form source wirings 316 and drain wirings 317 made of a material containing aluminum as a main component. Finally, furnace annealing is performed on the entire device in a hydrogen atmosphere at 300 ° C. for 2 hours to complete the hydrogenation.
[0045]
In this way, a TFT as shown in FIG. 3E is obtained. Note that the structure described in this embodiment is merely an example, and the TFT structure to which the present invention can be applied is not limited thereto. Therefore, the present invention can be applied to any known TFT structure.
[0046]
Needless to say, the present invention can be easily applied not only to the top gate structure but also to a bottom gate structure typified by an inverted staggered TFT.
[0047]
In this embodiment, an N-channel TFT is described as an example, but a P-channel TFT can be easily manufactured. Further, an N-channel TFT and a P-channel TFT can be formed on the same substrate and complementarily combined to form a CMOS circuit.
[0048]
Further, if a pixel electrode (not shown) electrically connected to the drain wiring 317 in the structure of FIG. 3E is formed by a known means, it is easy to form a pixel switching element of an active matrix display device. is there.
[0049]
That is, the present invention is a very effective technique as a method for manufacturing an electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.
[0050]
(Example 3)
In this embodiment, an example in which a single crystal silicon thin film is formed by a method different from that in Embodiment 1 will be described. FIG. 7 is used for the description.
[0051]
In this embodiment, a porous silicon layer 702 is formed on an N-type or P-type single crystal silicon substrate 701 by an anodic oxidation method similar to that in Embodiment 1. Then, an amorphous silicon layer 703 is formed on the porous silicon layer 702. As a method for forming the amorphous silicon layer 703, any one of a low pressure thermal CVD method, a plasma CVD method, and a sputtering method may be used.
[0052]
The film thickness of the amorphous silicon layer 703 may be 15 to 100 nm (typically 25 to 70 nm).
[0053]
When an amorphous silicon layer is formed on the porous silicon layer as in this embodiment, the amorphous silicon is filled inside the surface holes of the porous silicon layer (however, to a depth of about 10 to 50 nm from the main surface). This is as shown in the enlarged view surrounded by the dotted line in FIG.
[0054]
Next, after the amorphous silicon layer 703 is provided, a heat treatment step in a reducing atmosphere (in this embodiment, 1100 ° C. for 1 hour in a hydrogen atmosphere) is performed. In this step, the amorphous silicon layer 703 is crystallized. At this time, the crystallization proceeds reflecting the crystal state of the porous silicon layer 702, and as a result, the single crystal silicon layer 704 can be obtained. Of course, the heat treatment process may be performed using other conditions shown in the first embodiment.
[0055]
After the single crystal silicon layer 704 is formed in this way, an SOI substrate having a single crystal silicon layer is manufactured according to the steps of Embodiment 1 and then a TFT is formed according to the steps of Embodiment 2. Then, various semiconductor devices may be manufactured by assembling a circuit on the substrate with the TFT.
[0056]
(Example 4)
In this embodiment, an example in which a single crystal silicon layer is selectively formed over a porous silicon layer will be described. FIG. 8 is used for the description.
[0057]
First, a porous silicon layer 802 is formed on a single crystal silicon substrate 801 according to the first embodiment. Then, the porous silicon layer 802 is exposed to plasma formed in an oxygen atmosphere to form a silicon oxide layer 803 having a thickness of 50 nm on the surface. This process is called a plasma oxidation process. (Fig. 8 (A))
[0058]
The film thickness of the silicon oxide layer 803 may be 50 to 100 nm. In this embodiment, the plasma oxidation method is used. However, a thermal oxidation method may be used, and a CVD method or a sputtering method may be used.
[0059]
Further, in this embodiment, the silicon oxide layer is described as an example, but a silicon nitride layer or a silicon oxynitride layer (indicated by SiOxNy) may be formed by a CVD method or a sputtering method.
[0060]
Next, the silicon oxide layer 803 is patterned to form a mask 804. Note that the etching of the silicon oxide layer 803 is preferably a wet etching process using a hydrofluoric acid aqueous solution. If the aqueous hydrofluoric acid solution is used, the silicon oxide layer 803 can be etched without substantially etching the porous silicon layer 802.
[0061]
In addition, an opening 805 is formed simultaneously with the mask 804. This opening 805 is provided in a place where a single crystal silicon layer is formed later. (Fig. 8 (B))
[0062]
8B is obtained, a main surface of the porous silicon layer 802 exposed at the opening 805 is obtained by performing a heat treatment step at 1150 ° C. for 1 hour in an atmosphere in which 3% hydrogen is added to a nitrogen atmosphere. A single crystal silicon layer 806 is formed in the vicinity (a region where the mask 804 is not formed). Detailed heat treatment conditions may be in accordance with Example 1. (Fig. 8 (C))
[0063]
Since the single crystal silicon layer 806 thus formed is selectively formed, there is no need to pattern as an active layer later.
[0064]
Next, after removing the mask 804, a silicon oxide film 807 necessary for the bonding process is formed. In this step, an extremely thin silicon oxide layer of about 5 to 10 nm may be formed. Therefore, a means that can form a silicon oxide film as thin as possible with good controllability is desirable. In this sense, the plasma oxidation method is most preferable. Of course, a thermal oxidation method may be used, or a film may be formed using a CVD method or a sputtering method. (Fig. 8 (D))
[0065]
After the state shown in FIG. 8D is obtained in this way, an SOI substrate having a single crystal silicon layer is manufactured by bonding to a second substrate having an insulating surface in accordance with the steps of Embodiment 1, and then the steps of Embodiment 2. A TFT may be formed according to the above. Then, various semiconductor devices may be manufactured by assembling a circuit on the substrate with the TFT.
[0066]
(Example 5)
In this embodiment, an example of a reflective liquid crystal display device manufactured using the SOI substrate of the present invention is shown in FIG. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.
[0067]
In FIG. 4A, 11 is a substrate having an insulating surface, 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is signal processing. Circuit. As the signal processing circuit 17, it is possible to form a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC. Of course, it is also possible to provide an IC chip on a glass substrate and perform signal processing on the IC chip.
[0068]
Further, in this embodiment, the liquid crystal display device is described as an example, but the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromic) display device as long as it is an active matrix display device. It goes without saying that it is also possible to do.
[0069]
Here, FIG. 4B shows an example of a circuit constituting the driver circuits 13 and 14 in FIG. Since the TFT portion has already been described in Embodiment 2, only necessary portions will be described here.
[0070]
In FIG. 4B, 401 and 402 are N-channel TFTs, and 403 is a P-channel TFT. The TFTs 401 and 403 constitute a CMOS circuit. Reference numeral 404 denotes an insulating layer made of a laminated film of silicon nitride film / silicon oxide film / resin film, and a titanium wiring 405 is provided on the insulating layer, and the aforementioned CMOS circuit and TFT 402 are electrically connected. The titanium wiring is further covered with an insulating layer 406 made of a resin film. The two insulating layers 404 and 406 also have a function as a planarization film.
[0071]
FIG. 4C illustrates part of a circuit included in the pixel matrix circuit 12 in FIG. In FIG. 4C, reference numeral 407 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 408 is formed so as to spread widely in the pixel region.
[0072]
An insulating layer 404 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is dropped into a part of the insulating layer 404, and only the lowermost silicon nitride and silicon oxide are left. As a result, an auxiliary capacitance is formed between the drain wiring 408 and the titanium wiring 405.
[0073]
Further, the titanium wiring 405 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, it functions as a black mask in the gaps between a plurality of pixel electrodes.
[0074]
An insulating layer 406 is provided to cover the titanium wiring 405, and a pixel electrode 409 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 409 may be devised to increase the reflectance.
[0075]
In practice, an alignment film or a liquid crystal layer is provided on the pixel electrode 409, but the description thereof is omitted here.
[0076]
A reflection type liquid crystal display device having the above-described configuration can be manufactured using the present invention. Needless to say, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique. Further, an active matrix EL display device can be easily manufactured by combining with a known technique.
[0077]
(Example 6)
The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on a single chip, or from a signal processing circuit such as a D / A converter to a portable device (cell phone, PHS, mobile computer). You may apply to a high frequency circuit.
[0078]
FIG. 5 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.
[0079]
Needless to say, the microprocessor shown in FIG. 5 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on its application.
[0080]
However, it is an IC (Integrated Circuit) 28 that functions as the center of a microprocessor having any function. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected with ceramic or the like.
[0081]
The N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention constitute an integrated circuit formed on the semiconductor chip 29. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.
[0082]
The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.
[0083]
(Example 7)
The electro-optical device of the present invention is used as a display of various electronic devices. Such electronic devices include video cameras, still cameras, projectors, projection TVs, head mounted displays, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones, etc.), etc.
FIG. 6A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, an operation switch 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.
[0085]
FIG. 6B illustrates a video camera which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention is applied to a display device 2102, a voice input unit 2103, and other signal controls.
FIG. 6C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0087]
FIG. 6D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The present invention can be applied to the display device 2302 and other signal control circuits.
[0088]
FIG. 6E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.
[0089]
FIG. 6F illustrates a front type projector which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The present invention can be applied to the display device 2503 and other signal control circuits.
[0090]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.
[0091]
【The invention's effect】
By implementing the present invention, it is possible to realize an SOI substrate having an extremely thin single crystal silicon thin film of 5 to 30 nm (typically 5 to 10 nm) which cannot be achieved by the conventional ELTRAN method.
[0092]
Then, it is possible to manufacture a thin film transistor with high performance and a small off-current value using the SOI substrate, and it is possible to improve the performance of all semiconductor devices in which a circuit is assembled with a plurality of TFTs.
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of an SOI substrate. FIGS.
FIGS. 2A and 2B illustrate a manufacturing process of an SOI substrate. FIGS.
FIG. 3 is a view showing a manufacturing process of a TFT.
FIG. 4 is a diagram showing a configuration of a semiconductor device (electro-optical device).
FIG. 5 illustrates a structure of a semiconductor device (semiconductor circuit).
FIG. 6 illustrates a structure of a semiconductor device (electronic device).
FIGS. 7A to 7C illustrate a manufacturing process of an SOI substrate. FIGS.
FIGS. 8A and 8B illustrate a manufacturing process of an SOI substrate. FIGS.

Claims (2)

Forming a porous silicon layer on a single crystal silicon substrate as a first substrate;
Plasma oxidation is performed on the porous silicon layer to form a silicon oxide layer,
Etching a portion of the silicon oxide layer to form a mask and an opening;
A single crystal silicon layer is formed near the surface of the porous silicon layer in the opening by performing a heat treatment in a nitrogen atmosphere containing hydrogen,
Removing the mask,
Plasma oxidation is performed near the surface of the single crystal silicon layer to form a first silicon oxide layer,
Forming a second silicon oxide layer on the main surface of the second substrate;
Bonding the first substrate and the second substrate by bonding the first silicon oxide layer and the second silicon oxide layer;
Grinding the first substrate from the back side to expose the porous silicon layer;
Removing the exposed porous silicon layer to expose the single crystal silicon layer;
A method for manufacturing an SOI substrate, wherein the single crystal silicon layer exposed by heat treatment in a hydrogen atmosphere is planarized to form a single crystal silicon film having a thickness of 5 to 30 nm. Forming a porous silicon layer on a single crystal silicon substrate as a first substrate;
Plasma oxidation is performed on the porous silicon layer to form a silicon oxide layer,
Etching a portion of the silicon oxide layer to form a mask and an opening;
A single crystal silicon layer is formed near the surface of the porous silicon layer in the opening by performing a heat treatment in a nitrogen atmosphere containing hydrogen,
Removing the mask,
Plasma oxidation is performed near the surface of the single crystal silicon layer to form a first silicon oxide layer,
Forming a second silicon oxide layer on the main surface of the second substrate;
Bonding the first substrate and the second substrate by bonding the first silicon oxide layer and the second silicon oxide layer;
Grinding the first substrate from the back side to expose the porous silicon layer;
Removing the exposed porous silicon layer to expose the single crystal silicon layer;
The single crystal silicon layer exposed by performing a heat treatment in a hydrogen atmosphere is planarized to form a single crystal silicon film having a thickness of 5 to 30 nm,
A method for manufacturing a semiconductor device, wherein the single crystal silicon film is used as an island-shaped silicon layer to form a plurality of thin film transistors.

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