JP4282582B2 - Information processing apparatus and program used in the same apparatus - Google Patents

Description

  The present invention relates to an information processing apparatus such as a personal computer and a decoding program used in the apparatus.

  In recent years, personal computers having the same AV function as audio / video (AV) devices such as DVD (Digital Versatile Disc) players and TV devices have been developed.

  In such a personal computer, a software decoder that decodes a compression-coded moving image stream by software is used. By using a software decoder, it is possible to decode a compression-coded moving image stream by a processor (CPU) without providing dedicated hardware.

As a typical compression coding technique, motion compensation interframe predictive coding is known. As a system that performs motion compensation interframe predictive coding, a system that generates a predicted image using an image with decimal pixel accuracy is known (see, for example, Patent Document 1). In this system, in order to reduce the processing amount required for pixel interpolation processing, when decoding a B picture, a reference screen is used by using a filter having a smaller number of taps than a filter used when decoding a P picture. The pixel interpolation process is performed.
JP 2003-169337 A

  However, in the above system, when decoding a B picture, a filter with a small number of taps is always used.

  Recently, as a next-generation moving image compression coding technology, H.264 has been introduced. The H.264 / AVC (AVC: Advanced Video Coding) standard has attracted attention. H. The H.264 / AVC standard is a compression encoding technique that is more efficient than conventional compression encoding techniques such as MPEG2 and MPEG4, and is used for encoding high-definition images such as HD (High Definition). For this reason, H.C. Each of the encoding process and the decoding process corresponding to the H.264 / AVC standard requires a larger amount of processing than the conventional compression encoding techniques such as MPEG2 and MPEG4.

  Therefore, H.H. In a personal computer designed to decode a moving image stream compression-encoded by the H.264 / AVC standard by software, high-definition images can be reproduced. However, when the load on the system increases, the decoding process itself is performed. There is a risk that a delay occurs, which prevents smooth video playback.

  The present invention has been made in consideration of the above-described circumstances, and provides an information processing apparatus and program capable of automatically switching between moving image reproduction with priority on image quality and reproduction of moving image with priority on smoothness over image quality. For the purpose.

  In order to solve the above-described problem, the present invention includes an information processing apparatus for decoding a compression-coded moving image stream, means for performing pixel interpolation processing on the decoded screen, and the moving image stream. Based on motion vector information, motion compensation means for generating a motion compensation inter-frame prediction signal corresponding to the decoding target screen from the pixel-interpolated screen, and a prediction error signal corresponding to the decoding target screen to the decoding target screen Means for adding the motion compensated inter-frame prediction signal corresponding to the above, decoding the screen to be decoded, load detecting means for detecting the load of the information processing device, and the load detected by the load detecting means being a predetermined reference If the value is greater than the value, the content of the pixel interpolation process is changed so that the load on the information processing apparatus is reduced. Characterized by comprising a control means.

  According to the present invention, it is possible to automatically switch between video playback with priority on image quality and video playback with priority on smoothness over image quality.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the configuration of an information processing apparatus according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. This information processing apparatus is realized as, for example, a notebook personal computer 10.

  FIG. 1 is a front view of the notebook personal computer 10 with the display unit opened. The computer 10 includes a computer main body 11 and a display unit 12. The display unit 12 incorporates a display device composed of an LCD (Liquid Crystal Display) 17, and the display screen of the LCD 17 is positioned substantially at the center of the display unit 12.

  The display unit 12 is attached to the computer main body 11 so as to be rotatable between an open position and a closed position. The computer main body 11 has a thin box-shaped casing, and a keyboard 13, a power button 14 for turning on / off the computer 1, an input operation panel 15, and a touch pad 16 are arranged on the upper surface. Has been.

  The input operation panel 15 is an input device that inputs an event corresponding to a pressed button, and includes a plurality of buttons for starting a plurality of functions. These button groups also include a TV start button 15A and a DVD (Digital Versatile Disc) start button 15B. The TV activation button 15A is a button for activating a TV function for reproducing and recording broadcast program data such as a digital TV broadcast program. When the TV activation button 15A is pressed by the user, an application program for executing the TV function is automatically activated. The DVD start button 15B is a button for playing back video content recorded on a DVD. When the DVD activation button 15B is pressed by the user, an application program for reproducing video content is automatically activated.

  Next, the system configuration of the computer 10 will be described with reference to FIG.

  As shown in FIG. 2, the computer 10 includes a CPU 111, a north bridge 112, a main memory 113, a graphics controller 114, a south bridge 119, a BIOS-ROM 120, a hard disk drive (HDD) 121, and an optical disk drive (ODD) 122. , A digital TV broadcast tuner 123, an embedded controller / keyboard controller IC (EC / KBC) 124, a network controller 125, and the like.

  The CPU 111 is a processor provided to control the operation of the computer 10, and various types such as an operating system (OS) and a video playback application program 201 loaded from the hard disk drive (HDD) 121 to the main memory 113. Run the application program.

  The video reproduction application program 201 is software for decoding and reproducing the compression-coded moving image data. This video playback application program 201 is an H.264 file. This is a software decoder corresponding to the H.264 / AVC standard. The video playback application program 201 is an H.264 file. A moving image stream (for example, a digital TV broadcast program received by the digital TV broadcast tuner 123, an HD (High) read out from the optical disc drive (ODD) 122) that is compressed and encoded by the encoding method defined in the H.264 / AVC standard. Definition) standard video content, etc.).

  As shown in FIG. 3, the video playback application program 201 includes a load detection module 211, a decode control module 212, and a decode execution module 213.

  The decode execution module 213 is an H.264 implementation. It is a decoder that executes a decoding process defined in the H.264 / AVC standard. The load detection module 211 is a module that detects the load of the computer 10. For example, the load detection module 211 detects the current load amount of the computer 10 by inquiring the current load of the computer 10 to the operating system (OS) 200. The load amount of the computer 10 is determined based on the usage rate of the CPU 111, for example.

  Further, the load amount of the computer 10 can be determined by a combination of the usage rate of the CPU 111 and the usage rate of the memory 113. Usually, in order to smoothly execute the software decoder, a memory having a certain size or more is required. As the memory usage rate of the system increases, the decoding performance of the software decoder decreases due to paging of the OS. Therefore, by detecting the load amount of the computer 10 based on the combination of the usage rate of the CPU 111 and the usage rate of the memory 113, the current load amount of the computer 10 interferes with the execution of the software decoder (high load state). ) Can be more accurately determined.

  The decode control module 212 controls the content of the decoding process executed by the decode execution module 213 according to the load on the computer 10 detected by the load detection module 211.

  Specifically, when the load amount of the computer 10 is equal to or less than a predetermined reference value, the decode control module 212 determines the H.264 standard. The contents of the decoding process to be executed by the decoding execution module 213 are controlled so that the decoding process defined by the H.264 / AVC standard is executed by the CPU 111. On the other hand, when the load amount of the computer 10 is larger than the reference value (high load state), the decode control module 212 determines that the H.264 is in the H.264 standard. The content of the decoding process to be executed by the decoding execution module 213 is controlled so that a part of the decoding process defined in the H.264 / AVC standard is replaced with a process that is omitted or simplified.

  The moving image data decoded by the video playback application program 201 is sequentially written into the video memory 114A of the graphics controller 114 via the display driver 202. As a result, the decoded moving image data is displayed on the LCD 17. The display driver 202 is software for controlling the graphics controller 114.

  The CPU 111 also executes a system BIOS (Basic Input Output System) stored in the BIOS-ROM 120. The system BIOS is a program for hardware control.

  The north bridge 112 is a bridge device that connects the local bus of the CPU 111 and the south bridge 119. The north bridge 112 also includes a memory controller that controls access to the main memory 113. The north bridge 112 also has a function of executing communication with the graphics controller 114 via an AGP (Accelerated Graphics Port) bus or the like.

  The graphics controller 114 is a display controller that controls the LCD 17 used as a display monitor of the computer 10. The graphics controller 114 generates a display signal to be sent to the LCD 17 from the image data written in the video memory (VRAM) 114A.

  The south bridge 119 controls each device on an LPC (Low Pin Count) bus and each device on a PCI (Peripheral Component Interconnect) bus. The south bridge 119 incorporates an IDE (Integrated Drive Electronics) controller for controlling the HDD 121 and the ODD 122. Further, the south bridge 119 has a function of controlling the digital TV broadcast tuner 123 and a function of controlling access to the BIOS-ROM 120.

  The HDD 121 is a storage device that stores various software and data. The optical disk drive (ODD) 123 is a drive unit for driving a storage medium such as a DVD in which video content is stored. The digital TV broadcast tuner 123 is a receiving device for receiving broadcast program data such as a digital TV broadcast program from the outside.

  The embedded controller / keyboard controller IC (EC / KBC) 124 is a one-chip microcomputer in which an embedded controller for power management and a keyboard controller for controlling the keyboard (KB) 13 and the touch pad 16 are integrated. . The embedded controller / keyboard controller IC (EC / KBC) 124 has a function of powering on / off the computer 10 in accordance with the operation of the power button 14 by the user. Furthermore, the embedded controller / keyboard controller IC (EC / KBC) 124 can also power on the computer 10 in accordance with the operation of the TV start button 15A and the DVD start button 15B by the user. The network controller 125 is a communication device that executes communication with an external network such as the Internet.

  Next, the functional configuration of the software decoder realized by the video playback application program 201 will be described with reference to FIG.

  The decode execution module 213 of the video playback application program 201 is an H.264 file. As shown in the figure, the entropy decoding unit 301, the inverse quantization unit 302, the inverse DCT unit (DCT: Discrete Cosine Transform) 303, the addition unit 304, the deblocking filter unit 305, the frame memory 306, a motion vector prediction unit 307, an interpolation prediction unit 308, a weighted prediction unit 309, an intra prediction unit 310, and a mode changeover switch unit 311. H. The H.264 orthogonal transform has integer precision and is different from the conventional DCT, but is referred to as DCT here.

  Each screen (picture) is encoded in units of macroblocks of 16 × 16 pixels, for example. For each macroblock, either the intraframe coding mode (intra coding mode) or the motion compensated interframe prediction coding mode (inter coding mode) is selected.

  In motion-compensated interframe predictive coding mode, motion-predicted interframe prediction signals corresponding to the current picture are generated in a defined shape unit by estimating the motion from the already coded picture (picture). Is done. A prediction error signal obtained by subtracting the motion compensation inter-frame prediction signal from the encoding target screen (picture) is encoded by orthogonal transform (DCT), quantization, and entropy encoding. Further, in the intra coding mode, a prediction signal is generated from a coding target screen (picture), and the prediction signal is encoded by orthogonal transform (DCT), quantization, and entropy coding.

H. In order to further increase the compression rate, the codec corresponding to the H.264 / AVC standard
(1) Motion compensation with higher pixel accuracy (1/4 pixel accuracy) than conventional MPEG (2) Intraframe prediction for efficient intraframe coding (3) Deblocking to reduce block distortion Filter (4) 4x4 pixel integer DCT
(5) A technique such as multi-reference frame (6) weighted prediction that can use a plurality of screens (pictures) at arbitrary positions as a reference screen is used.

  Hereinafter, the operation of the software decoder of FIG. 4 will be described.

  H. A moving image stream compression-encoded according to the H.264 / AVC standard is first input to the entropy decoding unit 301. In addition to encoded image information, motion vector information used in motion-compensated interframe prediction encoding (inter-prediction encoding), intra-frame prediction encoding (intra prediction encoding) Intraframe prediction information used in (encoding), mode information indicating a prediction mode (inter prediction encoding / intra prediction encoding), and the like are included.

  The decoding process is executed in units of macro blocks of 16 × 16 pixels, for example. The entropy decoding unit 301 performs entropy decoding processing such as variable length decoding on the moving image stream, and from the moving image stream, the quantized DCT coefficient, motion vector information (motion vector difference information), intra-frame prediction information, and Separate mode information. In this case, for example, each macroblock in the decoding target screen (picture) is subjected to entropy decoding processing for each block of 4 × 4 pixels (or 8 × 8 pixels), and each block is converted into 4 × 4 (or 8 × 8 pixels) quantized DCT coefficients. The In the following, it is assumed that each block is 4 × 4.

  The motion vector information is sent to the motion vector prediction unit 307. The intra-frame prediction information is sent to the intra prediction unit 310. The mode information is sent to the mode changeover switch unit 311.

  The 4 × 4 quantized DCT coefficients of each decoding target block are converted into 4 × 4 DCT coefficients (orthogonal transform coefficients) by the inverse quantization process by the inverse quantization unit 302. The 4 × 4 DCT coefficients are converted from frequency information into 4 × 4 pixel values by an inverse integer DCT (inverse orthogonal transform) process by the inverse DCT unit 303. This 4 × 4 pixel value is a prediction error signal corresponding to the decoding target block. This prediction error signal is sent to the adding unit 304, where a prediction signal (motion compensation inter-frame prediction signal or intra-frame prediction signal) corresponding to the decoding target block is added, and thereby a 4 × 4 pixel value corresponding to the decoding target block. Is decoded.

  In the intra prediction mode, the intra prediction unit 310 is selected by the mode changeover switch unit 311, and thereby the intraframe prediction signal from the intra prediction unit 310 is added to the prediction error signal. In the inter prediction mode, the weighted prediction unit 309 is selected by the mode changeover switch unit 311, and thereby the motion compensation interframe prediction signal obtained by the motion vector prediction unit 307, the interpolation prediction unit 308, and the weighted prediction unit 309. Is added to the prediction error signal.

  As described above, the process of adding the prediction signal (motion-compensated inter-frame prediction signal or intra-frame prediction signal) to the prediction error signal corresponding to the decoding target screen and decoding the decoding target screen is executed in predetermined block units.

  Each decoded screen (picture) is subjected to deblocking filter processing by the deblocking filter unit 305 and then stored in the frame memory 306. The deblocking filter unit 305 performs a deblocking filter process for reducing block noise on each decoded screen, for example, in units of 4 × 4 pixel blocks. This deblocking filter processing prevents block distortion from being included in the reference image, and thereby block distortion propagates to the decoded image. The amount of processing for the deblocking filter processing is enormous and may occupy 50% of the total processing amount of the software decoder. The deblocking filter process is adaptively executed such that a stronger filtering is performed on a portion where block distortion is likely to occur, and a weak filtering is performed on a portion where block distortion is less likely to occur. The deblocking filter process is realized by a loop filter process.

  Each screen subjected to the deblocking filter processing is read out from the frame memory 306 as an output image frame (or output image field). Each screen (reference screen) to be used as a reference image for motion compensation inter-frame prediction is held in the frame memory 306 for a certain period. H. In motion compensation interframe predictive coding according to the H.264 / AVC standard, a plurality of screens can be used as reference screens. For this reason, the frame memory 306 includes a plurality of frame memory units for storing images for a plurality of screens.

  The motion vector prediction unit 307 generates motion vector information based on the motion vector difference information corresponding to the decoding target block. The interpolation prediction unit 308 generates a motion compensation inter-frame prediction signal from the integer precision pixel group and the quarter pixel precision prediction interpolation pixel group in the reference screen based on the motion vector information corresponding to the decoding target block. To do. A 6-tap filter (six inputs, one output) is used in the generation of the prediction interpolation pixel with 1/4 pixel accuracy. For this reason, it is possible to execute highly accurate predictive interpolation processing considering even high frequency components. However, a large amount of processing is required for motion compensation.

  The weighted prediction unit 309 generates a weighted motion compensation inter-frame prediction signal by executing a process of multiplying the motion compensation inter-frame prediction signal by a weighting coefficient for each motion compensation block. This weighted prediction is a process for predicting the brightness of the decoding target screen. This weighted prediction process can improve the image quality of an image whose brightness changes over time, such as fade-in and fade-out. However, the amount of processing required for software decoding increases accordingly.

  The intra prediction unit 310 generates an intra-frame prediction signal of a decoding target block included in the screen from the decoding target screen. The intra prediction unit 310 performs intra-screen prediction processing according to the intra-frame prediction information described above, and exists in the same screen as the decoding target block, in other already decoded blocks close to the decoding target block. An intra-frame prediction signal is generated from the pixel value. This intra-frame prediction (intra prediction) is a technique for increasing the compression rate using pixel correlation between blocks. In this intraframe prediction, four types including vertical prediction (prediction mode 0), horizontal prediction (prediction mode 1), average value prediction (prediction mode 3), and plane prediction (prediction mode 4) are determined according to the intraframe prediction information. One of the prediction modes is selected in units of intra-frame prediction blocks (for example, 16 × 16 pixels). The frequency with which plane prediction is selected is lower than in other intra-frame prediction modes, but the amount of processing required for plane prediction is greater than the processing amount in any other intra-frame prediction mode.

  In the present embodiment, even if the load on the computer 10 increases, the decoding process (FIG. 4) described in FIG. Hereinafter, the normal decoding process) and the special decoding process are selectively executed. The special decoding process is a decoding process in which the content of the pixel interpolation process is simplified or omitted. Hereinafter, this special decoding process will be referred to as a special interpolation prediction decoding process.

  Hereinafter, the procedure of the decoding process executed by the video playback application program 201 will be described with reference to the flowchart of FIG.

  During the execution of the decoding process, the video playback application program 201 periodically and repeatedly executes a process for detecting the current load on the computer 10 by inquiring about the current load on the computer 10 from the OS (step S101). In this step S101, the video playback application program 201 acquires the current usage rate (processor usage rate) of the CPU 111 and the current usage rate (memory usage rate) of the main memory 113 from the OS.

  Then, the video reproduction application program 201 determines whether or not the computer 10 is in a high load state depending on whether or not the current load amount of the computer 10 is larger than a predetermined reference value (step S102). In step S102, for example, the video playback application program 201 determines whether or not the current processor usage rate is larger than a predetermined processor reference usage rate, and the current memory usage rate is a predetermined memory. It is determined whether it is larger than the reference usage rate. If any one of the current processor usage rate and the current memory usage rate is larger than the corresponding reference usage rate, the video playback application program 201 determines that the computer 10 is in a high load state. If both the current processor usage rate and the current memory usage rate are equal to or lower than the corresponding reference usage rate, the video playback application program 201 determines that the computer 10 is not in a high load state.

  If the computer 10 is not in a high load state (NO in step S102), the video playback application program 201 selects the above-described normal decoding process as the decoding process to be executed by the CPU 111, and thereby the series of sequences described in FIG. Processing is executed on the CPU 111 (step S103).

  In the normal decoding process, as shown in FIG. 6, the interpolation prediction unit 308 first uses a 6-tap filter (6 inputs, 1 output) from the reference screen to predict interpolation pixels (1/2 pixel accuracy). (1/2 pixel signal) is generated (step S201). After generating ½ pixel signals corresponding to all pixel positions with ½ pixel accuracy, the interpolation prediction unit 308 uses a 2-tap average value filter (two inputs, one output) to 1 A prediction interpolation pixel (1/4 pixel signal) with / 4 pixel accuracy is generated. After generating all ¼ pixel signals corresponding to all the pixel positions with ¼ pixel accuracy, the interpolation prediction unit 308 performs motion compensation processing using the generated ¼ pixel signal (step S203).

  Unless the computer 10 is in a high load state, that is, unless the decoding performance is deteriorated, the moving image stream is normally decoded by the decoding process.

  On the other hand, if the computer 10 is in a high-load state (YES in step S102), the video playback application program 201 selects the above-described special interpolation prediction decoding process as a decoding process to be executed by the CPU 111, thereby relating to the interpolation prediction. A decoding process in which the process is simplified or omitted is executed on the CPU 111 (step S104).

  The pixel interpolation process executed in the special interpolation prediction decoding process is divided into the following three types.

(A) Interpolation with 1/4 pixel accuracy is replaced with interpolation with 1/2 pixel accuracy.

(B) Replace the 6-tap filter with a 2-tap filter.

(C) No filter (ie integer pixel accuracy)
In the present embodiment, as shown in FIG. 7, the above methods (a), (b), and (c) are selectively executed according to the current load amount of the computer 10. The high load state is classified into three decode performance levels 1, 2, and 3. It shows a state in which the load on the computer increases in the order of levels 1, 2, and 3. If the current load corresponds to the decoding performance level 1 (YES in step S301), the interpolation prediction unit 308 selects the method (a) and generates a ½ pixel signal using a 6-tap filter. Processing is executed (step S302). Then, the interpolation prediction unit 308 performs motion compensation processing using the ½ pixel signal (Step S303). If the current load amount corresponds to decode performance level 2 (YES in step S304), the interpolation prediction unit 308 selects the method (b) above, and first uses a 2-tap filter to generate a 1/2 pixel signal. Then, a 1/4 pixel signal is generated using a 2-tap filter (step S305). Then, the interpolation prediction unit 308 performs motion compensation processing using the ¼ pixel signal (step S303). If the current load corresponds to the decoding performance level 3 (YES in step S306), the interpolation prediction unit 308 selects the above methods (a) and (b), and performs 1/2 pixel interpolation with a 2-tap filter. This is performed (step S307). If the current load is higher than the decoding performance level 3 (NO in step S306), the interpolation prediction unit 308 selects the method (c) and skips the pixel interpolation process (step S308). In this case, the interpolation prediction unit 308 performs the motion compensation process using the reference screen before the pixel interpolation process, that is, the integer pixel signal (step S303).

  In this way, by simplifying the contents of the pixel interpolation process or omitting the execution, the processing amount required for software decoding per screen can be reduced. Therefore, even if another program is executed during execution of software decoding and the computer 10 is in a high load state, the moving image data does not cause a problem such as dropped frames or extremely slow movement of the object. Can be smoothly and continuously executed.

  Note that if the content of the pixel interpolation process is simplified or omitted, the accuracy of motion compensation may be reduced. However, it is possible to display a moving image with sufficiently good visibility as compared with a case where frames are dropped or the movement of an object is extremely slow.

  Until the decoding of all the moving image streams is completed, the processing of steps S101 to S104 in FIG. 5 is repeatedly executed (step S105). When the load on the computer 10 is reduced, for example, when execution of another program is terminated, the decoding process is switched again from the special interpolation prediction decoding process to the normal decoding process.

  As described above, according to the present embodiment, it is possible to automatically switch between video playback with priority on image quality and video playback with priority on smoothness over image quality in accordance with the load on the computer 10. That is, when the system is in a low load state, the moving image can be displayed with high image quality by executing the normal decoding process. Also, when the system is in a heavy load state, changing the contents of pixel interpolation processing that requires a large amount of processing to reduce the load on the system will cause frame dropping and object movement to be extremely slow. Smooth video playback can be realized without incurring problems such as.

  Since all the decoding control processes described above are realized by a computer program, the same effect as that of the present embodiment can be easily realized simply by introducing this computer program into a normal computer through a computer-readable storage medium. be able to.

  Further, the software decoder of the present embodiment can be applied not only to a personal computer but also to a PDA, a mobile phone, and the like.

  Further, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine a component suitably in different embodiment.

1 is a perspective view showing an overview of a computer according to an embodiment of the present invention. The block diagram which shows the system configuration | structure of the computer of FIG. The block diagram which shows the function structure of the video reproduction application program used with the computer of FIG. The block diagram which shows the structure of the software decoder implement | achieved by the video reproduction application program of FIG. FIG. 4 is a flowchart showing a procedure of decoding processing executed by the video playback application program of FIG. 3. FIG. The flowchart which shows the example of the 1st interpolation prediction process performed by the video reproduction application program of FIG. The flowchart which shows the example of the 2nd interpolation prediction process performed by the video reproduction application program of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Computer, 111 ... CPU, 113 ... Memory, 114 ... Graphics controller, 201 ... Load detection module, 212 ... Decode control module, 213 ... Decode execution module, 301 ... Entropy decoding part, 302 ... Inverse quantization part, 303 ... Inverse DCT unit, 304 ... adding unit, 305 ... deblocking filter unit, 306 ... frame memory, 307 ... motion vector prediction unit, 308 ... interpolation prediction unit, 309 ... weighted prediction unit, 310 ... intra prediction unit, 311 ... mode Changeover switch part.

Claims (10)

In an information processing apparatus for decoding a compression-coded moving image stream,
First pixel interpolation processing means for performing pixel interpolation processing with a first decimal pixel accuracy on a decoded image using a filter with a first tap number ;
Second pixel interpolation processing means for performing pixel interpolation processing with a first pixel accuracy using a filter having a second tap number smaller than the first tap number on the decoded image ;
A third pixel that performs pixel interpolation processing with a second pixel accuracy smaller than the first pixel accuracy on the decoded image using a filter with a first tap number and a filter with the second tap number Interpolation processing means ;
Motion compensation means for generating a motion compensation inter-frame prediction signal corresponding to a decoding target image from the pixel-interpolated image based on motion vector information included in the moving image moving image stream;
Means for adding the motion compensation inter-frame prediction signal corresponding to the decoding target image to the prediction error signal corresponding to the decoding target image to decode the decoding target image;
The decoding process of the moving image stream is performed using any one of the first pixel interpolation processing unit, the second pixel interpolation processing unit, and the third pixel interpolation processing unit. the information processing apparatus characterized by comprising a control means for controlling whether. A fourth pixel interpolation processing unit that performs the second pixel precision pixel interpolation processing on the decoded image by using the second tap number filter processing a plurality of times;
The control means uses any one of the first pixel interpolation processing means, the second pixel interpolation processing means, the third pixel interpolation processing means, and the fourth pixel interpolation processing means as a pixel. The information processing apparatus according to claim 1, wherein the information processing apparatus controls whether to perform interpolation processing . The control means includes means for skipping execution of the pixel interpolation process,
The information processing apparatus according to claim 1, wherein the motion compensation unit generates a motion compensation inter-frame prediction signal corresponding to the decoding target screen from a reference screen before the pixel interpolation process. Further comprising a load detection means for detecting the load of the information processing apparatus,
The control means is any one of the first pixel interpolation processing means, the second pixel interpolation processing means, and the third pixel interpolation processing means in accordance with the load detected by the load detection means. The information processing apparatus according to claim 1, wherein the information processing unit controls whether to perform the pixel interpolation process . The information processing apparatus according to claim 4 , wherein the load detection means includes means for inquiring a load of the information processing apparatus with respect to an operating system executed on the information processing apparatus. 5. The information processing apparatus according to claim 4, wherein the load detection means includes means for detecting a load on the information processing apparatus based on a usage rate of a processor provided in the information processing apparatus. The load detecting means includes means for detecting a load on the information processing device based on a usage rate of a processor provided in the information processing device and a usage rate of a memory provided in the information processing device. The information processing apparatus according to claim 4 . A program for causing a computer to execute a decoding process for decoding a compression-encoded moving image stream,
A first pixel interpolation procedure for performing a first decimal pixel precision pixel interpolation process on the decoded image using a filter with a first tap number;
A second pixel interpolation processing procedure for performing pixel interpolation processing with a first pixel accuracy on a decoded image using a filter having a second tap number smaller than the first tap number;
A third pixel that performs pixel interpolation processing with a second pixel accuracy smaller than the first pixel accuracy on the decoded image using a filter with a first tap number and a filter with the second tap number Interpolation process,
A motion compensation procedure for generating a motion compensation inter-frame prediction signal corresponding to a decoding target image from the pixel-interpolated image based on motion vector information included in the moving image moving image stream;
A procedure for decoding the decoding target image by adding a motion compensation inter-frame prediction signal corresponding to the decoding target image to a prediction error signal corresponding to the decoding target image;
Regarding the decoding process of the moving image stream, the pixel interpolation process is performed using any one of the first pixel interpolation process procedure, the second pixel interpolation process procedure, and the third pixel interpolation process procedure. And a control procedure for controlling the computer . A fourth pixel interpolation processing procedure for performing pixel interpolation processing of the second pixel accuracy by using the second tap number filtering processing a plurality of times for the decoded image;
The control procedure is a pixel using any one of the first pixel interpolation processing procedure, the second pixel interpolation processing procedure, the third pixel interpolation processing procedure, and the fourth pixel interpolation processing procedure. 9. The program according to claim 8, which controls whether to perform interpolation processing . A load detection procedure for detecting a load of the information processing apparatus;
The control procedure includes any one of the pixel interpolation processing of the first pixel interpolation processing procedure, the second pixel interpolation processing procedure, and the third pixel interpolation processing procedure according to the load detected by the load detection procedure. 9. The program according to claim 8, wherein whether to perform pixel interpolation processing using a procedure is controlled .

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