JP4273651B2

JP4273651B2 - Deposition time deriving method and film forming method

Info

Publication number: JP4273651B2
Application number: JP2000325095A
Authority: JP
Inventors: 繁藤田; 信幸山口
Original assignee: Sony Corp
Current assignee: Sony Corp
Priority date: 2000-10-25
Filing date: 2000-10-25
Publication date: 2009-06-03
Anticipated expiration: 2020-10-25
Also published as: JP2002134493A

Description

【０００１】
【発明の属する技術分野】
本発明は、成膜時間導出方法および成膜方法に関し、特には表面積の大きなウエハ表面に対してバッチ式のＣＶＤ装置を用いて所定膜厚の成膜を行う場合の成膜時間導出方法および成膜方法に関する。
【０００２】
【従来の技術】
近年半導体装置の高集積化にともない、ＤＲＡＭのようなキャパシタを有する半導体装置においては、セル面積を縮小しながらもキャパシタ容量を確保する必要があり、種々の技術検討が進められている。例えばＤＲＡＭにおいては、キャパシタを単純スタック構造からシリンダ構造へ変更することでキャパシタ表面積を増加させる構成が採用されている。またノード電極表面にリンをドープしたポリシリコンの半球グレイン（hemispherical grained-silicon以下、ＨＳＧ−Ｓｉと記す）を形成してノード電極の表面積を増加させ、これによってさらにキャパシタの表面積を増加させる構成も採用されている。
【０００３】
また、キャパシタ絶縁膜としては窒化シリコン膜が採用されているが、その薄膜形成は一般的に縦型のバッチ式減圧ＣＶＤ(chemical vapor deposition）装置にて２５枚〜１５０枚程度のウエハに対して一括して行われている。ところが、上述したように表面積が増加したノード電極を有するウエハに対してバッチ式のＣＶＤ装置で成膜処理を行う場合、ウエハの処理枚数が多い程、窒化シリコン膜の成膜レートが遅くなるといった現象が生じる。これは、成膜表面積が極端に増大した場合、成膜表面に対する成膜ガス（ＳｉＨ₂Ｃｌ₂およびＮＨ₃）の供給が不足するためであり、キャパシタが単純スタック構造である場合には見られない現象であった。このような成膜ガスの供給不足を補うために、成膜ガスを大流量化することが考えられるが、この場合ＣＶＤ装置内におけるパーティクル（副生成物であるＨＮ₄Ｃｌ）の発生を誘起するため望ましい方法ではなかった。
【０００４】
そこで、キャパシタ絶縁膜の形成工程においては、ＣＶＤ装置へのウエハ充填枚数毎に予め成膜レートに関する基礎データを実験的に導出しておき、これに基づいてねらい膜厚が得られるような処理時間を求めてＣＶＤ成膜を行っている。
【０００５】
【発明が解決しようとする課題】
ところが半導体装置の製造工程においては、例えば所定回数の処理を繰り返す毎に製造装置のメンテナンスを行うが、ＣＶＤ装置においてはメンテナンスを行う毎に成膜レートが微妙に変化する。このため、キャパシタ絶縁膜の成膜のようなねらい膜厚を厳しく管理する必要のある工程では、メンテナンスを行う毎に成膜レートに関する基礎データを実験的に導出する必要が生じる。
【０００６】
特に、上述したようなウエハの充填枚数によって成膜レートが変化するような成膜処理を行う場合、基礎データを実験的に導出する方法をそのまま適用すると、ＣＶＤ装置のメンテナンスを行う毎に、処理枚数毎の基礎データを実験的に導出する必要がある。例えば、この成膜処理が、ＣＶＤ装置内に２５枚、５０枚、７５枚、１００枚の各毎数でウエハを充填して行われる場合、成膜レートの基礎データを得るためには、各枚数段階での処理を２回ずつ成膜時間を変化させた実験的な成膜を行う必要があり、各成膜において５時間程度の処理時間を要するとした場合、全ての基礎データを得るためには４段階×２回×５時間＝４０時間の時間を要することになる。これは、ＣＶＤ装置のマシンダウンタイムを増大させる要因になる。
【０００７】
そこで本発明は、大表面積上へのＣＶＤ成膜においてＣＶＤ装置のマシンダウンタイムの低減を達成することが可能な成膜時間導出方法および成膜方法を提供することを目的としている。
【０００８】
【課題を解決するための手段】
このような目的を達成するための本発明の成膜時間導出方法は、表面に凹凸を有する製品ウエハと当該製品ウエハと比較して表面平坦なダミーウエハとを合わせて最大処理枚数のウエハをバッチ式のＣＶＤ装置内に充填し、製品ウエハの表面に所定膜厚の成膜を行う際の成膜時間導出方法であり、次のように行うことを特徴としている。先ず、ＣＶＤ装置内に第１の所定枚数の製品ウエハと共にダミーウエハを装填して最大処理枚数とした実験的な成膜処理を複数回行い、前記ＣＶＤ装置内に第１の所定枚数の製品ウエハと共にダミーウエハを装填して最大処理枚数とした実験的な成膜処理を複数回行い、成膜時間Ｘと成膜膜厚Ｙとの関係を示す一次式Ｙ＝ａ_n1Ｘ＋ｂ_n1…（９）を求める。また、ＣＶＤ装置内に第２の所定枚数の製品ウエハと共にダミーウエハを装填して最大処理枚数とした実験的な成膜処理を複数回行い、成膜時間Ｘと成膜膜厚Ｙとの関係を示す一次式Ｙ＝ａ_n2Ｘ＋ｂ_n2…（１０）を求める。その後、ＣＶＤ装置の状態が変化した後に、当該ＣＶＤ装置内に前記第１の所定枚数の製品ウエハと共にダミーウエハを装填して最大処理枚数とした実験的な成膜処理を複数回行い、成膜時間Ｘと成膜膜厚Ｙとの関係を示す一次式Ｙ＝ａ_n11Ｘ＋ｂ_n11…（１１）を求める。次いで、一次式（９）〜（１１）における各定数ａ_n1，ｂ_n1，ａ_n2，ｂ_n2，ａ_n11，ｂ_n11を用いて、前記ＣＶＤ装置の状態が変化した後における前記第２の所定枚数の製品ウエハの成膜処理における成膜時間Ｘと成膜膜厚Ｙとの関係を示す一次式Ｙ＝（ａ_n2／ａ_n1）×ａ_n11×Ｘ＋（ｂ_n2／ｂ_n1）×ｂ_n11…（１２）を求める。そして、この一次式（１２）に基づいて、ＣＶＤ装置の状態が変化した後における前記第２の所定枚数の製品ウエハの成膜処理において所定の成膜膜厚が得られる成膜時間を求める。
【０００９】
また、本発明の成膜方法は、上述した成膜時間導出方法によって得られた成膜時間に従って所定枚数の製品ウエハに対する成膜を行うことを特徴としている。
【００１０】
このような成膜時間導出方法および成膜方法では、ＣＶＤ装置の状態が変化した後には、第１の所定枚数の製品ウエハをＣＶＤ装置内に充填しての実験的な成膜処理のみを行うことで、つまり第２の所定枚数の製品ウエハをＣＶＤ装置内に充填しての実験的な成膜処理を行うことなく、第２の所定枚数の製品ウエハを成膜処理する場合の成膜膜厚と成膜時間との関係が得られる。したがって、ＣＶＤ装置の状態が変化した後に、各所定枚数の製品ウエハをＣＶＤ装置内に充填しても実験的な成膜処理を行うことで成膜時間を導出する場合と比較して、実験的な成膜処理の回数を削減することができる。
【００１１】
【発明の実施の形態】
以下本発明の成膜時間導出方法および成膜方法の実施の形態を図面に基づいて詳細に説明する。ここでは、縦型バッチ式減圧ＣＶＤ装置を用い、ＤＲＡＭの製造工程において、ノード電極を覆う状態でキャパシタシリコン窒化膜を形成する場合に本発明を適用した実施の形態を説明する。
【００１２】
図１（１）に示すように、成膜処理を行う製品ウエハＷは、例えば単結晶シリコンからなる基板１表面が絶縁膜２で覆われ、この絶縁膜２に基板１に達するノードコンタクト３が形成され、このノードコンタクト３に接続する状態で絶縁膜２上にノード電極４が形成されている。このノード電極４は、バレル型に形成された非晶質シリコンの表面にＨＳＧ−Ｓｉ４ａを成長させてなるものであり、これによって表面積を増大させたものである。
【００１３】
このような構成のノード電極４が形成された製品ウエハＷに対して、図１(２)に示すように、ノード電極４表面を覆うキャパシタシリコン窒化膜５を所定膜厚で形成する場合には、キャパシタシリコン窒化膜形成用縦型バッチ式減圧ＣＶＤ装置（以下、単にＣＶＤ装置と記す）を用いる。
【００１４】
図２に示すように、このＣＶＤ装置は、円筒型の上端を閉塞させた状態で立設させたアウターチューブ１１内に、上端側を解放させた状態でインナーチューブ１２を立設させ、このインナーチューブ１２内に製品ウエハＷを保持したボート１３が収納される。またアウターチューブ１１の外周にはヒータ１５が設けられ、内部の加熱が自在に構成されている。さらに、アウターチューブ１１には排気管１６が接続され、インナーチューブ１２には反応ガスの導入管１７が接続されており、インナーチューブ１２に導入された反応ガスがアウターチューブ１１側から排気されるように構成されている。また、インナーチューブ１２の下方には真空ロードロック室１８が設けられ、このロードロック室１８からインナーチューブ１２内に、ボート１３に保持された製品ウエハＷが搬入出されるように構成されている。
【００１５】
図３に示すように、このＣＶＤ装置には、水平状態に保たれた製品ウエハＷが上下方向に所定間隔を保った積層状態で装填され、１００枚の製品ウエハＷを一括して成膜処理できる。また通常、製品ウエハＷは２５枚を１単位（１ロット）として生産ラインで流すため、本実施形態においてもＣＶＤ装置に対する製品ウエハＷの装填枚数は２５枚、５０枚、７５枚、１００枚を想定する。また製品ウエハＷのＣＶＤ装置内への充填枚数が１００枚に満たない場合には、上から順に製品ウエハＷを装填して行くこととする。そして、製品ウエハＷのない場所にはダミーウエハを装填することとする。このダミーウエハは、表面に凹凸が設けられていないウエハであることとする。
【００１６】
また、このＣＶＤ装置内には、製品ウエハＷおよびダミーウエハの他に、膜厚管理ウエハが充填されることとする。この膜厚管理ウエハは、表面平坦ウエハであり、製品ウエハＷおよびダミーウエハの装填位置の直下（ボトム位置、以下ＢＴＭと記す）と、製品ウエハの装填位置の直上（トップ位置、以下ＴＯＰと記す）と、製品ウエハ５０枚ずつの装填位置の間（センター位置、以下ＣＮＴと記す）の３箇所に装填可能である。
【００１７】
次に、このようなＣＶＤ装置を用いたキャパシタシリコン窒化膜の成膜を説明する。以下の１）〜５）のようにして、基礎データを得る。
【００１８】
１）先ず、ＣＶＤ装置に、図１（１）を用いて説明した構成の表面積の大きい製品ウエハＷを０枚装填し（装填せず）、ダミーウエハを１００枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。ここでは、製品ウエハＷの充填枚数０枚が、請求項に示す第１の所定枚数となる。
【００１９】
この状態で膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（最低２回）のシリコン窒化膜成膜を行う。そして、図４に示すように、製品ウエハＷを０枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１３）を得る。
Ｙ＝ａ₀Ｘ＋ｂ₀…（１３）
ただし、ａ₀，ｂ₀は定数である。
【００２０】
２）次に、ＣＶＤ装置に、表面積の大きい製品ウエハＷを２５枚装填し、ダミーウエハを７５枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。
【００２１】
この状態で、膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（最低２回）のシリコン窒化膜成膜を行う。そして、製品ウエハＷを２５枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１４）を得る。
Ｙ＝ａ₂₅Ｘ＋ｂ₂₅…（１４）
ただし、ａ₂₅，ｂ₂₅は定数である。
【００２２】
３）さらに、ＣＶＤ装置に、表面積の大きい製品ウエハＷを５０枚装填し、ダミーウエハを５０枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。
【００２３】
この状態で、膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（最低２回）のシリコン窒化膜成膜を行う。そして、製品ウエハＷを５０枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１５）を得る。
Ｙ＝ａ₅₀Ｘ＋ｂ₅₀…（１５）
ただし、ａ₅₀,ｂ₅₀は定数である。
【００２４】
４）また、ＣＶＤ装置に、表面積の大きい製品ウエハＷを７５枚、ダミーウエハを２５枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。
【００２５】
この状態で、膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（最低２回）のシリコン窒化膜成膜を行う。そして、製品ウエハＷを７５枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１６）を得る。
Ｙ＝ａ₇₅Ｘ＋ｂ₇₅…（１６）
ただし、ａ₇₅,ｂ₇₅は定数である。
【００２６】
５）そして、ＣＶＤ装置に、表面積の大きい製品ウエハＷを１００枚、ダミーウエハを０枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。
【００２７】
この状態で、膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（最低２回）のシリコン窒化膜成膜を行う。そして、製品ウエハＷを１００枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１７）を得る。
Ｙ＝ａ₁₀₀Ｘ＋ｂ₁₀₀…（１７）
ただし、ａ₁₀₀，ｂ₁₀₀は定数である。
【００２８】
図４に示すように、製品ウエハＷの装填枚数が多くなるほど同じ成膜時間で成膜膜厚が低減していることが分かる。尚、ここでは、一次式（１３）〜（１７）および図４のプロットが基礎データとなる。そして、この基礎データを得るための各成膜工程は、上述した順序に限定されることはない。また、以上においては、製品ウエハＷの装填枚数２５枚、５０枚、７５枚、１００枚の各枚数が、請求項に示す第２の所定枚数となる。
【００２９】
次に、上述のようにして取得した基礎データに基づいて、ＣＶＤ装置の状態が変化した後における、製品ウエハＷの各充填枚数に対するシリコン窒化膜厚Ｙと成膜時間Ｘの関係を導出する手順を説明する。
【００３０】
６）先ず、例えばＣＶＤ装置のメンテナンスを行うことで、このＣＶＤ装置の状態が変化した後に、このＣＶＤ装置に図１（１）で示した製品ウエハＷを第１の所定枚数である０枚装填し（装填せず）、ダミーウエハを１００枚装填すると共に、膜厚管理ウエハをＣＮＴへ装填する。
【００３１】
この状態で、膜厚管理ウエハを交換しながら成膜時間を変化させた複数回（例えば１７分と２５分との２回）のシリコン窒化膜成膜を行う。そして、図５に示すように、製品ウエハ０枚充填におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係をプロットし、膜厚Ｙと成膜時間Ｘとの関係を表す下記一次式（１８）を得る。
Ｙ＝ａ₀₁Ｘ＋ｂ₀₁…（１８）
ただし、ａ₀₁，ｂ₀₁は定数であることとする。
【００３２】
７）次に、ＣＶＤ装置メンテナンス後における表面積の大きい製品ウエハを２５枚装填した場合の膜厚Ｙと成膜時間Ｘとの関係を得るが、この際、実験的な成膜を行うことなく、次のような本発明に特徴的なパラメータ導出を行うことによって、実際に成膜条件出しを行うことなくこの関係を導出する。
【００３３】
すなわち、得ようとする膜厚Ｙと成膜時間Ｘとの関係を示す一次式をＹ＝ａ₂₅₁Ｘ＋ｂ₂₅₁とした場合、一次式（１３），（１４），（１８）の定数を用い、ａ₂₅₁＝（a₀₁／ａ₀）×ａ₂₅、ｂ₂₅₁＝（ｂ₀₁／ｂ₀）×ｂ₂₅としてこの一次式における定数ａ₂₅₁，ｂ₂₅₁を導出する。そして、この一次式から図５に示すように、製品ウエハＷを２５枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係を示すプロットを得る。
【００３４】
８）同様に、ＣＶＤ装置メンテナンス後における表面積の大きい製品ウエハＷを５０枚装填した場合の膜厚Ｙと成膜時間Ｘとの関係を得る。すなわち、得ようとする膜厚Ｙと成膜時間Ｘとの関係を示す一次式をＹ＝ａ_5o1Ｘ＋ｂ₅₀₁とした場合、一次式（１３），（１５），（１８）の定数を用い、ａ₅₀₁＝（a₀₁／ａ₀）×ａ₅₀、ｂ₅₀₁＝（ｂ₀₁／ｂ₀）×ｂ₅₀としてこの一次式における定数ａ₅₀₁，ｂ₅₀₁を導出する。そして、この一次式から図５に示すように、製品ウエハＷを５０枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係を示すプロットを得る。
【００３５】
９）また、ＣＶＤ装置メンテナンス後における表面積の大きい製品ウエハＷを７５枚装填した場合の膜厚Ｙと成膜時間Ｘとの関係を得る。すなわち、得ようとする膜厚Ｙと成膜時間Ｘとの関係を示す一次式をＹ＝ａ₇₅₁Ｘ＋ｂ₇₅₁とした場合、一次式（１３），（１６），（１８）の定数を用い、ａ₇₅₁＝（a₀₁／ａ₀）×ａ₇₅、ｂ₇₅₁＝（ｂ₀₁／ｂ₀）×ｂ₇₅としてこの一次式における定数ａ₇₅₁，ｂ₇₅₁を導出する。そして、この一次式から図５に示すように、製品ウエハＷを７５枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係を示すプロットを得る。
【００３６】
１０）さらに、ＣＶＤ装置メンテナンス後における表面積の大きい製品ウエハＷを１００枚装填した場合の膜厚Ｙと成膜時間Ｘとの関係を得る。すなわち、得ようとする膜厚Ｙと成膜時間Ｘとの関係を示す一次式をＹ＝ａ₁₀₀₁Ｘ＋ｂ₁₀₀₁とした場合、一次式（１３），（１７），（１８）の定数を用い、ａ₁₀₀₁＝（a₀₁／ａ₀）×ａ₁₀₀、ｂ₁₀₀₁＝（ｂ₀₁／ｂ₀）×ｂ₁₀₀としてこの一次式における定数ａ₁₀₀₁，ｂ₁₀₀₁を導出する。そして、この一次式から図５に示すように、製品ウエハＷを１００枚充填した場合におけるシリコン窒化膜厚Ｙと成膜時間Ｘの関係を示すプロットを得る。
【００３７】
１１）以上の後、これらの関係式または図５のプロットから、ＣＶＤ装置の状態が変化した後において、製品ウエハＷに対してキャパシタシリコン窒化膜５を所定膜厚で形成する場合の成膜時間を、ＣＶＤ装置に充填される製品ウエハＷの枚数毎に導出する。例えば、キャパシタシリコン窒化膜５のねらい膜厚が５ｎｍである場合、製品ウエハＷの充填枚数が２５枚であれば成膜時間２２分１５秒、製品ウエハＷの充填枚数が５０枚であれば成膜時間２２分４５秒、製品ウエハＷの充填枚数が７５枚であれば成膜時間２３分１５秒、製品ウエハＷの充填枚数が１００枚であれば成膜時間２３分４５秒と導出される。
【００３８】
以上の実施形態においては、ＣＶＤ装置のメンテナンスを行った後等のように、ＣＶＤ装置の状態が変化した後には、０枚の製品ウエハＷをＣＶＤ装置内に充填しての実験的な成膜処理のみを行うことで、つまり２５枚、５０枚、７５枚、１００枚の各枚数の製品ウエハＷをＣＶＤ装置内に充填しての、各実験的な成膜処理を行うことなく、それぞれの充填枚数の製品ウエハＷを成膜処理する場合の成膜膜厚と成膜時間との関係を得ている。
【００３９】
このため、ＣＶＤ装置の状態が変化した後に、製品ウエハＷの各充填枚数毎に実験的な成膜処理を行う場合と比較して、実験的な成膜処理の回数を削減し、ＣＶＤ装置のマシンダウンタイムの低減を図ることが可能になる。また実験的な成膜処理に要する人的工数を削減することが可能になる。
【００４０】
具体的には、２５枚、５０枚、７５枚、１００枚の各充填枚数に関して最低２回ずつの成膜処理が削減される。このため、各成膜処理に５時間要する場合には、４段階×２回×５時間＝４０時間のマシンダウンタイムの削減を図ることができる。
【００４１】
この結果、半導体装置の生産性の向上を図ることができる。
【００４２】
また、ＣＶＤ装置に充填する製品ウエハＷの第１の所定枚数を０枚としたことから、図４のプロットや一次式（１３）〜（１７）等の基礎データを取得した後におけるＣＶＤ装置の状態変化後には、各充填枚数に最適な成膜時間を導出するために、実験的な成膜処理に製品ウエハＷを用いる必要はない。このため、成膜時間導出のための実験的な成膜処理を、通常の平坦なウエハ（ダミーウエハと膜厚評価用ウエハと）のみを用いて容易に行うことが可能になる。尚、第１の所定枚数は、０枚に限定されることはない。ただし、第１の所定枚数を０枚としない場合には、製造工程における製品ウエハＷの充填枚数（２５枚、５０枚…）の中から第１の所定枚数を選択する。この場合、選択された充填枚数以外の充填枚数が第２の所定枚数となる。
【００４３】
以上実施形態においては、ＤＲＡＭのキャパシタシリコン窒化膜を形成する工程を例に採って本発明を説明した。しかし、本発明はこれに限定されることはなく、例えばＦeＲＡＭ（ferroelectric Random Access Memory）やＭＲＡＭ（Magnetic Random Access Memory）などの製造においてキャパシタ誘電膜を形成する工程にも適用可能である。この際、成膜材料は、シリコン窒化膜に限定されることはなく、それぞれのデバイスに適する材料を適宜選択して用いることとする。さらに、キャパシタの構成としても、図１を用いて説明したような基板上に形成する積み上げ型に限定されることはなくトレンチキャパシタであっても良い。また、キャパシタの形成に限定されることもなく、凹凸を有することでその表面積が極端に拡大された製品ウエハに対して膜厚精度の高い成膜を行う場合に広く適用可能である。
【００４４】
【発明の効果】
以上説明したように本発明の成膜時間導出方法および成膜方法によれば、メンテナンスなどによりＣＶＤ装置の状態が変化した後に、所望の成膜膜厚を得るための成膜時間を導出するための実験的な成膜処理の回数を大幅に削減することが可能になり、ＣＶＤ装置のマシンダウンタイムおよび人的工数を低減することができる。この結果、表面積が大幅に拡大された製品ウエハに対する成膜処理において、生産性を大幅に向上させることが可能になる。
【図面の簡単な説明】
【図１】本発明が適用される製品ウエハの一構成例を示す断面図である。
【図２】本発明が適用されるバッチ式ＣＶＤ装置の一構成例を示す図である。
【図３】図２のバッチ式ＣＶＤ装置における製品ウエハの充填状態を説明するための図である。
【図４】実験的に導出した成膜膜厚と成膜時間との関係を示す図である。
【図５】本発明の導出方法によって得られた成膜膜厚と成膜時間との関係を示す図である。
【符号の説明】
Ｗ…製品ウエハ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a film formation time derivation method and a film formation method, and more particularly, to a film formation time derivation method and a film formation method when a film having a predetermined film thickness is formed on a wafer surface having a large surface area using a batch-type CVD apparatus. The present invention relates to a membrane method.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the high integration of semiconductor devices, in a semiconductor device having a capacitor such as a DRAM, it is necessary to secure a capacitor capacity while reducing the cell area, and various technical studies are being conducted. For example, a DRAM employs a configuration in which the capacitor surface area is increased by changing the capacitor from a simple stack structure to a cylinder structure. In addition, a structure in which the surface area of the node electrode is increased by forming a hemispherical grained silicon (hereinafter referred to as HSG-Si) doped with phosphorus on the surface of the node electrode, thereby further increasing the surface area of the capacitor. It has been adopted.
[0003]
In addition, a silicon nitride film is used as the capacitor insulating film, but the thin film is generally formed on about 25 to 150 wafers using a vertical batch type low pressure CVD (chemical vapor deposition) apparatus. It is done in bulk. However, as described above, when a film formation process is performed on a wafer having a node electrode with an increased surface area using a batch-type CVD apparatus, the film formation rate of the silicon nitride film decreases as the number of wafers processed increases. A phenomenon occurs. This is because when the film forming surface area is extremely increased, the supply of the film forming gas (SiH ₂ Cl ₂ and NH ₃ ) to the film forming surface is insufficient, which is seen when the capacitor has a simple stack structure. There was no phenomenon. In order to make up for such a short supply of the film forming gas, it is conceivable to increase the flow rate of the film forming gas. In this case, the generation of particles (HN ₄ Cl as a by-product) in the CVD apparatus is induced. Therefore, it was not a desirable method.
[0004]
Therefore, in the capacitor insulating film forming process, basic data on the film forming rate is experimentally derived in advance for each wafer filling number in the CVD apparatus, and based on this, a processing time in which a target film thickness can be obtained. For this reason, CVD film formation is performed.
[0005]
[Problems to be solved by the invention]
However, in the manufacturing process of the semiconductor device, for example, maintenance of the manufacturing device is performed every time a predetermined number of processes are repeated. However, in the CVD device, the deposition rate slightly changes every time maintenance is performed. For this reason, in a process where the target film thickness needs to be strictly controlled, such as the formation of a capacitor insulating film, it is necessary to experimentally derive basic data regarding the film formation rate every time maintenance is performed.
[0006]
In particular, when performing a film forming process in which the film forming rate varies depending on the number of wafers filled as described above, the method of experimentally deriving basic data is applied as it is every time a CVD apparatus is maintained. It is necessary to experimentally derive basic data for each number. For example, when this film forming process is performed by filling the CVD apparatus with wafers of 25, 50, 75, and 100 sheets, in order to obtain basic data of the film forming rate, In order to obtain all the basic data when it is necessary to perform an experimental film formation in which the film formation time is changed twice each in the number of sheets, and it takes about 5 hours for each film formation, It takes 4 stages × 2 times × 5 hours = 40 hours. This increases the machine downtime of the CVD apparatus.
[0007]
Therefore, an object of the present invention is to provide a film formation time deriving method and a film forming method capable of achieving a reduction in machine down time of a CVD apparatus in CVD film formation on a large surface area.
[0008]
[Means for Solving the Problems]
In order to achieve such an object, the film formation time derivation method of the present invention is a batch-type method in which a product wafer having irregularities on the surface and a dummy wafer whose surface is flat compared to the product wafer are combined to process the maximum number of wafers. This is a film formation time deriving method for filling the CVD apparatus and forming a film with a predetermined film thickness on the surface of the product wafer, which is characterized as follows. First, an experimental film forming process is performed a plurality of times by loading a dummy wafer together with a first predetermined number of product wafers into the CVD apparatus to obtain the maximum number of processed wafers, and with the first predetermined number of product wafers in the CVD apparatus. An experimental film forming process in which a dummy wafer is loaded and the maximum number of processed sheets is performed is performed a plurality of times, and a primary expression Y = an ₁ X + b _n1 (9) indicating the relationship between the film forming time X and the film thickness Y is obtained. . In addition, an experimental film forming process is performed a plurality of times by loading a dummy wafer together with a second predetermined number of product wafers into the CVD apparatus to obtain the maximum number of processed wafers, and the relationship between the film forming time X and the film thickness Y is shown. The following linear expression Y = a _n2 X + b _n2 (10) is obtained. Thereafter, after the state of the CVD apparatus is changed, an experimental film forming process is performed a plurality of times by loading a dummy wafer together with the first predetermined number of product wafers into the CVD apparatus to obtain a maximum processing number, and a film forming time A linear expression Y = a _n11 X + b _n11 (11) indicating the relationship between X and the film thickness Y is obtained. Next, the second predetermined value after the state of the CVD apparatus is changed using the constants a _n1 , b _n1 , a _n2 , b _n2 , a _n11 , b _n11 in the linear expressions (9) to (11). A linear expression Y = (a _n2 / a _n1 ) × a _n11 × X + (b _n2 / b _n1 ) × b _n11 showing the relationship between the film forming time X and the film thickness Y in the film forming process for the number of product wafers ... (12) is obtained. Then, based on the linear expression (12), a film formation time during which a predetermined film thickness is obtained in the film forming process of the second predetermined number of product wafers after the state of the CVD apparatus is changed is obtained.
[0009]
The film forming method of the present invention is characterized in that a film is formed on a predetermined number of product wafers according to the film forming time obtained by the film forming time deriving method described above.
[0010]
In such a film formation time deriving method and film formation method, after the state of the CVD apparatus changes, only an experimental film formation process is performed by filling the CVD apparatus with the first predetermined number of product wafers. That is, a film formation film in the case where a second predetermined number of product wafers are formed without performing an experimental film formation process by filling the second predetermined number of product wafers into the CVD apparatus. A relationship between the thickness and the film formation time can be obtained. Therefore, after changing the state of the CVD apparatus, even if each predetermined number of product wafers are filled in the CVD apparatus, it is more experimental than when the film formation time is derived by performing an experimental film formation process. The number of film forming processes can be reduced.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a film formation time deriving method and a film forming method according to the present invention will be described below in detail with reference to the drawings. Here, an embodiment in which the present invention is applied to a case where a capacitor silicon nitride film is formed in a state of covering a node electrode in a DRAM manufacturing process using a vertical batch type low pressure CVD apparatus will be described.
[0012]
As shown in FIG. 1A, a product wafer W to be subjected to film formation processing has a substrate 1 surface made of, for example, single crystal silicon covered with an insulating film 2, and a node contact 3 reaching the substrate 1 is formed on the insulating film 2. A node electrode 4 is formed on the insulating film 2 so as to be connected to the node contact 3. The node electrode 4 is formed by growing HSG-Si4a on the surface of amorphous silicon formed in a barrel shape, and thereby increasing the surface area.
[0013]
When the capacitor silicon nitride film 5 covering the surface of the node electrode 4 is formed with a predetermined thickness on the product wafer W on which the node electrode 4 having such a configuration is formed, as shown in FIG. A vertical batch type low pressure CVD apparatus (hereinafter simply referred to as a CVD apparatus) for forming a capacitor silicon nitride film is used.
[0014]
As shown in FIG. 2, this CVD apparatus has an inner tube 12 erected in an outer tube 11 erected with the upper end of a cylindrical shape closed, and an inner tube 12 is erected with the upper end side released. A boat 13 holding a product wafer W is accommodated in the tube 12. Further, a heater 15 is provided on the outer periphery of the outer tube 11 so that the inside can be heated freely. Further, an exhaust pipe 16 is connected to the outer tube 11, and a reaction gas introduction pipe 17 is connected to the inner tube 12, so that the reaction gas introduced into the inner tube 12 is exhausted from the outer tube 11 side. It is configured. A vacuum load lock chamber 18 is provided below the inner tube 12, and the product wafers W held on the boat 13 are loaded into and out of the inner tube 12 from the load lock chamber 18.
[0015]
As shown in FIG. 3, in this CVD apparatus, product wafers W kept in a horizontal state are loaded in a stacked state with a predetermined interval in the vertical direction, and 100 product wafers W are collectively formed into a film. it can. Normally, 25 product wafers W are flown on the production line as one unit (1 lot), so in this embodiment, the number of product wafers W loaded into the CVD apparatus is 25, 50, 75, 100. Suppose. When the number of product wafers W filled in the CVD apparatus is less than 100, the product wafers W are loaded in order from the top. A dummy wafer is loaded in a place where there is no product wafer W. The dummy wafer is a wafer having no irregularities on the surface.
[0016]
The CVD apparatus is filled with a film thickness control wafer in addition to the product wafer W and the dummy wafer. This film thickness control wafer is a surface flat wafer, directly below the loading position of the product wafer W and the dummy wafer (bottom position, hereinafter referred to as BTM), and immediately above the loading position of the product wafer (top position, hereinafter referred to as TOP). In addition, it can be loaded at three positions between the loading positions of 50 product wafers (center position, hereinafter referred to as CNT).
[0017]
Next, film formation of a capacitor silicon nitride film using such a CVD apparatus will be described. Basic data is obtained as in 1) to 5) below.
[0018]
1) First, in the CVD apparatus, zero product wafers W having the structure described with reference to FIG. 1A are loaded (not loaded), 100 dummy wafers are loaded, and a film thickness control wafer is loaded. Load into CNT. Here, the number 0 of the product wafers W filled is the first predetermined number indicated in the claims.
[0019]
In this state, the silicon nitride film is formed a plurality of times (at least twice) while changing the film formation time while replacing the film thickness control wafer. Then, as shown in FIG. 4, the relationship between the silicon nitride film thickness Y and the film formation time X when zero product wafers W are filled is plotted, and the relationship between the film thickness Y and the film formation time X is expressed as follows. Equation (13) is obtained.
Y = a ₀ X + b ₀ (13)
However, a ₀ and b ₀ are constants.
[0020]
2) Next, 25 product wafers W having a large surface area are loaded into the CVD apparatus, 75 dummy wafers are loaded, and a film thickness control wafer is loaded into the CNTs.
[0021]
In this state, the silicon nitride film is formed a plurality of times (at least twice) while changing the film formation time while changing the film thickness control wafer. Then, the relationship between the silicon nitride film thickness Y and the film formation time X when 25 product wafers W are filled is plotted, and the following linear expression (14) representing the relationship between the film thickness Y and the film formation time X is obtained.
Y = a ₂₅ X + b ₂₅ (14)
However, a ₂₅ and b ₂₅ are constants.
[0022]
3) Further, 50 product wafers W having a large surface area are loaded into the CVD apparatus, 50 dummy wafers are loaded, and a film thickness management wafer is loaded into the CNT.
[0023]
In this state, the silicon nitride film is formed a plurality of times (at least twice) while changing the film formation time while changing the film thickness control wafer. Then, the relationship between the silicon nitride film thickness Y and the film formation time X when 50 product wafers W are filled is plotted, and the following linear expression (15) representing the relationship between the film thickness Y and the film formation time X is obtained.
Y = a ₅₀ X + b ₅₀ (15)
However, a ₅₀ and b ₅₀ are constants.
[0024]
4) Further, 75 product wafers W and 25 dummy wafers having a large surface area are loaded into the CVD apparatus, and a film thickness control wafer is loaded into the CNTs.
[0025]
In this state, the silicon nitride film is formed a plurality of times (at least twice) while changing the film formation time while changing the film thickness control wafer. Then, the relationship between the silicon nitride film thickness Y and the film formation time X when 75 product wafers W are filled is plotted, and the following linear expression (16) representing the relationship between the film thickness Y and the film formation time X is obtained.
Y = a ₇₅ X + b ₇₅ (16)
However, a ₇₅ and b ₇₅ are constants.
[0026]
5) Then, 100 product wafers W having a large surface area and 0 dummy wafers are loaded into the CVD apparatus, and a film thickness control wafer is loaded into the CNTs.
[0027]
In this state, the silicon nitride film is formed a plurality of times (at least twice) while changing the film formation time while changing the film thickness control wafer. Then, the relationship between the silicon nitride film thickness Y and the film formation time X when 100 product wafers W are filled is plotted, and the following linear expression (17) representing the relationship between the film thickness Y and the film formation time X is obtained.
Y = a ₁₀₀ X + b ₁₀₀ (17)
However, a ₁₀₀ and b ₁₀₀ are constants.
[0028]
As shown in FIG. 4, it can be seen that as the number of loaded product wafers W increases, the film thickness decreases in the same film formation time. Here, the primary expressions (13) to (17) and the plot of FIG. 4 are the basic data. And each film-forming process for obtaining this basic data is not limited to the order mentioned above. In the above description, the number of product wafers W loaded is 25, 50, 75, and 100, which is the second predetermined number of claims.
[0029]
Next, a procedure for deriving the relationship between the silicon nitride film thickness Y and the film formation time X with respect to each number of filled product wafers W after the state of the CVD apparatus changes based on the basic data acquired as described above. Will be explained.
[0030]
6) First, after changing the state of the CVD apparatus, for example, by performing maintenance of the CVD apparatus, the CVD apparatus is loaded with the first predetermined number of product wafers W shown in FIG. Then, 100 dummy wafers are loaded, and a film thickness management wafer is loaded into the CNT.
[0031]
In this state, the silicon nitride film is formed a plurality of times (for example, twice at 17 minutes and 25 minutes) while changing the film formation time while changing the film thickness control wafer. Then, as shown in FIG. 5, the relationship between the silicon nitride film thickness Y and the film formation time X in filling zero product wafers is plotted, and the following linear expression (18) expressing the relationship between the film thickness Y and the film formation time X Get.
Y = a ₀₁ X + b ₀₁ (18)
However, a ₀₁ and b ₀₁ are constants.
[0032]
7) Next, the relationship between the film thickness Y and the film formation time X when 25 product wafers having a large surface area after the CVD apparatus maintenance are loaded is obtained. By deriving parameters characteristic of the present invention as follows, this relationship is derived without actually determining the film formation conditions.
[0033]
That is, when the primary expression indicating the relationship between the film thickness Y to be obtained and the film formation time X is Y = a ₂₅₁ X + b ₂₅₁ , the constants of the linear expressions (13), (14), and (18) are used. Constants a ₂₅₁ and b ₂₅₁ in this linear expression are derived as a ₂₅₁ = (a ₀₁ / a ₀ ) × a ₂₅ and b ₂₅₁ = (b ₀₁ / b ₀ ) × b ₂₅ . Then, as shown in FIG. 5, a plot showing the relationship between the silicon nitride film thickness Y and the film formation time X when 25 product wafers W are filled is obtained from this linear expression.
[0034]
8) Similarly, the relationship between the film thickness Y and the film formation time X when 50 product wafers W having a large surface area after the CVD apparatus maintenance are loaded is obtained. That is, when the primary expression indicating the relationship between the film thickness Y to be obtained and the film formation time X is Y = a _5o1 X + b ₅₀₁ , the constants of the linear expressions (13), (15), and (18) are used. Constants a ₅₀₁ and b ₅₀₁ in this linear expression are derived as a ₅₀₁ = (a ₀₁ / a ₀ ) × a ₅₀ and b ₅₀₁ = (b ₀₁ / b ₀ ) × b ₅₀ . Then, as shown in FIG. 5, a plot showing the relationship between the silicon nitride film thickness Y and the film formation time X when 50 product wafers W are filled is obtained from this linear expression.
[0035]
9) Further, the relationship between the film thickness Y and the film formation time X when 75 product wafers W having a large surface area after the CVD apparatus maintenance are loaded is obtained. That is, when the primary expression showing the relationship between the film thickness Y to be obtained and the film formation time X is Y = a ₇₅₁ X + b ₇₅₁ , the constants of the primary expressions (13), (16), and (18) are used. Constants a ₇₅₁ and b ₇₅₁ in this linear expression are derived as a ₇₅₁ = (a ₀₁ / a ₀ ) × a ₇₅ and b ₇₅₁ = (b ₀₁ / b ₀ ) × b ₇₅ . Then, as shown in FIG. 5, a plot showing the relationship between the silicon nitride film thickness Y and the film formation time X when 75 product wafers W are filled is obtained from this linear expression.
[0036]
10) Furthermore, the relationship between the film thickness Y and the film formation time X when 100 product wafers W having a large surface area after the CVD apparatus maintenance are loaded is obtained. That is, when the primary expression showing the relationship between the film thickness Y to be obtained and the film formation time X is Y = a ₁₀₀₁ X + b ₁₀₀₁ , the constants of the primary expressions (13), (17), and (18) are used. Constants a ₁₀₀₁ and b ₁₀₀₁ in this linear expression are derived as a ₁₀₀₁ = (a ₀₁ / a ₀ ) × a ₁₀₀ and b ₁₀₀₁ = (b ₀₁ / b ₀ ) × b ₁₀₀ . Then, as shown in FIG. 5, a plot showing the relationship between the silicon nitride film thickness Y and the film formation time X when 100 product wafers W are filled is obtained from this linear expression.
[0037]
11) After the above, the film formation time when the capacitor silicon nitride film 5 is formed with a predetermined film thickness on the product wafer W after the state of the CVD apparatus changes from these relational expressions or the plot of FIG. Is derived for each number of product wafers W filled in the CVD apparatus. For example, when the target film thickness of the capacitor silicon nitride film 5 is 5 nm, if the number of product wafers W is 25, the film formation time is 22 minutes and 15 seconds, and if the product wafer W is 50, If the film time is 22 minutes and 45 seconds and the number of product wafers W is 75, the film formation time is 23 minutes and 15 seconds. If the number of product wafers W is 100, the film formation time is 23 minutes and 45 seconds. .
[0038]
In the above embodiment, after the CVD apparatus is changed, such as after maintenance of the CVD apparatus, an experimental film formation is performed by filling the CVD apparatus with zero product wafers W. By performing only the processing, that is, each of the product wafers W of 25 sheets, 50 sheets, 75 sheets, and 100 sheets is filled in the CVD apparatus without performing each experimental film forming process. The relationship between the film thickness and the film formation time in the case where the product wafer W of the filled number is formed is obtained.
[0039]
For this reason, after the state of the CVD apparatus is changed, the number of experimental film forming processes is reduced as compared with the case where the experimental film forming process is performed for each filling number of the product wafers W. It becomes possible to reduce machine downtime. Further, it is possible to reduce the man-hours required for the experimental film forming process.
[0040]
Specifically, the film forming process is reduced at least twice for each of the 25 sheets, 50 sheets, 75 sheets, and 100 sheets. For this reason, when each film forming process takes 5 hours, it is possible to reduce the machine downtime of 4 stages × 2 times × 5 hours = 40 hours.
[0041]
As a result, the productivity of the semiconductor device can be improved.
[0042]
Further, since the first predetermined number of product wafers W filled in the CVD apparatus is set to 0, the CVD apparatus after the basic data such as the plot of FIG. 4 and the primary equations (13) to (17) is acquired. After the state change, it is not necessary to use the product wafer W for the experimental film forming process in order to derive the optimum film forming time for each filling number. Therefore, an experimental film formation process for deriving the film formation time can be easily performed using only normal flat wafers (dummy wafer and film thickness evaluation wafer). The first predetermined number is not limited to zero. However, if the first predetermined number is not 0, the first predetermined number is selected from the number of product wafers W (25 sheets, 50 sheets,...) In the manufacturing process. In this case, the filling number other than the selected filling number is the second predetermined number.
[0043]
In the above embodiments, the present invention has been described by taking the process of forming the capacitor silicon nitride film of the DRAM as an example. However, the present invention is not limited to this, and can be applied to a process of forming a capacitor dielectric film in the manufacture of, for example, a FeRAM (ferroelectric random access memory) or an MRAM (magnetic random access memory). At this time, the film forming material is not limited to the silicon nitride film, and a material suitable for each device is appropriately selected and used. Further, the configuration of the capacitor is not limited to the stacked type formed on the substrate as described with reference to FIG. 1, and may be a trench capacitor. Further, the present invention is not limited to the formation of capacitors, and can be widely applied to the case where film formation with high film thickness accuracy is performed on a product wafer whose surface area is extremely enlarged by having irregularities.
[0044]
【The invention's effect】
As described above, according to the film formation time derivation method and film formation method of the present invention, after the state of the CVD apparatus changes due to maintenance or the like, the film formation time for obtaining a desired film thickness is derived. It is possible to significantly reduce the number of times of the experimental film forming process, and it is possible to reduce the machine downtime and man-hours of the CVD apparatus. As a result, the productivity can be greatly improved in the film forming process for the product wafer having a greatly increased surface area.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration example of a product wafer to which the present invention is applied.
FIG. 2 is a diagram showing a configuration example of a batch type CVD apparatus to which the present invention is applied.
3 is a diagram for explaining a filling state of product wafers in the batch type CVD apparatus of FIG. 2; FIG.
FIG. 4 is a diagram showing a relationship between an experimentally derived film thickness and a film formation time.
FIG. 5 is a diagram showing the relationship between the film thickness obtained by the derivation method of the present invention and the film formation time.
[Explanation of symbols]
W ... Product wafer

Claims

A batch-type CVD apparatus is filled with a wafer having the maximum number of wafers by combining a product wafer having an uneven surface and a dummy wafer whose surface is flat compared to the product wafer, and forming a predetermined film thickness on the surface of the product wafer. A method for deriving a film formation time when performing a film,
An experimental film forming process in which a maximum number of processed wafers is loaded together with a first predetermined number of product wafers in the CVD apparatus is performed a plurality of times, and the relationship between the film forming time X and the film thickness Y is shown. Obtaining the linear expression Y = a _n1 X + b _n1 (1);
An experimental film forming process in which a maximum number of processed wafers is loaded together with a second predetermined number of product wafers in the CVD apparatus is performed a plurality of times, and the relationship between the film forming time X and the film thickness Y is shown. _Obtaining a linear expression Y = a _n2 X + b _n2 (2);
After the state of the CVD apparatus is changed, an experimental film formation process is performed a plurality of times by loading a dummy wafer together with the first predetermined number of product wafers into the CVD apparatus to obtain the maximum processing number, and a film formation time X And a step of obtaining a primary expression Y = a _n11 X + b _n11 (3) indicating a relationship between the film thickness Y and the film thickness Y;
Using the constants a _n1 , b _n1 , a _n2 , b _n2 , a _n11 , b _n11 in the primary expressions (1) to (3), the second predetermined number of sheets after the state of the CVD apparatus has changed. A linear expression Y = (a _n2 / a _n1 ) × a _n11 × X + (b _n2 / b _n1 ) × b _n11 ... Obtaining (4);
A step of obtaining a film formation time for obtaining a predetermined film thickness in the film forming process of the second predetermined number of product wafers after the state of the CVD apparatus is changed based on the primary expression (4); A film formation time deriving method characterized by:

A batch-type CVD apparatus is filled with a wafer having the maximum number of wafers by combining a product wafer having an uneven surface and a dummy wafer whose surface is flat compared to the product wafer, and forming a predetermined film thickness on the surface of the product wafer. A method of forming a film, in which a film forming time X and a film forming time are formed a plurality of times by carrying out an experimental film forming process in which a maximum number of processed wafers are loaded together with a first predetermined number of product wafers in the CVD apparatus. A step of _obtaining a primary expression Y = a _n1 X + b _n1 (5) indicating a relationship with the film thickness Y;
An experimental film forming process in which a maximum number of processed wafers is loaded together with a second predetermined number of product wafers in the CVD apparatus is performed a plurality of times, and the relationship between the film forming time X and the film thickness Y is shown. _Obtaining a linear expression Y = a _n2 X + b _n2 (6);
After the state of the CVD apparatus is changed, an experimental film formation process is performed a plurality of times by loading a dummy wafer together with the first predetermined number of product wafers into the CVD apparatus to obtain the maximum processing number, and a film formation time X And a step of obtaining a linear expression Y = a _n11 X + b _n11 (7) showing the relationship between the film thickness Y and the film thickness Y;
Using the constants a _n1 , b _n1 , a _n2 , b _n2 , a _n11 , b _n11 in the linear expressions (5) to (7), the second predetermined number of sheets after the state of the CVD apparatus changes A linear expression Y = (a _n2 / a _n1 ) × a _n11 × X + (b _n2 / b _n1 ) × b _n11 ... Obtaining (8);
Based on the linear expression (8), a film formation time for obtaining a predetermined film thickness in the film forming process of the second predetermined number of product wafers after the state of the CVD apparatus is changed is obtained. A film forming method comprising forming the second predetermined number of product wafers in a film forming time.