JP4270263B2 - Display device - Google Patents

Description

  The present invention relates to a display device, and in particular, a plurality of display pixels which are selected by a predetermined scanning line selection signal for a scanning line and supplied with an image signal from a data signal line are arranged on a substrate in a matrix. The present invention relates to an active matrix display device.

  For example, like a liquid crystal display element, a plurality of scanning lines and a plurality of data signal lines intersecting with each other are arranged on a glass substrate or the like, and a switching circuit is provided at the intersection of each scanning line and each data signal line. An active matrix display device in which display pixels are arranged is widely used. In the active matrix display device, when target image display or the like is not performed, a dummy still image or the like is displayed to reduce power consumption.

  For example, Patent Document 1 discloses an active matrix liquid crystal display device that can perform multi-color display with low power consumption during standby and can perform full-color intermediate display and moving image display during a call. Here, the gate of the first switch element is connected to the scanning line, the source is connected to the data signal line, the drain is connected to the pixel electrode, and the pixel electrode is connected to the digital memory via the second switch element. The second switch element is composed of two switch elements connected in parallel, each having a drain connected to the output terminal and the inverted output terminal of the digital memory, a source connected to the pixel electrode, and two A configuration in which a gate is connected to a control signal line is described.

  Patent Document 2 discloses a configuration for supporting two displays of a full-color moving image display and a low power consumption still image display with a single display device. Here, in the vicinity of the intersection of the gate signal line and the drain signal line of the display pixel, a circuit selection circuit composed of two TFTs having different polarities and another circuit selection circuit paired therewith are provided. In addition, an image selection circuit is provided which is adjacent to the circuit selection circuit and is connected in a column with the two previous TFTs, and is composed of two different TFTs having different polarities. A gate signal line is connected to both of these gates. Both TFTs are turned on simultaneously in response to the scanning signal. When the two circuit selection circuits select full color moving image display, one of the two TFTs of the circuit selection circuit and the storage capacitor constitute a first display circuit. On the other hand, a holding circuit made up of a static memory is connected between the other of the two TFTs of the circuit selection circuit and the pixel electrode of the liquid crystal, and the signal selection circuit receives an AC drive signal (signal A) or The counter electrode signal (signal B) is selected and supplied to the pixel electrode of the liquid crystal 21. Therefore, it is described that when the two circuit selection circuits select still image display, the other of the two TFTs of the circuit selection circuit, the holding circuit, and the signal selection circuit constitute a second display circuit.

JP 2001-264814 A JP 2002-91366 A

  According to the above prior art, when analog full color display such as halftone is not performed, binary digital still image data is held by digital memory or static memory and still image display is performed. The power consumption concerning can be reduced.

  However, according to the above prior art, since the same scanning line is used for analog display and digital display, the scanning line driving circuit is the same, and power consumption relating to scanning line driving or the like is not reduced.

  An object of the present invention is to provide a display device capable of further reducing power consumption in a display device capable of performing analog display and digital display.

A display device according to the present invention is arranged in one direction on a substrate and has a plurality of first scanning lines for analog display and a plurality of second scanning lines in one direction on the substrate and for digital display. And a plurality of data signal lines arranged in a direction crossing the one direction, and a predetermined scanning line selection signal for the first scanning line or the second scanning line, and the data signal line Are connected to a plurality of display pixels arranged on the substrate in a matrix form via a first switch circuit operated by the scanning line selection signal, and the display A first display circuit for analog display, which is arranged in a pixel and sequentially supplies the image signal input sequentially to the pixel electrode of the display pixel; and the second scanning line is generated by the scanning line selection signal. The digital circuit is connected via a second switch circuit, is disposed in the display pixel, has a holding circuit that holds the image signal, and supplies a voltage corresponding to the signal held by the holding circuit to the pixel electrode. A second display circuit for display, and mode switching for switching between an analog display mode in which the first display circuit operates and a digital display mode in which the second display circuit operates in response to a mode switching signal The mode switching signal is composed of a mode first switching signal and a mode second switching signal which are signals of opposite polarities to each other, and the mode switching circuit is provided on condition that the mode switching first signal is turned on. the first display to operate the circuit, and wherein Rukoto activates the second display circuit, subject to on-mode switching換第2 signal as.

  In the display device according to the present invention, a first scanning line driving circuit that outputs a scanning line selection signal for the first scanning line, and a second scanning line that outputs a scanning line selection signal for the second scanning line. The first scanning line driving circuit and the second scanning line driving circuit share a shift register circuit unit that outputs a sequential designation pulse for sequentially designating the display pixels in units of scanning lines. In the distribution circuit unit provided after the shared shift register circuit unit, it is preferable that the sequential designation pulses are distributed to the first scanning line or the second scanning line according to the distribution signal.

  In the display device according to the present invention, the first output circuit and the second output circuit are connected in parallel for each output of the shift register circuit unit, and correspond to each of the plurality of first scanning lines. A plurality of first output circuits provided, and a plurality of second output circuits provided corresponding to each of the plurality of second scanning lines, and the distribution circuit unit uses the distribution signal, It is preferable to distribute the output of the first output circuit or the output of the second output circuit to the first scanning line or the second scanning line.

  Moreover, it is preferable that the said distribution circuit part is comprised with a NOR circuit or a transmission gate.

  Further, it is preferable to use the mode switching signal as the distribution signal.

In the display device according to the present invention, the mode and the switching mode constitutes the signal first switching signal and a mode second switching signal, it is preferable that mutual signal amplitude is different.

  The mode switching circuit is provided between the first switch circuit and the pixel electrode, and is provided between the holding circuit and the pixel electrode, and a third switch circuit that operates according to a mode switching first signal. , Operating in accordance with the mode switching second signal, and supplying the pixel electrode with a signal in phase or opposite phase to the counter electrode signal applied to the counter electrode facing the pixel electrode in accordance with the signal held by the holding circuit And a fourth switch circuit.

  In the display device according to the present invention, it is preferable that the scanning line selection signal for the first scanning line and the scanning line selection signal for the second scanning line have mutually different signal amplitudes.

  With the above configuration, the display device is provided with the scanning lines for each display pixel separately into a plurality of first scanning lines for analog display and a plurality of second scanning lines for digital display. The first scanning line has a first display circuit for analog display via a first switch circuit, and the second scanning line has a second display circuit for digital display via a second switch circuit. The second display circuit is provided with a holding circuit for holding an image signal. Here, mode switching is performed between an analog display mode in which the first display circuit operates and a digital display mode in which the second display circuit operates in response to the mode switching signal. In this way, since separate scanning lines are used for analog display and digital display, scanning line driving for analog display and scanning line driving for digital display can be controlled separately. It becomes possible. Compared to the scanning line drive for analog display, the scanning line drive for digital display is not required to have high speed or the like, so that the power consumption can be further reduced as compared with the case where the scanning lines are the same.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Hereinafter, as an active matrix display device, COG (Chip On Glass) technology in which an IC chip is mounted on a substrate on which a polysilicon TFT (Thin Film Transistor) is arranged can be illuminated with a backlight. Although a liquid crystal display device will be described, a display mechanism other than a liquid crystal device may be used as long as the display device is an active matrix type and can display analog display and digital display with one device. For example, in some cases, an LED (Light Emission Diode) array display device, a plasma display device, or the like may be used.

  Further, a switching element other than the polysilicon TFT may be used, or a COG technique may not be used. For example, an amorphous silicon TFT may be used. The polysilicon TFT may be a high temperature polysilicon TFT or a low temperature polysilicon TFT. Further, instead of the TFT, for example, a non-linear switching element such as a diode ring may be used. Moreover, the structure using mounting techniques other than COG technique may be sufficient. For example, the control IC or the like may be arranged on a circuit board different from the glass substrate. Moreover, the structure which does not use a backlight may be sufficient. For example, a reflective display device that includes a reflector and can visually recognize the display by external light may be used.

  The voltage values and the like in the following are examples for explanation, and can be appropriately changed according to the use of the display device and the like.

  FIG. 1 is a perspective view of the display device 10. The display device 10 includes a lower glass substrate 30, an upper glass substrate 12, a sealing material 16 that seals the liquid crystal 14 between both glass substrates, and a light guide element 18 on the back side of the lower glass substrate 30. The liquid crystal display device can be illuminated with a backlight of an active matrix type including the backlight 20 disposed and the polarizing element 22 disposed on the surface side of the upper glass substrate 12. A control IC 32 is mounted on the lower glass substrate 30 using COG technology, and is connected to the external circuit substrate 26 by a suitable flexible circuit substrate 24 such as an FPC (Flexible Print Circuit).

  The upper glass substrate 12, together with the lower glass substrate 30, sandwiches the liquid crystal 14 and applies a predetermined driving voltage to both sides of the liquid crystal 14 to display, and is opposed to the lower glass substrate 30. Also called a substrate. A common electrode that is a counter electrode is provided on the upper glass substrate 12 so as to face the pixel electrodes in the lower glass substrate 30, and a common electrode potential is applied thereto.

  The lower glass substrate 30 is a transparent substrate in which a plurality of scanning lines and a plurality of data signal lines are arranged in a lattice shape, and display pixels and polysilicon TFTs as switching elements are arranged in each lattice region. Here, two types of scanning lines are used as the scanning lines, and one type of scanning line is the same as the scanning line of a normal active matrix liquid crystal display device. That is, when this scanning line is used, the image signal from the data signal line is supplied to the pixel electrode of each display pixel selected by the scanning line by the function of the switching element, and the counter electrode is provided on the upper glass substrate 12. Display can be performed by driving the liquid crystal molecules sealed between the upper glass substrate 12 and the lower glass substrate 30 in accordance with the potential difference between the electrodes. The other type of scanning line is for displaying a still image.

  In this way, two types of scanning lines are used. As described above, one type of scanning line is the same as the scanning line of a normal active matrix type liquid crystal device, and performs intermediate gradation display, moving image display, and the like. Used when In the case of a color display device, it is used for full color display. The other type of scanning line is used to display a still image by using a holding circuit capable of holding a binary value, which will be described later, while suppressing power consumption related to image display. By distinguishing these two displays, the former can be called analog display and the latter can be called digital display. Instead of the distinction between analog display and digital display, in the case of dynamic display, static display, or color display, they can also be called full color display and still image display. In the following, the designations of analog display and digital display are used, and other designations are used as appropriate when other designations are appropriate.

  In order to distinguish between the two types of scanning lines, one type of scanning line used for analog display is called a first scanning line, and the other type of scanning line used for digital display is called a second scanning line. When analog display and digital display are performed for each display pixel, two scanning lines of the first scanning line and the second scanning line and one data signal line are arranged for each display pixel. Will be.

  FIG. 2 is a diagram showing a state of arrangement of each element on the lower glass substrate 30. A display area 40 having a substantially rectangular shape in a planar arrangement is provided at the center of the lower glass substrate 30, and the scanning lines are sequentially selected for the first scanning line 82 and the second scanning line 84 around the display area 40. Scanning line driving circuits A and B (80) for the above, an image signal corresponding to each gradation, that is, a data line driving circuit 70 for inputting a video signal to the data signal line 72, and a video signal to the data signal line 72. Before inputting, a data line precharge circuit 34 for inputting an intermediate potential of video amplitude is arranged. The scanning line drive circuits A and B (80), the data line drive circuit 70, and the data line precharge circuit 34 are connected to the control IC 32, respectively.

  The scanning line drive circuits A and B (80), the data line drive circuit 70, and the data line precharge circuit 34 are similar to the TFTs in the display area 40, using the TFTs formed by the polysilicon transistor formation technique to form the lower glass. Built on the substrate 30. That is, the lower glass substrate 30 is a SOG (System On Glass) substrate in which active elements are formed.

  As the scanning line driving circuits A and B (80), a scanning line driving circuit used in a normal active matrix liquid crystal display device can be used as it is. However, in order to reduce power consumption related to scanning line driving, an analog display is used. It is preferable to use one suitable for distinguishing between the digital display and the digital display. The detailed contents of the scanning line driving circuits A and B (80) will be described later.

  As the data line driving circuit 70, a data line driving circuit used in a normal active matrix liquid crystal display device can be used as it is. Details of the data line driving circuit 70 will be described later.

  The control IC 32 is an LSI (Large Scale Integrated circuit) chip having a function of controlling operations of the scanning line driving circuits A and B (80), the data line driving circuit 70, the data line precharge circuit 34, and the like. It is mounted on the wiring pattern provided above by COG technology. This wiring pattern extends to the scanning line driving circuits A and B (80), the data line driving circuit 70, the data line precharge circuit 34, and the like, and also extends to the end of the lower glass substrate 30, and as described in FIG. In this manner, the flexible circuit board 24 is connected.

  The display area 40 is an area where a plurality of display pixels 42 are arranged in a matrix. There, a plurality of first scanning lines 82 and a plurality of second scanning lines 84 from the scanning line driving circuits A and B (80) are arranged along one direction of the planar arrangement of the lower glass substrate 30, and the data lines A plurality of data signal lines 72 from the drive circuit 70 are arranged along a direction intersecting the one direction, for example, a direction orthogonal to the one direction. In the example of FIG. 2, the first scanning line 82 and the second scanning line 84 are arranged along the left-right direction of the paper surface, and the data signal line 72 is arranged along the vertical direction of the paper surface. The first scanning line 82 and the second scanning line 84 are arranged to form a pair, and the display area 40 is divided into a plurality of grid-like areas by the paired scanning lines and the data signal line 72. The display pixels 42 are arranged in the grid area. Here, in the case of a color display device, subpixels are used for each of R, G, and B. In the following, this subpixel will be described as a display pixel 42.

  FIG. 3 is a diagram illustrating the configuration of the display pixel 42. In the following description, the reference numerals in FIGS. 1 and 2 are used. Here, one pixel in the upper left corner of the display area 40 in FIG. 2 is representatively shown. That is, in order to distinguish the plurality of display pixels 42, the position of the grid-like region divided by the first scanning line 82, the second scanning line 84, and the data signal line 72 is shown in FIG. 3, the right direction is the X direction and the lower direction is the Y direction, and X and Y indicate that the display pixel 42 in FIG. Similarly, in order to distinguish the plurality of first scanning lines 82, the plurality of second scanning lines 84, and the plurality of data signal lines 72 from each other, the upper left of FIG. If the number is increased, the first scanning line 82, the second scanning line 84, and the data signal line 72 corresponding to the display pixel 42 in FIG. In FIG. 3, the first scanning line 82 is represented as GATE-1A, the second scanning line 84 is represented as GATE-1B, and the data signal line 72 is represented as DATA-1.

In FIG. 3, the liquid crystal 14 for display is shown as a liquid crystal capacitance C _LC (54). Liquid crystal capacitance C _LC (54) includes a pixel electrode wiring 55, the capacitance between the common electrode signal line 60 which is a counter electrode. Here, the common electrode signal line 60 is shown as SC.

  Each signal line in FIG. 3 will be described first. VDD (36) and VSS (38) are a power supply voltage line and a ground line of the control IC 32. For example, VDD = + 5V, VSS = 0V, etc. are set.

  As described above, the common electrode signal line 60 is a signal line that transmits the common electrode signal SC applied to the common electrode that is a counter electrode provided on the upper glass substrate 12. As the common electrode signal SC, a rectangular wave signal is used for AC driving of the liquid crystal 14. For example, a rectangular wave signal that changes between 0V and + 4V can be used.

  Vb (64) and Vw (66) are signal lines used for AC driving of the liquid crystal 14 during digital display. Vw (66) is a signal line that transmits a potential at which the liquid crystal 14 displays white when it is applied to the pixel electrode wiring 55, and is a signal line that transmits the same signal as the common electrode signal in the common electrode signal line 60. . Vb (64) is a signal line that transmits a potential at which the liquid crystal 14 displays black when it is applied to the pixel electrode wiring 55, and a signal line that transmits a signal obtained by inverting the common electrode signal in the common electrode signal line 60. is there.

  MODE (62) and XMODE (63) are signal lines for transmitting two mode switching signals for switching between the analog display mode and the digital display mode for the display pixel. By distinguishing the two mode switching signals, the signal in MODE (62) can be called a mode switching first signal, and the signal in XMODE (63) can be called a mode switching second signal. The mode switching first signal in MODE (62) and the mode switching second signal in XMODE (63) are mutually inverted signals. The mode switching first signal in MODE (62) is at the H level, and in XMODE (63). When the mode switching second signal is at L level, the analog display mode is set. When the mode switching first signal in MODE (62) is at L level and when the mode switching second signal in XMODE (63) is at H level, digital display is performed. Mode.

  The mode switching first signal in MODE (62) and the mode switching second signal in XMODE (63) have opposite polarities as described above, but are further different in amplitude and are asymmetric in waveform. . This is because the N-channel transistor 48 is turned on / off by the H level of MODE (62) and an analog image signal is transmitted to the pixel electrode wiring 55, whereas the H level of XMODE (63) is Vb (64). Or it comes from the difference of simply switching between two potential levels at Vw (66). For example, for switching between the analog display mode and the digital display mode, the mode switching first signal in MODE (62) is set to H level = + 9V, L level = 0V, and the mode switching second signal in XMODE (63) is set to L level. = -4V, H level = + 4V.

  In FIG. 3, each element constituting the display pixel 42 will be described next. The N channel transistor 44 is an element that operates in response to a scanning line selection signal of the first scanning line 82. The N-channel transistor 46 is an element that operates in response to a scanning line selection signal for the second scanning line 84. By distinguishing these two elements, the N-channel transistor 44 can be called a first switch circuit, and the N-channel transistor 46 can be called a second switch circuit.

  An N-channel transistor 48 is also connected between the N-channel transistor 44 that is the first switch circuit and the pixel electrode wiring 55. The N-channel transistor 48 is an element that operates in response to a mode switching first signal in MODE (62), and can be called a third switch circuit. When both the N-channel transistor 44 as the first switch circuit and the N-channel transistor 48 as the third switch circuit are on, that is, the first scan line 82 is selected by the scan line selection signal, and the mode When the analog display mode is selected by the switching first signal, the image signal data of the data signal line 72, that is, the video signal data is transmitted to the pixel electrode wiring 55 and written into the liquid crystal 14.

Here, in a narrow sense, if a circuit for analog display that sequentially supplies image signals sequentially input from the data signal line 72 to the pixel electrode wiring 55 of the display pixel 42 for the display pixel 42 is the first display circuit. The liquid crystal capacitor C _LC 54 and the holding capacitor C _S 52 correspond to the first display circuit. In a broad sense, the N channel transistor 44 and the N channel transistor 48 are further referred to as a first display circuit. Can do.

  A holding circuit 56 that can hold data statically by connecting two inverters in a ring shape is connected to the output side of the N-channel transistor 46 that is the second switch circuit. The holding circuit 56 is a circuit having a function of holding image signal data statically when the image signal data is written therein, and is a static memory that consumes little power for holding the data.

  In addition, two sets of transmission gates 58 and 59 provided between the output terminals of the two inverters constituting the holding circuit 56 have a Vb (64) signal or Vw according to the signal held by the holding circuit 56. The function of supplying the signal (66) to the transmission gate 50 is provided. Since the tip of the transmission gate 50 is the pixel electrode wiring 55, the transmission gates 58 and 59 set the potential supplied to the pixel electrode wiring 55 according to the data stored in the holding circuit 56 to the signal level of Vb (64). Or a function of a pixel electrode potential selection switch for selecting the signal level of Vw (66).

  The transmission gate 50 is a circuit that operates according to the second mode switching signal of XMODE (63) and the inverted signal of the first mode switching signal of MODE (62), and can be called a fourth switch circuit. The transmission gate 50 as the fourth switch circuit has a function of supplying the Vb (64) signal or the Vw (66) signal, which is the output of the two sets of transmission gates 58 and 59, to the pixel electrode wiring 55. That is, when XMODE (63) is at the H level and MODE (62) is at the L level, the Vb (64) signal or the Vw (66) signal is applied to the pixel electrode wiring 55 in accordance with the signal held by the holding circuit 56. To supply. As described above, the signal of Vw (66) is the same signal as the SC of the common electrode signal line 60, and the signal of Vb (64) is an inverted signal of the SC. The liquid crystal 14 between the pixel electrode wiring 55 and the common electrode signal line 60 can be AC driven. That is, the liquid crystal 14 can display a binary still image corresponding to the signal held by the holding circuit 56.

  Here, the display pixel 42 includes a holding circuit 56 that holds an image signal, and a circuit for digital display that supplies a voltage corresponding to the signal held by the holding circuit 56 to the pixel electrode wiring 55 is a second display. In the narrow sense, the holding circuit 56 corresponds to the second display circuit. In the broad sense, the N-channel transistor 46, the holding circuit 56, the transmission gates 58 and 59, and the transmission gate 50. Can be called a second display circuit. In FIG. 3, a circuit portion 43 surrounded by a broken line corresponds to the second display circuit in a broad sense. In the display pixel 42, a circuit portion excluding the circuit portion 43 surrounded by a broken line corresponds to the above-described broad first display circuit.

  The N-channel transistor 48 is operated by the first mode switching signal in MODE (62), and the transmission gate 50 is operated by the second mode switching signal in XMODE (63). Since it has a function of switching between the digital display modes, these circuit portions can be collectively referred to as a mode switching circuit.

  In this way, for each display pixel 42 of the display device 10, the first scanning line 82 and the second scanning line 84 are selected by the predetermined scanning line selection signal, the image signal is received from the data signal line 72, and the mode switching operation is performed. The analog display mode or the digital display mode can be selected by the 1 signal and the mode switching second signal, and the first display circuit or the second display circuit can be operated to perform the analog display or the digital display.

  Returning to FIG. 2 again, the scanning line driving circuits A and B (80) will be described. The scanning line driving circuits A and B (80) are circuits having a function of generating a scanning line selection signal. Specifically, the selection between the first scanning line 82 and the second scanning line 84 is performed, and further, between the plurality of first scanning lines 82 and the plurality of second scanning lines 84, every time. This circuit generates a scanning line selection signal for performing selection in order.

  In FIG. 2, the scanning line driving circuits A and B (80) are shown as one chip, but may be constituted by a plurality of chips. In that case, a plurality of chips may be arranged along a plurality of arbitrary sides of the display area 40. For example, the scanning line driving circuits A and B (80) may be two chips, and one chip may be arranged on one side of two sides facing each other across the display region 40, and another chip may be arranged on the other side. .

  Therefore, a circuit for generating a signal for selecting a specific scanning line among the plurality of first scanning lines 82 is a first scanning line driving circuit, and a signal for selecting a specific scanning line among the plurality of second scanning lines 84 is used. When the circuit for generating the second scanning line driving circuit is referred to as the second scanning line driving circuit, the scanning line driving circuits A and B (80) combine the first scanning line driving circuit and the second scanning line driving circuit. A circuit having a configuration and a function. Specifically, in the first scanning line driving circuit and the second scanning line driving circuit, the common element has a common part and has a specific element separately.

  FIG. 4 is a diagram showing the configuration of the scanning line driving circuits A and B (80). The scanning line drive circuits A and B (80) sequentially select each first scanning line 82 and each second scanning line 84 based on a sequential signal 86 composed of a start signal and a clock signal. Is a circuit that generates The scanning line driving circuits A and B (80) include a shift register circuit unit 90, a distribution circuit unit 88, a level shift circuit unit 92, and an output driver circuit unit 94.

  The shift register circuit unit 90 is a circuit having a function of sequentially shifting sequential signals 86 sequentially input and outputting sequential designation pulses for designating display pixels in units of scanning lines. The number of shift register circuit units 90 is the same as the number of the display pixels 42 arranged in the scanning direction. In other words, if one first scanning line 82 and one second scanning line 84 are arranged for each display pixel 42, the number of first scanning lines = the number of second scanning lines = the shift register. This is the number of circuit units 90. That is, the shift register circuit unit 90 uses one shift register circuit in common for the first scanning line 82 and the second scanning line 84. Thereby, the scale of the scanning line driving circuits A and B (80) can be suppressed. As the shift register circuit portion 90, for example, one that operates at a voltage of 0 V to +5 V can be used.

  The distribution circuit unit 88 is arranged after the shift register circuit unit 90, and has a function of distributing the output of each shift register circuit unit 90 to the first scanning line 82 or the second scanning line 84 in accordance with the distribution signal. is there. The distribution signal may be a signal that selects either the first scanning line 82 or the second scanning line 84. For example, a special signal for analog display or a special signal for digital display can be supplied from the control IC 32.

  The mode switching first signal or the mode switching second signal can be used as the distribution signal. In FIG. 4, in addition to the enable signal of the enable signal line 87, a mode switching first signal which is a MODE (62) signal is used. As described above, the mode switching first signal is a signal for selecting the analog display mode at the H level and the digital display mode at the L level, so that the first scanning line 82 is at the H level and the L level is at the L level. It can be distributed to the second scanning line 84. Instead of the first mode switching signal, the second mode switching signal of XMODE (63) may be used. Thus, it is not necessary to generate a special distribution signal by using the mode switching first signal or the mode switching second signal.

  The level shift circuit unit 92 is a circuit having a function of converting the level and amplitude of the distributed signal into a level and amplitude suitable for the scanning line selection signal. The level shift circuit unit 92 can be configured using a known signal level shift circuit technique. The output driver circuit unit 94 is a buffer circuit for supplying a current sufficient to drive the scanning line. The level shift circuit unit 92 and the output driver circuit unit 94 are provided for each of the first scanning lines 82 and for each of the second scanning lines 84. In other words, (number of first scanning lines 82 + number of second scanning lines 84) = number of level shift circuit units 92 = number of output driver circuit units 94. That is, the level shift circuit unit 92 and the output driver circuit unit 94 are provided separately for the first scanning line 82 and for the second scanning line 84, and can be shared. Absent. Although the output level of the output driver circuit unit 94 varies depending on the application of the display device 10, it can be set to, for example, 0 V to −5 V, 0 V to +8 V, +9 V, or the like.

  The output level of the output driver circuit section 94, that is, the level of the scanning line selection signal can be the same as that for the first scanning line 82 and that for the second scanning line 84. As a result, the level shift circuit unit 92 can be shared, and the output driver circuit unit 94 can be shared.

  In some cases, the output level of the output driver circuit section 94 may be different for the first scanning line 82 and for the second scanning line 84. For example, the first scanning line 82 has a larger amplitude than that for the second scanning line 84 in the case of static digital display in consideration of capacitive coupling with the common electrode in the case of analog display. It is preferable to set. In other words, the signal amplitude with respect to the second scanning line 84 in the case of digital display can be made smaller than the signal amplitude with respect to the first scanning line 82 in the case of analog display. Can do. For example, the scanning line selection signal for the first scanning line 82 may have an amplitude of −4 V to +9 V, the scanning line selection signal for the second scanning line 84 may have an amplitude of 0 V to +5 V, and the like.

  FIG. 5 is a diagram showing the configuration of the scanning line driving circuit in comparison with that used in a normal active matrix liquid crystal display device and that described in FIG. FIG. 5A shows a configuration of a scanning line driving circuit conventionally used in an active matrix liquid crystal display device, and is controlled by a shift register circuit unit (SR UNIT) 90 and an enable signal for each scanning line. One enable circuit unit (ENB UNIT) 89, one level shift circuit unit (LS UNIT) 92, and one output driver circuit unit (BUF UNIT) 94 are used. The shift register circuit unit 90, the level shift circuit unit 92, and the output driver circuit unit 94 are the same as those described in FIG.

  On the other hand, FIG. 5B is a diagram showing the configuration of the scanning line drive circuits A and B (80) described in FIG. 4, and the first scanning line (GATE1A etc.) 82 and the second scanning line (GATE1B etc.). ) 84, the shift register unit (SR UNIT) 90 is used in common, and the output of the shift register circuit unit 90 is connected to the first scanning line 82 by the distribution circuit unit 88 that adds the MODE signal to the enable circuit unit. This is distributed to the second scanning line 84. Here, the distribution circuit unit 88 validates the enable signal according to the MODE signal, and outputs the output of the shared shift register circuit unit 90 to the level shift circuit unit and output driver circuit for the first scanning line. Therefore, the second scanning line level shift circuit unit and the output driver circuit unit function.

  Therefore, in FIG. 5A of the prior art, the number of the shift register circuit unit 90, the enable circuit unit 89, the level shift circuit unit 92, and the output driver circuit unit 94 is respectively required by the number of scanning lines. According to the configuration described with reference to FIG. 4, as shown in FIG. 5B, since the shift register circuit unit 90 is shared for the first scanning line and the second scanning line, the number of shift register circuit units 90 is scanned. Half the total number of lines. As a result, the overall scale of the scanning line driving circuits A and B can be suppressed.

  FIG. 6 is a diagram for explaining the operation of the scanning line driving circuits A and B. In FIG. 6A shows a case where the mode switching second signal in XMODE is at L level, and FIG. 6B shows a case where each of the first scanning lines (GATE1A, etc.) and each of the mode switching second signal is at H level. It is a figure which shows how a 2nd scanning line (GATE1B etc.) is selected. As shown in FIG. 6A, when the mode switching second signal in XMODE is at L level, each first scanning line (GATE1A, etc.) is selected sequentially. On the other hand, when the mode switching second signal in XMODE is at the H level, as shown in FIG. 6B, each second scanning line (GATE1B, etc.) is selected sequentially.

  Returning to FIG. 2 again, the data line driving circuit 70 is a circuit having a function for inputting an image signal corresponding to each gradation, that is, a video signal, to the data signal line 72 as described above. Here, a data line driving circuit for a normal active matrix liquid crystal display device can be used as it is.

  FIG. 7 is a diagram showing a configuration of the data line driving circuit 70. The data line driving circuit 70 is mainly composed of a plurality of demultiplexers 78, and is connected to a video signal line 74 supplied from the outside and a select signal line 76 also supplied from the outside. The video signal is divided into three components of R, G, and B by the select signal and output to the data signal line 72 of each display pixel that is a color display sub-pixel.

  The operation of the display device 10 having the above configuration will be described. In the normal operation of the display device 10, full-color analog display is performed. At this time, the control IC 32 sets the mode switching to the analog display mode, sets the mode switching first signal in MODE (62) to H, sets the mode switching second signal in XMODE (63) to L, each display pixel 42, This is supplied to the scanning line driving circuits A and B (80). In the scanning line driving circuits A and B (80), the distribution circuit unit 88 outputs the scanning line selection signal so as to select the first scanning line 82 side and select the first scanning line 82 of each display pixel 42. To do. As a result, in each display pixel 42, the N-channel transistor 44 is turned on, and the mode selection circuit turns on the N-channel transistor 48 to operate the first display circuit and execute analog display. At this time, the N-channel transistor 46 on the digital display side is turned off, and since the mode switching second signal in XMODE (63) is L, the second display circuit side is completely disconnected from the first display circuit side. It will be in the state.

  When the display device 10 enters the standby state, the control IC 32 sets the mode switching to the digital display mode, sets the mode switching first signal in MODE (62) to L, sets the mode switching second signal in XMODE (63) to H, This is supplied to the display pixel 42 and the scanning line driving circuits A and B (80). In the scanning line driving circuits A and B (80), the distribution circuit unit 88 outputs the scanning line selection signal so that the second scanning line 84 side is selected and the second scanning line 84 of each display pixel 42 is selected. To do. As a result, in each display pixel 42, the N-channel transistor 46 is turned on, and the holding circuit 56 holds the image signal as binary data. Then, the mode selection circuit sets the transmission gate 50 in the conductive state, operates the second display circuit, and executes digital display. At this time, the N-channel transistor 44 on the analog circuit side is turned off, and the mode switching first signal in MODE (62) is L, so that the first display circuit side is completely disconnected from the second display circuit side. It will be in the state.

  Thereby, in one display device 10, it is possible to perform the analog display mode and the digital display mode, and the power consumption related to the display during standby can be reduced. Further, since the scanning line driving circuits A and B (80) share the shift register circuit unit 90 between the first scanning line 82 and the second scanning line 84, even if two types of scanning lines are used, The configuration scale can be suppressed. Further, the amplitude of the scanning line selection signal can be set differently between the first scanning line 82 and the second scanning line 84, and in this case, power consumption related to scanning line driving can also be reduced.

  In the above description, in the scanning line driving circuits A and B (80), the distribution circuit unit 88 is described as being disposed between the shift register circuit unit 90 and the level shift circuit unit 92. In addition to this, in the scanning line driving circuits A and B, the distribution circuit portion can be provided after the output driver circuit portion. FIG. 8 is a diagram showing the configuration of the scanning line driving circuits A and B (100) having such a configuration. Here, the same code | symbol is attached | subjected to the element which is common in FIG. 4, and detailed description is abbreviate | omitted.

  The scanning line driving circuits A and B (100) share the shift register circuit unit 90, the level shift circuit unit 92, and the output driver circuit unit 94 for the first scanning line and the second scanning line, and output driver circuit The unit 94 is provided with two outputs. These two outputs are distributed to the first scanning line (GATE1A and the like) and the second scanning line (GATE1B and the like) by the distribution circuit unit 106 including the NOR circuit 104 using a pair of distribution signals 102 having different polarities. . As the distribution signal, a dedicated signal may be used, or a MODE or XMODE signal may be used. The connection between the shift register circuit unit 90 and the level shift circuit unit 92 is controlled by an enable signal line 87.

  By doing so, the common part between the first scanning line and the second scanning line is enlarged, and the overall size of the scanning line driving circuits A and B (100) can be further suppressed. it can.

  The NOR circuit in FIG. 8 can be replaced with another circuit having a signal distribution function. FIG. 9 is a diagram illustrating a configuration of the scanning line driving circuits A and B (110) having the distribution circuit unit 116 using the transmission gate 114. In FIG. Elements similar to those in FIGS. 4 and 8 are denoted by the same reference numerals, and detailed description thereof is omitted. The configuration of FIG. 8 is merely the replacement of the NOR circuit 104 with the transmission gate 114, and this configuration also enlarges the common portion between the first scanning line and the second scanning line, and the scanning line. The overall size of the drive circuits A and B (110) can be suppressed.

1 is a perspective view of a display device in an embodiment according to the present invention. It is a figure which shows the mode of arrangement | positioning of each element on the lower glass substrate of embodiment which concerns on this invention. It is a figure explaining the structure of a display pixel in embodiment which concerns on this invention. It is a figure which shows the structure of the scanning line drive circuits A and B in embodiment which concerns on this invention. It is a figure shown compared with what is used for the normal active matrix liquid crystal display device about the structure of the scanning-line drive circuit of embodiment which concerns on this invention. It is a figure explaining the effect | action of the scanning line drive circuits A and B in embodiment which concerns on this invention. It is a figure which shows the structure of a data line drive circuit in embodiment which concerns on this invention. It is a figure which shows the structure of the scanning line drive circuits A and B in other embodiment. It is a figure which shows the structure of the scanning line drive circuits A and B in other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display apparatus, 12 Upper glass substrate, 14 Liquid crystal, 16 Sealing material, 18 Light guide element, 20 Backlight, 22 Polarization element, 24 Flexible circuit board, 26 External circuit board, 30 Lower glass board, 32 Control IC, 34 data line precharge circuit, 36 VDD, 38 VSS, 40 display area, 42 display pixel, 43 circuit portion, 44, 46, 48 N channel transistor, 50, 58, 59, 114 transmission gate, 52 holding capacitor C _S , 54 liquid crystal capacitance C _LC , 55 pixel electrode wiring, 56 holding circuit, 60 common electrode signal line, 62 MODE, 63 XMODE, 64 Vb, 66 Vw, 70 data line driving circuit, 72 data signal line, 74 video signal line, 76 Select signal line, 78 Demultiplexer, 80, 100, 110 Scan line drive circuits A, B, 82 First scan line, 8 Second scanning line, 86 sequential signal, 87 enable signal line, 88, 106, 116 distribution circuit unit, 89 enable circuit unit, 90 shift register circuit unit, 92 level shift circuit unit, 94 output driver circuit unit, 102 distribution signal 104 NOR circuit.

Claims (8)

A plurality of first scan lines arranged in one direction on the substrate for analog display;
A plurality of second scan lines arranged in one direction on the substrate for digital display;
A plurality of data signal lines arranged in a direction crossing the one direction;
A plurality of display pixels which are selected by a predetermined scanning line selection signal for the first scanning line or the second scanning line and supplied with an image signal from the data signal line and arranged on the substrate in a matrix form When,
Connected to the first scanning line via a first switch circuit operated by the scanning line selection signal, arranged in the display pixel, and sequentially supplied to the pixel electrode of the display pixel. A first display circuit for analog display;
A signal connected to the second scanning line via a second switch circuit operated by the scanning line selection signal, disposed in the display pixel, and holding the image signal, the signal held by the holding circuit A second display circuit for digital display that supplies a voltage corresponding to the pixel electrode to the pixel electrode;
A mode switching circuit that performs mode switching between an analog display mode in which the first display circuit operates and a digital display mode in which the second display circuit operates in response to a mode switching signal;
Equipped with a,
The mode switching signal is composed of a mode first switching signal and a mode second switching signal which are signals of opposite polarities to each other,
Mode switching circuit, mode switching換第actuates said first display circuit turns on the condition of the first signal, the mode switching換第 display device comprising Rukoto activates the second display circuit turns on the condition of the two signals . The display device according to claim 1,
A first scanning line driving circuit for outputting a scanning line selection signal for the first scanning line;
A second scanning line driving circuit for outputting a scanning line selection signal for the second scanning line;
With
The first scanning line driving circuit and the second scanning line driving circuit are shared by using a shift register circuit unit that outputs a sequential designation pulse for sequentially designating the display pixels in units of scanning lines. In the distribution circuit unit provided after the shift register circuit unit, the sequential designation pulses are distributed to the first scanning line or the second scanning line according to the distribution signal. The display device according to claim 2,
A first output circuit and a second output circuit connected in parallel for each output of the shift register circuit section, and a plurality of first output circuits provided corresponding to each of the plurality of first scanning lines. And a plurality of second output circuits provided corresponding to each of the plurality of second scanning lines,
The distribution circuit unit uses the distribution signal to distribute the output of the first output circuit or the output of the second output circuit to the first scanning line or the second scanning line. The display device according to claim 3,
The display device according to claim 1, wherein the distribution circuit unit includes a NOR circuit or a transmission gate. The display device according to any one of claims 2 to 4,
The display device using the mode switching signal as the distribution signal. The display device according to claim 1,
The mode is off constitutes a signal mode first switching signal and a mode second switching signal, the display device characterized by mutual signal amplitude is different. The display device according to claim 6,
The mode switching circuit is
A third switch circuit provided between the first switch circuit and the pixel electrode and operating according to a mode switching first signal;
Provided between the holding circuit and the pixel electrode, operates in accordance with a mode switching second signal, and is in phase with a counter electrode signal applied to a counter electrode facing the pixel electrode or in accordance with a signal held by the holding circuit or A fourth switch circuit for supplying a negative-phase signal to the pixel electrode;
A display device comprising: The display device according to claim 1,
The display device, wherein the scanning line selection signal of the first scanning line and the scanning line selection signal of the second scanning line have different signal amplitudes.

Images