JP4265478B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device in which an IC chip is mounted on a circuit board and a manufacturing method thereof.

  Conventionally, a semiconductor device in which an IC chip is mounted on a circuit board is known, and an example thereof is disclosed in Patent Document 1.

In this semiconductor device (semiconductor package), an electrode (metallized surface) provided on an IC chip and a pad provided on the circuit board are electrically connected by a plurality of wires in a state where the IC chip is arranged on the circuit board. Are connected to each other. As a result, the resistance of the electrical wiring portion (including electrodes, pads, and wires) between the semiconductor element formed on the IC chip and the external electrode on the circuit board, that is, the wiring resistance is reduced.

  However, in the case of the above configuration, since the electrode area for connecting a plurality of wires needs to be secured on the surface of the IC chip, the size of the IC chip is increased. Further, since the IC chip and the circuit board are connected by wires, the physique of the semiconductor device cannot be made substantially equal to the IC chip. That is, the size cannot be reduced. Moreover, since it is necessary to connect a some wire, processing time becomes long.

  In addition, there is a method of reducing the wiring resistance by increasing the thickness of the electrode formed on the surface of the IC chip. However, since this electrode is usually formed using a CVD method or the like, there is a problem that processing time becomes long if it is formed thick.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a semiconductor device that can reduce the physique and reduce the processing time while reducing the wiring resistance, and a method for manufacturing the same.

The invention described in claims 1 to 8 is an invention related to a semiconductor device.

In order to achieve the above object, a semiconductor device according to claim 1, an IC chip having a plurality of electrodes on one surface, an insulating substrate, a wiring pattern provided on at least one of the inside and the surface of the insulating substrate, A circuit board having a via hole filled with a connection material and a circuit board having an external electrode provided on the surface of the insulating substrate and electrically connected to the wiring pattern, the IC chip being formed on the circuit board; It is mounted and the electrode and the wiring pattern are electrically connected via a connecting material. The wiring pattern is thicker than the electrode, and a plurality of via holes are provided in a substantially uniform manner for each electrode of the IC chip. The insulating substrate is made of a thermoplastic resin. It is bonded to a connection material filled in a via hole, and the bonded portion is sealed with a thermoplastic resin.

Thus, according to the semiconductor device of the present invention, the wiring pattern on the circuit board is thicker than the electrode of the IC chip. Further, the electrodes of the IC chip are directly bonded to the connection material filled in the via holes. Furthermore, a plurality of via holes are provided in each electrode so as to be distributed substantially evenly, so that the wiring length from the electrode to the via hole filled with the connection material can be shortened even when the electrode area is large. It has become. Therefore, it is possible to reduce the resistance (wiring resistance) of the connection portion (wiring portion) that electrically connects the semiconductor element in the IC chip and the external electrode in the circuit board, that is, the wiring resistance in the semiconductor device (semiconductor package).

In addition, a thermoplastic resin is used as the insulating substrate, and the joining portion between the electrode in the IC chip and the connection material in the circuit board is resin-sealed by this thermoplastic resin. Therefore, no mold resin can be required.

Further, the wiring pattern of the circuit board can be easily made thicker than the electrodes of the IC chip (for example, a thick conductor foil is prepared in advance and patterned), so that the processing time can be shortened. Furthermore, since the electrodes of the IC chip are connected to the wiring pattern through the connection material filled in the via holes, the size of the semiconductor device can be reduced.

  As an example of the circuit board, as described in claim 2, the external electrode is provided on the back surface of the IC chip mounting surface, the wiring pattern is provided in the insulating substrate, and the via hole is filled in a layer different from the via hole. A material electrically connected to the external electrode can be applied through the connected material. Thus, the semiconductor device can be a so-called CSP (Chip Size package). In addition, a configuration in which a wiring pattern is provided on one surface of the circuit board may be employed.

According to a third aspect of the present invention, the wiring pattern is preferably formed using a metal material having a specific resistance smaller than that of the electrode. Thereby, the wiring resistance in the semiconductor device can be further reduced.

According to a fourth aspect of the present invention, the electrode is preferably provided on an element formation region in the IC chip. With such a structure, the wiring length between the semiconductor element and the electrode in the IC chip can be shortened, so that the wiring resistance in the semiconductor device can be reduced. Since the insulating substrate is a thermoplastic resin, the connection between the electrode and the circuit board and the adhesion between the IC chip outside the electrode formation region and the thermoplastic resin (that is, sealing of the connection portion) are almost achieved by heating and pressing. Can be performed simultaneously. Therefore, although the electrode is formed on the element formation region, the stress applied to the element formation region at the time of heating and pressurization can be reduced, and thus the generation of cracks can be prevented.

The via hole provided in a different layer from the via hole, wherein the wiring pattern is provided in the insulating substrate , and the via hole filled with the connection material for electrically connecting the wiring pattern and the electrode is formed as described in claim 5. It is preferable that they are provided with a predetermined amount so as not to overlap.

  In this case, the stress at the time of heating and pressurization can be relieved by the thermoplastic resin at the position opposite to the via hole filled with the connecting material that electrically connects the wiring pattern and the electrode with the wiring pattern interposed therebetween. Therefore, the stress applied to the element formation region of the IC chip can be further reduced and the occurrence of cracks can be prevented.

The electrodes of the IC chip may be flat with respect to the chip surface. However, if the electrodes protrude from one surface of the IC chip as described in claim 6 , the connection portion between the electrodes and the circuit board is first. Since the contact state can be obtained, the wraparound of the softened thermoplastic resin during heating / pressurization can be reduced, and a good connection state between the electrode and the wiring pattern can be ensured.

Further, there may be only one IC chip mounted on the circuit board, or a plurality of IC chips as described in claim 7 . When a plurality of IC chips are mounted on the same circuit board, for example, the mounting area on the mother board can be made smaller than preparing a plurality of semiconductor devices each having one IC chip mounted on the circuit board. At this time, all of the plurality of IC chips may be the same IC chip, or different types of IC chips may be used as described in claim 8 .

Next, invention of Claim 9-16 is invention regarding the manufacturing method of a semiconductor device.

The method of manufacturing a semiconductor device according to claim 9 includes a semiconductor substrate preparation step of preparing a semiconductor substrate having a plurality of electrodes on one surface, an insulating substrate, and a wiring provided on at least one of the inside and the surface of the insulating substrate. A circuit board preparation step of preparing a circuit board having a pattern, a via hole having the wiring pattern as a bottom, filled with a connection material, and an external electrode provided on the surface of the insulating substrate and electrically connected to the wiring pattern; And a mounting step of mounting the semiconductor substrate on the circuit board so that the electrodes and the wiring pattern are electrically connected via the connecting material. Then, in the circuit board preparation step, an insulating substrate made of a thermoplastic resin is used, and the wiring pattern is formed thicker than the thickness of the electrode, and the via holes are arranged so that a plurality of via holes are distributed substantially evenly for each electrode. Forming a circuit board having an insulating substrate made of thermoplastic resin, and heating and pressurizing the semiconductor substrate on the circuit board in a mounting process so that the electrodes of the semiconductor substrate and the circuit board The connecting material filled in the via hole is bonded, and the bonded portion is sealed with a softened thermoplastic resin.

  Since the operational effects of the present invention are the same as the operational effects of the invention described in claim 1, the description thereof is omitted.

The operational effects of the invention according to claim 11 are the same as the operational effects of the invention according to claim 3 , and therefore description thereof is omitted.

Since the operational effects of the inventions according to claims 11 to 13 are the same as the operational effects of the inventions according to claims 4 to 6 , the description thereof is omitted.

In the invention according to any one of claims 9 to 13 , the semiconductor substrate indicates either a wafer or a chip cut from the wafer. In the case where the semiconductor substrate is a wafer, a cutting process for cutting the semiconductor substrate and the circuit board into a predetermined size may be provided after the mounting process as described in claim 14 .

At this time, as described in claim 15 , when the semiconductor substrate and the circuit board are cut into a predetermined size so as to have a plurality of element formation regions, the mounting area of the semiconductor device on the mother board can be reduced. In addition, the mounting time can be shortened compared to the case of individual mounting.

Since the operational effect of the invention described in claim 16 is the same as that of the invention described in claim 8 , the description is omitted.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
1A and 1B are diagrams illustrating a schematic configuration of a semiconductor device according to the present embodiment, in which FIG. 1A is a partially enlarged cross-sectional view, and FIG. 1B is a plan view viewed from the lower side (bump side) of FIG. is there.

  As shown in FIG. 1A, the semiconductor device 100 includes an IC chip 10 having electrodes on one surface and a circuit board 20 on which the IC chip 10 is mounted.

  In the IC chip 10, a semiconductor element (not shown) is formed on a substrate such as silicon, and an electrode 11 as an external connection terminal is electrically connected to the element formation region via a wiring portion (not shown). . And the site | part (electrode non-formation part) except this electrode 11 is coat-protected by the protective film which consists of organic resin materials (for example, polyimide and polybenzoxazole) and inorganic materials (for example, silicon nitride).

  For example, aluminum (Al) or gold (Au) can be used as the constituent material of the electrode 11. In this embodiment, the electrode 11 made of Al having a thickness of about 1 μm is formed by, for example, a CVD method using an IC chip. A plurality of IC chips 10 are formed on the periphery of the IC chip 10 so as to protrude from the surface to the circuit board 20 side. The electrode 11 may be configured to be flat with respect to the surface of the IC chip 10, or may be configured such that a protruding electrode made of Ni—Au is formed on the flat electrode by, for example, electroless plating.

  The circuit board 20 is electrically connected to the insulating substrate 21, the wiring pattern 22 provided in and / or on the surface of the insulating substrate 21, the wiring pattern 22 as a bottom, and the electrode 11 and the wiring pattern 22 of the IC chip 10. The first via hole 24 is filled with the first connection material 23 to be connected.

  The insulating substrate 21 can be made of a thermoplastic resin, for example, and a liquid crystal polymer is applied in the present embodiment. A wiring pattern 22 is provided inside an insulating substrate 21 made of a thermoplastic resin.

  For the wiring pattern 22, a low-resistance metal material such as copper (Cu), silver (Ag), Au, Al, or the like can be applied as a constituent material. In this embodiment, the wiring pattern 22 has a thickness of 10 to 30 μm, for example. The wiring pattern 22 is formed by etching the Cu foil. The wiring pattern 22 can be formed using a known technique such as a screen printing method or a plating method.

  The first connection material 23 is not limited as long as it is a material that can electrically connect the electrode 11 and the wiring pattern 22, but in the present embodiment, a conductive paste made of a low-resistance metal material is applied. ing. Further, the first via hole 24 is formed corresponding to the formation position of the electrode 11 of the IC chip 10 with the wiring pattern 22 as the bottom.

  In the semiconductor device 100 configured as described above, the electrode 11 of the IC chip 10 is directly bonded to the first connection material 23 in a state where the IC chip 10 is mounted on the circuit board 20. The joint is hermetically sealed by a thermoplastic resin, which is a constituent material of the insulating substrate 21, whose periphery is bonded to an electrode non-formation portion (protective film) on the surface having the electrode 11 of the IC chip 10. .

The wiring pattern 22 is provided thicker than the electrode 11 of the IC chip 10. Therefore, even if the electrode 11 of the IC chip 10 is thin, the wiring resistance of the semiconductor device 100 can be reduced by the wiring pattern 22 thicker than that.

The wiring pattern 22 is formed using copper (Cu) having a specific resistance smaller than that of Al, which is a constituent material of the electrode 11. Therefore, the wiring resistance of the semiconductor device 100 can be further reduced. Furthermore, in this embodiment, since the electrode 11 of the IC chip 10 is directly bonded to the first connection material 23 that is in contact with the wiring pattern 22, the wiring resistance can be further reduced.

  In addition, since the electrode 11 of the IC chip 10 is configured to be connected to the wiring pattern 22 via the first connection material 23 filled in the first via hole 24, a wire or the like is unnecessary, and the semiconductor device 100 It is possible to reduce the size of the physique. In particular, as shown in FIG. 1A, the circuit board 20 in the present embodiment has bumps 25 as external electrodes for connecting to the mother board on the back surface of the mounting surface of the IC chip 10, and the wiring pattern 22. Is electrically connected to the bump 25 by a second connecting material 27 filled in the second via hole 26. Therefore, since both surfaces of the circuit board 20 can be utilized, the circuit board 20 can be made substantially the same size as the IC chip 10 in the planar direction of the circuit board 20, and the size of the semiconductor device 100 can be reduced. (In this embodiment, a so-called CSP (Chip Size package) type) can be used. The second connection material 27 may be a different material from the first connection material 23, but the same material is applied in the present embodiment.

  As shown in FIG. 1B, the first via hole 24 and the second via hole 26 formed in different layers of the circuit board 20 are shifted by a predetermined amount in the plane direction of the circuit board 20 (FIG. 1). (A) and (b) so as not to overlap. This effect will be described in the manufacturing method described later.

  Next, an example of a method for manufacturing the semiconductor device 100 will be described with reference to FIGS. 2A and 2B are cross-sectional views showing the manufacturing method, wherein FIGS. 2A and 2B show a circuit board preparation process, FIGS. 2C and 2D show a mounting process, and FIG. 2E shows a bump forming process. In the present embodiment, although not shown, the IC chip 10 is prepared using a known semiconductor process before the circuit board 20 is formed or in parallel with the formation of the circuit board 20. At this time, the electrode 11 of the IC chip 10 is formed on the element formation region in order to reduce the size of the IC chip 10 and is formed so as to protrude from the surface of the chip 10.

  First, a circuit board preparation step is performed. The circuit board 20 in this embodiment is formed by laminating two types of resin films, and heating and pressing.

  As shown in FIG. 2A, the wiring pattern 22 is formed by etching the copper foil in the first resin film 21a made of a liquid crystal polymer having a copper foil stuck on one side. The first resin film 21a in the present embodiment is processed so that the size in the planar direction is substantially the same as that of the IC chip 10 mounted on the surface thereof. The wiring pattern 22 can also be formed by a printing method, a plating method, or the like. However, when the wiring pattern 22 is formed by etching the conductive foil (copper foil), the conductive foil having a predetermined thickness in advance. It is preferable to select (copper foil) because the thickness of the wiring pattern 22 can be adjusted.

  After the formation of the wiring pattern 22, as shown in FIG. 2A, for example, laser light is irradiated from the back surface side of the wiring pattern 22 forming surface of the first resin film 21a to penetrate the first resin film 21a. A first via hole 24 having the wiring pattern 22 as a bottom surface is formed. For example, a carbon dioxide laser or a UV-YAG laser can be used to form the first via hole 24. In addition, it is possible to mechanically form the first via hole 24 by drilling or the like. However, since it is necessary to perform processing so as not to damage the wiring pattern 22 with a small diameter, a laser processing method is used. Is preferably selected.

  When the formation of the first via hole 24 is completed, the first connection material 23 is filled in the first via hole 24. In the present embodiment, as the first connecting material 23, a conductive paste obtained by adding an organic solvent to metal particles such as Cu, Ag, Sn, and kneading the organic solvent is used. In addition, a low melting glass frit, an organic resin, or an inorganic filler may be appropriately added to and mixed with the conductive paste. This conductive paste is filled in the first via hole 24 by using a screen printing machine, a dispenser or the like (not shown).

  At this time, the first connection material 23 is filled with a predetermined gap from the upper opening surface of the first via hole 24 toward the bottom as shown in FIG. As a result, at the time of joining with the electrode 11 of the IC chip 10 to be described later, the first connecting material 23 overflows by being pushed by the electrode 11 protruding from the surface of the IC chip 10, and between the adjacent first via holes 24. Can prevent a short circuit from occurring. When the electrode 11 is not a protruding electrode, it is preferable that the upper opening surface of the first via hole 24 is filled in order to secure the connection with the electrode 11.

  In parallel with the processing of the first resin film 21a, the processing of the second resin film that constitutes the circuit board 20 together with the first resin film 21a is performed. As shown in FIG. 2B, as in the first resin film 21a, the second resin film 21b made of a liquid crystal polymer is irradiated with, for example, a laser beam and penetrates through the second resin film 21b. A second via hole 26 having the wiring pattern 22 as a bottom surface is formed in a state where the resin film 21a is laminated. The second via hole 26 has substantially the same diameter as the first via hole 24, for example, and is formed at a position (predetermined by a predetermined amount) different from the formation position of the first via hole 24 in the stacking direction. The second via hole 26 may have a diameter different from that of the first via hole 24. For example, depending on the interval between the bumps 25, the second via hole 26 can have a larger diameter than the first via hole 24.

  After the formation of the second via hole 26, the second connection material 27 is filled in the second via hole 26. In the present embodiment, the same conductive paste as that of the first connection material 23 is filled using a screen printer, a dispenser or the like (not shown). In addition, although the material different from the 1st connection material 23 may be used as the 2nd connection material 27, since a manufacturing process increases, it is preferable to use the same material.

  Thus, the manufacturing process is simplified by carrying out the processing of the first resin film 21a and the second resin film 21b in parallel at the same time. However, each formation may be performed separately.

  And each processed resin film 21a, 21b is laminated | stacked so that the wiring pattern 22 may be arrange | positioned inside, and it heats and pressurizes from the upper and lower surfaces of this laminated body. Thereby, the resin films 21a and 21b are softened and bonded to each other to form the insulating substrate 21, and the wiring pattern 22 and the connection materials 23 and 27 are joined to each other to form the circuit board 20 shown in FIG. Is formed. The above is the circuit board preparation step.

  Next, a mounting process for mounting the IC chip 10 on the formed circuit board 20 is performed. First, as shown in FIG. 2C, the electrode 11 of the IC chip 10 is positioned with respect to the first via hole 24 formed in the circuit board 20, and the IC chip 10 is mounted on the circuit board 20 in this positioning state. Put. At this time, the electrode 11 of the IC chip 10 and the surface of the circuit board 20 (including the first via hole 24 forming region) are in contact with each other. And it heats and pressurizes in this positioning mounting state. In FIG. 2 (c), both are shown separated for convenience.

  As a heating and pressurizing method, for example, using a pulse heat type thermocompression bonding tool (not shown), heating to a temperature of 250 to 400 ° C., pressurizing at a pressure of 1 to 10 MPa for several to several tens of seconds, The IC chip 10 is pressed against the circuit board 20.

Due to this heating and pressurization, the metal atoms constituting both of the electrodes 11 and the first connection material 23 of the IC chip 10 are thermally diffused at the interface between the electrodes 11 and the first connection material 23. 23 are bonded to each other electrically by diffusion bonding with sufficient bonding strength. Then, the electrode 11 of the IC chip 10 is electrically connected to the wiring pattern 22 of the circuit board 20 made of a metal material having a smaller specific resistance than the electrode 11 through the first connection material 23. Therefore, the wiring resistance of the semiconductor device 100 can be reduced without increasing the thickness of the electrode 11 of the IC chip 10 or connecting it via a plurality of wires.

  Further, since the wiring pattern 22 is formed by etching a conductor foil (copper foil) having a predetermined thickness, the processing time is longer than that when the electrode 11 is formed thick by depositing a metal material by, for example, a CVD method or the like. It can be shortened. Furthermore, since the electrode 11 of the IC chip 10 is configured to be connected to the wiring pattern 22 via the first connection material 23 filled in the first via hole 24, a wire or the like is unnecessary, and the semiconductor device 100. Can be downsized.

  In addition to the above-described diffusion bonding, the thermoplastic resin constituting the insulating substrate 20 is softened by heating, and is bonded to the electrode non-formation portion (protective film) of the IC chip 10 by pressurization from the IC chip 10. That is, the joint between the electrode 11 of the IC chip 10 and the first connection material 23 is hermetically sealed with the thermoplastic resin that is the constituent material of the insulating substrate 20. Therefore, since it is not necessary to seal the joint portion with a separate mold resin, the number of steps can be reduced and the manufacturing cost can be reduced.

  In the present embodiment, since the electrode 11 of the IC chip 10 protrudes from the surface of the chip 10, the electrode 11 and the first connection material 23 of the circuit board 20 are in contact with each other at the time of heating and pressurization. can do. That is, since it is possible to reduce the thermoplastic resin softened by heating from reaching the joint before joining, a good connection state between the electrode 11 and the first connecting material 23 (that is, the wiring pattern 22) is ensured. can do.

  Although the electrode 11 of the IC chip 10 is formed on the element formation region, the insulating substrate 21 constituting the circuit board 20 is made of a thermoplastic resin that is softened by heating. The stress transmitted to the element formation region can be reduced. That is, the occurrence of cracks in the element formation region of the IC chip 10 can be prevented.

  Furthermore, the first via hole 24 and the second via hole 26 that are in contact with the wiring pattern 22 arranged inside the circuit board 20 are shifted from each other by a predetermined amount in the plane direction of the circuit board 20 (they do not overlap in FIG. 2). Is formed). That is, in the stacking direction, a thermoplastic resin constituting the insulating substrate 21 is arranged at a position opposed to the first via hole 24 across the wiring pattern 22. Therefore, the stress transmitted to the element formation region of the IC chip 10 by pressurization can be further reduced by the thermoplastic resin softened by heating. In the present embodiment, the first via hole 24 and the second via hole 26 are formed so as not to overlap each other, but may be formed so as to be shifted by a predetermined amount.

  After the mounting process is completed, bumps 25 made of, for example, solder are formed at the positions where the second via holes 26 are formed on the back surface side of the circuit chip 20 mounting surface of the IC chip 10. Thus, the semiconductor device 100 shown in FIG. 2E can be formed.

  In this embodiment, as shown in FIG. 2A, the first via material 24 is filled with the first connection material 23 to form the first resin film 21a, and then the first resin is formed. The example which forms the circuit board 20 by heating and pressurizing the laminated body of the film 21a and the 2nd resin film 21b was shown. However, the formation of the circuit board 20 is not limited to the above example.

  For example, after the first resin film 21a and the second resin film 21b in which the first via hole 24 is not formed are stacked and heated and pressed to form the circuit board 20, the first via hole 24 is formed by laser. And the first connecting material 23 is filled. Then, the mounting step may be performed by positioning the IC chip 10 on the circuit board 20 and heating and pressing. Depending on the material composition of the first connection material 23, this procedure can provide a better diffusion bonding state between the electrode 11 of the IC chip 10 and the first connection material 23, thereby electrically and Bonded with sufficient bonding strength.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view illustrating a schematic configuration of the semiconductor device 100 according to the present embodiment. FIG. 3 corresponds to FIG.

  Since the semiconductor device 100 and the manufacturing method thereof in the second embodiment are often in common with those according to the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  The second embodiment is different from the first embodiment in that a plurality of first via holes 24 are arranged substantially evenly with respect to one electrode 11.

  When configured as shown in FIG. 3, for example, even if the area of the electrode 11 (the planar direction of the circuit board 20) is large, the first connection material can be obtained from any point of the electrode 11 as compared with the case where there is one first via hole 24. Since the wiring length to the first via hole 24 filled with 23 is shortened, the wiring resistance of the IC chip 10 can be reduced.

  The semiconductor device 100 having the configuration shown in this embodiment can be formed by using the manufacturing method shown in the first embodiment.

(Third embodiment)
Next, the 3rd Embodiment of this invention is described based on Fig.4 (a)-(c). 4A to 4C are cross-sectional views for each process for explaining a method for manufacturing the semiconductor device 100 according to the present embodiment.

  Since the semiconductor device 100 and the manufacturing method thereof in the third embodiment are often in common with those of the first embodiment, detailed description of the common parts will be omitted, and different parts will be described mainly.

  The third embodiment is different from the first embodiment in that it is mounted on the circuit board 20 in a wafer state.

  The wafer is not cut into chip units like the IC chip 10 and is formed by a normal semiconductor process. As shown in FIG. 4A, for example, on the surface corresponding to one surface of the IC chip 10, A plurality of electrodes 11 projecting in the direction of the circuit board 20 are provided. Also in the present embodiment, the electrode 11 is formed on the element formation region via a wiring portion (not shown), and the electrode non-formation portion of the wafer 10a is covered and protected by the protective film.

  Further, as shown in FIG. 4A, the circuit board 20 is filled with the first connection material 23 that electrically connects the electrode 11 and the wiring pattern 22 as in the first embodiment. The via hole 24 is formed corresponding to the position where the electrode 11 is formed.

  Next, the electrode 11 of the wafer 10 a is positioned with respect to the first via hole 24 formed in the circuit board 20, and the wafer 10 a is placed on the circuit board 20 in this positioned state. In this state, the electrode 11 of the wafer 10a and the surface of the circuit board 20 (including the first via hole 24 formation region) are in contact with each other.

  And in this positioning mounting state, it heats and pressurizes and the wafer 10a is mounted on the circuit board 20 as shown in FIG.4 (b). As a result, as in the first embodiment, the electrode 11 of the wafer 10 a and the first connection material 23 are bonded together, and the bonded portion is sealed with the thermoplastic resin constituting the insulating substrate 21. Then, the electrode 11 of the wafer 10a is electrically connected to the wiring pattern 22 of the circuit board 20 made of a metal material having a smaller specific resistance than the electrode 11 through the first connection material 23.

  If necessary for connection to the mother board after the mounting process, as shown in FIG. 4C, the second via hole 26 is made of, for example, solder on the back surface of the mounting surface of the wafer 10a on the circuit board 20. Bumps 25 are formed. A plurality of CSP type semiconductor devices 100 can be obtained at a time by cutting the wafer 10a and the circuit board 20 in units of chips (broken lines in FIG. 4C).

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made.

  In this embodiment, the example in which the insulated substrate 21 was comprised from the 1st and 2nd resin films 21a and 21b consisting of a thermoplastic resin was shown. However, the constituent material of the insulating substrate 21 is not limited to the thermoplastic resin. For example, a thermosetting resin, a composite material in which a glass cloth is impregnated with a resin, or ceramic can be applied.

  Moreover, the example which applies a liquid crystal polymer as a thermoplastic resin was shown. However, other than that, for example, polyetheretherketone (PEEK), polyetherimide (PEI), polyethersulfone (PES), polyphenylene ether (PPE), polyethylene naphthalate (PEN), etc. alone or in various mixtures Can be used.

  Moreover, in this embodiment, the example in which the wiring pattern 22 is arrange | positioned inside the circuit board 20 was shown. However, since the characteristic part of the present invention is the thickness of the wiring pattern 22 with respect to the electrode 11 of the IC chip 10 (wafer 10a), the arrangement is not limited to the above example. For example, the circuit board 20 may be composed of a single first resin film 20a and may have a wiring pattern 22 on one side thereof. Further, the number of layers constituting the circuit board 20 is not limited.

  In the present embodiment, an example in which the electrode 11 of the IC chip 10 (wafer 10a) protrudes from the surface of the IC chip 10 (wafer 10a) is shown. However, as shown in FIG. 6, the electrode 11 may be formed flat on the surface of the IC chip 10 (wafer 10a). However, in this case, in the positioning state, the IC chip 10 (wafer 10a) is in contact with the circuit board 20 at a portion other than the electrode 11 (electrode non-formation portion). There is a possibility that the plastic resin may enter the joint surface between the electrode 11 and the first connection material 23 to deteriorate the connection state. Therefore, it is preferable to protrude the electrode 11 from the surface of the IC chip 10 (wafer 10a). FIG. 6 is a schematic sectional view showing a modification.

  Further, in the present embodiment, an example is shown in which a plurality of CSP type semiconductor devices 100 are obtained at a time by cutting the wafer 10a and the circuit board 20 in units of chips (including one element formation region). However, in the cutting step, as shown in FIG. 7A, the wafer includes a plurality of element formation regions (four element formation regions indicated by bold lines in FIG. 7A) formed on the wafer 10a. 10a and the circuit board 20 may be cut into a predetermined size and mounted on the mother board 40 as the semiconductor device 100 as shown in FIG. In this case, the mounting area of the semiconductor device 100 with respect to the mother board 40 can be made smaller than mounting the semiconductor device 100 in which the plurality of IC chips 10 are mounted on the circuit board 20 on the mother board 40. In addition, the mounting time can be shortened compared to the case of individual mounting. FIG. 7 is a view showing a modification, wherein (a) is a plan view seen from the wafer 10a side, and (b) is a schematic cross-sectional view.

  In the present embodiment, an example in which only one IC chip 10 is mounted on the circuit board 20 is shown. However, the number of IC chips 10 mounted on the circuit board 20 is not limited. When a plurality of IC chips 10 are mounted on the same circuit board 20, the mounting area on the mother board 40 can be made smaller than preparing a plurality of semiconductor devices 100 each having one IC chip 10 mounted on the circuit board 20. At that time, the plurality of IC chips 10 may be of the same type, or may be configured of different types (IC chips 10 and 12 in FIG. 8A) as shown in FIG. . When the sizes (particularly heights) of the plurality of IC chips 10 and 12 are different, the height of the thermocompression bonding tool 50 is adjusted according to the IC chips 10 and 12 as shown in FIG. Thus, each of the IC chips 10 and 12 can be pressurized with a preferable pressure, and the plurality of IC chips 10 and 12 can be mounted on the circuit board 20 at a time. FIG. 8 is a view showing a modification, in which (a) is a schematic cross-sectional view, and (b) is a diagram for explaining a manufacturing method. Further, between the flat thermocompression bonding tool 50 and the plurality of IC chips 10 and 12 having different sizes (heights), thermocompression bonding is performed while deforming according to the size (height) of the IC chips 10 and 12. A buffer member (not shown) for transmitting a pressing force from the tool 50 to the IC chips 10 and 12 may be provided. As the buffer member, for example, a metal such as stainless steel is cut into a fiber shape, and the fiber metal is formed into a plate shape as a nonwoven fabric, or a woven fabric is formed into a knit or cloth (so-called NASRON (registered trademark)). Can be used.

It is a figure which shows schematic structure of the semiconductor device in 1st Embodiment, (a) is a partial expanded sectional view, (b) is the top view seen from the lower side (bump side) of (a). It is sectional drawing according to process which shows a manufacturing method, (a), (b) has shown the circuit board preparation process, (c), (d) has shown the mounting process, (e) has shown the bump formation process. It is sectional drawing which shows schematic structure of the semiconductor device in 2nd Embodiment. It is sectional drawing according to process which shows the manufacturing method of the semiconductor device in 3rd Embodiment, (a), (b) has shown the mounting process, (c) has shown the bump formation and cutting process. It is a schematic sectional drawing which shows a modification. It is a figure which shows a modification, (a) is a top view seen from the wafer side, (b) is a rough section FIG. It is a figure which shows a modification, (a) is schematic sectional drawing, (b) demonstrates a manufacturing method. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... IC chip 10a ... Wafer 11 ... Electrode 20 ... Circuit board 21 ... Insulating substrate 22 ... Wiring pattern 23 ... 1st connection material 24 ... 1st Via hole 100... Semiconductor device

Claims (16)

An IC chip having a plurality of electrodes on one surface;
An insulating substrate; a wiring pattern provided on at least one of the inside and the surface of the insulating substrate; a via hole having the wiring pattern as a bottom and filled with a connection material; and the wiring pattern provided on the surface of the insulating substrate. And a circuit board having external electrodes electrically connected,
The IC chip is mounted on the circuit board, and the electrode and the wiring pattern are electrically connected via the connection material,
The wiring pattern is thicker than the electrode,
For each electrode of the IC chip, a plurality of the via holes are provided substantially uniformly distributed,
The insulating substrate is made of a thermoplastic resin,
The electrode is bonded to a connection material filled in the via hole, and the bonding portion is sealed with the thermoplastic resin. The external electrode is provided on the back surface of the IC chip mounting surface of the circuit board,
The wiring pattern is provided in the insulating substrate, and is electrically connected to the external electrode through a connection material filled in a via hole of a layer different from the via hole. A semiconductor device according to 1.   The semiconductor device according to claim 1, wherein the wiring pattern is formed using a metal material having a specific resistance smaller than that of the electrode. The semiconductor device according to claim 1, wherein the electrode is provided on a formation region of a semiconductor element in the IC chip . The wiring pattern is provided in the insulating substrate,
The via hole filled with a connection material for electrically connecting the wiring pattern and the electrode is provided by being shifted by a predetermined amount so as not to overlap with a via hole provided in a layer different from the via hole. The semiconductor device according to claim 4 . The semiconductor device according to claim 1, wherein the electrode protrudes from one surface of the IC chip . The semiconductor device according to claim 1, wherein a plurality of the IC chips are mounted on the circuit board . The semiconductor device according to claim 7 , wherein the plurality of IC chips are of different types . A semiconductor substrate preparation step of preparing a semiconductor substrate having a plurality of electrodes on one surface;
An insulating substrate; a wiring pattern provided on at least one of the inside and the surface of the insulating substrate; a via hole having the wiring pattern as a bottom and filled with a connection material; and the wiring pattern provided on the surface of the insulating substrate. A circuit board preparation step of preparing a circuit board having an external electrode electrically connected to;
A mounting method of mounting the semiconductor substrate on the circuit board so that the electrode and the wiring pattern are electrically connected via the connection material,
In the circuit board preparation step, the insulating substrate made of a thermoplastic resin is used, the wiring pattern is formed thicker than the thickness of the electrode, and a plurality of the via holes are substantially uniformly distributed for each electrode. Forming the via hole as
In the mounting step, the semiconductor substrate is heated and pressed in a state where the semiconductor substrate is positioned on the circuit board, thereby joining the electrode of the semiconductor substrate and the connection material filled in the via hole in the circuit board. A method for manufacturing a semiconductor device, wherein a bonding portion is sealed with the softened thermoplastic resin. The method for manufacturing a semiconductor device according to claim 9 , wherein, in the circuit board preparation step, the wiring pattern is formed using a metal material having a specific resistance smaller than that of the electrode . 11. The method of manufacturing a semiconductor device according to claim 9, wherein, in the semiconductor substrate preparation step, the electrode is formed on a formation region of a semiconductor element . In the circuit board preparation step, the wiring pattern is formed in the insulating substrate, and the via hole filled with a connection material for electrically connecting the wiring pattern and the electrode is provided in a layer different from the via hole. 12. The method of manufacturing a semiconductor device according to claim 11 , wherein the semiconductor device is formed so as to be shifted by a predetermined amount so as not to overlap with a via hole to be formed . 13. The method of manufacturing a semiconductor device according to claim 9, wherein, in the semiconductor substrate preparation step, the electrode is formed so as to protrude from a surface of the semiconductor substrate . The semiconductor device according to claim 9, further comprising a cutting step of cutting the semiconductor substrate and the circuit board into a predetermined size after the mounting step . Production method. 15. The method of manufacturing a semiconductor device according to claim 14 , wherein, in the cutting step, the semiconductor substrate and the circuit substrate are cut into a predetermined size so as to include a plurality of semiconductor elements . In the semiconductor substrate preparation step, preparing a plurality of different types of IC chips,
The method for manufacturing a semiconductor device according to claim 9, wherein, in the mounting step, a plurality of the IC chips are mounted on the same circuit board .