JP4258391B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4258391B2 JP4258391B2 JP2004022984A JP2004022984A JP4258391B2 JP 4258391 B2 JP4258391 B2 JP 4258391B2 JP 2004022984 A JP2004022984 A JP 2004022984A JP 2004022984 A JP2004022984 A JP 2004022984A JP 4258391 B2 JP4258391 B2 JP 4258391B2
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- metal
- heat sink
- mold resin
- metal body
- semiconductor device
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 138
- 239000002184 metal Substances 0.000 claims description 158
- 229910052751 metal Inorganic materials 0.000 claims description 158
- 229920005989 resin Polymers 0.000 claims description 79
- 239000011347 resin Substances 0.000 claims description 79
- 230000005855 radiation Effects 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims 2
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000012986 modification Methods 0.000 description 9
- 230000004048 modification Effects 0.000 description 9
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 239000000725 suspension Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000011888 foil Substances 0.000 description 6
- 239000003822 epoxy resin Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 229920002050 silicone resin Polymers 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
図1は本発明の第1実施形態に係る半導体装置S1の一般的な概略構成を示す図であり、(a)はモールド樹脂80内の各部の平面的な配置を示す図、(b)は概略断面構成を示す図である。
図5は、本発明の第2実施形態に係る半導体装置の要部構成を示す図であり、(a)は斜視図、(b)は概略断面図である。
図8は、本発明の第3実施形態に係る半導体装置の要部構成を示す概略断面図である。
なお、金属部20aは、第1の金属体20または第2の金属体30の吊りピン20bを切断した部位でなくてもよく、信号端子21、31、60および第1および第2の金属体20、30の放熱面以外のものであればよい。
20…第1の金属体としての下側ヒートシンク、20a…金属部、
21…信号端子としての下側ヒートシンクの端子部、
30…第2の金属体としての上側ヒートシンク、
31…信号端子としての上側ヒートシンクの端子部、60…信号端子、
80…モールド樹脂、81…樹脂部材としてのコーティング部材、
82…樹脂部材としてのキャップ部材、83…樹脂部材としてのシール部材、
84…突起部、85…凹部。
Claims (2)
- 半導体素子(10)と、
前記半導体素子(10)の一面側に設けられ、電極と放熱体とを兼ねる第1の金属体(20)と、
前記半導体素子(10)の他面側に設けられ、電極と放熱体とを兼ねる第2の金属体(30)と、
前記半導体素子(10)、前記第1の金属体(20)および前記第2の金属体(30)を包み込むように封止するモールド樹脂(80)とを備え、
前記モールド樹脂(80)からは、信号端子(21、31、60)および前記第1および第2の金属体(20、30)の放熱面以外に金属部(20a)が露出している半導体装置において、
前記モールド樹脂(80)の表面のうち前記金属部(20a)の周囲には、前記金属部(20a)よりも前記モールド樹脂(80)の表面からの突出高さが大きい突起部(84)が設けられており、
前記突起部(84)は、前記金属部(20a)の全周に設けられていることを特徴とする半導体装置。 - 半導体素子(10)と、
前記半導体素子(10)の一面側に設けられ、電極と放熱体とを兼ねる第1の金属体(20)と、
前記半導体素子(10)の他面側に設けられ、電極と放熱体とを兼ねる第2の金属体(30)と、
前記半導体素子(10)、前記第1の金属体(20)および前記第2の金属体(30)を包み込むように封止するモールド樹脂(80)とを備え、
前記モールド樹脂(80)からは、信号端子(21、31、60)および前記第1および第2の金属体(20、30)の放熱面以外に金属部(20a)が露出している半導体装置において、
前記モールド樹脂(80)の表面のうち前記金属部(20a)の周囲には、前記金属部(20a)よりも前記モールド樹脂(80)の表面からの突出高さが大きい突起部(84)が設けられており、
前記突起部(84)は、前記金属部(20a)の周囲の1方向に設けられていることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004022984A JP4258391B2 (ja) | 2004-01-30 | 2004-01-30 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004022984A JP4258391B2 (ja) | 2004-01-30 | 2004-01-30 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005217248A JP2005217248A (ja) | 2005-08-11 |
JP4258391B2 true JP4258391B2 (ja) | 2009-04-30 |
Family
ID=34906155
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004022984A Expired - Fee Related JP4258391B2 (ja) | 2004-01-30 | 2004-01-30 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4258391B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4450230B2 (ja) | 2005-12-26 | 2010-04-14 | 株式会社デンソー | 半導体装置 |
JP2008218455A (ja) * | 2007-02-28 | 2008-09-18 | Denso Corp | リードフレームおよびリードフレーム収納治具 |
WO2010004609A1 (ja) * | 2008-07-07 | 2010-01-14 | 三菱電機株式会社 | 電力用半導体装置 |
-
2004
- 2004-01-30 JP JP2004022984A patent/JP4258391B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JP2005217248A (ja) | 2005-08-11 |
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