JP4249852B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to display data signal input system switching in a liquid crystal display device.
[0002]
[Prior art]
FIG. 5 is a circuit configuration diagram of an active matrix liquid crystal display device using a conventional TFT (thin film transistor) as a switching element. 1 is a liquid crystal display device, 10 is a digital control circuit, 11 is an input selection circuit inside 10, 12 is a drive IC control signal generation circuit inside 10, 13 is an analog signal generation circuit, and 21 is a liquid crystal cell , 22 are source driving ICs, and 23 is a gate driving IC.
[0003]
A plurality of parallel source lines 31 and gate lines 32 are provided in the liquid crystal cell, and are driven by a source drive IC 22 and a gate drive IC 23, respectively. A display pixel 30 is provided at each intersection of the source wiring 31 and the gate wiring 32, and a TFT is provided as a switching element 33 in each pixel. In this way, in a plurality of display pixels of the liquid crystal cell, the liquid crystal is driven by each TFT to suppress the transmittance of the liquid crystal layer, and further, the transmitted light of the backlight light under the liquid crystal cell as a light source is controlled to display an image. To do. Each TFT is connected to a source and gate wiring, and a terminal (drain) opposite to the source wiring is connected to a liquid crystal capacitor 34 and a storage capacitor 35. The liquid crystal capacitor 34 and the holding capacitor 35 are connected to a common wiring 36 in the liquid crystal cell.
[0004]
RO, GO, BO are input display data signals to the odd-numbered liquid crystal display device 1, RE, GE, BE are input display data signals to the even-numbered liquid crystal display device 1, and CLK is an input clock to the liquid crystal display device 1. The signal, DENA is an input display enable signal for transmitting a display data period to the liquid crystal display device 1, HD is an input horizontal synchronization signal to the liquid crystal display device 1, VD is an input vertical synchronization signal to the liquid crystal display device 1, and VDD is a liquid crystal display. This is the input power supply voltage to the device 1. Here, RO and RE are input red display data signals, GO and GE are input green display data signals, and BO and BE are input blue display data signals, and the number of bits varies depending on the number of display colors. In this case, since 8 bits are assumed, each display data signal is 8 lines. The numeral 8 and the diagonal line attached to the wiring indicate that it is 8 bits.
[0005]
RO1, GO1, BO1, RE1, GE1, and BE1 are display data signals selected by the input selection circuit 11, and CLK1 is a clock signal selected by the input selection circuit 11.
[0006]
RO2, GO2, BO2, RE2, GE2, and BE2 are display data signals input to the source drive IC 22, SD is a control signal input to the source drive IC 22, GD is a control signal input to the gate drive IC 23, and AD is analog A control signal input to the signal generation circuit 13, AS is an analog signal input to the source drive IC 22, AG is an analog signal input to the gate drive IC 23, and AC is an analog signal input to the common wiring 36.
[0007]
As for the input method of the input display data signal, as described above, each R, G, B 8-bit data string is divided into an odd number column and an even number column, and two data are input in parallel in one clock cycle. There is a method in which only one data is input in one clock cycle without doing so. 4A and 4B show the timings of both types of display data signals. The former is called a two-pixel method per clock, and the latter is called a one-pixel method per clock. Since the clock frequency can be halved in the 2-pixel method per clock, when the signal frequency becomes high in a high-definition liquid crystal display device, electromagnetic radiation is suppressed by lowering the clock frequency, circuit sampling error due to signal distortion, etc. This is effective in reducing display noise caused by the above. For example, in a liquid crystal display device of the XGA specification having a display pixel number of 1024 × 768, the clock frequency in the one-pixel method per clock is generally 65 MHz, but if the two-pixel method per clock is adopted, the clock frequency is 32.times. It can be reduced to 5 MHz. On the other hand, since the number of input signals per clock can be reduced to half that of the two-pixel method per clock in the one-pixel method per clock, the cost can be reduced by reducing the number of connectors and cables. As described above, both methods have advantages and disadvantages, and therefore, both the two-pixel method per clock and the one-pixel method per clock are generally used for the form of signals input from the signal source device to the liquid crystal display device. ing.
[0008]
Therefore, in order to make the liquid crystal display device versatile, it is necessary to be able to input both types of display data signals. For example, in the case of the two-pixel method per clock, odd column input display data signals are input to RO, GO, and BO, and even column input display data signals are input to RE, GE, and BE, respectively. On the other hand, in the case of the one-pixel method per clock, serial input display data signals that are not separated into odd columns and even columns are input to RO, GO, and BO, and no signals are input to RE, GE, and BE.
[0009]
Here, with respect to each R, G, B8 bit data string input from the digital control circuit 10 to the source drive IC 22 in the liquid crystal display device, it is generally 1 in the case of the XGA specification because of the limitation of the operating frequency of the drive IC. A two-pixel system for each clock is applied. Therefore, it is necessary to select a processing method in the circuit according to the display data input method, and to always output the same RO1, GO1, BO1, RE1, GE1, BE1 signal from the input selection circuit 11 regardless of the input method. .
[0010]
FIG. 6 is a circuit configuration diagram illustrating the inside of the input selection circuit 11. Reference numeral 101 denotes a data buffer circuit, and reference numeral 102 denotes a clock control circuit that divides and adjusts the phase of CLK to generate a clock of each circuit. ROS, GOS, and BOS are signals in which the phase, voltage, and voltage of RO, GO, and BO are adjusted by the data buffer circuit 101, and in the case of the two-pixel method per clock, the data signals are odd-numbered columns as they are. On the other hand, in the case of the one-pixel system per clock, the serial data signal is not separated into odd and even columns.
[0011]
RES, GES, and BES are signals in which the phase, voltage, and voltage of RE, GE, and BE are adjusted by the data buffer circuit 101. In the case of the two-pixel method for each clock, the data signals are even columns. On the other hand, nothing is input in the case of the one-pixel method per clock.
[0012]
103 is a serial / parallel conversion circuit that divides a serial data signal that is not separated into odd and even columns, and generates an odd column signal. 104 is a frequency that divides serial data signals that are not separated into odd and even columns. Serial / parallel conversion circuit for generating even column signals, ROPO, GOPO, BOPO are odd column data signals generated in 103, ROPE, GOPE, BOPE are even column data signals generated in 104, and CLKPO is A clock signal generated at 102 and used for frequency division at 103, and CLKPE is a clock signal generated at 102 and used for frequency division at 104.
[0013]
Reference numeral 105 denotes ROPO, GOPO, BOPO for the one-pixel method, ROS, GOS for the two-pixel method depending on whether the data input method is the two-pixel method per clock or the one-pixel method per clock. , BOS is selected, and in any case, the odd column switching circuit 106 outputs as RO1, GO1, BO1 depending on whether the input method is the two-pixel method per clock or the one-pixel method per clock. ROPE, GOPE, and BOPE are selected for the 1-pixel method, and RES, GES, and BES are selected for the 2-pixel method. The clock signal for switching at 105 and 106.
[0014]
CLK1P is a clock signal corresponding to one pixel system per clock whose phase and voltage are only adjusted, and CLK2P is a clock signal corresponding to two pixel systems per clock whose CLK and phase are divided by two. Is a clock switching circuit that selects CLK1P or CLK2P in accordance with the display data input method according to the two-pixel method per clock or the one-pixel method per clock, and outputs it as CLK1.
[0015]
Here, the switching state of 105, 106, and 107 is controlled by the ST signal input to the input selection circuit 11. In the conventional liquid crystal display device, the ST signal is switched by switching the ST signal selector switch 40. When the input display data is a two-pixel system per clock, the ST terminal is connected to VDD, and the input display data is displayed. However, in the case of one pixel system per clock, the ST terminal is connected to the ground side.
[0016]
[Problems to be solved by the invention]
In the conventional liquid crystal display device, it is necessary to change the voltage setting of the ST signal according to the one-pixel method per clock or the two-pixel method per clock, but it is impossible to change the setting from the outside of the device. . Therefore, two types of liquid crystal display devices must be produced separately and managed in inventory. Therefore, there is a problem that the product cost increases. Further, the display method cannot be switched during the operation of the liquid crystal display device.
[0017]
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a liquid crystal display device in which the display method can be switched by a setting signal from the outside of the device in correspondence with the data input method. And Another object of the present invention is to provide a liquid crystal display device that automatically determines an input signal and switches a display method without requiring an external setting signal.
[0018]
[Means for solving problems]
Liquid crystal display device of the present invention, in synchronization with the clock input signal, a liquid crystal display device to read the display data input signal, the display input scheme 2 pixels per clock of the data input signal to the liquid crystal display device in so can cope cases the method or one clock per pixel mode, selects a signal processing method in a digital control circuit in response to the input mode of the display data input signal, regardless of the input method An input selection circuit that generates the same internal display data signal; and an input method determination circuit that determines whether the input method is a two-pixel method per clock or a one-pixel method per clock; mosquito the number of clocks in the input display enable signal period in one horizontal synchronizing signal period that corresponds to the number of display pixels n arranged in the horizontal direction of the liquid crystal display device in the clock input signal And a counter circuit and the determination output circuit for cement, the determination output circuit, wherein when the count number of the counter circuit is n / 2, it is determined that the input method is 2 pixels schemes each clock, the counting number If n is judged to the input method is one pixel scheme every clock and outputs the determination result as a setting signal of the input selection circuit, the input selection circuit, said in the liquid crystal display device In the digital control circuit , the setting signal is input, and a signal processing method in the digital control circuit in the liquid crystal display device is selected .
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
FIG. 1 is a circuit configuration diagram of an active matrix type liquid crystal display device for explaining a first embodiment of the present invention. Here, the internal configuration of the input selection circuit 11 is the same as in FIG. In the present embodiment, the ST signal terminal is connected to an input terminal that inputs to the liquid crystal display device, and the ST signal is input from the outside. Therefore, it is not necessary to change the setting in the liquid crystal display device depending on whether the display data input method is the one-pixel method per clock or the two-pixel method per clock. In this case, in the signal source device connected to the liquid crystal display device, for example, when the display data input method is the two-pixel method per clock, the ST signal input terminal is connected to VDD, and the input display data is one per clock. In the case of the pixel method, it may be connected to the ground side. Alternatively, in the cable connecting the signal source device connected to the liquid crystal display device and the liquid crystal display device, for example, when the input display data is a two-pixel system per clock, the input display data is one clock. In the case of the one-pixel method, ST may be connected to the ground side.
[0021]
When the display method needs to be switched during the operation of the liquid crystal display device, the data method of the input signal and the ST terminal input signal may be changed simultaneously in the signal source device.
[0022]
As a result, it is not necessary to change the setting in the liquid crystal display device according to the one-pixel method per clock or the two-pixel method per clock, so that one type of liquid crystal display device can cope with the signal input of the two methods. . Accordingly, the production and inventory management of the liquid crystal display device are facilitated, and as a result, the product cost can be reduced. Further, the display method can be switched during the operation of the liquid crystal display device, and a flexible response according to the situation becomes possible.
[0023]
Embodiment 2
FIG. 2 is a circuit configuration diagram of an active matrix liquid crystal display device for explaining a second embodiment of the present invention. Reference numeral 51 denotes a data input type determination circuit that determines whether the data input method of the input signal is a one-pixel method or a two-pixel method per clock. VDD, DENA, CLK, and HD are input to the determination circuit 51, and a setting signal STO corresponding to one pixel method per clock or two pixel methods per clock is output.
[0024]
FIG. 3 is a circuit configuration diagram inside the determination circuit 51. 201 is a counter circuit, and 202 is a determination output circuit. DENA, CLK, HD, and VDD are input to the counter circuit 201, and HD and VDD are input to the determination output circuit 202.
[0025]
FIG. 4 is a signal timing diagram of DENA, display data, CLK, and HD in the one-pixel method per clock or the two-pixel method per clock in the XGA specification where the number of display pixels is 1024 (horizontal direction) × 768 (vertical direction). is there. Here, t _CLK is a clock cycle, and t _H is one horizontal synchronization period. The signals in the figure are all digital signals. For example, the upper side is a power supply (VDD) voltage and is called a high state, and the lower side is a ground voltage and called a low state. Therefore, t _WDH is a period during which DENA is in a high state.
[0026]
First, the 2-pixel method for each clock will be described. Here, as the display data, the odd-numbered column display data RO and the even-numbered column display data RE displayed in red are shown, but the same applies to the other green and blue display data. The numbers (1, 2, 3, 4, 5,... 1021, 1022, 1023, 1024) shown in the display data indicate what number of data input to the display pixels arranged in the horizontal direction of the liquid crystal display device. This is a number indicating whether the data is input to the display pixel, and each corresponds to a generation period of data input to each display pixel. Therefore, 1 corresponds to the first data, and 1024 corresponds to the last data. Thus, the DENA signal is a signal that conveys the display data period in the t _H period. That is, DENA transitions from a low state to a high state in synchronization with the start of RO for the first data and RE for the second data. RO ends the 1023rd data and RE ends the 1024th data and DENA. Transitions from a high state to a low state. Further, the generation period of each display data signal and t _CLK are synchronized. Therefore, the following relationship is established in the 2-pixel method for each clock.
t _WDH / t _CLK = 512
[0027]
Next, a one-pixel method for each clock will be described. Here, as the display data, red R is shown, but the same applies to other green and blue display data. The numbers (1, 2, 3, 4, 5,..., 1023, 1024) shown in the display data are input to the display pixel of the data input to the display pixels arranged in the horizontal direction of the liquid crystal display device. Each of which corresponds to a generation period of data input to each display pixel. Therefore, 1 corresponds to the first data, and 1024 corresponds to the last data. Thus, the DENA signal is a signal that conveys the display data period in the t _H period. That is, in synchronization with the start of the first data R, DENA transitions from the low state to the high state, and when R finishes the 1024th data, DENA transitions from the high state to the low state. Further, the generation period of each display data signal and t _CLK are synchronized. Therefore, the following relationship is established in the one-pixel method per clock.
t _WDH / t _CLK = 1024
[0028]
As described above, by detecting the timing relationship between t _WDH and t _CLK , it is possible to automatically determine the one-pixel method per clock or the two-pixel method per clock.
[0029]
The determination method will be described with reference to FIG. The counter circuit 201 counts the number of clocks during the t _WDH period in the DENA signal in synchronization with HD using the CLK signal. The count result is transmitted to the determination output circuit 202 as a count. In 202, it is determined whether the number is 512 or 1024, and STO is output based on the determination result. For example, VDD may be output in the case of 512, and ground voltage may be output in the case of 1024.
[0030]
By performing the determination as described above for each HD cycle, it is possible to automatically cope with the change of the input signal from the one-pixel method per clock to the two-pixel method per clock during the operation of the liquid crystal display device. Normal display is possible.
[0031]
As a result, it is not necessary to change the setting in the liquid crystal display device according to the one-pixel method per clock or the two-pixel method per clock, so that one type of liquid crystal display device can cope with the signal input of the two methods. . Accordingly, the production and inventory management of the liquid crystal display device are facilitated, and as a result, the product cost can be reduced. Further, the display method can be switched during the operation of the liquid crystal display device, and a flexible response according to the situation becomes possible.
[0032]
Embodiment 3
In the above embodiment, it is assumed that the determination result goes as calculated. However, in actuality, the value may not be as calculated due to the influence of noise or the like. Even in such a case, the same effect can be realized by widening the range of the criterion.
[0033]
For example, the following determination is used in the two-pixel method per clock.
0 <t _WDH / t _CLK <767
[0034]
For example, the following determination is used in the one-pixel method per clock.
768 <t _WDH / t _CLK
[0035]
Embodiment 4
In the above embodiment, the case of the XGA specification in which the number of display pixels is 1024 (horizontal direction) × 768 (vertical direction) has been described, but the present invention is other 1280 (horizontal direction) × 1024 (vertical direction). ) And other display specifications. In that case, generally, the determination formula in which the number of display pixels in the horizontal direction is n is as follows.
[0036]
In case of 2 pixel system per clock.
t _WDH / t _CLK = n / 2
[0037]
In the case of one pixel system per clock.
t _WDH / t _CLK = n
[0038]
Embodiment 5
In the above embodiments, active matrix liquid crystal display devices using TFTs as switching elements have been described. However, the present invention is applied to other liquid crystal display devices such as passive matrix liquid crystal display devices having no switching elements. Even so, it is equally effective.
[0039]
【The invention's effect】
In the present invention, the setting signal of the input selection circuit in the liquid crystal display device which is set corresponding to whether the display data signal input method is the one-pixel method per clock or the two-pixel method per clock is the display data input signal. since the so determined set from, it is not necessary to change the settings in the internal liquid crystal display device according to one pixel scheme or one clock every two pixels schemes each clock, the two systems in one type liquid crystal display device It can correspond to the signal input. Accordingly, the production and inventory management of the liquid crystal display device are facilitated, and as a result, the product cost can be reduced. The input signal to the liquid crystal display device during operation also becomes possible normal display when changes in one clock every two pixels manner from one pixel scheme per clock.
[Brief description of the drawings]
FIG. 1 is a circuit configuration diagram of an active matrix liquid crystal display device for explaining a first embodiment of the present invention;
FIG. 2 is a circuit configuration diagram of an active matrix liquid crystal display device for explaining a second embodiment of the present invention;
3 is a circuit configuration diagram illustrating the inside of a determination circuit 51 in FIG. 2;
FIG. 4 is a signal timing diagram of DENA, display data, CLK, and HD in a 1-pixel per clock system and a 2-pixel per clock system in the XGA specification where the number of display pixels is 1024 (horizontal direction) × 768 (vertical direction). It is.
FIG. 5 is a circuit configuration diagram of a conventional active matrix liquid crystal display device.
6 is a circuit configuration diagram illustrating the inside of the input selection circuit 11 of FIGS. 5 and 1; FIG.
[Name of code]
DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Digital control circuit 11 Input selection circuit 12 Drive IC control circuit 13 Analog signal generation circuit 21 Liquid crystal cell 22 Source drive IC
23 Gate drive IC
30 display pixel 31 source line 32 gate line 33 switching element 34 liquid crystal capacitor 35 holding capacitor 36 common line 40 ST signal changeover switch 51 determination circuit 101 data buffer circuit 102 clock control circuit 103, 104 serial / parallel conversion circuit 105 odd column change circuit 106 Even-numbered column switching circuit 107 Clock switching circuit 201 Counter circuit 202 Determination output circuit

Claims (1)

A liquid crystal display device that reads a display data input signal in synchronization with a clock input signal,
To accommodate in each case of the liquid crystal display wherein the display data input signal input method is one clock every two pixels scheme or one clock per pixel mode of the apparatus, depending on the input method of the display data input signal an input selection circuit for selecting a signal processing method in a digital control circuit, for generating the same internal display data signal regardless of the input method Te,
An input method determination circuit for determining whether the input method is a two-pixel method per clock or a one-pixel method per clock;
The decision circuit, the liquid crystal display wherein the number of clocks in the input display enable signal period in one horizontal synchronizing signal period that corresponds to the display pixel number n arranged in the horizontal direction the clock input signal judgment a counter circuit for counting the output of the device With circuit,
The determination output circuit determines that the input method is a two-pixel method per clock when the count number of the counter circuit is n / 2, and the input method is every clock when the count number is n. It is determined that it is a single pixel system, and these determination results are output as setting signals for the input selection circuit,
Wherein the input selection circuit, a feature that there within said digital control circuit in the liquid crystal display device, inputs the setting signal, for selecting the digital control circuit internal signal processing method in the liquid crystal display device Liquid crystal display device.

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