JP4248987B2 - Method for manufacturing array substrate - Google Patents

Description

  The present invention relates to a method for manufacturing an array substrate used in a liquid crystal display.

  In recent years, liquid crystal displays have been used in various devices. In the liquid crystal display, the array substrate and the color filter substrate are opposed to each other with a predetermined interval. Liquid crystal is sealed between the two substrates. In the array substrate, a plurality of gate lines and a plurality of signal lines are arranged on a matrix, and TFTs (thin film transistors) are provided at intersections of these lines. By sequentially turning on the TFTs, a signal voltage is applied to the pixel electrodes connected to the TFTs, and the liquid crystal is driven.

A known method for manufacturing an array substrate will be described. (1) A glass substrate is prepared. (2) A gate line is formed on a glass substrate. The gate line is formed by forming a metal film and patterning it. (3) An insulating film is stacked. For the insulating film, SiOx or SiNx is used. (4) A semiconductor layer is selectively formed on the insulating film. The semiconductor layer includes two layers of an i-type a-Si layer that is an intrinsic semiconductor layer that is not doped with impurities and an n ⁺ -type a-Si layer that is a semiconductor layer in which electrons remain due to high concentration doping. Configure as follows. The i-type a-Si layer becomes a TFT channel, and the n ⁺ -type a-Si layer becomes a drain / source. (5) Form signal lines and drain / source electrodes. Formation is performed by laminating metal films, forming a resist pattern with a resist, and then etching. (6) The heavily doped n ⁺ -type a-Si layer is separated by dry etching such as a plasma etcher or a reactive ion etcher (hereinafter referred to as channel cut). (7) Strip the resist. (8) Before forming the passivation film, cleaning is performed to remove deposits generated by etching or the like. (9) A passivation film is formed and patterned. (10) A pixel electrode is formed and patterned.

Although not described in the above manufacturing method, an etching stopper is provided between the i-type a-Si layer and the n ⁺ -type a-Si layer or the i-type a-Si layer is thickened to cut the channel. . The etching stopper functions to prevent over-etching to the i-type a-Si layer.

When the i-type a-Si layer is thickened, the i-type a-Si layer having a desired thickness can be secured even if the i-type a-Si layer is etched by overetching. However, since the i-type a-Si layer is exposed to plasma etching, a defect level is generated in the i-type a-Si layer. Etching products and the like accumulate in the channel portion. As a result, V _th (operating voltage of the transistor) shifts to minus, and the off-current I _{off of the} TFT deteriorates. I _off is a current flowing between the source and the drain when the TFT is set to _Vth or less (usually between −5 V to −15 V).

Therefore, in the dry etcher or at the time of passivation film formation in a subsequent process, a process of repairing the defect level by plasma treatment with hydrogen, argon, oxygen or the like and stabilizing I _off and V _th has been performed. Since additional processing is performed in an apparatus such as a CVD or an etcher, the throughput in manufacturing the array substrate is lowered. For example, in the case of plasma processing, about 60 seconds are required for processing, and the productivity by CVD is reduced by 25% compared to the case without plasma processing.

  Alternatively, annealing is performed in a nitrogen atmosphere around 200 degrees instead of plasma treatment. However, the defect level repair method by annealing requires a new apparatus. In order to perform annealing, the throughput is lowered in the same manner as described above.

  Patent Document 1 describes a manufacturing method of a TFT using a poly-Si semiconductor. The oxygen plasma treatment has an advantage that a stronger Si—O bond can be formed than an Si—H bond. Therefore, the method of the cited document 1 terminates the trap level generated in poly-Si by laser crystallization by oxygen plasma treatment. The trap level is not activated again, and the reliability of the TFT is improved. However, although the method of the cited document 1 is effective for poly-Si, it is unclear whether it is effective for a-Si. A chamber or the like for performing oxygen plasma treatment is required, and the cost of the entire manufacturing apparatus increases. Since the oxygen plasma treatment is performed, the throughput of manufacturing the TFT is lowered.

JP 2003-124231 A

  An object of the present invention is to provide a method of manufacturing an array substrate that performs termination processing of TFTs that have high production efficiency and can obtain electrical characteristics equivalent to those of the prior art.

  The array substrate manufacturing method of the present invention includes the steps of preparing an insulating substrate, forming a gate line on the insulating substrate, laminating an insulating film covering the gate line on the insulating substrate, and intrinsically Forming a stacked body of a semiconductor layer and a semiconductor layer doped with impurities on the insulating film; stacking a metal film on the insulating film and the semiconductor layer doped with impurities; and on the metal film Forming a resist pattern with a resist; etching the metal film to form a signal line that crosses the source / drain electrodes and the gate line; and exposing the intrinsic semiconductor layer to expose the impurity. Etching the doped semiconductor layer; removing the resist; and etching the impurity-doped semiconductor layer. The defect level of the intrinsic semiconductor layer produced in the step of includes a step of repairing by a solution oxidizing agent is added, forming a passivation layer on the intrinsic semiconductor layer exposed, the.

  The step of repairing the defect level includes a step of spraying the exposed intrinsic semiconductor layer with a solution added with an oxidizing agent.

  The oxidizing agent is ozone. Ozone is active oxygen and easily combines with Si in the intrinsic semiconductor layer to repair the defect level.

  The step of repairing the defect level includes removal of deposits generated by the etching step and the peeling step, or cleaning before the formation of the passivation film.

  According to the manufacturing method of the present invention, the defect level of the intrinsic semiconductor layer is repaired using a solution containing an oxidizing agent. This repair can be performed simultaneously with removal of deposits on the surface of the array substrate. Unlike the prior art, the termination process is not performed with plasma, and the throughput of the array substrate is improved.

  A method for manufacturing an array substrate of the present invention will be described with reference to the drawings. In the present invention, an i-type a-Si layer is thickened without providing an etching stopper in a TFT, and defect levels generated by the method shown in FIGS. 1A to 1C are repaired.

  The manufacturing method of the array substrate 10 is performed in the following order (1) to (9). (1) A transparent insulating substrate, for example, a glass substrate 12 is prepared. (2) The gate line 14 is formed on the glass substrate 12. There are a plurality of gate lines 14, which are formed in parallel. The gate line 14 is formed by forming a metal film such as aluminum and patterning it. A part of the gate line 14 becomes a gate electrode of a TFT to be formed later. In addition to the gate line 14, a Cs (storage capacity) line is also formed. The Cs line is formed between the gate lines 14.

  (3) An insulating film 16 is formed on the glass substrate 12 so as to cover the gate line 14 and the Cs line. The material of the insulating film 16 is, for example, SiOx or SiNx.

(4) Insulating a laminated body in which an amorphous silicon intrinsic semiconductor layer (i-type a-Si layer) 18 and an amorphous silicon semiconductor layer (n ⁺ -type a-Si layer) 20 doped with impurities at a high concentration are sequentially laminated. It is selectively formed on the film 16. The stacked body is formed by sequentially stacking the semiconductor layers 18 and 20 and then patterning them. The i-type a-Si layer 18 becomes a TFT channel, and the n ⁺ -type a-Si layer 20 becomes a drain / source of the TFT.

(5) A signal line that crosses the gate line 14 through the insulating film 16 is formed. A source / drain electrode 22 of the TFT is also formed. As a forming method, a metal film such as molybdenum / aluminum / molybdenum laminated film is formed by a sputtering method or the like. The n ⁺ type a-Si layer 20 is under this metal film. A resist pattern (not shown) is formed by resist application / exposure / development. The signal lines and the source / drain electrodes 22 are formed by etching.

(6) The n ⁺ -type a-Si layer 20 is etched using the previously formed resist pattern as a mask to remove the n ⁺ -type a-Si layer 20 between the source and drain of the TFT (channel cut). Etching is plasma dry etching or the like. By this etching, a part of the i-type a-Si layer 18 is also etched and exposed. That is, the etching of the n ⁺ -type a-Si layer 20 is over-etching. By this over-etching, a defect level is generated in the i-type a-Si layer 18, and the operating voltage of the TFT changes.

  (7) The substrate 10 is placed in a peeling apparatus, and the resist is peeled off with a peeling solution. As the stripping solution, an amine stripping solution is used. For example, the stripping solution contains monoethanolamine as a main component.

  (8) Before covering the exposed i-type a-Si layer 18 with a passivation film, an a-Si termination process for repairing defect levels generated in the i-type a-Si layer 18 is performed. This treatment uses a solution to which an oxidizing agent is added. The solution is obtained by adding ozone as an oxidizing agent to pure water. The termination of a-Si is performed by ozone treatment, that is, radicals generated by opening of Si molecules by plasma etching are stabilized by ozone. By this ozone treatment, Si in which defect levels are generated is stabilized as SiO. Further, ozone is added at about 10 ppm with respect to pure water. A solution is generated by blowing a gas containing ozone into pure water. For example, when the solution is sprayed on the substrate for about 30 seconds, the defect level can be repaired.

Simultaneously with the repair of the defect level, the above solution is used to perform the cleaning before forming the passivation film for removing the deposit 24 generated by etching the n ⁺ -type a-Si layer 20. The cleaning performed simultaneously with the defect repair may be performed after the resist is stripped in the stripping apparatus.

  (9) A passivation film is formed. The passivation film is formed of pSiNx. Conventionally, a termination process using plasma such as hydrogen is performed immediately before the formation of the passivation film, but this is not performed in the present invention.

  In the present invention, cleaning is performed with cleaning water containing an oxidizing agent such as ozone in cleaning before forming a passivation film without providing a new apparatus. Simultaneously with cleaning, the defect level generated in the i-type a-Si layer 18 is repaired, and a-Si termination treatment is performed. Therefore, it is not necessary to use an apparatus for performing special termination treatment with plasma as in the prior art. When terminating with plasma, since the i-type a-Si layer 18 is slightly etched, the i-type a-Si layer 18 is damaged, but in the present invention, plasma is not used. No damage to 18 will occur. Since the termination process is not performed with plasma, the production efficiency of the array substrate 10 can be improved.

FIG. 2 shows the experimental results of the relationship between the gate-source voltage (Vgs) and the drain-source current (Ids) after termination of the present invention and the prior art. The drain-source voltage is 10V. The relationship between Vgs and Ids when no termination processing is performed is also shown. From FIG. 2, V _th and I _off equivalent to the conventional hydrogen plasma treatment were obtained in the present invention. That is, the termination treatment can be easily performed according to the present invention without performing the termination treatment with plasma as in the prior art.

  Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment. In addition, the present invention can be implemented in a mode in which various improvements, modifications, and changes are made based on the knowledge of those skilled in the art without departing from the spirit of the present invention.

It is the figure which showed the termination | terminus process of a-Si typically, (a) is a figure which etches n ⁺ type | mold a-Si layer, (b) performs termination | terminus process, removing a deposit with a solution. It is a figure, (c) is a figure after termination processing. It is a graph which shows the difference in the characteristic of TFT by the difference in termination processing.

Explanation of symbols

10: array substrate 12: transparent substrate 14: gate line 16: insulating film 18: i-type a-Si layer 20: n ⁺ -type a-Si layer 22: source / drain electrode 24: deposit

Claims (4)

Preparing an insulating substrate; and
Forming a gate line on the insulating substrate;
Laminating an insulating film covering the gate line on the insulating substrate;
Forming a stack of an intrinsic semiconductor layer and a semiconductor layer doped with impurities on the insulating film;
Laminating a metal film on the insulating film and the semiconductor layer doped with impurities; and
Forming a resist pattern with a resist on the metal film;
Etching the metal film to form a signal line that crosses the source / drain electrode and the gate line;
Etching the impurity-doped semiconductor layer to expose the intrinsic semiconductor layer;
Stripping the resist;
Repairing a defect level in the intrinsic semiconductor layer generated in the step of etching the semiconductor layer doped with the impurity with a solution to which an oxidant is added; and
Forming a passivation film on the exposed intrinsic semiconductor layer;
A method for manufacturing an array substrate including:   The method of manufacturing an array substrate according to claim 1, wherein the step of repairing the defect level includes a step of spraying a solution to which an oxidizing agent is added to the exposed intrinsic semiconductor layer.   The method for manufacturing an array substrate according to claim 2, wherein the oxidizing agent is ozone.   4. The array substrate manufacturing method according to claim 1, wherein the step of repairing the defect level includes removal of deposits generated by the etching step and the peeling step, or cleaning before forming the passivation film. Method.

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