JP4112587B2

JP4112587B2 - Display device

Info

Publication number: JP4112587B2
Application number: JP2006001931A
Authority: JP
Inventors: 吉晴平形; 舜平山崎
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2006-01-07
Filing date: 2006-01-07
Publication date: 2008-07-02
Anticipated expiration: 2017-03-27
Also published as: JP2006119667A

Description

本発明は対向する基板にそれぞれ形成された配線を導電性スペーサを介して電気的に接続するためのコンタクト構造に関する。特に、本発明は、液晶表示装置等の電気光学装置のコモンコンタクトに応用されるコンタクト構造に関する。 The present invention relates to a contact structure for electrically connecting wirings formed on opposing substrates via conductive spacers. In particular, the present invention relates to a contact structure applied to a common contact of an electro-optical device such as a liquid crystal display device.

近年、モバイルコンピュータや携帯電話（ＰＨＳを含む）等の携帯情報端末機器（携帯機器）の表示部に液晶表示装置が広く使用されている。また液晶表示装置として、薄膜トランジスタをスイッチング素子に使用したアクティブマトリクス型の液晶表示装置が広く知られている。 2. Description of the Related Art In recent years, liquid crystal display devices have been widely used in display units of portable information terminal devices (mobile devices) such as mobile computers and mobile phones (including PHS). As a liquid crystal display device, an active matrix liquid crystal display device using a thin film transistor as a switching element is widely known.

液晶表示装置は２枚の基板に液晶を封入し、２枚の基板にそれぞれ形成された電極により電界を形成し、その電界強度を制御することにより表示を行っている。アクティブマトリクス型液晶表示装置においては、２枚の基板のうち、一方の基板は画素電極に電圧供給を制御するための薄膜トランジスタ（ＴＦＴ）が形成されるため、ＴＦＴ基板と呼ばれ、他方の基板は画素電極に対向する対向電極が形成されるため、対向基板と呼ばれている。 In a liquid crystal display device, liquid crystal is sealed in two substrates, an electric field is formed by electrodes respectively formed on the two substrates, and display is performed by controlling the electric field strength. In an active matrix liquid crystal display device, one of two substrates is called a TFT substrate because a thin film transistor (TFT) for controlling voltage supply is formed on a pixel electrode, and the other substrate is called Since a counter electrode facing the pixel electrode is formed, it is called a counter substrate.

アクティブマトリクス型表示装置においては、ＴＦＴ基板上の画素電極と対向基板上の対向電極間で電界を発生して、表示を実現している。ＴＦＴ基板上の画素電極の電位は薄膜トランジスタにより制御されて変動するが、対向基板上の対向電極は一定のコモン電位に固定される。対向電極をコモン電位に固定するために、対向電極は、ＴＦＴ基板上に形成されたコモンコンタクトを介して取出し端子に接続され、この取出し端子は基板外部の電源に接続される。このような接続構成により、対向電極の電位は電源によりコモン電位に固定される。 In an active matrix display device, display is realized by generating an electric field between a pixel electrode on a TFT substrate and a counter electrode on a counter substrate. Potential of the pixel electrodes on the TFT substrate varies is controlled by thin film transistors, but the counter electrode on the counter substrate are fixed to a constant common potential. In order to fix the counter electrode at a common potential, the counter electrode is connected to an extraction terminal via a common contact formed on the TFT substrate, and the extraction terminal is connected to a power supply outside the substrate. With such a connection configuration, the potential of the counter electrode is fixed to the common potential by the power supply.

以下に、図１２〜図１４を用いて、従来のアクティブマトリクス型表示装置のコモンコンタクトの構造を簡単に説明する。 The structure of the common contact of the conventional active matrix display device will be briefly described below with reference to FIGS.

図１２はＴＦＴ基板１０の上面図であり、基板１１上には、画素電極、画素電極に接続された薄膜トランジスタがマトリクス状に配置された画素領域１２と、薄膜トランジスタのＯＮ／ＯＦＦのタイミングを制御するための走査線駆動回路１３と、画素電極に画像データを供給するための信号線駆動回路１４が設けられている。更に、外部から電力や制御信号を供給するための取出し端子１５が設けられ、対向電極との接続部となるコモンコンタクト部１６ａ〜１６ｄが設けられている。 FIG. 12 is a top view of the TFT substrate 10. On the substrate 11, the pixel region 12 in which pixel electrodes and thin film transistors connected to the pixel electrodes are arranged in a matrix and the ON / OFF timing of the thin film transistors are controlled. There are provided a scanning line driving circuit 13 and a signal line driving circuit 14 for supplying image data to the pixel electrodes. Furthermore, an extraction terminal 15 for supplying electric power and a control signal from the outside is provided, and common contact portions 16a to 16d serving as connection portions with the counter electrode are provided.

図１３は画素領域１２及びコモンコンタクト部１６の断面構成図である。図１３に示すように、ＴＦＴ基板１１の画素領域１２には、基板１１上に薄膜トランジスタ１７が形成され、薄膜トランジスタ１７上には層間絶縁膜１８が形成され、層間絶縁膜１８上には、薄膜トランジスタ１７のドレイン電極に接続された画素電極１９が形成されている。 FIG. 13 is a cross-sectional configuration diagram of the pixel region 12 and the common contact portion 16 . As shown in FIG. 13, in the pixel region 12 of the TFT substrate 11, a thin film transistor 17 is formed on the substrate 11 , an interlayer insulating film 18 is formed on the thin film transistor 17, and a thin film transistor 17 is formed on the interlayer insulating film 18. A pixel electrode 19 connected to the drain electrode is formed.

コモンコンタクト部１６において、内部配線２１が薄膜トランジスタ１７のソース・ドレイン電極の出発膜をパターニングして形成されている。層間絶縁膜１８には矩形状の開口部が形成され、この開口部において内部配線２１に接続される導電性パッド２２が形成されている。画素電極１９と導電性パッド２２は同じ出発膜からパターニングされている。 In the common contact portion 16, the internal wiring 21 is formed by patterning the starting film of the source / drain electrode of the thin film transistor 17. A rectangular opening is formed in the interlayer insulating film 18, and a conductive pad 22 connected to the internal wiring 21 is formed in the opening. The pixel electrode 19 and the conductive pad 22 are patterned from the same starting film.

図１４は従来例のコモンコンタクト部１６の上面図であり、導電性パッド２２の内側の点線の領域が層間絶縁膜１８に形成された開口部に相当する。 FIG. 14 is a top view of the conventional common contact portion 16, and the dotted line region inside the conductive pad 22 corresponds to the opening formed in the interlayer insulating film 18.

図１３に示すように、対向基板２３表面には透明導電膜でなる対向電極２４が形成され、対向電極２４は画素領域１２において画素電極１９に対向し、コモンコンタクト部１６において導電性パッド２２と対向する。 As shown in FIG. 13, a counter electrode 24 made of a transparent conductive film is formed on the surface of the counter substrate 23, the counter electrode 24 faces the pixel electrode 19 in the pixel region 12, and the conductive pad 22 in the common contact portion 16. Opposite.

そして、基板１１と２３の間隔を保持するため、画素領域１２には球状の絶縁性のスペーサ２５が配置され、コモンコンタクト部１６には球状の導電性スペーサ２６が配置される。導電性スペーサ２６により対向電極２４はＴＦＴ基板の導電性パッド２２に電気的に接続される。導電性パッド２２は内部配線２１に電気的に接続され、内部配線２１は取出し端子１５に電気的に接続されている。このような接続構成により、対向基板２３側の対向電極２４は、ＴＦＴ基板１１側の取出し端子１５に接続されている。 In order to maintain the distance between the substrates 11 and 23, a spherical insulating spacer 25 is disposed in the pixel region 12, and a spherical conductive spacer 26 is disposed in the common contact portion 16. The counter electrode 24 is electrically connected to the conductive pad 22 of the TFT substrate by the conductive spacer 26. The conductive pad 22 is electrically connected to the internal wiring 21, and the internal wiring 21 is electrically connected to the extraction terminal 15 . With such a connection configuration, the counter electrode 24 on the counter substrate 23 side is connected to the extraction terminal 15 on the TFT substrate 11 side.

従来の液晶表示装置においては、図１３に示すように、コモンコンタクト部１６には層間絶縁膜１８に開口部が形成されるため、（コモンコンタクト部のセルギャップＧc ）≒（画素領域のセルギャップＧp ）＋（層間絶縁膜１８の膜厚ｔ）の関係がある。 In the conventional liquid crystal display device, as shown in FIG. 13, since an opening is formed in the interlayer insulating film 18 in the common contact portion 16, (cell gap Gc in the common contact portion) ≈ (cell gap in the pixel region) Gp) + (film thickness t of interlayer insulating film 18).

画素領域１２のセルギャップＧpはスペーサ２５により規定される。スペーサ２５には規格品が用いられるため、スペーサ２５の径が同じであれば、画素領域１２のセルギャップＧpは基板ごとにほぼ同じになる。しかしながら、コモンコンタクト部のセルギャップＧc が基板ごとにばらつくことを避けることは、困難である。 The cell gap Gp of the pixel region 12 is defined by the spacer 25. Since a standard product is used for the spacer 25, if the diameter of the spacer 25 is the same, the cell gap Gp of the pixel region 12 is substantially the same for each substrate. However, it is difficult to avoid the cell gap Gc of the common contact portion varying from substrate to substrate.

コモンコンタクト部のセルギャップＧcは、上記の関係からセルギャップＧpが一定なため、層間絶縁膜１８の膜厚ｔのみに依存する。よって、基板ごとにセルギャップＧc を一定にするには層間絶縁膜１８の膜厚ｔをばらつかないようにする必要があるが、この層間絶縁膜１８の膜厚ｔは、基板ごとに同じ膜厚ｔになるように成膜しても、基板ごとにその膜厚ｔがばらつくことは避けられない。 The cell gap Gc of the common contact portion depends only on the film thickness t of the interlayer insulating film 18 because the cell gap Gp is constant from the above relationship. Therefore, in order to make the cell gap Gc constant for each substrate, it is necessary to prevent the film thickness t of the interlayer insulating film 18 from varying. The film thickness t of this interlayer insulating film 18 is the same film for each substrate. Even if the film is formed to have a thickness t, it is inevitable that the film thickness t varies from substrate to substrate.

また、液晶表示装置のコモンコンタクト部は通常２〜４個形成されるが、同一基板でも層間絶縁膜１８の膜厚ｔが場所ごとに異なる場合があり、このような場合には、同一基板であってもコモンコンタクト部ごとに膜厚ｔが異なるおそれもある。 In addition, two to four common contact portions of the liquid crystal display device are usually formed. Even in the same substrate, the film thickness t of the interlayer insulating film 18 may vary from place to place. Even if it exists, there exists a possibility that the film thickness t may differ for every common contact part.

このような層間絶縁膜１８の膜厚ｔのばらつきため、コモンコンタクト部のセルギャップＧc は基板ごと、あるいはコモンコンタクト部ごとにばらついてしまう。更に、このセルギャップＧc のばらつきにより、画素領域のセルギャップＧpのばらつきを生じてしまう。 Due to such a variation in the film thickness t of the interlayer insulating film 18, the cell gap Gc of the common contact portion varies from substrate to substrate or from common contact portion. Further, the variation in the cell gap Gc causes the variation in the cell gap Gp in the pixel region.

このコモンコンタクト部のセルギャップＧc のばらつきが画素領域のセルギャップＧp に与える影響は、画素領域１２の面積がコモンコンタクト部の面積より相対的に狭くなる程顕在化することになる。特に、プロジェクターなどに用いる投射用ディスプレイは、１〜２inch 程度の極めて高精細な小型ディスプレイであるため、上述の画素領域のセルギャップＧp のばらつきの問題が顕在化してしまう。 The influence of the variation in the cell gap Gc in the common contact portion on the cell gap Gp in the pixel region becomes more apparent as the area of the pixel region 12 becomes relatively smaller than the area of the common contact portion. In particular, a projection display used for a projector or the like is an extremely high-definition small display of about 1 to 2 inches, and thus the above-described problem of variation in the cell gap Gp in the pixel region becomes obvious.

また、導電性スペーサ２６も規格品が用いられるが、その径は画素領域１２のスペーサ２５の径と設計時の層間絶縁膜１８の膜厚で決定される。しかしながら、層間絶縁膜１８の膜厚が設計値よりも非常に厚くなった場合、コモンコンタクト部のセルギャップＧc が非常に大きくなるため、導電性スペーサ２６により、対向電極を導電性パッドに良好に接続することができなくなってしまう。このような場合には、対向電極の電位をコモン電位に固定できなくなり、表示が行えなくなる。 A standard product is also used for the conductive spacer 26, and the diameter is determined by the diameter of the spacer 25 in the pixel region 12 and the thickness of the interlayer insulating film 18 at the time of design. However, when the film thickness of the interlayer insulating film 18 is much larger than the design value, the cell gap Gc of the common contact portion becomes very large, and therefore the conductive spacer 26 makes the counter electrode a conductive pad. It becomes impossible to connect. In such a case, the potential of the counter electrode cannot be fixed to the common potential, and display cannot be performed.

本発明の目的は、上記の問題点を解消し、層間絶縁膜の膜厚がばらついても、基板ごとの基板間隔のばらつきをなくし、かつ導電性スペーサが原因となる接触不良の発生を減少することを可能にしたコンタクト構造を提供することにある。 An object of the present invention is to solve the above problems, even variations in thickness of the interlayer insulating film, it eliminates the variations in substrate spacing of each substrate, and the conductive spacer to reduce the occurrence of contact defects causes An object of the present invention is to provide a contact structure that makes it possible.

上述した問題点を解消するために、本発明の構成は、
基板と、
前記基板に設けられ、薄膜トランジスタと前記薄膜トランジスタに電気的に接続された画素電極とを有する画素領域と、
前記基板に設けられた複数の端子と、
前記画素領域の周辺に設けられたコモンコンタクト部と、
前記画素領域の周辺に設けられ、前記コモンコンタクト部に電気的に接続された配線とを有し、
前記複数の端子のうちの少なくとも１つの端子は、前記コモンコンタクト部に電気的に接続され、
前記コモンコンタクト部には、
前記基板に形成された第１の導電膜と、
前記第１の導電膜上に形成された絶縁膜と、
前記絶縁膜に形成された前記第１の導電膜に達する開口部と、
前記絶縁膜上に形成され、前記開口部において前記第１の導電膜に電気的に接続された第２の導電膜と、
導電性スペーサとが設けられ、
前記導電性スペーサは前記絶縁膜上において、前記第２の導電膜と前記基板に対向する対向基板に設けられた第３の導電膜との双方に接し、
前記コモンコンタクト部に対向する前記対向基板の箇所に第４の導電膜を設け、前記第４の導電膜の前記開口部に対向する箇所に開口を設けることを特徴とする。 In order to solve the problems described above, the configuration of the present invention is as follows.
A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion ;
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film .

更に、本発明の他の構成は、
基板と、
前記基板に設けられ、薄膜トランジスタと前記薄膜トランジスタに電気的に接続された画素電極とを有する画素領域と、
前記基板に設けられた複数の端子と、
前記画素領域の周辺に設けられたコモンコンタクト部と、
前記画素領域の周辺に設けられ、前記コモンコンタクト部に電気的に接続された配線とを有し、
前記複数の端子のうちの少なくとも１つの端子は、前記コモンコンタクト部に電気的に接続され、
前記コモンコンタクト部には、
前記基板に形成された第１の導電膜と、
前記第１の導電膜上に形成された絶縁膜と、
前記絶縁膜に形成された前記第１の導電膜に達する開口部と、
前記絶縁膜上に形成され、前記開口部において前記第１の導電膜に電気的に接続された第２の導電膜と、
導電性スペーサとが設けられ、
前記導電性スペーサは前記絶縁膜上において、前記第２の導電膜と前記基板に対向する対向基板に設けられた第３の透明導電膜との双方に接し、
前記コモンコンタクト部に対向する前記対向基板の箇所に第４の導電膜を設け、前記第４の導電膜の前記開口部に対向する箇所に開口を設けることを特徴とする。 Furthermore, another configuration of the present invention is as follows:
A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion ;
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film .

更に、本発明の他の構成は、
基板と、
前記基板に設けられ、薄膜トランジスタと前記薄膜トランジスタに電気的に接続された画素電極とを有する画素領域と、
前記基板に設けられ、複数の端子を有する取出し端子部と、
前記画素領域の周辺に設けられ、前記取出し端子部に電気的に接続されたコモンコンタクト部と、
前記画素領域の周辺に設けられ、前記コモンコンタクト部に電気的に接続された配線とを有し、
前記取出し端子部は、前記導電膜に電気的に接続され、かつ一番端に配置されていない端子を有し、
前記コモンコンタクト部には、
前記基板に形成された第１の導電膜と、
前記第１の導電膜上に形成された絶縁膜と、
前記絶縁膜に形成された前記第１の導電膜に達する開口部と、
前記絶縁膜上に形成され、前記開口部において前記第１の導電膜に電気的に接続された第２の導電膜と、
導電性スペーサとが設けられ、
前記導電性スペーサは前記絶縁膜上において、前記第２の導電膜と前記基板に対向する対向基板に設けられた第３の導電膜との双方に接し、
前記コモンコンタクト部に対向する前記対向基板の箇所に第４の導電膜を設け、前記第４の導電膜の前記開口部に対向する箇所に開口を設けることを特徴とする。 Furthermore, another configuration of the present invention is as follows:
A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion, have a said conductive film are electrically connected, and terminals which are not located at the very end,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film .

更に、本発明の他の構成は、
基板と、
前記基板に設けられ、薄膜トランジスタと前記薄膜トランジスタに電気的に接続された画素電極とを有する矩形状の画素領域と、
前記画素領域の周辺に設けられた第１のコモンコンタクト部および第２のコモンコンタクト部と、
前記基板に設けられた複数の端子と、
前記画素領域の１辺に沿って設けられ、前記第１のコモンコンタクト部に電気的に接続された第１の配線と、
前記画素領域の他の１辺に沿って設けられ、前記第２のコモンコンタクト部に電気的に接続された第２の配線とを有し、
前記第１のコモンコンタクト部および前記第２のコモンコンタクト部は、それぞれ、前記複数の端子のうちの少なくとも１つの端子に電気的に接続され、
前記第１のコモンコンタクト部および前記第２のコモンコンタクト部には、
前記基板に形成された第１の導電膜と、
前記第１の導電膜上に形成された絶縁膜と、
前記絶縁膜に形成された前記第１の導電膜に達する開口部と、
前記絶縁膜上に形成され、前記開口部において前記第１の導電膜に電気的に接続された第２の導電膜と、
導電性スペーサとが設けられ、
前記導電性スペーサは前記絶縁膜上において、前記第２の導電膜と前記基板に対向する対向基板に設けられた第３の導電膜との双方に接し、
前記第１のコモンコンタクト部および前記第２のコモンコンタクト部に対向する前記対向基板の箇所に第４の導電膜を設け、前記第４の導電膜の前記開口部に対向する箇所に開口を設けることを特徴とする。 Furthermore, another configuration of the present invention is as follows:
A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A first common contact portion and a second common contact portion provided around the pixel region;
A plurality of terminals provided on the substrate;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The first common contact portion and the second common contact portion are each electrically connected to at least one of the plurality of terminals ,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. It is characterized by that.

更に、本発明の他の構成は、
基板と、
前記基板に設けられ、薄膜トランジスタと前記薄膜トランジスタに電気的に接続された画素電極とを有する矩形状の画素領域と、
前記基板に設けられ、複数の端子を有する取出し端子部と、
前記画素領域の周囲に設けられ、前記取出し端子部に電気的に接続された第１のコモンコンタクト部および第２のコモンコンタクト部と、
前記画素領域の１辺に沿って設けられ、前記第１のコモンコンタクト部に電気的に接続された第１の配線と、
前記画素領域の他の１辺に沿って設けられ、前記第２のコモンコンタクト部に電気的に接続された第２の配線とを有し、
前記取出し端子部は、前記導電膜に電気的に接続され、かつ一番端に配置されていない端子を有し、
前記第１のコモンコンタクト部および前記第２のコモンコンタクト部には、
前記基板に形成された第１の導電膜と、
前記第１の導電膜上に形成された絶縁膜と、
前記絶縁膜に形成された前記第１の導電膜に達する開口部と、
前記絶縁膜上に形成され、前記開口部において前記第１の導電膜に電気的に接続された第２の導電膜と、
導電性スペーサとが設けられ、
前記導電性スペーサは前記絶縁膜上において、前記第２の導電膜と前記基板に対向する対向基板に設けられた第３の導電膜との双方に接し、
前記第１のコモンコンタクト部および前記第２のコモンコンタクト部に対向する前記対向基板の箇所に第４の導電膜を設け、前記第４の導電膜の前記開口部に対向する箇所に開口を設けることを特徴とする。 Furthermore, another configuration of the present invention is as follows:
A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A first common contact portion and a second common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The extraction terminal portion, have a said conductive film is electrically connected, and terminals not located at the very end,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. It is characterized by that.

本発明のコモンコンタクト構造により、層間絶縁膜の膜厚がばらついても、基板ごとの基板間隔のばらつきをなくし、かつ導電性スペーサが原因となる接触不良の発生を減少することが可能になる。 Common-contact structure of the present invention, even if variations in thickness of the interlayer insulating film, eliminates the variations in substrate spacing of each substrate, and the conductive spacers is possible to reduce the occurrence of contact defects causes.

即ち、本発明においては、基板間隔は導電性スペーサの大きさのみに依存することになるため、導電性スペーサの大きさが同じであれば、第１の導電膜と第２の導電膜とを絶縁している絶縁膜の厚さが基板ごとに異なっても、その対向する基板の間隔を基板ごとに同じにすることができる。 That is, in the present invention, since the substrate interval depends only on the size of the conductive spacer, if the size of the conductive spacer is the same, the first conductive film and the second conductive film are connected. Even when the thickness of the insulating film that is insulated differs from one substrate to another, the distance between the opposing substrates can be the same for each substrate.

図１、図２を用いて本発明の実施の形態を説明する。 An embodiment of the present invention will be described with reference to FIGS.

［実施の形態１］図１は本実施の形態のコモンコンタクト部の断面構成図であり、図２はＴＦＴ基板側の上面図である。また、図２（Ａ）に示す領域１２０の断面拡大図が図１に相当する。 First Embodiment FIG. 1 is a cross-sectional configuration diagram of a common contact portion according to the present embodiment, and FIG. 2 is a top view on the TFT substrate side. A cross-sectional enlarged view of the region 120 shown in FIG.

図１３に示すように、従来例では画素領域１２のスペーサは画素電極１９を介して、層間絶縁膜１８上に配置されるが、コモンコンタクト部１６の導電性パッド２２の下層には層間絶縁膜１８が存在しない。層間絶縁膜１８が存在しないことが、コモンコンタクト部のセルギャップＧc が層間絶縁膜１８の膜厚に依存することの原因である。 As shown in FIG. 13, in the conventional example, the spacer in the pixel region 12 is disposed on the interlayer insulating film 18 via the pixel electrode 19, but the interlayer insulating film is formed below the conductive pad 22 of the common contact portion 16. 18 does not exist. The interlayer insulating film 18 is not present, the cause of the Serugya-up Gc of the common contact portion is dependent on the thickness of the interlayer insulating film 18.

そこで、本実施形態においては、コモンコンタクト部にも導電性パッドの下層に絶縁体を存在させ、絶縁体上に導電性スペーサを配置することにより、コモンコンタクト部のセルギャップＧc が層間絶縁膜１８の膜厚に依存しないようにするものであり、本実施形態では、層間絶縁膜１８を選択的に残存するように開口部を形成することを特徴とする。 Therefore, in this embodiment, the presence of a lower insulator of conductive pads to the common contact section, by disposing the conductive spacer on an insulator, Serugya-up Gc interlayer insulating film of the common contact portion 18 is intended to be independent of the thickness of, in this embodiment, and forming an opening to selectively leave the interlayer insulating film 18.

本実施形態において、第１の基板１０１には第１の導電膜１０３と、第１の導電膜１０３を覆う絶縁膜１０４と、絶縁膜１０４を選択的に残存して開口され第１の導電膜１０３を露出する開口部１１１と、残存された前記絶縁膜１０４ａと開口部１１１とを覆う第２の導電膜１０５がそれぞれ形成される。 In this embodiment, the first substrate 101 has a first conductive film 103, an insulating film 104 covering the first conductive film 103, and the insulating film 104 is selectively left open so that the first conductive film is opened. 103 an opening 111 for exposing the second conductive film 105 covering the remaining has been the insulating film 104a and the opening 111 is made forms, respectively.

第２の基板１０２上には第３の導電膜１０６が形成され、第１の基板１０１と第２の基板１０２との間には、導電性スペーサ１０７が挟持されている。 A third conductive film 106 is formed over the second substrate 102, and a conductive spacer 107 is sandwiched between the first substrate 101 and the second substrate 102.

図１３に示す従来のコモンコンタクト部１６であれば、開口部１１０においては、層間絶縁膜１８はすべて除去されていたが、本実施形態では、絶縁膜１０４ａを選択的に残存させて開口部１１１を形成する。この開口部１１１により第１の導電膜１０３が露出され、ここで第１の導電膜１０３と第２の導電膜１０５とが接続される。 If conventional common contact portion 16 shown in FIG. 13, in the opening 110, which had been removed Te interlayer insulating film 18 Hasube, in the present embodiment, by selectively leaving the insulating film 104a opening A portion 111 is formed. The first conductive film 103 is exposed through the opening 111, and the first conductive film 103 and the second conductive film 105 are connected to each other.

また、第１の基板１０１側において、残存された絶縁膜１０４ａが最も第２の基板１０２に接近しているため、図１に示すように、この残存された絶縁膜１０４ａ上において、導電性スペーサ１０７により、第１の基板上の第２の導電膜１０５と第２の基板１０２上の第３の導電膜１０６が電気的に接続される。 Further, since the remaining insulating film 104a is closest to the second substrate 102 on the first substrate 101 side, a conductive spacer is formed on the remaining insulating film 104a as shown in FIG. By 107, the second conductive film 105 on the first substrate and the third conductive film 106 on the second substrate 102 are electrically connected.

更に、開口部１１０では残存された絶縁膜１０４ａが最も第２の基板に接近しているため、第２の導電膜１０５と第３の導電膜１０６を電気的に接続している導電性スペーサ１０７により、基板間隔Ｇが保持される。よって、この基板間隔Ｇは導電性スペーサ１０７の大きさのみに依存することになる。従って、導電性スペーサ１０７の大きさが同じであれば、絶縁膜１０４の厚さｔが基板ごとに異なっても、その基板間隔Ｇは基板ごとに同じにすることができる。 Further, since the remaining insulating film 104 a is closest to the second substrate in the opening 110, the conductive spacer 107 that electrically connects the second conductive film 105 and the third conductive film 106. Thus, the substrate gap G is maintained. Therefore, this substrate interval G depends only on the size of the conductive spacer 107. Therefore, if the size of the conductive spacer 107 is the same, even if the thickness t of the insulating film 104 is different for each substrate, the substrate gap G can be the same for each substrate.

また、本実施形態において、開口部１１１の面積は１つの導電性スペーサが占める面積よりも十分に広く、導電性スペーサが自由に移動できるような余裕を持たせることが好ましい。この理由は開口部１１１に存在する導電性スペーサ１０７がギャップの保持には寄与しないようにするためである。もし、この領域に導電性スペーサが自由に移動できるような余裕がないと、ここで導電性スペーサ１０７が複数個積み重なってしまい、基板間隔Ｇを基板全体で均一にすることができなくなる。 In the present embodiment, the area of the opening 111 is preferably sufficiently larger than the area occupied by one conductive spacer, and it is preferable to have a margin that allows the conductive spacer to move freely. The reason for this is to prevent the conductive spacer 107 present in the opening 111 from contributing to maintaining the gap. If there is no room for the conductive spacers to move freely in this region, a plurality of conductive spacers 107 are stacked here, and the substrate interval G cannot be made uniform over the entire substrate.

更に、本実施形態において、残存された絶縁膜１０４ａ表面の面積は１つの導電性スペーサ１０７が占めるよりも十分に広く、導電性スペーサ１０７が確実に配置されるような空間であることが好ましい。これは、絶縁膜１０４ａ上に導電性スペーサ１０７が確実に配置されないと、第１の基板と第２の基板間で電気的な接続を取ることができず、更にギャップを保持することもできなくなるからである。 Furthermore, in the present embodiment, the area of the remaining insulating film 104a surface is preferably sufficiently larger than one conductive spacer 107 to occupy and is a space where the conductive spacer 107 is surely disposed. This is because if the conductive spacer 107 is not reliably disposed on the insulating film 104a, it is impossible to establish an electrical connection between the first substrate and the second substrate, and further it is impossible to maintain a gap. Because.

また、本実施形態において、図２（Ａ）に示すように開口部１１１を形成したが、図２（Ｂ）に示すように、残存された絶縁膜１０４ａと開口部１１１の関係を逆にすることもできる。なお、図２（Ａ）で点線で示す領域１２０の拡大断面図が図１に相当する。 In this embodiment, the opening 111 is formed as shown in FIG. 2A. However, as shown in FIG. 2B, the relationship between the remaining insulating film 104a and the opening 111 is reversed. You can also. Incidentally, enlarged cross-sectional view of a region 120 indicated by the dotted line in FIG. 2 (A) corresponds to FIG.

［実施形態２］図１、図２（Ａ）を用いて本発明の実施の形態を説明する。図１は本実施の形態のコモンコンタクト部の断面構成図であり、図２（Ａ）はＴＦＴ基板側の上面図である。図２（Ａ）で点線で示す領域１２０の拡大断面図が図１に相当する。 Embodiment Mode 2 An embodiment mode of the present invention is described with reference to FIGS. 1 and 2A. FIG. 1 is a cross-sectional configuration diagram of the common contact portion of the present embodiment, and FIG. 2A is a top view on the TFT substrate side. An enlarged cross-sectional view of a region 120 indicated by a dotted line in FIG. 2A corresponds to FIG.

本実施形態も実施形態１と同様に、コモンコンタクト部にも導電性パッドの下層に絶縁体を存在させ、絶縁体上に導電性スペーサを配置することにより、コモンコンタクト部のセルギャップＧc が層間絶縁膜１８の膜厚に依存しないようにするものである。そこで、本実施形態では、層間絶縁膜１８を選択的に残存するように開口部を形成することを特徴とする。 Like the present implementation embodiment also embodiments 1, by the presence of the lower insulator of the conductive pad to the common contact portion, disposing a conductive spacer on an insulator, Serugya-up Gc of common contact portion There is to not rely on the thickness of the interlayer insulating film 18. Therefore, the present embodiment is characterized in that the opening is formed so as to selectively leave the interlayer insulating film 18.

即ち、本実施形態においては、導電性パッド２２の下層に絶縁体を形成し、この絶縁体上に導電性スペーサを配置することにより、コモンコンタクト部のセルギャップＧcが層間絶縁膜１８の膜厚に依存しないようにした。 That is, in this embodiment, the lower layer to form an insulator of the conductive pads 22, by disposing the conductive spacers on the insulator, film of the common contact portion Serugya-up Gc interlayer insulating film 18 It did not depend on the thickness.

図１に示すように、第１の基板１０１には、第１の導電膜１０３と、第１の導電膜１０３を覆う絶縁膜１０４と、絶縁膜１０４に形成された第１の導電膜１０３を露出する開口部１１１と、開口部１１１より露出された第１の導電膜１０３表面に選択的に形成された絶縁膜１０４ａと、開口部１１１を覆う第２の導電膜１０５が形成されている。 As shown in FIG. 1, the first substrate 101 includes a first conductive film 103, an insulating film 104 covering the first conductive film 103, and a first conductive film 103 formed on the insulating film 104. an opening 111 for exposing the first insulating film 104a to the conductive film 103 surface is selectively formed which is exposed from the opening 111, the second conductive film 105 that covers the opening portion 111 is formed.

第２の基板１０２上には第３の導電膜１０６が形成され、第１の基板１０１と第２の基板１０２との間には導電性スペーサ１０７が配置されている。 A third conductive film 106 is formed over the second substrate 102, and a conductive spacer 107 is disposed between the first substrate 101 and the second substrate 102.

図２（Ａ）はＴＦＴ基板側の上面図であり、第２の導電膜１０５が形成されていない状態を示す。図２（Ａ）において、点線で示す開口部１１０は従来例の層間絶縁膜１８に形成されたコモンコンタクト用の開口部に相当する。本実施形態では、この開口部１１０に、第１の導電膜１０３が露出される部分を残すように、選択的に絶縁膜１０４ａを形成する。 FIG. 2A is a top view on the TFT substrate side and shows a state where the second conductive film 105 is not formed. In FIG. 2A, an opening 110 indicated by a dotted line corresponds to an opening for a common contact formed in the interlayer insulating film 18 of the conventional example. In this embodiment, the insulating film 104a is selectively formed so as to leave a portion where the first conductive film 103 is exposed in the opening 110.

開口部１１０において、絶縁膜１０４ａが形成されない領域では、第１の導電膜１０３が露出され、その上に形成される第２の導電膜１０５と接続される。 In the opening 110, in the region where the insulating film 104a is not formed, the first conductive film 103 is exposed and connected to the second conductive film 105 formed thereon.

また、第１の基板１０１側において、開口部１１０では絶縁膜１０４ａが最も第２の基板に接近しているため、図１に示すように、この絶縁膜１０４ａ上において、導電性スペーサ１０７により、第１の基板１０１上の第２の導電膜１０５と第２の基板１０２上の第３の導電膜１０６が電気的に接続される。 Further, on the first substrate 101 side, since the insulating film 104a is closest to the second substrate in the opening 110, the conductive spacer 107 on the insulating film 104a as shown in FIG. The second conductive film 105 over the first substrate 101 and the third conductive film 106 over the second substrate 102 are electrically connected.

更に、開口部１１０では絶縁膜１０４ａが最も第２の基板１０２に接近しているため、第２の導電膜１０５と第３の導電膜１０６を電気的に接続している導電性スペーサ１０７により、基板間隔Ｇが保持される。よって、この基板間隔Ｇは導電性スペーサ１０７の大きさのみに依存することになる。従って、導電性スペーサ１０７の大きさが同じであれば、絶縁膜１０４の厚さｔが基板ごとに異なっても、その基板間隔Ｇを基板ごとに同じにすることができる。 Further, since the insulating film 104a is closest to the second substrate 102 in the opening portion 110, the conductive spacer 107 that electrically connects the second conductive film 105 and the third conductive film 106 is used. The substrate gap G is maintained. Therefore, this substrate interval G depends only on the size of the conductive spacer 107. Therefore, if the conductive spacers 107 have the same size, the substrate gap G can be made the same for each substrate even if the thickness t of the insulating film 104 is different for each substrate.

本実施形態において、絶縁膜１０４ａが形成されない領域の面積は１つの導電性スペーサ１０７が占めるよりも十分に広く、導電性スペーサ１０７が自由に移動できるような余裕を持たせることが好ましい。この理由は絶縁膜１０４ａが形成されない領域に存在する導電性スペーサ１０７がギャップの保持には寄与しないようにするためである。もし、この領域に導電性スペーサが自由に移動できるような余裕がないと、ここで導電性スペーサ１０７が複数個積み重なってしまい、基板間隔Ｇを基板全体で均一にすることができなくなってしまう。 In the present embodiment, the area of the region where the insulating film 104a is not formed is sufficiently larger than that occupied by one conductive spacer 107, and it is preferable to have a margin that allows the conductive spacer 107 to move freely. This is because the conductive spacer 107 existing in the region where the insulating film 104a is not formed does not contribute to maintaining the gap. If there is no room for the conductive spacers to move freely in this region, a plurality of conductive spacers 107 are stacked here, and the substrate interval G cannot be made uniform over the entire substrate.

更に、本実施形態において、絶縁膜１０４ａの表面の面積は１つの導電性スペーサ１０７が占めるよりも十分に広く、導電性スペーサ１０７が確実に配置されるような空間であることが好ましい。これは、絶縁膜１０４ａ上に導電性スペーサ１０７が確実に配置されないと、第１と第２の基板間で電気的な接続を取ることができず、更にギャップを保持することができなくなるからである。 Furthermore, in the present embodiment, the surface area of the insulating film 104a is sufficiently larger than one conductive spacer 107 to occupy, and is preferably a space where the conductive spacer 107 is surely arranged. This is because if the conductive spacer 107 is not securely arranged on the insulating film 104a, it is impossible to establish an electrical connection between the first and second substrates, and it is impossible to maintain a gap. is there.

また、本実施形態において、図２（Ａ）に示すように絶縁膜１０４ａを形成したが、図２（Ｂ）に示すように、絶縁膜１０４ａを形成する領域と、第１の導電膜１０３を露出させる領域の関係を逆にすることもできる。 In this embodiment mode, the insulating film 104a is formed as shown in FIG. 2A. However, as shown in FIG. 2B, the region where the insulating film 104a is formed and the first conductive film 103 are formed. It is also possible to reverse the relationship of the exposed areas.

本実施例では本発明を反射型液晶表示装置のコモンコンタクト部に応用した例を示す。図３は本実施例のＴＦＴ基板の上面図であり、図４は対向基板の上面図である。 In this embodiment, an example in which the present invention is applied to a common contact portion of a reflective liquid crystal display device is shown. FIG. 3 is a top view of the TFT substrate of this embodiment, and FIG. 4 is a top view of the counter substrate.

図３に示すように、ＴＦＴ基板２００において、基板２０１上には、画素電極、画素電極に接続された薄膜トランジスタがマトリクス状に配置された画素領域２０２と、薄膜トランジスタのＯＮ／ＯＦＦのタイミングを制御するための走査線駆動回路２０３と、画素電極に画像データを供給するための信号線駆動回路２０４が設けられている。更に、外部から電力や制御信号を供給するための取出し端子２０５が設けられ、対向電極との接続部となるコモンコンタクト部２０６ａ〜２０６ｄが設けられている。 As shown in FIG. 3, in the TFT substrate 200, on the substrate 201, a pixel region 202 in which thin film transistors connected to the pixel electrode and the pixel electrode are arranged in a matrix, and ON / OFF timing of the thin film transistor are controlled. A scanning line driving circuit 203 for supplying image data to the pixel electrode and a signal line driving circuit 204 for supplying image data are provided. Further, an extraction terminal 205 for supplying electric power and a control signal from the outside is provided, and common contact portions 206a to 206d serving as connection portions with the counter electrode are provided.

図４に示すように、対向基板２５０は、基板上に透光性導電膜からなる対向電極２５２が形成されている構造を有する。中央部の矩形の領域２５３はＴＦＴ基板２００の画素領域２０２と対向する領域であり、４隅の領域２５４ａ〜２５４ｄはＴＦＴ基板２００のコンタクト部２０６ａ〜２０６ｄと電気的に接続される領域である。 As shown in FIG. 4, the counter substrate 250 has a structure in which a counter electrode 252 made of a light-transmitting conductive film is formed on the substrate. A rectangular region 253 at the center is a region facing the pixel region 202 of the TFT substrate 200, and regions 254 a to 254 d at the four corners are regions electrically connected to the contact portions 206 a to 206 d of the TFT substrate 200.

そして、図３に示すように、ＴＦＴ基板２００のコモンコンタクト部２０６ａ〜２０６ｄにはそれぞれ導電性パッドが形成されている。これら導電性パッドは内部配線２０７ａ〜２０７ｃによって電気的に接続されている。また、内部配線２０７ａ、２０７ｂは取出し端子２０５に延在し、コモン端子２０５ａ、２０５ｂに電気的に接続されている。 As shown in FIG. 3, conductive pads are formed on the common contact portions 206a to 206d of the TFT substrate 200, respectively. These conductive pads are electrically connected by internal wiring 207a-207c. The internal wirings 207a and 207b extend to the extraction terminal 205 and are electrically connected to the common terminals 205a and 205b.

以下、ＴＦＴ基板の画素領域２０２、及びコモンコンタクト部２０６を作製する工程を図５を用いて説明する。 Hereinafter, a process of manufacturing the pixel region 202 and the common contact portion 206 of the TFT substrate will be described with reference to FIGS.

まず、絶縁表面を有する基板２０１を用意する。本実施例ではガラス基板上に下地膜として酸化珪素膜を形成した。基板２０１の上には結晶性珪素膜でなる活性層３０２を形成する。なお、本実施例では１つの薄膜トランジスタのみを図示しているが、実際には、画素領域２０２には１００万個以上の薄膜トランジスタが形成される。 First, a substrate 201 having an insulating surface is prepared. In this embodiment, a silicon oxide film is formed as a base film on a glass substrate. An active layer 302 made of a crystalline silicon film is formed on the substrate 201. Note that although only one thin film transistor is illustrated in this embodiment, in reality, one million or more thin film transistors are formed in the pixel region 202.

本実施例では非晶質珪素膜を熱結晶化させて結晶性珪素膜を得ている。そして、その結晶性珪素膜を通常のフォトリソ工程でパターニングして活性層３０２を得る。なお、本実施例では結晶化の際に結晶化を助長する触媒元素（ニッケル）を添加している。この技術については特開平7-130652号公報に詳細に記載されている。 In this embodiment, an amorphous silicon film is thermally crystallized to obtain a crystalline silicon film. Then, the crystalline silicon film is patterned by a normal photolithography process to obtain an active layer 302. In this embodiment, a catalyst element (nickel) that promotes crystallization is added during crystallization. This technique is described in detail in Japanese Patent Application Laid-Open No. 7-130652.

次に、１５０ｎｍの厚さの酸化珪素膜３０３を形成し、その上に0.2wt%のスカンジウムを含有させたアルミニウム膜（図示せず）を成膜し、レジストマスク３０４を用いてアルミニウム膜をパターニングし、ゲイト電極の原型となる島状パターン３０５を形成した（図５（Ａ））。 Next, a 150 nm thick silicon oxide film 303 is formed, an aluminum film (not shown) containing scandium of 0.2 wt% is formed thereon, and the aluminum film is patterned using the resist mask 304. Then, an island pattern 305 was formed as a prototype of the gate electrode (FIG. 5A).

本実施例では、ここで特開平7-135318号公報に記載された陽極酸化技術を利用する。なお、詳細は同公報を参考にすると良い。 In this embodiment, the anodic oxidation technique described in JP-A-7-135318 is used here. For details, refer to the publication.

まず、上記島状パターン３０５上にパターニングで使用したレジストマスク３０４を残したまま、３％のシュウ酸水溶液中で陽極酸化を行う。この時、白金電極を陰極として２〜３ｍＶの化成電流を流し、到達電圧は８Ｖとする。この結果、上面にレジストマスク３０４が存在しているため、多孔質状の陽極酸化膜３０６が島状パターン３０５の側面に形成される（図５（Ｂ））。 First, anodic oxidation is performed in a 3% oxalic acid aqueous solution while leaving the resist mask 304 used for patterning on the island pattern 305. At this time, a formation current of 2 to 3 mV is passed using the platinum electrode as a cathode, and the ultimate voltage is 8V. As a result, since the resist mask 304 exists on the upper surface, a porous anodic oxide film 306 is formed on the side surface of the island pattern 305 (FIG. 5B).

その後、レジストマスク３０４を除去した後に３％の酒石酸のエチレングリコール溶液をアンモニア水で中和した溶液中で陽極酸化を行う。この時、化成電流は５〜６ｍＶとし、到達電圧は１００Ｖとすれば良い。こうして、緻密な陽極酸化膜３０７が形成される。 Thereafter, after removing the resist mask 304, anodization is performed in a solution obtained by neutralizing an ethylene glycol solution of 3% tartaric acid with aqueous ammonia. At this time, the formation current may be 5 to 6 mV, and the ultimate voltage may be 100V. Thus, a dense anodic oxide film 307 is formed.

そして、上記陽極酸化工程によって、島状パターン３０５の陽極酸化されない部分がゲイト電極３０８として画定する。なお、コモンコンタクト部２０６ｃ、２０６ｄを接続する内部配線２０７ｃも、上記アルミニウム膜を出発膜として、ゲイト電極３０８の形成と同時に形成されている。 Then, the portion of the island pattern 305 that is not anodized is defined as the gate electrode 308 by the anodizing step. Note that the internal wiring 207c that connects the common contact portions 206c and 206d is also formed simultaneously with the formation of the gate electrode 308 using the aluminum film as a starting film.

次に、ゲイト電極３０８及びその周囲の陽極酸化膜３０６、３０７をマスクとして酸化珪素膜３０３をエッチングし、ゲイト絶縁膜３０９を形成する。エッチングはＣＦ_４ガスを用いたドライエッチング法を採用した（図５（Ｃ））。 Next, a silicon oxide film 303 et etching the gate electrode 308 and the anodic oxide film 306, 307 of the surrounding as a mask to form a gate insulating film 309. Etching employed a dry etching method using CF ₄ gas (FIG. 5C).

ゲイト絶縁膜３０９を形成した後、多孔質状の陽極酸化膜３０６をアルミ混酸を用いたウェットエッチングにより、除去した。 After forming the gate insulating film 309, the porous anodic oxide film 306 was removed by wet etching using aluminum mixed acid.

次に、イオン注入法またはプラズマドーピング法により一導電性を付与する不純物イオンを添加する。画素領域にＮ型薄膜トランジスタを配置するならばＰ（リン）イオンを、Ｐ型薄膜トランジスタを配置するならばＢ（ボロン）イオンを添加すれば良い。 Next, impurity ions imparting one conductivity are added by an ion implantation method or a plasma doping method. If an N-type thin film transistor is arranged in the pixel region, P (phosphorus) ions may be added, and if a P-type thin film transistor is arranged, B (boron) ions may be added.

本実施例では、上記不純物イオンの添加工程をイオン注入法を用いて、２度に分けて行った。１度目は８０ｋｅＶの高加速電圧で行い、ゲイト絶縁膜３０９の端部（突出部）の下に不純物イオンのピークがくるように調節した。そして、２度目は５ｋｅＶの低加速電圧で行い、ゲイト絶縁膜３０９の端部（突出部）の下に不純物イオンが添加されないように、加速電圧を調節した。 In this example, the impurity ion addition step was performed twice using an ion implantation method. The first time was performed at a high acceleration voltage of 80 keV, and adjustment was made so that the peak of impurity ions was located under the end (protrusion) of the gate insulating film 309. The second time was performed at a low acceleration voltage of 5 keV, and the acceleration voltage was adjusted so that impurity ions were not added under the end portion (projecting portion) of the gate insulating film 309.

こうして薄膜トランジスタのソース領域３１０、ドレイン領域３１１、低濃度不純物領域３１２、３１３、チャネル形成領域３１４が形成される。なお、ドレイン領域３１１側の低濃度不純物領域３１３はＬＤＤ領域とも呼ばれる（図５（Ｄ））。 Thus, the source region 310, the drain region 311, the low concentration impurity regions 312, 313, and the channel formation region 314 of the thin film transistor are formed. Note that the low-concentration impurity region 313 on the drain region 311 side is also referred to as an LDD region (FIG. 5D).

この時、ソース、ドレイン領域３１０、３１１は 300〜500 Ω／□のシート抵抗が得られる程度に不純物イオンを添加することが好ましい。また、低濃度不純物領域３１２、３１３は薄膜トランジスタの性能に合わせて最適化を行う必要がある。不純物イオンの添加工程が終了したら熱処理を行い、不純物イオンの活性化を行った。 At this time, the source and drain regions 310 and 311 are preferably doped with impurity ions to such an extent that a sheet resistance of 300 to 500 Ω / □ can be obtained. The low concentration impurity regions 312 and 313 need to be optimized in accordance with the performance of the thin film transistor. After the impurity ion addition step was completed, heat treatment was performed to activate the impurity ions.

次に、第１の層間絶縁膜３１５として酸化珪素膜を１μｍの厚さに形成した。第１の層間絶縁膜３１５の膜厚を１μｍと膜厚にしたのは第１の層間絶縁膜３１５の表面をできるだけ平坦にするためであり、膜厚にすることで、ゲイト電極３０８による突出を緩和できる。 Next, a silicon oxide film having a thickness of 1 μm was formed as the first interlayer insulating film 315. The reason why the thickness of the first interlayer insulating film 315 is set to 1 μm is to make the surface of the first interlayer insulating film 315 as flat as possible. Can be relaxed.

第１の層間絶縁膜３１５として、酸化珪素膜の他に窒化珪素膜、酸化窒化珪素膜を形成しても良い。或いは、これら絶縁膜の多層膜としても良い。 As the first interlayer insulating film 315, a silicon nitride film or a silicon oxynitride film may be formed in addition to the silicon oxide film. Alternatively, a multilayer film of these insulating films may be used.

そして、第１の層間絶縁膜３１５に、ソース、ドレイン領域３１０、３１１に対するコンタクトホールと、コモンコンタクト部２０６ｃ、２０６ｄに内部配線２０７ｃに対するコンタクトホールをそれぞれ形成した後、ソース、ドレイン電極３１６、３１７や内部配線３１８の出発膜となる導電膜を形成する。 Then, after forming contact holes for the source and drain regions 310 and 311 in the first interlayer insulating film 315 and contact holes for the internal wiring 207c in the common contact portions 206c and 206d, the source and drain electrodes 316 and 317, A conductive film to be a starting film for the internal wiring 318 is formed.

ここでは、導電膜としてチタン（Ｔｉ）膜、アルミニウム（Ａｌ）膜、チタン（Ｔｉ）膜の多層膜を、スパッタリング法で形成した。なお、チタン（Ｔｉ）膜の膜厚はそれぞれ１００ｎｍとし、アルミニウム膜の膜厚は３００ｎｍとした。この多層膜をパターニングして、ソース電極３１６、ドレイン電極３１７及び内部配線３１８をそれぞれ形成した（図５（Ｅ））。 Here, a multilayer film of a titanium (Ti) film, an aluminum (Al) film, and a titanium (Ti) film was formed by a sputtering method as the conductive film. The thickness of the titanium (Ti) film was 100 nm, and the thickness of the aluminum film was 300 nm. The multilayer film was patterned to form a source electrode 316, a drain electrode 317, and an internal wiring 318 (FIG. 5E).

図５の内部配線３１８は図３の内部配線２０７ａ、２０７ｂに対応する。内部配線２０７ａ、２０７ｂはコモンコンタクト部２０６ｂ、２０６ｃにおいて、ゲイト電極３０８と同一工程を経て形成された内部配線２０７ｃに接続される。 The internal wiring 318 in FIG. 5 corresponds to the internal wirings 207a and 207b in FIG. Internal wiring 207a, 207b in the common contact portion 206 b, 206 c, are connected to the internal wiring 207c formed through the gate electrode 308 and the same process.

次に、第２の層間絶縁膜３１９として有機性樹脂膜を１〜２μｍの厚さに形成する。有機性樹脂膜としては、ポリイミド、ポリアミド、ポリイミドアミド、アクリル等を用いることができる。有機樹脂膜を用いるのは第２の層間絶縁膜３１９の表面を平坦にするためである。第２の層間絶縁膜３１９の表面を平坦にすることは、セルギャップを均一にするのに重要である。本実施例では、第２の層間絶縁膜３１９としてポリイミドを１μｍの膜厚に形成した。 Next, an organic resin film is formed to a thickness of 1 to 2 μm as the second interlayer insulating film 319. As the organic resin film, polyimide, polyamide, polyimide amide, acrylic, or the like can be used. The organic resin film is used in order to flatten the surface of the second interlayer insulating film 319. To flatten the surface of the second interlayer insulating film 319 is important in a uniform cell gap. In this embodiment, polyimide is formed to a thickness of 1 μm as the second interlayer insulating film 319.

次に、第２の層間絶縁膜３１９にドレイン電極３１７、内部配線３１８それぞれに対するコンタクトホール３２０、３２１を開口した。内部配線３１８のコンタクトホール３２１は、図２（Ａ）に示す開口部１１１のように、１．１ｍｍ×１．１ｍｍの矩形状の領域１１０内に、１００μｍ×１００μｍの矩形状の開口を、１００μｍの間隔で５×５のマトリクス状に形成した。またコンタクトホール３２１の他に、取出し端子２０５部において内部配線３１８（２０７ａ、２０７ｂ）とコモン端子２０５ａ、２０５ｂとを接続するためのコンタクトホールも形成される（図５（Ｆ））。 Next, contact holes 320 and 321 for the drain electrode 317 and the internal wiring 318 were opened in the second interlayer insulating film 319. The contact hole 321 of the internal wiring 318 has a rectangular opening of 100 μm × 100 μm in a rectangular region 110 of 1.1 mm × 1.1 mm, like the opening 111 shown in FIG. The matrix was formed in a 5 × 5 matrix at intervals of In addition to the contact hole 321, a contact hole for connecting the internal wiring 318 (207a, 207b) and the common terminal 205a, 205b in the extraction terminal 205 is also formed (FIG . 5F) .

後述するが、本実施例では、導電性スペーサの直径を３．５μｍとするため、開口部を１００μｍ×１００μｍとし、ここに配置される導電性スペーサが移動できるような十分なゆとりを与え、開口部で導電性スペーサが積み重ならないようにした。 As will be described later, in this embodiment, since the diameter of the conductive spacer is set to 3.5 μm, the opening is set to 100 μm × 100 μm, and a sufficient clearance is provided so that the conductive spacer disposed therein can move. The conductive spacers were not stacked on the part.

また、コモンコンタクト部において、第２の層間絶縁膜３１９が残存している領域の面積も導電性スペーサが移動できるような十分な広い領域としているため、この領域に導電性スペーサを確実に配置することができる。よって、この領域に配置された導電性スペーサにより、セルギャップの保持、電気的接続を確実に行うことができる。 In addition, since the area of the region where the second interlayer insulating film 319 remains in the common contact portion is also a sufficiently wide area so that the conductive spacer can move, the conductive spacer is surely disposed in this area. be able to. Therefore, the cell gap can be held and the electrical connection can be reliably performed by the conductive spacer disposed in this region.

そして、後に画素電極３２２、導電性パッド３２３となる金属薄膜を１００ｎｍ〜４００ｎｍの厚さに形成する。本実施例では金属薄膜として１ｗｔ％のチタンを添加したアルミニウム膜を３００ｎｍの厚さに、スパッタ法で形成した。しかる後、金属薄膜をパターニングして、画素電極３２２、導電性パッド３２３をそれぞれ形成した。導電性パッド３２３は、コンタクトホール３２１を覆うように１．１ｍｍ×１．１ｍｍの矩形状に形成した。更に、取出し端子２０５もパターニングされる。以上によりＴＦＴ基板が完成する（図５（Ｇ））。 Then, a metal thin film that will later become the pixel electrode 322 and the conductive pad 323 is formed to a thickness of 100 nm to 400 nm. In this embodiment, an aluminum film to which 1 wt% titanium is added as a metal thin film is formed to a thickness of 300 nm by sputtering. Thereafter, a metal thin film and Patani in g, to form the pixel electrode 322, the conductive pads 323, respectively. The conductive pad 323 was formed in a 1.1 mm × 1.1 mm rectangular shape so as to cover the contact hole 321. Further, the extraction terminal 205 is also patterned. Thus, the TFT substrate is completed (FIG. 5G).

他方、図６に示すように対向基板２５０においては、透光性基板２５１上にＩＴＯ膜でなる対向電極２５２を形成した。基板２５１には、ガラスや石英基板を用いることができる。 On the other hand, as shown in FIG. 6, in the counter substrate 250, the counter electrode 252 made of an ITO film was formed on the translucent substrate 251. As the substrate 251, a glass or a quartz substrate can be used.

次にＴＦＴ基板２００と対向基板２５０を貼り合わる。この貼り合わせ工程は公知のセル組み法に従って行えば良い。 Next, the TFT substrate 200 and the counter substrate 250 are bonded together. The bonding process may be carried out in accordance with a known cell Le set method.

まず、ＴＦＴ基板２００、対向基板２５０のいずれか一方の基板に、シール材を塗布する。本実施例では対向基板２５０側にシール材を塗布した。シール材には紫外線・熱硬化型の樹脂材料を用い、シールディスペンサー装置により、液晶注入口を残して、基板周囲にシール材を線状に塗布した。また、図４に示す領域２５４ａ〜２５４ｄには、球状の導電性スペーサ４０１を３．０ｗｔ％混入したシール材を塗布した。導電性スペーサが混入されたシール材は異方性導電膜として機能する。 First, a sealing material is applied to one of the TFT substrate 200 and the counter substrate 250. In this embodiment, a sealing material is applied to the counter substrate 250 side. An ultraviolet / thermosetting resin material was used as the sealing material, and the sealing material was applied linearly around the substrate with the seal dispenser device leaving the liquid crystal injection port. Further, a sealing material in which 3.0 wt% of the spherical conductive spacer 401 is applied is applied to the regions 254a to 254d shown in FIG. The sealing material mixed with the conductive spacer functions as an anisotropic conductive film.

導電性スペーサ４０１は樹脂材料でなる球体に導電膜が被覆されたものが一般的に使用されており、本実施例では金（Ａｕ）で被覆された、導電性スペーサ４０１を使用した。導電性スペーサ４０１の直径はセルギャップよりも０．２μｍ〜１μｍ程大きくすればよい。本実施例では、セルギャップを３μｍとするため、直径３．５μｍの導電性スペーサ４０１を使用した。シール材を塗布した後、仮焼成する。 As the conductive spacer 401, a sphere made of a resin material coated with a conductive film is generally used. In this embodiment, the conductive spacer 401 coated with gold (Au) is used. The diameter of the conductive spacer 401 may be about 0.2 μm to 1 μm larger than the cell gap. In this example, a conductive spacer 401 having a diameter of 3.5 μm was used in order to set the cell gap to 3 μm. After applying the sealing material, it is temporarily fired.

次に、ＴＦＴ基板２００、対向基板２５０のいずれか一方の基板に、セルギャップを維持するためのスペーサ４０２を散布する。本実施例では、スペーサ４０２を対向基板２５０側に散布した。また、セルギャップを３μｍとするため、スペーサ４０２は直径３μｍのポリマ系材料でなる球状のスペーサを用いた。 Next, spacers 402 for maintaining the cell gap are dispersed on one of the TFT substrate 200 and the counter substrate 250. In this embodiment, the spacers 402 are dispersed on the counter substrate 250 side. In order to make the cell gap 3 μm, a spherical spacer made of a polymer material having a diameter of 3 μm was used as the spacer 402.

次に、ＴＦＴ基板２００と対向基板２５０とを対向し、画素領域のセルギャップがスペーサ４０２の直径となるまでプレスした。プレスした状態で十数秒紫外線を照射してシール材を紫外硬化させ、セルギャップを固定し、しかる後加圧しながら加熱してシール材の接着強度を向上させる。 Next, the TFT substrate 200 and the counter substrate 250 were opposed to each other and pressed until the cell gap in the pixel region became the diameter of the spacer 402. In the pressed state, the sealing material is irradiated with ultraviolet rays for 10 seconds or more to cure the sealing material, fix the cell gap, and then heat while applying pressure to improve the adhesive strength of the sealing material.

そして、液晶を封入し、封入口を封止することでセル組工程が完了する。図６に示すように、対向基板２５０の対向電極２５２は導電性スペーサ４０１によりＴＦＴ基板２００の導電性パッド３２３に電気的に接続され、ＴＦＴ基板側において、導電性パッド３２３は内部配線３１８を介してコモン端子に接続されている。このような接続構造により、対向基板２５０側の対向電極２５２をＴＦＴ基板側の配線によって、外部の電源と接続することが可能になる。なお、図６のコモンコンタクト部の拡大図が図１に対応する。 And a cell assembly process is completed by enclosing a liquid crystal and sealing an enclosure port. As shown in FIG. 6, the counter electrode 252 of the counter substrate 250 is electrically connected to the conductive pad 323 of the TFT substrate 200 by the conductive spacer 401, and the conductive pad 323 is connected via the internal wiring 318 on the TFT substrate side. Connected to the common terminal. With such a connection structure, the counter electrode 252 on the counter substrate 250 side can be connected to an external power source by wiring on the TFT substrate side. An enlarged view of the common contact portion in FIG. 6 corresponds to FIG.

本実施例では、セルギャップを３μｍとするために、画素領域に散布されるスペーサ４０２の直径を３μｍとし、導電性スペーサ４０１の直径を３．５μｍとした。導電性スペーサの直径をスペーサ４０２の直径（セルギャップ）よりも大きくするのは、対向電極２５２と導電性パッド３２３の接続を確実にするためである。基板貼り合わせ工程のプレス工程において、導電性スペーサ４０１はセルギャップよりも直径が大きいため、押しつぶされる。押しつぶされることにより、対向電極２５２、導電性パッド３２３との接触面積が大きくなり、電気的な接続が確実になるとともに、セルギャップを画素領域と同じに維持することができる。 In this embodiment, in order to set the cell gap to 3 μm, the diameter of the spacer 402 dispersed in the pixel region is 3 μm, and the diameter of the conductive spacer 401 is 3.5 μm. The reason why the diameter of the conductive spacer is larger than the diameter (cell gap) of the spacer 402 is to ensure the connection between the counter electrode 252 and the conductive pad 323 . In the pressing step of the substrate bonding step, the conductive spacer 401 is crushed because it has a diameter larger than the cell gap. By being crushed, the contact area between the counter electrode 252 and the conductive pad 323 is increased, electrical connection is ensured, and the cell gap can be kept the same as the pixel region.

また、本実施例では、内部配線３１８をソース、ドレイン電極３１６、３１７の出発膜で構成したが、内部配線３１８は画素電極３２２よりも下層の配線であればよい。例えば、第２の層間絶縁膜３１９内にチタン等の導電膜でなるブラックマトリクスを形成した場合、この導電膜で内部配線３１８を形成することができる。 In this embodiment, the internal wiring 318 is formed by the starting films of the source and drain electrodes 316 and 317, but the internal wiring 318 may be a wiring below the pixel electrode 322. For example, when a black matrix made of a conductive film such as titanium is formed in the second interlayer insulating film 319, the internal wiring 318 can be formed using this conductive film.

また、本実施例ではセルギャップを均一にするため、その表面に画素電極３２２が形成される第２の層間絶縁膜３１９の表面が平坦であることが重要であると共に、内部配線３１８が形成される第１の層間絶縁膜３１５の表面の平坦性も重要になる。 In this embodiment, in order to make the cell gap uniform, it is important that the surface of the second interlayer insulating film 319 on which the pixel electrode 322 is formed is flat, and the internal wiring 318 is formed. The flatness of the surface of the first interlayer insulating film 315 is also important.

表面が平坦な層間絶縁膜を得る方法として、層間絶縁膜の厚膜化による方法、有機性樹脂膜を用いたレベリングによる方法、機械的な研磨による方法、エッチバック技術による方法などが挙げられる。本実施例では、第１の層間絶縁膜３１５の平坦化に厚膜化による方法を採用し、第２の層間絶縁膜３１９の平坦化に有機性樹脂膜を用いたレベリングによる方法を採用したが、他の手法を用いて平坦化しても良い。 Examples of a method for obtaining an interlayer insulating film having a flat surface include a method by increasing the thickness of the interlayer insulating film, a method by leveling using an organic resin film, a method by mechanical polishing, and a method by an etch back technique. In this embodiment , a method using a thick film is adopted for flattening the first interlayer insulating film 315, and a method using leveling using an organic resin film is adopted for flattening the second interlayer insulating film 319. Other methods may be used for planarization.

本実施例の液晶表示装置において、液晶層に二色性色素を分散させたり、ＴＦＴ基板、対向基板に配向膜を設けたり、対向基板にカラーフィルタを設けたりすることも可能である。その様な液晶層の種類、配向膜、カラーフィルタの有無等は、駆動方法、液晶の種類等により実施者が適宜決定すれば良い。 In the liquid crystal display device of the present embodiment, or by dispersing a dichroic dye in the liquid crystal layer, TFT substrate, may be provided an orientation film on the counter substrate, it is also possible to or providing the color filters on the counter substrate. Types of such liquid crystal layer, orientation film, presence or absence of the color filter is driving method, practitioner a liquid crystal type or the like may be appropriately determined.

例えば、対向基板２５０の側にカラーフィルタを設けた場合、カラーフィルタはコモンコンタクト部には形成されないので、対向基板において、画素領域とコモンコンタクト部に段差が生ずる。この段差を補正するため、導電性スペーサの直径をカラーフィルタの厚さ程度大きくする必要がある。 For example, when a color filter is provided on the counter substrate 250 side, the color filter is not formed in the common contact portion, so that a step is generated between the pixel region and the common contact portion in the counter substrate. In order to correct this step, it is necessary to increase the diameter of the conductive spacer by about the thickness of the color filter.

また、本実施例は反射型の液晶表示装置の例を示したが、透過型の液晶表示装置とすることもでき、この場合には、画素電極及び導電性パッドの出発膜を透光性を有するＩＴＯ膜等で形成すればよい。 Although this embodiment shows an example of a reflective liquid crystal display device can also be of a transmissive liquid crystal display device, in this case, the light-permeable a starting film of the pixel electrodes and the conductive pad What is necessary is just to form with the ITO film | membrane etc. which have.

本実施例では代表的なトップゲイト型薄膜トランジスタであるコプレナー型薄膜トランジスタを一例として記載したが、ボトムゲイト型薄膜トランジスタであっても構わない。また、薄膜トランジスタ以外にも、薄膜ダイオード、ＭＩＭ素子、バリスタ素子等を用いることができる。 In this embodiment, a coplanar thin film transistor which is a typical top gate thin film transistor is described as an example, but a bottom gate thin film transistor may be used. In addition to the thin film transistor, a thin film diode, an MIM element, a varistor element, or the like can be used.

本実施例は、実施例１のコモンコンタクト部の変形例である。図７は本実施例のアクティブマトリクス型表示装置の断面構成図である。図７において、ＴＦＴ基板の構成は図６と同じであり、符号の記載を一部省略した。また図７において図６と同一の符号は同一の部材を示す。また、図７に示すコモンコンタクト部の拡大図を図９に示す。 The present embodiment is a modification of the common contact portion of the first embodiment. FIG. 7 is a cross-sectional configuration diagram of the active matrix display device of this embodiment. In FIG. 7, the configuration of the TFT substrate is the same as that in FIG. In FIG. 7, the same reference numerals as those in FIG. 6 denote the same members. FIG. 9 shows an enlarged view of the common contact portion shown in FIG.

図６に示す実施例１において、対向電極２５２は透明導電膜であるＩＴＯ膜で構成されているため、対向電極２５２と導電性スペーサ４０１間の電気抵抗は、金属膜と比較して大きくなる。本実施例はこの電気抵抗を低減することを目的とする。 In Example 1 shown in FIG. 6, since the counter electrode 252 is made of an ITO film that is a transparent conductive film, the electrical resistance between the counter electrode 252 and the conductive spacer 401 is larger than that of the metal film. The present embodiment aims to reduce this electrical resistance.

このため、対向基板２５０側に金属膜を形成し、パターニングして、コモンコンタクト部２５４ａ〜２５４ｄに導電膜でなる接続パッド５０１をそれぞれ形成する。接続パッド５０１を形成することで、対向電極２５２と導電性スペーサ４０１間の抵抗値を下げることができる。だだし、接続パッド５０１を構成する導電膜は対向電極２５２に使用される導電膜よりも電気抵抗が低いことが重要である。 For this reason, a metal film is formed on the counter substrate 250 side and patterned to form connection pads 501 made of conductive films on the common contact portions 254a to 254d, respectively. By forming the connection pad 501, the resistance value between the counter electrode 252 and the conductive spacer 401 can be reduced. However, it is important that the conductive film forming the connection pad 501 has a lower electrical resistance than the conductive film used for the counter electrode 252.

また、対向基板側のブラックマトリクスをクロム等の導電膜で形成した場合には、接続パッド５０１をこの導電膜で形成することができ、導電膜をパターニングしてブラックマトリクスを形成する際に、接続パッド５０１を形成すればよい。 In addition, when the black matrix on the counter substrate side is formed of a conductive film such as chromium, the connection pad 501 can be formed of this conductive film, and when the black matrix is formed by patterning the conductive film, the connection pad 501 can be formed. A pad 501 may be formed.

本実施例は実施例２の変形例であり、図８は本実施例のアクティブマトリクス型表示装置の断面構成図である。図８において、ＴＦＴ基板の構成は図６と同じであり、符号の記載を一部省略した。なお、図８において図６と同一の符号は同一の部材を示す。また、図８のコモンコンタクト部の拡大図が図１０に対応する。 The present embodiment is a modification of the second embodiment, and FIG. 8 is a cross-sectional configuration diagram of the active matrix display device of the present embodiment. In FIG. 8, the configuration of the TFT substrate is the same as that in FIG. 6, and some of the reference numerals are omitted. In FIG. 8, the same reference numerals as those in FIG. 6 denote the same members. Moreover, the enlarged view of the common contact part of FIG. 8 corresponds to FIG.

実施例１においては、対向基板２５１、対向電極２５２双方とも透光性を有するため、基板を貼り合わせた状態で、対向基板２５０側からコモンコンタクト部に導電性スペーサ４０１の分布の様子を視認することができた。しかし、実施例２では金属膜でなる接続パッド５０１を形成したため、導電性スペーサ４０１の分布の様子を視認することができない。 In Example 1, since both the counter substrate 251 and the counter electrode 252 are translucent, the state of the distribution of the conductive spacer 401 is visually recognized from the counter substrate 250 side to the common contact portion in a state where the substrates are bonded together. I was able to. However, since the connection pad 501 made of a metal film is formed in the second embodiment, the state of distribution of the conductive spacer 401 cannot be visually recognized.

本実施例では、抵抗値を下げるための接続パッドを設けた状態で、導電性スペーサ４０１の分布の様子を視認することを可能することを目的とする。このため、接続パッド６０１に選択的に開口部を設け、この開口部を介して導電性スペーサ４０１が見えるようにした。 The object of the present embodiment is to make it possible to visually recognize the distribution of the conductive spacer 401 in a state where a connection pad for lowering the resistance value is provided. Therefore, an opening is selectively provided in the connection pad 601 so that the conductive spacer 401 can be seen through the opening.

図１１は、本実施例のコンタクト部の上面図であり、対向基板側から見た状態を示す。また、図１０は、図１１の点線で囲まれた領域６００のコモンコンタクト部の断面構成図に対応する。図１１に示すように導電性パッド６０１には開口部６０２が形成される。開口部６０２では対向基板２５１と対向電極２５２だけが存在し、双方とも透光性を有するため、開口部６０２から導電性スペーサ４０１の分布の様子を確認することが可能になる。 FIG. 11 is a top view of the contact portion of the present embodiment and shows a state viewed from the counter substrate side. 10 corresponds to a cross-sectional configuration diagram of a common contact portion in a region 600 surrounded by a dotted line in FIG. As shown in FIG. 11, an opening 602 is formed in the conductive pad 601. Since only the counter substrate 251 and the counter electrode 252 exist in the opening portion 602, and both have translucency, it is possible to check the distribution of the conductive spacer 401 from the opening portion 602.

開口部６０２はセルギャップを維持するため、導電性スペーサ４０１が対向電極と接しない箇所である、ＴＦＴ基板の第２の層間絶縁膜に開口されたコンタクトホール３２１に対峙する箇所に形成するとよい。更に、その面積を第２の層間絶縁膜の開口部よりも若干、数％〜３０％程度大きく形成すると良い。なお、開口部６０２の数や配置、形状等は図１１に限定されるものではなく、実施者が適宜に設定することができる。 In order to maintain the cell gap, the opening 602 is preferably formed at a position facing the contact hole 321 opened in the second interlayer insulating film of the TFT substrate, where the conductive spacer 401 is not in contact with the counter electrode. Further, the area is preferably slightly larger than the opening of the second interlayer insulating film by several% to 30%. Note that the number, arrangement, shape, and the like of the openings 602 are not limited to those in FIG. 11, and can be set as appropriate by the practitioner.

接続パッド６０１の開口部６０２を第２の層間絶縁膜の開口部よりも若干大きく形成するのは、電気的な接続に寄与している、第２の層間絶縁膜３１９上の導電性パッド３２３を視認できるようにするためである。 The reason why the opening 602 of the connection pad 601 is formed to be slightly larger than the opening of the second interlayer insulating film is that the conductive pad 323 on the second interlayer insulating film 319 that contributes to electrical connection is formed. This is to make it visible.

実施例２、３においては、コモンコンタクト部のセルギャップを均一にすることと、導電性スペーサ４０１と対向電極２５２の接続抵抗を下げることを同時に実現するための構成を示したが、導電性スペーサ４０１と対向電極２５２の抵抗値を下げることを主要な目的とする場合であれば、ＴＦＴ基板側のコモンコンタクト部の構造を図１３に示すような、従来のコモンコンタクト部の構成としてもよい。この場合、図１３のコモンコンタクト部１６において、基板２３と対向電極２４の間に、実施例２、３で示した接続パッド５０１、６０１を形成すればよい。 In Examples 2 and 3, but showing the arrangement for realizing the method comprising: a uniform cell gap of the common contact portion, to lower the connection resistance of the conductive spacer 401 and the counter electrode 252 at the same time, conductive spacer If the main purpose is to lower the resistance values of 401 and the counter electrode 252, the structure of the common contact portion on the TFT substrate side may be a conventional common contact portion as shown in FIG. In this case, the connection pads 501 and 601 shown in the second and third embodiments may be formed between the substrate 23 and the counter electrode 24 in the common contact portion 16 of FIG.

上述した実施例１〜３においては、本発明をアクティブマトリクス型液晶表示装置に応用した例を示したが、本発明のコンタクト構造は、対向する基板にそれぞれ形成された配線を導電性スペーサを介して電気的に接続するようなコンタクト構造を有する装置に応用可能であり、例えば、異なるシリコンウェハに形成されたＩＣ等を接続することも可能である。 In Examples 1 to 3 described above, the present invention showing an example of application to an active matrix type liquid crystal display device, the contact structure of the present invention, the conductive spacer wires which are formed on opposing substrates For example, it is possible to connect ICs or the like formed on different silicon wafers.

本実施形態のコモンコンタクト部の断面構成図。The cross-sectional block diagram of the common contact part of this embodiment. 本実施形態のコモンコンタクト部の上面図。The top view of the common contact part of this embodiment. 実施例１の液晶表示装置のＴＦＴ基板の上面図。3 is a top view of a TFT substrate of the liquid crystal display device of Example 1. FIG. 実施例１の液晶表示装置の対向基板の上面図。3 is a top view of a counter substrate of the liquid crystal display device according to Embodiment 1. FIG. 実施例１のＴＦＴ基板の作製工程を示す図。FIG. 5 shows a manufacturing process of the TFT substrate of Example 1; 実施例１の画素領域、コモンコンタクト部の断面構成図。FIG. 3 is a cross-sectional configuration diagram of a pixel region and a common contact portion according to the first embodiment. 実施例２の画素領域、コモンコンタクト部の断面構成図。FIG. 6 is a cross-sectional configuration diagram of a pixel region and a common contact portion in Example 2. 実施例３の画素領域、コモンコンタクト部の断面構成図。FIG. 6 is a cross-sectional configuration diagram of a pixel region and a common contact portion in Example 3. 実施例２のコモンコンタクト部の拡大構成図。FIG. 6 is an enlarged configuration diagram of a common contact portion according to the second embodiment. 実施例３のコモンコンタクト部の断面構成図である。FIG. 6 is a cross-sectional configuration diagram of a common contact portion according to a third embodiment. 実施例３のコンタクト部の上面図。FIG. 10 is a top view of a contact portion according to the third embodiment. 従来例のＴＦＴ基板の上面図。The top view of the TFT substrate of a prior art example. 従来例の画素領域、コモンコンタクト部の断面構成図。The cross-sectional block diagram of the pixel region of a prior art example, and a common contact part. 従来例のコモンコンタクト部の上面図。The top view of the common contact part of a prior art example.

Explanation of symbols

１０１第１の基板
１０２第２の基板
１０３第１の導電膜
１０４絶縁膜
１０５第２の導電膜
１０６第３の導電膜
１０７導電性スペーサ
２００ＴＦＴ基板
２０５取出し端子
２０６コモンコンタクト部
２０７内部配線
２５０対向基板
２５２対向電極
３１５第１の層間絶縁膜
３１８内部配線
３１９第２の層間絶縁膜
３２２画素電極
３２３導電性パッド
４０１導電性スペーサ
４０２スペーサ
５０１、６０１接続パッド 101 First substrate 102 Second substrate 103 First conductive film 104 Insulating film 105 Second conductive film 106 Third conductive film 107 Conductive spacer 200 TFT substrate 205 Extraction terminal 206 Common contact portion 207 Internal wiring 250 Opposing Substrate 252 Counter electrode 315 First interlayer insulating film 318 Internal wiring 319 Second interlayer insulating film 322 Pixel electrode 323 Conductive pad 401 Conductive spacer 402 Spacer 501, 601 Connection pad

Claims

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion ;
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion;
The wiring viewed contains the same conductive film as the gate electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion;
See containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion ;
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion;
The wiring viewed contains the same conductive film as the gate electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
A plurality of terminals provided on the substrate;
A common contact portion provided around the pixel region;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
At least one of the plurality of terminals is electrically connected to the common contact portion;
See containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion, have a said conductive film are electrically connected, and terminals which are not located at the very end,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
The wiring viewed contains the same conductive film as the gate electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
See containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion, have a said conductive film are electrically connected, and terminals which are not located at the very end,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
The wiring viewed contains the same conductive film as the gate electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, and the picture element regions that have a pixel electrode electrically connected to the thin film transistor and before Symbol TFT,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
Provided around the pixel region, and a wiring electrically connected to the common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
See containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third transparent conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A first common contact portion and a second common contact portion provided around the pixel region;
A plurality of terminals provided on the substrate;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The first common contact portion and the second common contact portion are each electrically connected to at least one of the plurality of terminals ,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A first common contact portion and a second common contact portion provided around the pixel region;
A plurality of terminals provided on the substrate;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The first wiring includes the same conductive film as the gate electrode of the thin film transistor,
The second wiring is seen containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
The first common contact portion and the second common contact portion are each electrically connected to at least one of the plurality of terminals ,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A first common contact portion and a second common contact portion provided around the pixel region;
A plurality of terminals provided on the substrate;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The first wiring and the second wiring include the same conductive film as the gate electrode of the thin film transistor,
The first common contact portion and the second common contact portion are each electrically connected to at least one of the plurality of terminals ,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A first common contact portion and a second common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The extraction terminal portion, have a said conductive film are electrically connected, and terminals which are not located at the very end,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A first common contact portion and a second common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
The first wiring includes the same conductive film as the gate electrode of the thin film transistor,
The second wiring is seen containing the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
An extraction terminal portion provided on the substrate and having a plurality of terminals;
A first common contact portion and a second common contact portion provided around the pixel region and electrically connected to the extraction terminal portion;
A first wiring provided along one side of the pixel region and electrically connected to the first common contact portion;
Provided along the other one side of the pixel region, and a electrically connected to the second wiring to said second common contact portion,
The extraction terminal portion has a terminal that is electrically connected to the conductive film and is not disposed at the end.
The first wiring and the second wiring, see contains the same conductive film as the gate electrode of the thin film transistor,
In the first common contact portion and the second common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A fourth conductive film is provided at a location of the counter substrate facing the first common contact portion and the second common contact portion, and an opening is provided at a location facing the opening of the fourth conductive film. A display device characterized by that.

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A common contact portion provided around the pixel region;
A wiring provided around three sides of the pixel region and electrically connected to the common contact portion ;
Provided in front Symbol substrate, a plurality of terminals electrically connected to the common contact portion,
I have a,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A common contact portion provided around the pixel region;
A wiring provided around three sides of the pixel region and electrically connected to the common contact portion ;
Provided in front Symbol substrate, a plurality of terminals electrically connected to the common contact portion,
Have,
The wiring viewed contains the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A common contact portion provided around the pixel region;
A wiring provided around three sides of the pixel region and electrically connected to the common contact portion ;
Provided in front Symbol substrate, a takeout lead terminal portion having a plurality of terminals,
Have
The takeout terminal unit may have a terminal to which the electrically connected to the common contact portion, and not arranged at the very end,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

A substrate,
Provided on the substrate, a rectangular pixel region and a thin film transistor and before Symbol pixel electrode electrically connected to the thin film transistor,
A common contact portion provided around the pixel region;
A wiring provided around three sides of the pixel region and electrically connected to the common contact portion ;
Provided in front Symbol substrate, a takeout lead terminal portion having a plurality of terminals,
Have
The extraction terminal portion has a terminal that is electrically connected to the common contact portion and is not disposed at the end.
The wiring viewed contains the same conductive film as the source electrode or the drain electrode of the thin film transistor,
In the common contact portion,
A first conductive film formed on the substrate;
An insulating film formed on the first conductive film;
An opening reaching the first conductive film formed in the insulating film;
A second conductive film formed on the insulating film and electrically connected to the first conductive film in the opening;
Conductive spacers are provided,
The conductive spacer is in contact with both the second conductive film and a third conductive film provided on a counter substrate facing the substrate on the insulating film,
A display device , wherein a fourth conductive film is provided at a position of the counter substrate facing the common contact portion, and an opening is provided at a position of the fourth conductive film facing the opening .

In any one of claims 4 to 6, 10 to 12, a display device, wherein the pre-Symbol third transparent conductive film is an ITO film.

In any one of claims 1 to 3, 7 to 9 and 13 to 22, wherein the third conductive film, the display characterized in that it is a transparent conductive film device.

In claim 24, a display device, wherein the pre-SL transparent conductive film is an ITO film.

26. The display device according to claim 1, wherein an area of the opening is larger than an area of the opening.

The display device according to any one of claims 1 to 26 is a liquid crystal display device.