JP4103977B2 - D / A conversion circuit, semiconductor device and electronic apparatus - Google Patents

Description

【００５８】
信号線ａ、ｂ、反転ａ、および反転ｂに入力されるデジタル信号によって一本の階調電圧線が選択され、ソース信号線に電圧が供給されることが表１に示されている。
【００５９】
本実施例では、上記のＤ／Ａ変換回路が、ソース信号線１本に対して１つ設けられている。ただし、ラッチ回路からＤ／Ａ変換回路へデジタル信号を供給する部分、および／あるいはＤ／Ａ変換回路からソース信号線に電圧を供給する部分に選択回路を設けることによって、Ｄ／Ａ変換回路の数を少なくすることも可能である。具体的な方法としては、特願平９−２８６０９８号に詳しく記載されている。
【００６０】
なお、本実施例では、駆動回路に備えられた複数のＤ／Ａ変換回路のうち１つについて説明した。実際は、複数のＤ／Ａ変換回路が存在し（本実施では１９２０個）、全てのＤ／Ａ変換回路が階調電圧線を共有している。
【００６１】
なお、本実施例のＤ／Ａ変換回路は、液晶表示装置の他の駆動回路、他の周辺装置と共に、石英基板やガラス基板などの絶縁基板上に一体形成され得る。また、本実施例のＤ／Ａ変換回路のそれぞれの階調電圧線に接続される２個のＰチャネル型ＴＦＴと２個のＮチャネル型ＴＦＴとは、同一半導体層上に形成されても良い。あるいは、２個の独立したＰチャネル型ＴＦＴと２個の独立したＮチャネル型ＴＦＴとがコンタクトを介して金属配線などによって接続されるようにしても良い。しかし、前者の場合の方がよりＤ／Ａ変換回路の小面積化が図れるので好ましい。
【００６２】
（実施例２）
【００６３】
本実施例では、本発明のＤ／Ａ変換回路の別の実施形態について説明する。なお、本実施例では２ビットのＤ／Ａ変換回路を例にとって説明するが、本発明はこれに限定されるわけではなく、２ビット以上の信号を扱うＤ／Ａ変換回路が実現される。
【００６４】
また、本実施例においても、画素数が、横１９２０×縦１０８０である液晶表示装置の駆動回路に備えられたＤ／Ａ変換回路を例にとって説明する。
【００６５】
図２を参照する。図２には本実施例の１つのＤ／Ａ変換回路が示されている。信号線２０１のａ、ｂ、反転ａ、および反転ｂには、ラッチ回路などからのデジタル信号が供給される。
【００６６】
図２に示されるように、本実施例のＤ／Ａ変換回路は８個のＮチャネル型ＴＦＴ（Tr3,1、Tr3,2、Tr2,3、Tr2,4、Tr1,1、Tr1,2、Tr0,3、およびTr0,4 ）と８個のＰチャネルＴＦＴ（Tr3,3、Tr3,4、Tr2,1、Tr2,2、Tr1,3、Tr1,4、Tr0,1、およびTr0,2）と４本の階調電圧線（Ｖ０〜Ｖ３）とを含んでいる。
【００６７】
また、上から３段目および４段目の電圧階調線を選択するための回路の位置が右にシフトしていることが理解される。さらに、４本の階調電圧線Ｖ３〜Ｖ０は、Ｖ３、Ｖ０、Ｖ１、Ｖ２といった順序で配置されているが、階調電圧線一段おきに、Ｎチャネル型ＴＦＴによって構成される回路とＰチャネル型ＴＦＴによって構成される回路との配置が逆になっていることが分かる。
【００６８】
４本の階調電圧線Ｖ３〜Ｖ０には、Ｖ３〜Ｖ０間に印加される電圧を抵抗分割することによって、所望の電圧が供給され、ソース信号線に供給される最も高い電圧がＶ３に印加され、最も低い電圧がＶ０に印加されるようになっている。
【００６９】
つまり、Ｖ０〜Ｖ３の電圧階調線には、Ｖ０〜Ｖ３に向かうに従ってより高い電圧が供給されている。ここで、最も低い階調電圧線Ｖ０を第１の階調電圧線とし、Ｖ１を第２の階調電圧線、Ｖ２を第３の階調電圧線、Ｖ３を第４の階調電圧線とすると、第４の階調電圧線Ｖ３と第１の階調電圧線Ｖ０とが隣接して（対になって）配置されており、かつそれぞれの電圧階調線に接続される２つのPチャネル型ＴＦＴから成る回路と、２つのＮチャネル型ＴＦＴから成る回路との配置が逆である。また、第２の電圧階調線Ｖ１と第３の電圧階調線Ｖ２とが隣接（対になって）して配置されており、かつそれぞれの電圧階調線に接続される２つのPチャネル型ＴＦＴから成る回路と、２つのＮチャネル型ＴＦＴから成る回路との配置が逆であることが分かる。
【００７０】
これらの電圧階調線の配列順序は、一見不規則に見えるが、ある規則に従っている。つまり、隣接している２つの電圧階調線が第何番と第何番であるかというところに注目すると、第４と第１（４＋１＝５）、第２と第３（２＋３＝５）と、両者の第何番という番号を加えると５になっている。この５という数字は、２²＋１（２は２ビットのＤ／Ａ変換回路であること）の意である。
【００７１】
ここで、ｎビットのＤ／Ａ変換回路を考えてみると、電圧階調線の数は２ⁿ本あり、最も低い電圧が供給される第１の電圧階調線を始めとして、最も高い電圧が供給される第２ⁿの電圧階調線が存在する。この場合、隣接する（対になる）２つの電圧階調線は、第ｘ（１≦ｘ≦２ⁿ；ｘは整数）の電圧階調線と第（２ⁿ ＋１−ｘ）の電圧階調線である。また、これらの隣接する（対になる）２つの電圧階調線は、接続されるｎ個のＰチャネル型ＴＦＴから成る回路とｎ個のＮチャネル型ＴＦＴから成る回路との配置が互いに逆になる。
【００７２】
また、４本の階調電圧線Ｖ３〜Ｖ０には、独立して所望の電圧が供給されるようにしても良い。ただし、この場合においても、ソース信号線に供給される最も高い電圧がＶ３に供給され、最も低い電圧がＶ０に供給されるようにする必要がある。
【００７３】
以下に本実施例のＤ／Ａ変換回路の回路構成の詳細について説明する。
【００７４】
階調電圧線Ｖ３に注目すると、２個のＮチャネル型ＴＦＴ（Tr3,1およびTr3,2）が直列に接続された回路と、２個のＰチャネル型ＴＦＴ（Tr3,3およびTr3,4）が直列に接続された回路とが接続され、前記２つの回路が接続された回路の両端が階調電圧線Ｖ３に接続されている構成をとる。前記２つの回路の接続部（Tr3,2とTr3,3との接続部）にソース信号線へつながる出力線２０３が接続されている。また、ラッチ回路等からの信号線ａ、ｂ、反転ａ、および反転ｂは、それぞれTr3,1、Tr3,2、Tr3,3、Tr3,4のゲイト電極に接続されている。これらの信号線ａ、ｂ、反転ａ、および反転ｂに供給されるデジタル信号によって、ＴＦＴTr3,1、Tr3,2、Tr3,3、Tr3,4のスイッチングが制御され、これら全てのＴＦＴがＯＮとなった時、階調電圧線Ｖ３に供給される電圧が出力線２０３に供給される。
【００７５】
次に、階調電圧線Ｖ０に注目すると、２個のＰチャネル型ＴＦＴ（Tr0,1およびTr0,2）が直列に接続された回路と、２個のＮチャネル型ＴＦＴ（Tr0,3およびTr0,4）が直列に接続された回路とが接続され、前記２つの回路が接続された回路の両端が階調電圧線Ｖ０に接続されている構成をとる。前記２つの回路の接続部（Tr0,2とTr0,3との接続部）に出力線２０３が接続されている。また、ラッチ回路等からの信号線ａ、ｂ、反転ａ、および反転ｂは、それぞれTr0,1、Tr0,2、Tr0,3、Tr0,4のゲイト電極に接続されている。これらの信号線ａ、ｂ、反転ａ、および反転ｂに供給されるデジタル信号によって、ＴＦＴTr0,1、Tr0,2、Tr0,3、Tr0,4のスイッチングが制御され、これら全てのＴＦＴがＯＮとなった時、階調電圧線Ｖ０に供給される電圧が出力線２０３に供給される。
【００７６】
次に、階調電圧線Ｖ１に注目すると、２個のＮチャネル型ＴＦＴ（Tr1,1およびTr1,2）が直列に接続された回路と、２個のＰチャネル型ＴＦＴ（Tr1,3およびTr1,4）が直列に接続された回路とが接続され、前記２つの回路が接続された回路の両端が階調電圧線Ｖ１に接続されている構成をとる。前記２つの回路の接続部（Tr1,2とTr1,3との接続部）に出力線２０３が接続されている。また、ラッチ回路等からの信号線ａ、ｂ、反転ａ、および反転ｂは、それぞれTr1,4、Tr1,1、Tr1,2、Tr1,3のゲイト電極に接続されている。これらの信号線ａ、ｂ、反転ａ、および反転ｂに供給されるデジタル信号によって、ＴＦＴTr1,4、Tr1,1、Tr1,2、Tr1,3のスイッチングが制御され、これら全てのＴＦＴがＯＮとなった時、階調電圧線Ｖ１に供給される電圧が出力線２０３に供給される。
【００７７】
次に、階調電圧線Ｖ２に注目すると、２個のＰチャネル型ＴＦＴ（Tr2,1およびTr2,2）が直列に接続された回路と、２個のＮチャネル型ＴＦＴ（Tr2,3およびTr2,4）が直列に接続された回路とが接続され、前記２つの回路が接続された回路の両端が階調電圧線Ｖ２に接続されている構成をとる。前記２つの回路の接続部（Tr2,2とTr2,3との接続部）に出力線２０３が接続されている。また、ラッチ回路等からの信号線ａ、ｂ、反転ａ、および反転ｂは、それぞれTr2,4、Tr2,1、Tr2,2、Tr2,3のゲイト電極に接続されている。これらの信号線ａ、ｂ、反転ａ、および反転ｂに供給されるデジタル信号によって、ＴＦＴTr2,4、Tr2,1、Tr2,2、Tr2,3のスイッチングが制御され、これら全てのＴＦＴがＯＮとなった時、階調電圧線Ｖ２に供給される電圧が出力線２０３に供給される。
【００７８】
以下の表２に、信号線ａ、ｂ、反転ａ、および反転ｂに供給されるデジタル信号によって選択される階調電圧線を示す。
【００７９】
【表２】

【００８０】
信号線ａ、ｂ、反転ａ、および反転ｂに入力されるデジタル信号によって一本の階調電圧線が選択され、ソース信号線に電圧が供給されることが表２に示されている。
【００８１】
また、上記のような回路構成をとることによって、階調電圧線Ｖ０からＶ１に信号線ａ、ｂ、反転ａ、および反転ｂの配線の引き回しを行なう際、１本の配線のみが他の配線と交差する以外は、他の配線の交差をなくすことができる。
【００８２】
ここで図３を参照する。図３において、３０１、３０２、および３０３は第１の配線（ゲイト電極配線）であり、３０４は第２の配線である。３０５および３０６第１の配線と第２の配線との接続（コンタクト）をとっている部分である。
【００８３】
図３に示すように、通常、配線が交差する場合は、交差する配線を絶縁膜を介して配線し、接続をとる部分にだけコンタクトホールを開孔し、その部分で接続をとる。この場合、コンタクトホールのずれを考慮して配線３０１の３０７で示される部分の面積を大きくしなければならない。また、配線３０１と配線３０３との短絡（ショート）、あるいは配線３０２と３０３との短絡を防ぐために、Ｘ₁、Ｘ₂で示されるようなマージンを十分にとらなくてはならない。従って、配線の交差の数が多くなるにつれて回路全体の面積が大きくなってしまう。
【００８４】
しかし、本実施例のＤ／Ａ変換回路は、交差する配線の数が少ないので、回路の面積を大幅に小さくすることができる。しかも、コンタクト不良などによる歩留まりの低下についても防ぐことができる。
【００８５】
本実施例では、上記のＤ／Ａ変換回路が、ソース信号線１本に対して１つ設けられている。ただし、ラッチ回路からＤ／Ａ変換回路へデジタル信号を供給する部分、および／あるいはＤ／Ａ変換回路からソース信号線に電圧を供給する部分に選択回路を設けることによって、Ｄ／Ａ変換回路の数を少なくすることも可能である。具体的な方法としては、特願平９−２８６０９８号に詳しく記載されている。
【００８６】
なお、本実施例のＤ／Ａ変換回路は、液晶表示装置の他の駆動回路、他の周辺装置と共に、石英基板やガラス基板などの絶縁基板上に一体形成され得る。また、本実施例のＤ／Ａ変換回路のそれぞれの階調電圧線に接続される２個のＰチャネル型ＴＦＴと２個のＮチャネル型ＴＦＴとは、同一半導体層上に形成されても良い。あるいは、２個の独立したＰチャネル型ＴＦＴと２個の独立したＮチャネル型ＴＦＴとがコンタクトを介して金属配線などによって接続されるようにしても良い。しかし、前者の場合の方がよりＤ／Ａ変換回路の小面積化が図れるので好ましい。
【００８７】
（実施例３）
【００８８】
本実施例では、実施例２で説明した本発明のＤ／Ａ変換回路において、４ビットの信号を扱うように具体化した場合について説明する。
【００８９】
図４を参照する。図４には、本実施例のＤ／Ａ変換回路が示されている。なお、本実施例においても、液晶表示装置に用いられる駆動回路の複数のＤ／Ａ変換回路のうち一つだけを例にとって説明する。
【００９０】
図４に示されるように、本実施例のＤ／A変換回路は、６４個のＮチャネル型ＴＦＴと６４個のＰチャネル型ＴＦＴと１６本の階調電圧線４０２（Ｖ０〜Ｖ１５）とを含んでいる。信号線４０１のａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄには、ラッチ回路などからのデジタル信号が供給される。
【００９１】
全ての電圧階調線４０２（Ｖ０〜Ｖ１５）のそれぞれには、４個のＰチャネル型ＴＦＴが直列に接続された回路と、４個のＮチャネル型ＴＦＴが直列に接続された回路と、が直列に接続された回路が並列に接続されている。また、上記２つの回路の接続部分は、ソース信号線につながる出力線４０３に接続されている。
【００９２】
本実施例のＤ／Ａ変換回路も、信号線ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄに供給されるデジタル信号によって階調電圧線Ｖ０〜Ｖ１５のうち、いずれか一つの階調電圧線が選択され、出力線４０３に選択された階調電圧が供給される。
【００９３】
以下の表３に、信号線ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄに入力されるデジタル信号によって選択される階調電圧線を示す。
【００９４】
【表３】

【００９５】
信号線ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄに入力されるデジタル信号によって一本の階調電圧線が選択され、ソース信号線に電圧が供給されることが示されている。
【００９６】
ここで、階調電圧線Ｖ０〜Ｖ１５が、実施例２で説明したある一定の規則に従って配置されていることを説明する。
【００９７】
例えば、第４の階調電圧線Ｖ３を例にとる。本実施例のＤ／Ａ変換回路は４ビットのＤ／Ａ変換回路であるので、第４の電圧階調線と隣接する（対になる）電圧階調線は、２⁴＋１−４＝１３となり、第１３の電圧階調線である。第１３の電圧階調線は、Ｖ１２であり、図４に示されるように本実施例のＤ／Ａ変換回路も実施例２で述べた規則に従って電圧階調線が配置されていることが分かる。
【００９８】
また、第４の電圧階調線Ｖ３と第１３の電圧階調線Ｖ１２とに接続されている４つのＰチャネル型ＴＦＴから成る回路と４つのＮチャネル型ＴＦＴから成る回路とは、それぞれ配置が逆になっていることも理解される。
【００９９】
本実施例のＤ／Ａ変換回路において、４０４で示される部分は、配線の交差が他の部分よりも多くなっている。これは、本発明を４ビットのＤ／Ａ変換回路に適応させる場合は１箇所このような交差する配線が多い部分が必要となる。
【０１００】
図５を参照する。図５（Ａ）には、本実施例のＤ／Ａ変換回路の一部の回路パターンが示されている。図５（Ｂ）には、本実施例のＤ／Ａ変換回路の一部が示されており、図５（Ａ）の回路パターンの等価回路である。図５（Ａ）において、５０１および５０２は半導体活性層である。５０３および５０４はゲイト電極配線であり、本実施例ではＡｌ（アルミニウム）が用いられている。５０５および５０６は第２配線であり、本実施例ではＡｌが用いられている。５０７は第３配線である。５０８は第２配線と半導体活性層との接続をとっている部分を示す。なお、図中で同じ模様の配線は、それぞれ同じ配線層にあるものとする。また、黒く塗りつぶしてある部分は、半導体活性層と配線、あるいは異なる層の配線の接続をとっている部分を示している。また、図中で破線によって示されている部分は、上部の配線によって隠れている下部の配線を示す。
【０１０１】
この第３配線は、液晶表示装置のアクティブマトリクス基板側のＢＭ（ブラックマスク）層を形成する時に同時に形成されても良い。その場合、用いられる材料（Ａｌ、Ｔｉ等）によってその線幅や膜厚を帰ることが望ましい。例えば、第３配線の材料にＴｉを用いた場合、ＴｉはＡｌと比較して抵抗率が高いので、線幅を太くしたり、膜厚を厚くしたりすることが望ましい。また、第３配線に、例えばＡｌとＴｉといったような２種類以上の金属の積層構造を用いても良い。
【０１０２】
本実施例では、上記のＤ／Ａ変換回路が、ソース信号線１本に対して１つ設けられている。ただし、ラッチ回路からＤ／Ａ変換回路へデジタル信号を供給する部分、および／あるいはＤ／Ａ変換回路からソース信号線に電圧を供給する部分に選択回路を設けることによって、Ｄ／Ａ変換回路の数を少なくすることも可能である。具体的な方法としては、特願平９−２８６０９８号に詳しく記載されている。
【０１０３】
なお、本実施例のＤ／Ａ変換回路は、液晶表示装置の他の駆動回路、他の周辺装置と共に、石英基板やガラス基板などの絶縁基板上に一体形成され得る。また、本実施例のＤ／Ａ変換回路のそれぞれの階調電圧線に接続される４個のＰチャネル型ＴＦＴと４個のＮチャネル型ＴＦＴとは、同一半導体層上に形成されているが、４個の独立したＰチャネル型ＴＦＴと４個の独立したＮチャネル型ＴＦＴとがコンタクトを介して金属配線などによって接続されるようにしても良い。しかし、前者の場合の方がよりＤ／Ａ変換回路の小面積化が図れるので好ましい。
【０１０４】
（実施例４）
【０１０５】
本実施例では、実施例３で説明した本発明の４ビットＤ／Ａ変換回路の別の実施形態について説明する。
【０１０６】
図６及び図１０を参照する。図６及び図１０には、本実施例の４ビットＤ／Ａ変換回路が示されている。本実施例のＤ／Ａ変換回路は、上記実施例３のＤ／Ａ変換回路と比較して、ラッチ回路などからのデジタル信号を供給する信号線６０１（ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄ）の順序が異なっている。
【０１０７】
本実施例のＤ／Ａ変換回路における階調電圧線の配置、ならびに４つのＰチャネル型ＴＦＴから成る回路および４つのＮチャネル型ＴＦＴから成る回路の配置も、実施例２で述べた規則に従っていることが理解される。
【０１０８】
以下の表４に、信号線ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄに入力されるデジタル信号によって選択される階調電圧線を示す。
【０１０９】
【表４】

【０１１０】
信号線ａ、ｂ、ｃ、ｄ、反転ａ、反転ｂ、反転ｃ、および反転ｄに入力されるデジタル信号によって一本の階調電圧線が選択され、ソース信号線に電圧が供給されることが示されている。
【０１１１】
本実施例のＤ／Ａ変換回路において、６０４で示される部分は、配線の交差が他の部分よりも多くなっている。これは、本発明を４ビットのＤ／Ａ変換回路に適応させる場合は１箇所このような交差する配線が多い部分が必要となる。
【０１１２】
本実施例では、上記のＤ／Ａ変換回路が、ソース信号線１本に対して１つ設けられている。ただし、ラッチ回路からＤ／Ａ変換回路へデジタル信号を供給する部分、および／あるいはＤ／Ａ変換回路からソース信号線に電圧を供給する部分に選択回路を設けることによって、Ｄ／Ａ変換回路の数を少なくすることも可能である。具体的な方法としては、特願平９−２８６０９８号に詳しく記載されている。
【０１１３】
なお、本実施例のＤ／Ａ変換回路は、液晶表示装置の他の駆動回路、他の周辺装置と共に、石英基板やガラス基板などの絶縁基板上に一体形成され得る。また、本実施例のＤ／Ａ変換回路のそれぞれの階調電圧線に接続される４個のＰチャネル型ＴＦＴと４個のＮチャネル型ＴＦＴとは、同一半導体層上に形成されているが、４個の独立したＰチャネル型ＴＦＴと４個の独立したＮチャネル型ＴＦＴとがコンタクトを介して金属配線などによって接続されるようにしても良い。しかし、前者の場合の方がよりＤ／Ａ変換回路の小面積化が図れるので好ましい。
【０１１４】
（実施例５）
【０１１５】
上記実施例では、本発明のＤ／Ａ変換回路を液晶表示装置の駆動回路に用いる例を説明した。この場合、液晶表示装置に用いられる表示方法としては、ネマチック液晶を用いたＴＮモードや電界制御複屈折を利用したモード、液晶と高分子との混合層、いわゆる高分子分散モードなどにも用いることができる。また、本発明のＤ／Ａ変換回路を、印加電圧に応答して光学的特性が変調され得るその他のいかなる表示媒体を備えた表示装置の駆動回路に用いてもよい。例えば、エレクトロルミネセンス素子などを用いた表示装置の駆動回路に用いても良い。
【０１１６】
（実施例６）
本実施例では、本発明を用いた様々な電子機器について説明する。なお、本実施例に挙げる電子機器とは、本発明のＤ/Ａ変換回路を搭載した製品と定義する。
【０１１７】
その様な電子機器としては、ビデオカメラ、スチルカメラ、プロジェクター、プロジェクションＴＶ、ヘッドマウントディスプレイ、カーナビゲーション、パーソナルコンピュータ（ノート型を含む）、携帯情報端末（モバイルコンピュータ、携帯電話等）などが挙げられる。それらの一例を図１１に示す。これらの電子機器には、上述の実施例１〜３の本発明のＤ/Ａ変換回路を用いた表示装置を用いることができる。
【０１１８】
図１１（Ａ）は携帯電話であり、本体２００１、音声出力部２００２、音声入力部２００３、表示装置２００４、操作スイッチ２００５、アンテナ２００６で構成される。本発明のＤ/Ａ変換回路は音声出力部２００２、音声入力部２００３、表示装置２００４等に適用することができる。
【０１１９】
図１１（Ｂ）はビデオカメラであり、本体２１０１、表示装置２１０２、音声入力部２１０３、操作スイッチ２１０４、バッテリー２１０５、受像部２１０６、で構成される。本発明のＤ/Ａ変換回路は表示装置２１０２、音声入力部２１０３、受像部２１０６に適用することができる。
【０１２０】
図１１（Ｃ）はモバイルコンピューター（モービルコンピューター）であり、本体２２０１、カメラ部２２０２、受像部２２０３、操作スイッチ２２０４、表示装置２２０５で構成される。本発明のＤ/Ａ変換回路は受像部２２０３、表示装置２２０５等に適用できる。
【０１２１】
図１１（Ｄ）はヘッドマウントディスプレイであり、本体２３０１、表示装置２３０２、バンド部２３０３で構成される。本発明のＤ/Ａ変換回路は表示装置２３０２に適用することができる。
【０１２２】
図１１（Ｅ）はリア型プロジェクターであり、本体２４０１、光源２４０２、表示装置２４０３、偏光ビームスプリッター２４０４、リフレクター２４０５、２４０６、スクリーン２４０７、で構成される。本発明のＤ/Ａ変換回路は表示装置２４０３に適用することができる。
【０１２３】
図１１（Ｆ）はフロンと型プロジェクターであり、本体２５０１、光源２５０２、表示装置２５０３、光学系２５０４、スクリーン２５０５で構成される。本発明のＤ/Ａ変換回路は表示装置２５０３に適用することができる。
【０１２４】
以上の様に、本発明のＤ/Ａ変換回路の適用範囲は極めて広く、あらゆる分野の電子機器に適用することが可能である。また、他にも電光掲示板、宣伝広告用ディスプレイなどにも活用することができる。
【０１２５】
【発明の効果】
本発明によると、配線の交差の少ないＤ／Ａ変換回路が実現できる。よって、大画面、高精細な半導体表示装置における、大きなビット数のデジタル信号を扱うＤ／Ａ変換回路でさえも、小面積で実現できる。また、本発明のＤ／Ａ変換回路はある一定の規則に従って設計され得るので、設計時間の大幅な節約にもつながる。
【図面の簡単な説明】
【図１】 本発明のＤ／Ａ変換回路のある実施形態を示す図である。
【図２】 本発明のＤ／Ａ変換回路の別の実施形態を示す図である。
【図３】 ２つ以上の配線の交差を示した図である。
【図４】 本発明のＤ／Ａ変換回路の別の実施形態を示す図である。
【図５】 本発明のＤ／Ａ変換回路の回路パターン図および等価回路図である。
【図６】 本発明のＤ／Ａ変換回路の別の実施形態を示す図である。
【図７】 液晶表示装置の概略構成図である。
【図８】 従来のＤ／Ａ変換回路の回路図である。
【図９】 ＮＡＮＤ回路の回路パターン図および等価回路図である。
【図１０】本発明のＤ／Ａ変換回路の別の実施形態を示す図である。
【図１１】本発明を用いた電子機器である。
【符号の説明】
１０１、２０１ アドレス線
１０２、２０２ 階調電圧線
１０３、２０３ 出力線[0001]
[Technical field to which the invention belongs]
[0002]
The present invention relates to a D / A conversion circuit that converts a digital signal into an analog signal. In particular, the present invention relates to a D / A conversion circuit used for a drive circuit of a semiconductor display device.
[0003]
[Prior art]
[0004]
Recently, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed on an inexpensive glass substrate, for example, a thin film transistor (TFT) has been rapidly developed. This is because the demand for active matrix semiconductor display devices (particularly active matrix liquid crystal display devices) has increased.
[0005]
In an active matrix liquid crystal display device, TFTs are arranged in several tens to several millions of pixel regions arranged in a matrix, and charges entering and exiting each pixel electrode are controlled by a switching function of the TFTs.
[0006]
Among them, as the display device becomes higher in definition and higher in image quality, a digital drive type active matrix liquid crystal display device capable of high-speed driving has been attracting attention.
[0007]
A conventional digital drive type active matrix liquid crystal display device is shown in FIG. As shown in FIG. 7, a conventional digital drive type active matrix liquid crystal display device includes a source signal line side shift register 701, an address line 702 of a digital decoder, a latch circuit 703 (LAT1), a latch circuit 704 (LAT2), and a latch. A pulse line 705, a D / A conversion circuit (digital / analog conversion circuit) 706, a source signal line 707, a gate signal line side shift register 708, a gate signal line (scanning line) 709, a pixel TFT 710, and the like. Here, a 2-bit digital drive type active matrix liquid crystal display device is taken as an example. Note that the latch circuits (LAT1 and LAT2) are shown with two latch circuits together for convenience.
[0008]
Digital gradation signals supplied to the address lines 1 and 2 of the digital decoder 702 are written into the LAT1 group by a timing signal from the source signal line side shift register.
[0009]
The time until the writing of the digital gradation signals to the LAT1 group is completed is called one line period. That is, the time from when the writing of the gradation signal from the digital decoder to the leftmost LAT1 is started until the time when the writing of the gradation signal from the digital decoder to the rightmost LAT1 is completed. The interval is one line period.
[0010]
After the writing of the grayscale signal to the LAT1 group is completed, the grayscale signal written to the latch 1 group is sent to the LAT2 group all together when the latch pulse flows through the latch pulse line in accordance with the operation timing of the shift register. And written.
[0011]
In the LAT1 group that has finished sending the gradation signal to the LAT2 group, the digital gradation signal supplied to the digital decoder is sequentially written again by the signal from the source signal line side shift register.
[0012]
During the second-order one-line period, four gradation voltages of the four gradation voltages are output by the D / A conversion circuit in accordance with the gradation signals sent to the LAT2 group at the start of the second-order one-line period. One of them is selected.
[0013]
The selected gradation voltage is supplied to the corresponding source signal line for one line period.
[0014]
By repeating the above-described operation, an image is provided to the entire pixel portion of the liquid crystal display device.
[0015]
[Problems to be solved by the invention]
[0016]
Here, a conventional D / A conversion circuit used in the drive circuit described above will be described. Please refer to FIG.
[0017]
FIG. 8 shows a D / A conversion circuit 706 of the above-described active matrix liquid crystal display device. As shown in FIG. 8, the D / A conversion circuit 706 includes four NAND circuits 802,1 to 4, four gradation voltage lines (V0 to V3) 803, and four P-channel TFTs 804,1 to 804. 4.
[0018]
The configuration is such that one of the four P-channel TFTs 804, 1 to 4 is selected in accordance with the signal supplied to the signal lines 801a and b of the LAT2 group and the inverted signals of a and b. Yes. Then, a voltage is applied to the source signal line 707 from the gradation voltage line connected to the selected TFT.
[0019]
FIG. 9 shows a circuit pattern diagram and a circuit diagram of the NAND circuit 802 of the D / A conversion circuit. In FIG. 9A, wirings with the same pattern indicate the same wiring layer. 903, 904, and 908 are gate electrode wiring layers, and 905 to 907 are second wiring layers formed through an insulating layer.
[0020]
Reference numeral 901 denotes a semiconductor active layer of a P-channel TFT, and reference numeral 902 denotes a semiconductor active layer of an N-channel TFT. Reference numerals 903 and 904 denote gate electrode wirings, which form Tr1 and Tr4, Tr2 and Tr3, respectively. An input signal Vin1 is input to 904, and an input signal Vin2 is input to 903. Reference numeral 905 denotes a wiring for supplying a voltage from Vdd, and is connected to the source regions of Tr1 and Tr2. 906 is connected to the drain regions of Tr1 and Tr2 and the drain region of Tr3, and supplies an output signal to 908Vout. Reference numeral 907 denotes a GND wiring, which is connected to the source region of Tr4. Note that the blacked portion 909 indicates a portion where the semiconductor active layer and the second wiring layer are connected, or a portion where the gate electrode wiring layer and the second wiring layer are connected. Show.
[0021]
FIG. 9B shows an equivalent circuit of the circuit pattern of the NAND circuit of the D / A conversion circuit shown in FIG.
[0022]
According to FIG. 9, in the NAND circuit, there are many portions (typically indicated by 910) that are connected to the semiconductor active layer or the gate electrode wiring layer (five locations). In these connection portions, the semiconductor active layer must be made larger than necessary in order to compensate for the deviation that occurs when the contact hole for making the above connection is opened. Therefore, there is a drawback that the area of the entire circuit becomes large.
[0023]
Four such NAND circuits are required in the above-described 2-bit D / A conversion circuit. Further, the entire drive circuit requires D / A conversion circuits as many as the number of source signal lines, and as a result, the ratio of the area of the D / A conversion circuit (NAND circuit) in the drive circuit has increased. This is one of the causes of hindering miniaturization of the semiconductor display device.
[0024]
In order to increase the definition of a semiconductor display device, it is necessary to increase the number of pixels, that is, increase the number of source signal line signal lines. However, as described above, one source signal line is provided for each source signal line. A D / A conversion circuit is necessary, and this is one of the causes of hindering high definition.
[0025]
Accordingly, the present invention has been made in view of the above-described problems, and provides a D / A conversion circuit having a small area.
[0026]
[Means for Solving the Problems]
[0027]
According to an embodiment of the invention,
2 corresponding to the input digital signal of n bits (n is an integer of 2 or more) ⁿ In the D / A conversion circuit in which one of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ A D / A conversion circuit for switching between the n P-channel TFTs and the n N-channel TFTs connected to each of the gradation voltage lines is provided. This achieves the above object.
[0028]
The n P-channel TFTs may be connected only by a semiconductor layer, and the n N-channel TFTs may be connected only by a semiconductor layer.
[0029]
The D / A conversion circuit may be formed on an insulating substrate.
[0030]
Also, according to an embodiment of the present invention,
2 corresponding to the input digital signal of n bits (n is an integer of 2 or more) ⁿ In the D / A conversion circuit in which one of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ A gate electrode of the n P-channel TFTs connected to each of the grayscale voltage lines and a D / A conversion circuit connected to the gate electrode of the n N-channel TFTs are provided. The This achieves the above object.
[0031]
The n P-channel TFTs may be connected only by a semiconductor layer, and the n N-channel TFTs may be connected only by a semiconductor layer.
[0032]
The D / A conversion circuit may be formed on an insulating substrate.
[0033]
Also, according to an embodiment of the present invention,
2 corresponding to the input digital signal of n bits (n is an integer of 2 or more) ⁿ In the D / A conversion circuit in which one of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
2 above ⁿ The gray scale voltage lines are first to second. ⁿ The higher voltage is supplied toward the grayscale voltage line, and the xth (1 ≦ x ≦ 2) is supplied. ⁿ ; X is an integer) gradation voltage line and the second (2 ⁿ The (+ 1-x) -th gradation voltage line is adjacent in a pair, and the arrangement of the first circuit and the second circuit is opposite;
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ A gate electrode of the n P-channel transistors connected to each of the grayscale voltage lines and a D / A converter circuit connected to the gate electrodes of the n N-channel transistors are provided. The This achieves the above object.
[0034]
The n P-channel TFTs may be connected only by a semiconductor layer, and the n N-channel TFTs may be connected only by a semiconductor layer.
[0035]
The D / A conversion circuit may be formed on an insulating substrate.
[0036]
Also, according to an embodiment of the present invention,
A plurality of pixel TFTs;
A semiconductor device having a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of pixel TFTs;
The source signal line side drive circuit has a D / A conversion circuit,
The D / A conversion circuit 2 corresponds to the input n-bit digital signal. ⁿ One of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ There is provided a semiconductor device for switching between the n P-channel TFTs and the n N-channel TFTs connected to each of the gradation voltage lines. This achieves the above object.
[0037]
Also, according to an embodiment of the present invention,
A plurality of pixel TFTs;
A semiconductor device having a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of pixel TFTs;
The source signal line side drive circuit has a D / A conversion circuit,
The D / A conversion circuit 2 corresponds to the input n-bit digital signal. ⁿ One of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ There is provided a semiconductor device connected to the gate electrode of the n P-channel TFTs and the gate electrode of the n N-channel TFTs connected to each of the gradation voltage lines. This achieves the above object.
[0038]
Also, according to an embodiment of the present invention,
A plurality of pixel TFTs;
A semiconductor device having a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of pixel TFTs;
The source signal line side drive circuit has a D / A conversion circuit,
The D / A conversion circuit corresponds to the n-bit digital signal inputted to the D / A conversion circuit, and 2 ⁿ One of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 corresponding to the input digital signal of n bits (n is an integer of 2 or more) ⁿ In the D / A conversion circuit in which one of the gradation voltage lines is selected, and the gradation voltage is supplied from the selected gradation voltage line to the output line,
2 above ⁿ Each of the grayscale voltage lines includes a first circuit in which n P-channel TFTs are connected in series, and a second circuit in which n N-channel TFTs are connected in series. The circuit connected in series is connected in parallel,
2 above ⁿ The gray scale voltage lines are first to second. ⁿ The higher voltage is supplied toward the grayscale voltage line, and the xth (1 ≦ x ≦ 2) is supplied. ⁿ ; X is an integer) gradation voltage line and the second (2 ⁿ The (+ 1-x) -th gradation voltage line is adjacent in a pair, and the arrangement of the first circuit and the second circuit is opposite;
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is the 2 ⁿ There is provided a semiconductor device connected to the gate electrodes of the n P-channel transistors and the gate electrodes of the n N-channel transistors connected to each of the gradation voltage lines. This achieves the above object.
[0039]
The BM layer of the semiconductor device may be used as a third wiring of the source signal line side driving circuit or the gate signal line side driving circuit.
[0040]
For the BM layer of the semiconductor device, an Al film or a laminated film of Al and Ti may be used.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
[0042]
The D / A conversion circuit of the present invention is a resistance voltage dividing type D / A conversion circuit capable of converting an n-bit (n>2; n is a natural number) digital signal into an analog signal. The D / A conversion circuit according to the present invention has 2 bits by an n-bit digital signal supplied from a digital decoder. ⁿ One of the voltage lines is selected and the voltage is supplied to a specific signal line.
[0043]
In each voltage line, a circuit in which n N-channel TFTs are connected in series and a circuit in which n P-channel TFTs are connected in series are connected in parallel. It is connected. The gate electrode of each TFT constituting each circuit is connected to an address line from the digital decoder (or a line for supplying an inverted signal thereof), and the switching of each TFT is controlled by the digital signal supplied to the address line. Is done. A connection portion between a circuit in which n N-channel TFTs are connected in series and a circuit in which n P-channel TFTs are connected in series is connected to a source signal line.
[0044]
Details of the D / A conversion circuit of the present invention will be described with the following embodiments. However, the D / A conversion circuit of the present invention is not limited to the following embodiments.
[0045]
【Example】
[0046]
(Example 1)
[0047]
In this example, an embodiment of the D / A conversion circuit of the present invention will be described. In this embodiment, a 2-bit D / A conversion circuit will be described as an example. However, the present invention is not limited to this, and a D / A conversion circuit that handles signals of 2 bits or more is realized.
[0048]
In this embodiment, a D / A conversion circuit provided in a driving circuit of a liquid crystal display device having a pixel number of 1920 × 1080 is described as an example. Note that the driving circuit of the liquid crystal display device described in this embodiment includes one D / A conversion circuit per source signal line. In other words, the driving circuit of the liquid crystal display device described in this embodiment includes 1920 D / A conversion circuits.
[0049]
Please refer to FIG. FIG. 1 shows one D / A conversion circuit of this embodiment. A digital signal from a latch circuit or the like is supplied to the signal lines a, b, inversion a, and inversion b.
[0050]
As shown in FIG. 1, the D / A converter circuit of this embodiment has eight N-channel TFTs (Tr3,1, Tr3,2, Tr2,1, Tr2,2, Tr1,1, Tr1,2, Tr0,1 and Tr0,2) and eight P-channel TFTs (Tr3,3, Tr3,4, Tr2,3, Tr2,4, Tr1,3, Tr1,4, Tr0,3, and Tr0,4) And four gradation voltage lines (V0 to V3). A desired voltage is supplied to the four gradation voltage lines V3 to V0 by dividing the voltage applied between V3 and V0, and the highest voltage supplied to the output line is applied to V3. The lowest voltage is applied to V0.
[0051]
In addition, voltages may be independently supplied to the four gradation voltage lines V3 to V0. However, even in this case, it is necessary that the highest voltage supplied to the output line is applied to V3 and the lowest voltage is applied to V0.
[0052]
Focusing on the gradation voltage line V3, a circuit in which two N-channel TFTs (Tr3,1 and Tr3,2) are connected in series and two P-channel TFTs (Tr3,3 and Tr3,4) Are connected in series, and both ends of the circuit to which the two circuits are connected are connected to the gradation voltage line V3. Further, signal lines a, b, inversion a, and inversion b from the latch circuit and the like are connected to gate electrodes of Tr3, 1, Tr3, 2, Tr3, 3, Tr3,4, respectively. Switching of the TFTs Tr3, 1, Tr3, 2, Tr3, 3, Tr3,4 is controlled by digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. When this happens, the voltage supplied to the gradation voltage line V3 is supplied to the output line 103 connected to the source signal line.
[0053]
Next, paying attention to the gradation voltage line V2, a circuit in which two N-channel TFTs (Tr2,1 and Tr2,2) are connected in series, and two P-channel TFTs (Tr2,3 and Tr2). , 4) are connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V2. Further, the signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to the gate electrodes of Tr2,1, Tr2,4, Tr2,3, Tr2,2, respectively. Switching of TFTs Tr2,1, Tr2,4, Tr2,3, Tr2,2 is controlled by digital signals supplied to signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. At this time, the voltage supplied to the gradation voltage line V2 is supplied to the output line 103 connected to the source signal line.
[0054]
Next, paying attention to the gradation voltage line V1, a circuit in which two N-channel TFTs (Tr1,1 and Tr1,2) are connected in series, and two P-channel TFTs (Tr1,3 and Tr1) , 4) are connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V1. Further, the signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to the gate electrodes of Tr1,3, Tr1,2, Tr1,1, Tr1,4, respectively. Switching of the TFTs Tr1,3, Tr1,2, Tr1,1, Tr1,4 is controlled by the digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. At this time, the voltage supplied to the gradation voltage line V1 is supplied to the output line 103 connected to the source signal line.
[0055]
Further, paying attention to the gradation voltage line V0, a circuit in which two N-channel TFTs (Tr0,1 and Tr0,2) are connected in series, and two P-channel TFTs (Tr0,3 and Tr0, 4) is connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V0. Further, the signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to the gate electrodes of Tr0, 3, Tr0, 4, Tr0, 1, Tr0, 2, respectively. The switching of the TFTs Tr0,3, Tr0,4, Tr0,1, Tr0,2 is controlled by the digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. At this time, the voltage supplied to the gradation voltage line V 0 is supplied to the output line connected to the source signal line 103.
[0056]
Table 1 below shows the gradation voltage lines selected by the digital signals supplied to the signal lines a, b, inversion a, and inversion b.
[0057]
[Table 1]

[0058]
Table 1 shows that one gradation voltage line is selected by a digital signal input to the signal lines a, b, inversion a, and inversion b, and a voltage is supplied to the source signal line.
[0059]
In this embodiment, one D / A conversion circuit is provided for one source signal line. However, by providing a selection circuit in a portion that supplies a digital signal from the latch circuit to the D / A conversion circuit and / or a portion that supplies a voltage from the D / A conversion circuit to the source signal line, the D / A conversion circuit It is also possible to reduce the number. A specific method is described in detail in Japanese Patent Application No. 9-286098.
[0060]
In this embodiment, one of the plurality of D / A conversion circuits provided in the drive circuit has been described. Actually, there are a plurality of D / A conversion circuits (1920 in this embodiment), and all the D / A conversion circuits share the gradation voltage line.
[0061]
The D / A conversion circuit of this embodiment can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits of the liquid crystal display device and other peripheral devices. Further, the two P-channel TFTs and the two N-channel TFTs connected to the respective gradation voltage lines of the D / A conversion circuit of this embodiment may be formed on the same semiconductor layer. . Alternatively, two independent P-channel TFTs and two independent N-channel TFTs may be connected by metal wiring or the like through contacts. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.
[0062]
(Example 2)
[0063]
In this example, another embodiment of the D / A conversion circuit of the present invention will be described. In this embodiment, a 2-bit D / A conversion circuit will be described as an example. However, the present invention is not limited to this, and a D / A conversion circuit that handles signals of 2 bits or more is realized.
[0064]
Also in this embodiment, a D / A conversion circuit provided in a driving circuit of a liquid crystal display device having a number of pixels of 1920 × 1080 is described as an example.
[0065]
Please refer to FIG. FIG. 2 shows one D / A conversion circuit of this embodiment. A digital signal from a latch circuit or the like is supplied to a, b, inversion a, and inversion b of the signal line 201.
[0066]
As shown in FIG. 2, the D / A converter circuit of this embodiment has eight N-channel TFTs (Tr3,1, Tr3,2, Tr2,3, Tr2,4, Tr1,1, Tr1,2, Tr0,3, and Tr0,4) and eight P-channel TFTs (Tr3,3, Tr3,4, Tr2,1, Tr2,2, Tr1,3, Tr1,4, Tr0,1, and Tr0,2) And four gradation voltage lines (V0 to V3).
[0067]
It is also understood that the position of the circuit for selecting the third and fourth voltage gradation lines from the top is shifted to the right. Further, the four gradation voltage lines V3 to V0 are arranged in the order of V3, V0, V1, and V2, but a circuit constituted by an N-channel TFT and a P channel are provided every other gradation voltage line. It can be seen that the arrangement with the circuit constituted by the type TFT is reversed.
[0068]
A desired voltage is supplied to the four gradation voltage lines V3 to V0 by dividing the voltage applied between V3 and V0, and the highest voltage supplied to the source signal line is applied to V3. The lowest voltage is applied to V0.
[0069]
That is, a higher voltage is supplied to the voltage gradation lines V0 to V3 toward V0 to V3. Here, the lowest gradation voltage line V0 is the first gradation voltage line, V1 is the second gradation voltage line, V2 is the third gradation voltage line, and V3 is the fourth gradation voltage line. Then, the fourth gradation voltage line V3 and the first gradation voltage line V0 are arranged adjacent to each other (in pairs), and two P channels connected to the respective voltage gradation lines. The arrangement of the circuit composed of the type TFT and the circuit composed of the two N-channel type TFTs is reversed. In addition, the second voltage gradation line V1 and the third voltage gradation line V2 are arranged adjacent to each other (in pairs), and two P channels connected to the respective voltage gradation lines It can be seen that the arrangement of the circuit composed of the TFTs and the circuit composed of the two N-channel TFTs is reversed.
[0070]
The arrangement order of these voltage gradation lines looks irregular, but follows a certain rule. That is, paying attention to what number and what number the two adjacent voltage gradation lines are, the fourth and first (4 + 1 = 5), the second and third (2 + 3 = 5). And if you add the number of both numbers, it is 5. The number 5 is 2 ² +1 (2 is a 2-bit D / A conversion circuit).
[0071]
Here, when considering an n-bit D / A conversion circuit, the number of voltage gradation lines is 2. ⁿ There is a book, the first voltage gradation line to which the lowest voltage is supplied, and the second to which the highest voltage is supplied. ⁿ Voltage gradation lines exist. In this case, two voltage gradation lines adjacent to each other (a pair) are represented by the xth (1 ≦ x ≦ 2). ⁿ X is an integer) voltage gradation line and the second (2 ⁿ + 1−x) voltage gradation line. Further, these two adjacent (paired) voltage gradation lines are arranged so that the arrangement of the circuit composed of n P-channel TFTs and the circuit composed of n N-channel TFTs is reversed. Become.
[0072]
Further, a desired voltage may be independently supplied to the four gradation voltage lines V3 to V0. However, even in this case, it is necessary to supply the highest voltage supplied to the source signal line to V3 and supply the lowest voltage to V0.
[0073]
Details of the circuit configuration of the D / A conversion circuit of this embodiment will be described below.
[0074]
Focusing on the gradation voltage line V3, a circuit in which two N-channel TFTs (Tr3,1 and Tr3,2) are connected in series and two P-channel TFTs (Tr3,3 and Tr3,4) Are connected in series, and both ends of the circuit to which the two circuits are connected are connected to the gradation voltage line V3. An output line 203 connected to the source signal line is connected to a connection portion (a connection portion between Tr3,2 and Tr3,3) of the two circuits. Further, signal lines a, b, inversion a, and inversion b from the latch circuit and the like are connected to gate electrodes of Tr3, 1, Tr3, 2, Tr3, 3, Tr3,4, respectively. Switching of the TFTs Tr3, 1, Tr3, 2, Tr3, 3, Tr3,4 is controlled by digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. When this happens, the voltage supplied to the gradation voltage line V 3 is supplied to the output line 203.
[0075]
Next, paying attention to the gradation voltage line V0, a circuit in which two P-channel TFTs (Tr0,1 and Tr0,2) are connected in series and two N-channel TFTs (Tr0,3 and Tr0). , 4) are connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V0. An output line 203 is connected to a connection portion (a connection portion between Tr0,2 and Tr0,3) of the two circuits. Further, signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to gate electrodes of Tr0, 1, Tr0, 2, Tr0, 3, Tr0, 4, respectively. Switching of the TFTs Tr0, 1, Tr0, 2, Tr0, 3, Tr0, 4 is controlled by digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. When this happens, the voltage supplied to the gradation voltage line V 0 is supplied to the output line 203.
[0076]
Next, paying attention to the gradation voltage line V1, a circuit in which two N-channel TFTs (Tr1,1 and Tr1,2) are connected in series, and two P-channel TFTs (Tr1,3 and Tr1) , 4) are connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V1. An output line 203 is connected to a connection portion (a connection portion between Tr1,2 and Tr1,3) of the two circuits. Further, the signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to the gate electrodes of Tr1, 4, Tr1, 1, Tr1, 2, Tr1, 3, respectively. Switching of the TFTs Tr1,4, Tr1,1, Tr1,2, Tr1,3 is controlled by digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. When this happens, the voltage supplied to the gradation voltage line V 1 is supplied to the output line 203.
[0077]
Next, paying attention to the gradation voltage line V2, a circuit in which two P-channel TFTs (Tr2,1 and Tr2,2) are connected in series and two N-channel TFTs (Tr2,3 and Tr2). , 4) are connected to a circuit connected in series, and both ends of the circuit connected to the two circuits are connected to the gradation voltage line V2. An output line 203 is connected to a connection portion (a connection portion between Tr2,2 and Tr2,3) of the two circuits. Further, the signal lines a, b, inversion a, and inversion b from the latch circuit or the like are connected to gate electrodes of Tr2, 4, Tr2, 1, Tr2, 2, Tr2, 3, respectively. Switching of the TFTs Tr2,4, Tr2,1, Tr2,2, Tr2,3 is controlled by digital signals supplied to the signal lines a, b, inversion a, and inversion b, and all these TFTs are turned on. When this happens, the voltage supplied to the gradation voltage line V 2 is supplied to the output line 203.
[0078]
Table 2 below shows the gradation voltage lines selected by the digital signals supplied to the signal lines a, b, inversion a, and inversion b.
[0079]
[Table 2]

[0080]
Table 2 shows that one gradation voltage line is selected by a digital signal input to the signal lines a, b, inversion a, and inversion b, and a voltage is supplied to the source signal line.
[0081]
Further, by adopting the circuit configuration as described above, when wiring the signal lines a, b, inversion a, and inversion b from the gradation voltage lines V0 to V1, only one wiring is connected to the other wiring. Except for crossing, it is possible to eliminate crossing of other wirings.
[0082]
Reference is now made to FIG. In FIG. 3, 301, 302, and 303 are first wirings (gate electrode wirings), and 304 is a second wiring. 305 and 306 are portions where the first wiring and the second wiring are connected (contacted).
[0083]
As shown in FIG. 3, normally, when wiring intersects, the intersecting wiring is wired through an insulating film, a contact hole is opened only at a portion to be connected, and connection is established at that portion. In this case, it is necessary to increase the area of the portion indicated by 307 of the wiring 301 in consideration of the displacement of the contact hole. In order to prevent a short circuit between the wirings 301 and 303 or a short circuit between the wirings 302 and 303, X ₁ , X ₂ A sufficient margin as shown in (1) must be taken. Therefore, the area of the entire circuit increases as the number of wiring intersections increases.
[0084]
However, since the D / A conversion circuit of this embodiment has a small number of intersecting wires, the circuit area can be greatly reduced. In addition, it is possible to prevent a decrease in yield due to contact failure.
[0085]
In this embodiment, one D / A conversion circuit is provided for one source signal line. However, by providing a selection circuit in a portion that supplies a digital signal from the latch circuit to the D / A conversion circuit and / or a portion that supplies a voltage from the D / A conversion circuit to the source signal line, the D / A conversion circuit It is also possible to reduce the number. A specific method is described in detail in Japanese Patent Application No. 9-286098.
[0086]
The D / A conversion circuit of this embodiment can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits of the liquid crystal display device and other peripheral devices. Further, the two P-channel TFTs and the two N-channel TFTs connected to the respective gradation voltage lines of the D / A conversion circuit of this embodiment may be formed on the same semiconductor layer. . Alternatively, two independent P-channel TFTs and two independent N-channel TFTs may be connected by metal wiring or the like through contacts. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.
[0087]
(Example 3)
[0088]
In this embodiment, a case where the D / A conversion circuit of the present invention described in Embodiment 2 is embodied so as to handle a 4-bit signal will be described.
[0089]
Please refer to FIG. FIG. 4 shows the D / A conversion circuit of this embodiment. In the present embodiment, only one of the plurality of D / A conversion circuits of the drive circuit used in the liquid crystal display device will be described as an example.
[0090]
As shown in FIG. 4, the D / A conversion circuit of this embodiment includes 64 N-channel TFTs, 64 P-channel TFTs, and 16 gradation voltage lines 402 (V0 to V15). Contains. A digital signal from a latch circuit or the like is supplied to a, b, c, d, inversion a, inversion b, inversion c, and inversion d of the signal line 401.
[0091]
Each of the voltage gradation lines 402 (V0 to V15) includes a circuit in which four P-channel TFTs are connected in series and a circuit in which four N-channel TFTs are connected in series. Circuits connected in series are connected in parallel. Further, the connection portion of the two circuits is connected to an output line 403 connected to the source signal line.
[0092]
The D / A converter circuit of this embodiment also includes the gradation voltage lines V0 to V15 by digital signals supplied to the signal lines a, b, c, d, inverted a, inverted b, inverted c, and inverted d. Any one of the gradation voltage lines is selected, and the selected gradation voltage is supplied to the output line 403.
[0093]
Table 3 below shows gradation voltage lines selected by digital signals input to the signal lines a, b, c, d, inversion a, inversion b, inversion c, and inversion d.
[0094]
[Table 3]

[0095]
One gradation voltage line is selected by a digital signal input to the signal lines a, b, c, d, inversion a, inversion b, inversion c, and inversion d, and a voltage is supplied to the source signal line. It is shown.
[0096]
Here, it will be described that the gradation voltage lines V0 to V15 are arranged according to a certain rule described in the second embodiment.
[0097]
For example, the fourth gradation voltage line V3 is taken as an example. Since the D / A conversion circuit of this embodiment is a 4-bit D / A conversion circuit, the voltage gradation line adjacent to (pairing with) the fourth voltage gradation line is 2 ^Four + 1−4 = 13, which is the thirteenth voltage gradation line. The thirteenth voltage gradation line is V12, and it can be seen that the voltage gradation lines are also arranged according to the rules described in the second embodiment in the D / A conversion circuit of this embodiment as shown in FIG. .
[0098]
Further, a circuit composed of four P-channel TFTs and a circuit composed of four N-channel TFTs connected to the fourth voltage gradation line V3 and the thirteenth voltage gradation line V12 are arranged in each case. It is understood that the reverse is also true.
[0099]
In the D / A conversion circuit of this embodiment, the portion indicated by 404 has more wiring intersections than the other portions. This is because, when the present invention is applied to a 4-bit D / A conversion circuit, a portion having such many intersecting wires is required.
[0100]
Please refer to FIG. FIG. 5A shows a partial circuit pattern of the D / A conversion circuit of this embodiment. FIG. 5B shows a part of the D / A conversion circuit of this embodiment, which is an equivalent circuit of the circuit pattern of FIG. In FIG. 5A, reference numerals 501 and 502 denote semiconductor active layers. Reference numerals 503 and 504 denote gate electrode wirings, and Al (aluminum) is used in this embodiment. Reference numerals 505 and 506 denote second wirings, and Al is used in this embodiment. Reference numeral 507 denotes a third wiring. Reference numeral 508 denotes a portion where the second wiring and the semiconductor active layer are connected. In the figure, wirings having the same pattern are assumed to be in the same wiring layer. Also, the blacked out portion shows a portion where the semiconductor active layer and the wiring or the wiring of a different layer are connected. Moreover, the part shown with the broken line in a figure shows the lower wiring hidden by the upper wiring.
[0101]
The third wiring may be formed simultaneously with the formation of the BM (black mask) layer on the active matrix substrate side of the liquid crystal display device. In that case, it is desirable to return the line width and film thickness depending on the material (Al, Ti, etc.) used. For example, when Ti is used as the material for the third wiring, Ti has a higher resistivity than Al, so it is desirable to increase the line width or increase the film thickness. Further, a laminated structure of two or more kinds of metals such as Al and Ti may be used for the third wiring.
[0102]
In this embodiment, one D / A conversion circuit is provided for one source signal line. However, by providing a selection circuit in a portion that supplies a digital signal from the latch circuit to the D / A conversion circuit and / or a portion that supplies a voltage from the D / A conversion circuit to the source signal line, the D / A conversion circuit It is also possible to reduce the number. A specific method is described in detail in Japanese Patent Application No. 9-286098.
[0103]
The D / A conversion circuit of this embodiment can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits of the liquid crystal display device and other peripheral devices. Further, the four P-channel TFTs and the four N-channel TFTs connected to the respective gradation voltage lines of the D / A conversion circuit of this embodiment are formed on the same semiconductor layer. Four independent P-channel TFTs and four independent N-channel TFTs may be connected by metal wiring or the like through contacts. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.
[0104]
Example 4
[0105]
In this embodiment, another embodiment of the 4-bit D / A conversion circuit of the present invention described in Embodiment 3 will be described.
[0106]
Please refer to FIG. 6 and FIG. 6 and 10 show the 4-bit D / A conversion circuit of this embodiment. Compared with the D / A conversion circuit of the third embodiment, the D / A conversion circuit of the present embodiment is a signal line 601 (a, b, c, d, inversion a) for supplying a digital signal from a latch circuit or the like. , Inversion b, inversion c, and inversion d) are different in order.
[0107]
The arrangement of the gradation voltage lines in the D / A conversion circuit of this embodiment, and the arrangement of the circuit consisting of four P-channel TFTs and the circuit consisting of four N-channel TFTs also follow the rules described in the second embodiment. It is understood.
[0108]
Table 4 below shows the gradation voltage lines selected by the digital signals input to the signal lines a, b, c, d, inversion a, inversion b, inversion c, and inversion d.
[0109]
[Table 4]

[0110]
One gradation voltage line is selected by a digital signal input to the signal lines a, b, c, d, inversion a, inversion b, inversion c, and inversion d, and a voltage is supplied to the source signal line. It is shown.
[0111]
In the D / A conversion circuit of this embodiment, the portion indicated by 604 has more wiring intersections than the other portions. This is because, when the present invention is applied to a 4-bit D / A conversion circuit, a portion having such many intersecting wires is required.
[0112]
In this embodiment, one D / A conversion circuit is provided for one source signal line. However, by providing a selection circuit in a portion that supplies a digital signal from the latch circuit to the D / A conversion circuit and / or a portion that supplies a voltage from the D / A conversion circuit to the source signal line, the D / A conversion circuit It is also possible to reduce the number. A specific method is described in detail in Japanese Patent Application No. 9-286098.
[0113]
The D / A conversion circuit of this embodiment can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate together with other driving circuits of the liquid crystal display device and other peripheral devices. Further, the four P-channel TFTs and the four N-channel TFTs connected to the respective gradation voltage lines of the D / A conversion circuit of this embodiment are formed on the same semiconductor layer. Four independent P-channel TFTs and four independent N-channel TFTs may be connected by metal wiring or the like through contacts. However, the former case is preferable because the area of the D / A conversion circuit can be further reduced.
[0114]
(Example 5)
[0115]
In the above embodiment, the example in which the D / A conversion circuit of the present invention is used for the driving circuit of the liquid crystal display device has been described. In this case, as a display method used in the liquid crystal display device, a TN mode using nematic liquid crystal, a mode using electric field control birefringence, a mixed layer of liquid crystal and polymer, a so-called polymer dispersion mode, or the like is used. Can do. Further, the D / A conversion circuit of the present invention may be used in a drive circuit of a display device including any other display medium whose optical characteristics can be modulated in response to an applied voltage. For example, you may use for the drive circuit of the display apparatus using an electroluminescent element etc.
[0116]
(Example 6)
In this embodiment, various electronic devices using the present invention will be described. Note that the electronic device described in this embodiment is defined as a product on which the D / A conversion circuit of the present invention is mounted.
[0117]
Examples of such electronic devices include a video camera, a still camera, a projector, a projection TV, a head mounted display, a car navigation, a personal computer (including a notebook type), a portable information terminal (a mobile computer, a mobile phone, etc.). . An example of them is shown in FIG. For these electronic devices, display devices using the D / A conversion circuit of the present invention of the above-described first to third embodiments can be used.
[0118]
FIG. 11A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, operation switches 2005, and an antenna 2006. The D / A conversion circuit of the present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and the like.
[0119]
FIG. 11B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The D / A conversion circuit of the present invention can be applied to the display device 2102, the audio input unit 2103, and the image receiving unit 2106.
[0120]
FIG. 11C illustrates a mobile computer (mobile computer), which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The D / A conversion circuit of the present invention can be applied to the image receiving unit 2203, the display device 2205, and the like.
[0121]
FIG. 11D illustrates a head mounted display which includes a main body 2301, a display device 2302, and a band portion 2303. The D / A conversion circuit of the present invention can be applied to the display device 2302.
[0122]
FIG. 11E shows a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The D / A conversion circuit of the present invention can be applied to the display device 2403.
[0123]
FIG. 11F shows a fluorocarbon and type projector, which includes a main body 2501, a light source 2502, a display device 2503, an optical system 2504, and a screen 2505. The D / A conversion circuit of the present invention can be applied to the display device 2503.
[0124]
As described above, the application range of the D / A conversion circuit of the present invention is extremely wide, and can be applied to electronic devices in various fields. In addition, it can also be used for electronic bulletin boards, advertising displays, and the like.
[0125]
【The invention's effect】
According to the present invention, a D / A conversion circuit with few wiring intersections can be realized. Therefore, even a D / A conversion circuit that handles a digital signal having a large number of bits in a large-screen, high-definition semiconductor display device can be realized with a small area. Further, since the D / A conversion circuit of the present invention can be designed according to a certain rule, it leads to a great saving of design time.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a D / A conversion circuit according to the present invention.
FIG. 2 is a diagram showing another embodiment of the D / A conversion circuit of the present invention.
FIG. 3 is a diagram showing an intersection of two or more wirings.
FIG. 4 is a diagram showing another embodiment of the D / A conversion circuit of the present invention.
FIG. 5 is a circuit pattern diagram and an equivalent circuit diagram of a D / A conversion circuit of the present invention.
FIG. 6 is a diagram showing another embodiment of the D / A conversion circuit of the present invention.
FIG. 7 is a schematic configuration diagram of a liquid crystal display device.
FIG. 8 is a circuit diagram of a conventional D / A conversion circuit.
FIG. 9 is a circuit pattern diagram and an equivalent circuit diagram of a NAND circuit.
FIG. 10 is a diagram showing another embodiment of the D / A conversion circuit of the present invention.
FIG. 11 shows an electronic device using the present invention.
[Explanation of symbols]
101, 201 Address line
102, 202 gradation voltage line
103, 203 Output line

Claims (6)

Corresponding to an input n-bit (n is an integer of 2 or more) digital signal, one gradation voltage line is selected from 2 ⁿ gradation voltage lines, and the selected gradation voltage is selected. A D / A conversion circuit in which a gradation voltage is supplied from a line to an output line,
a first circuit the n P-channel type TFT are connected in series, a second circuit the n N-channel type TFT are connected in series, a circuit but connected in series, the 2 ⁿ Are connected in parallel to each of the gradation voltage lines ,
The 2 ⁿ the gradation voltage lines from the 1st gradation voltage lines is supplied with a higher voltage toward the first 2 ^n-th gradation voltage lines, the x (1 ≦ x ≦ 2 ⁿ ; x is an integer) -th gradation voltage line and the Part (2 ⁿ + 1-x) th gradation voltage lines, disposed between the and the one only adjacent the first circuit second circuit paired Is the opposite,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is pre-SL and the gate electrodes of the n P-channel transistors, the n N-channel transistor and the gate electrode, and performs switching by being input to the D / A converter circuit.   2. The D / A conversion circuit according to claim 1, wherein the n P-channel TFTs and the n N-channel TFTs are formed of the same semiconductor layer. The D / A conversion circuit, D / A conversion circuit according to claim 1 or claim 2, characterized in that it is formed on an insulating substrate. At both ends of the circuit and the first circuit and the second circuit are connected in series, claim 1 to one of the 2 ⁿ the gradation voltage line, characterized in that it is connected D / a conversion circuit according to any one of claims 3. A plurality of pixel TFTs;
A semiconductor device having a source signal line side drive circuit and a gate signal line side drive circuit for driving the plurality of pixel TFTs;
The source signal line side drive circuit has a D / A conversion circuit,
The D / A conversion circuit, n-bit are entered (n is an integer of 2 or more) in response to digital signals, one of the gradation voltage lines of the 2 ⁿ the gradation voltage line is selected , the gray scale voltage is supplied to the output line from the gradation voltage line is selected,
a first circuit the n P-channel type TFT are connected in series, a second circuit the n N-channel type TFT are connected in series, a circuit but connected in series, the 2 ⁿ Are connected in parallel to each of the gradation voltage lines, the 2 ⁿ the gradation voltage lines is higher and more towards from the first gradation voltage line to the 2 ⁿ th gradation voltage lines The voltage is supplied, and the x-th (1 ≦ x ≦ 2 ⁿ ; x is an integer) -th gradation voltage line and the (2 ⁿ + 1−x) -th gradation voltage line are adjacent to each other in pairs. arrangement of the vital said first circuit and the second circuit is reversed,
A connection portion between the first circuit and the second circuit is connected to the output line,
The digital signal is pre-SL and the gate electrodes of the n P-channel transistors, the n semiconductor device which is characterized in that the switching by the gate electrode of the N-channel transistor, is inputted to. An electronic apparatus comprising the semiconductor device according to claim 5 .

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