JP4177798B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and in particular, in a semiconductor memory device having a memory element portion and a control circuit portion (passive circuit) for controlling the memory element portion, the specification is more specific than the memory element portion. The present invention relates to processing of wiring routed to a loose control circuit unit.

  In recent years, with increasing density and miniaturization, it has become essential for semiconductor devices to form wiring at an optical wavelength (λ) that is the limit of exposure. Therefore, as a method of bringing the wiring pitch (Line / Space) close to the exposure limit, for forming the wiring, a method of increasing the lens diameter (N), a method of using the lens ring zone, a semi-transparent mask (half A technique using a tone mask) or a technique using a phase technique is adopted. By adopting these methods, it is theoretically possible to form wiring at the exposure limit, and high density and miniaturization of the semiconductor device are achieved.

  However, in peripheral devices that control semiconductor memory devices and peripheral devices that are formed at the same time as semiconductor memory devices, the wiring width is larger than the desired design value by employing various methods for bringing the wiring pitch closer to the exposure limit. The phenomenon that the wiring short circuit (short circuit) by becoming or the disconnection by a wiring width becoming smaller than a design value becomes easy to generate | occur | produce appears notably. To solve this problem, the optical proximity effect and the wiring processing error are digitized at the time of manufacturing the mask, and correction (for example, optical proximity correction (hereinafter, OPC processing)) is performed on the wiring pattern data on the mask. Therefore, avoidance is possible.

  However, in the semiconductor memory device, there is a problem that it is very difficult to route wiring including pitch conversion between the cell of the memory element portion, the decoder, and the sense amplifier (hereinafter, control circuit portion).

  Here, the wiring pitch is usually different between the cell and the control circuit unit. This is because the cells are formed with a processing pitch, for example, a cell pitch. On the other hand, the control circuit section is formed at a peripheral circuit pitch, for example, in which the design rule is more relaxed than the cell specification. Therefore, it is necessary to route wiring including pitch conversion between the cell and the control circuit unit. In order to increase the density of the semiconductor memory device, for example, as shown in FIG. 11, the pitch conversion length of the wiring 101 (the length of the oblique lead wiring connecting the cell 103 and the control circuit unit 105) is minimized. For this purpose, an oblique lead-out wiring (hereinafter referred to as a 45-degree oblique lead-out wiring) 101a having a wiring incident angle of 45 degrees must be used. A method for this has already been proposed (see, for example, Patent Document 1).

  However, the routing of the wiring 101 including the pitch conversion between the cell 103 and the control circuit unit 105 having a different wiring pitch is greatly affected by the optical proximity effect during the exposure process. In particular, in the vicinity of the connection point between the wiring 101b on the cell 103 side and the 45-degree oblique lead-out wiring 101a, the influence becomes significant. For this reason, for example, like the processing simulation 102 shown in FIG. 12, the width of the wiring 101b on the cell 103 side is likely to be partially larger or smaller than the wiring 101c on the control circuit unit 105 side. The partial deformation of the wiring width (distortion of the wiring shape) may cause a short circuit or a disconnection in some cases, and may cause a decrease in productivity (yield) of the semiconductor memory device.

Therefore, the wiring pattern data 201 is subjected to OPC processing to adjust the shape of the wiring 101, or formed so that the width of the 45-degree oblique wiring 101a is larger than that of the wiring 101b on the cell 103 side. Previously it was supported. However, the formation of wiring pattern data at the time of mask production requires a huge amount of data processing, and at present it is difficult to fully automate. In particular, due to restrictions on computer aided drafting (hereinafter referred to as CAD) processing, it is extremely difficult to form wirings having wiring incident angles other than 45-degree oblique lead wiring and 90-degree lead wiring (wiring incident angle is 90 degrees). It was labor intensive.
JP2002-329783

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device that can reduce the influence of the optical proximity effect and can easily route wiring including pitch conversion. .

According to one aspect of the present invention, a plurality of first wiring layers having a first wiring pitch and a control circuit for driving the memory elements are arranged in a memory cell portion in which a plurality of memory elements are formed. A second wiring layer provided in the peripheral circuit portion corresponding to the first wiring layer, the second wiring layer having a second wiring pitch wider than the first wiring pitch; A plurality of third wiring layers provided between the memory cell portion and the peripheral circuit portion and respectively connecting the first wiring layer and the second wiring layer . A third wiring layer is provided in parallel with each other and has a wiring incident angle of less than 45 degrees with respect to the first wiring layer .

  With the above configuration, it is possible to provide a semiconductor device that can reduce the influence of the optical proximity effect and can easily route wiring including pitch conversion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of a semiconductor memory device having a memory element section and a control circuit section for controlling the memory element section according to the first embodiment of the present invention. Here, only the main part of the NAND flash memory is shown as an example. Also, wiring routing including pitch conversion between the memory cell array and the row decoder circuit unit having different wiring pitches will be described.

  As shown in FIG. 1, the flash memory 10 has a memory cell array (storage element unit) 11. A row decoder circuit unit (control circuit unit) 13 is disposed at each end of the memory cell array 11 in a direction perpendicular to the word lines (in the direction of the arrow in the drawing) via a high voltage transfer circuit unit 12a. In addition, oblique lead-out wiring portions (described later) 21 are provided between the high voltage transfer circuit portion 12a and the memory cell array 11, respectively.

  On the other hand, a sense amplifier circuit unit 14 is disposed at each end of the memory cell array 11 in the direction along the word line via a high voltage transfer circuit unit 12b. A column decoder (not shown) is connected to the sense amplifier circuit unit 14. The sense amplifier circuit unit 14 is provided with a plurality of sense amplifier circuits that also serve as latch circuits for writing and reading data. Each sense amplifier circuit is connected to a bit line of the memory cell array 11.

  The memory cell array 11 is formed at a processing limit pitch, for example, a cell pitch. On the other hand, at least the row decoder circuit section 13 is formed at a peripheral circuit pitch, for example, with a processing pitch relaxed from the cell specification. For example, when the cell pitch is 90 nm, the peripheral circuit pitch is set to about 500 nm.

  FIG. 2 shows a configuration example of the memory cell array 11. In the memory cell array 11, for example, a plurality of NAND cells 11a including 16 memory cells MC1, MC2,..., MC16 and first and second selection gate transistors Q11a, Q11b are arranged in a matrix in the row direction and the column direction. Is arranged. The first select gate transistor Q11a of each NAND cell 11a is connected to, for example, bit lines BL0A, BL1A,. The second select gate transistor Q11b of each NAND cell 11a is selectively connected to one of the source lines SL arranged in the row direction. Each of the source lines SL is commonly connected to a source bias line SBL arranged in the column direction. Each source line SL is connected to the source bias line SBL made of aluminum, polysilicon, or the like via a contact for every 64 bit lines, for example. The source bias line SBL is connected to a source line bias circuit (not shown).

  In the figure, CG1, CG2,..., CG16 are control gate lines (word lines) of the memory cells MC1, MC2,..., MC16, and SG1, SG2 are the first, second, respectively. This is the select gate line of the select gate transistors Q11a and Q11b.

  Here, in the NAND flash memory according to the present embodiment, one page is composed of, for example, 528 bytes (512 bytes (data storage unit) +16 bytes (redundant unit)) memory cells. Data is read from and written to the memory cells for one page almost simultaneously. Further, one block is composed of, for example, 16 k bytes + 0.5 k bytes (k is 1024) memory cells. Data in one block of memory cells is erased almost simultaneously.

  FIG. 3 shows a configuration example of the oblique lead-out wiring portion 21. As shown in FIG. 2A is a plan view showing an example of an oblique lead-out wiring, and FIG. 2B is an enlarged view showing the main part of FIG. In this embodiment, a 30-degree oblique lead-out wiring which is formed by a well-known exposure transfer technique and designed to have a wiring incident angle of 30 degrees will be described as an example.

  As shown in FIG. 3A, the oblique lead-out wiring portion 21 is formed with a plurality of wiring layers 22 including pitch conversion that are routed between the memory cell array 11 and the row decoder circuit portion 13, for example. ing. Each wiring layer 22 has a configuration in which wirings 22a and 22b having different wiring pitches are connected to each other by a 30-degree oblique lead-out wiring (third wiring layer) 22c. The 30-degree oblique lead-out wiring 22c is designed so that at least a wiring incident angle (P ') with respect to the wiring 22a is 30 degrees.

  In the present embodiment, the wirings 22a are control gate lines (first wiring layers having a first wiring pitch) CG1, CG2,..., CG16 of the memory cell array 11 formed at a cell pitch, for example. The wiring 22b is a signal line (second wiring layer having a second wiring pitch) of the high-voltage transfer circuit unit 12a connected to the row decoder circuit unit 13, for example, formed at a peripheral circuit pitch. .

  When the wiring incident angle P ′ of the 30-degree oblique lead-out wiring 22c with respect to the wiring 22a is set to 30 degrees, the influence of the optical proximity effect during the exposure process can be reduced. Thereby, for example, as shown in FIG. 3B, it is possible to suppress the occurrence of distortion of the wiring shape. As a result, disconnection and short circuit of the wiring layer 22 can be prevented. Further, the wiring pitch (F value / F ′ value) of the 30-degree oblique lead-out wiring 22c can be made the same as the wiring pitch of the wiring 22a, which is the processing limit of the exposure transfer apparatus.

  The 30-degree oblique lead-out wiring 22c may be formed to have a staircase shape, for example, as shown in FIG. For example, in the present embodiment, the 30-degree oblique lead-out wiring 22c is realized by making the wiring pattern shape stepped.

  Next, the CAD automatic design method (layout method) of the wiring layer 22 including the pitch conversion described above will be described. Here, the 30-degree oblique lead-out wiring 22c will be described as an example. For example, as shown in FIG. 5, the wiring pattern data 31 on the mask for forming the 30-degree oblique lead-out wiring 22c is CAD using F value, F ′ value, S value, P value, and P ′ value as parameters. Designed automatically by processing.

  Here, the F value is a parameter for determining the width (Line) of the 30-degree oblique lead-out wiring 22c and the length in the oblique direction (oblique length), and the F ′ value is an interval between the 30-degree oblique lead-out wiring 22c ( Space) is a parameter for determining, and all have the same minimum dimensions as the wiring 22a. The S value is a parameter for determining the horizontal (lateral) direction length of the 30-degree oblique lead-out wiring 22c, and is equal to or larger than the F value (S ≧ F). The P value is a parameter for determining an angle of the 30-degree oblique lead-out wiring 22c with respect to the wiring 22a, and is normally set to 45 degrees. The P ′ value is a parameter for determining the wiring incident angle P ′ of the 30-degree oblique lead-out wiring 22c, and satisfies a predetermined condition (for example, P′∝1 / S).

  As described above, by automatically designing the wiring pattern data 31 having the staircase shape according to the setting of each parameter, the design of the 30-degree oblique lead-out wiring 22c can be automated. In addition, in the CAD processing, the wiring pattern data 31 can be designed with less labor than in the prior art, so that complicated arithmetic processing and enormous data processing are not required. Of course, according to the setting of each parameter, it is also easy to design wiring pattern data for forming a wiring layer having a wiring incident angle P ′ other than the 30-degree oblique lead-out wiring 22c.

  In the actual exposure process, a processing simulation using the same parameters as the conventional one is performed.

  As described above, according to the present embodiment, it is possible to form an oblique lead-out wiring having a wiring incident angle of 30 degrees (less than 45 degrees) without requiring enormous data processing or complicated arithmetic processing. . As a result, it is possible to reduce the influence caused by the optical proximity effect during the exposure process, which causes distortion in the wiring shape. Therefore, it is possible to easily route the wiring including pitch conversion, such as preventing the wiring from being disconnected or short-circuited.

[Second Embodiment]
FIG. 6 shows a basic configuration of a semiconductor memory device having a memory element part and a control circuit part for controlling the memory element part according to the second embodiment of the present invention. Here, only the main part is shown by taking Dynamic Random Access Memory (hereinafter referred to as DRAM) as an example. Further, wiring routing including pitch conversion between the memory cell array and the sense amplifier circuit unit having different wiring pitches will be described.

  As shown in FIG. 6, the DRAM 40 has a memory cell array (storage element unit) 41. A row decoder circuit section 42 is disposed at each end of the memory cell array 41 in the direction orthogonal to the word lines (in the direction of the arrow in the drawing).

  On the other hand, a sense amplifier circuit section (control circuit section) 44 is disposed at each end of the memory cell array 41 in the direction along the word line via an oblique lead-out wiring section (described later) 43. A column decoder (not shown) is connected to the sense amplifier circuit unit 44. A plurality of sense amplifier circuits are provided in the sense amplifier circuit section 44. Each sense amplifier circuit is connected to a bit line of the memory cell array 41, respectively.

  The memory cell array 41 is formed at a processing limit pitch, for example, a cell pitch. On the other hand, at least the sense amplifier circuit section 44 is formed at a peripheral circuit pitch, for example, with a processing pitch relaxed from the cell specification. For example, when the cell pitch is 130 nm, the peripheral circuit pitch is set to 260 nm or more.

  FIG. 7 shows an example of wiring including pitch conversion that is routed between the memory cell array 41 and the sense amplifier circuit section 44. For example, a plurality of wiring layers 51 are routed between the memory cell array 41 and the sense amplifier circuit unit 44. Each wiring layer 51 includes a wiring on the memory cell array 41 side (first wiring layer having a first wiring pitch) 51a and a wiring on the sense amplifier circuit unit 44 side (second wiring layer having a second wiring pitch). 51b is connected to each other by a 30-degree oblique lead-out wiring (third wiring layer) 51c of the oblique lead-out wiring portion 43.

  In the case of this embodiment, the 30-degree oblique lead-out wiring 51c is designed so that at least the wiring incident angle P ′ with respect to the wiring 51a is 30 degrees, as in the case of the first embodiment described above. The 30-degree oblique lead-out wiring 51c is formed with the same wiring pitch (F value / F 'value) as the wiring 51a, which is the processing limit of the exposure transfer apparatus.

  In the present embodiment, the wiring 51a is a bit line of the memory cell array 41 formed with a cell pitch (F ′), for example. The wiring 51b is a signal line of the sense amplifier circuit section 44 formed with, for example, a peripheral circuit pitch (F ″) (where F ″ ≧ 2F ′).

  FIG. 8 shows a configuration example of the oblique lead-out wiring portion 43. In this embodiment, an explanation will be given by taking as an example a 30-degree oblique lead-out wiring formed by a known exposure transfer technique and designed to have a wiring incident angle of 30 degrees. In addition, the solid line shown in the figure is a 30-degree oblique lead-out wiring. Incidentally, the broken line shown in the figure is the locus of the conventional 45-degree oblique lead-out wiring.

  That is, the 30-degree oblique lead-out wiring 51c for connecting the wirings 51a and 51b having different wiring pitches has, for example, a step shape. As a result, a 30-degree oblique lead-out wiring 51c having a wiring incident angle of at least 30 degrees with respect to the wiring 51a is realized.

  As described above, in the DRAM 40 as well, the influence of the optical proximity effect during the exposure process can be reduced by setting the wiring incident angle P ′ of the 30-degree oblique lead-out wiring 51c to the wiring 51a to 30 degrees (less than 45 degrees). Become. As a result, it is possible to suppress the occurrence of distortion of the wiring shape, and it is possible to easily lead the wiring including the pitch conversion, such as the disconnection or short circuit of the wiring layer 51 can be prevented.

  In particular, in the case of the DRAM 40, it is possible to improve the margin in pattern transfer by employing the 30-degree oblique lead-out wiring 51c. Therefore, the bit line can be easily made thin. That is, the capacity (CBL) of the bit line can be reduced.

Here, with reference to FIGS. 9A and 9B, the operation of the cell in the DRAM 40 will be described. For example, it is assumed that the source of the cell transistor T is at the high voltage VSN in a state where data “1” is written in the cell capacitor C. Further, it is assumed that the potential of the bit line BL is held at VBL. Then, the total charge amount QI stored in the cell MC and the bit line BL is
QI = Cs (VSN−VP) + CBL · VBL (1)
It becomes. Where Cs is the capacitance of the cell capacitor C, VP is the plate potential, and CBL is the total parasitic capacitance of the bit line BL.

From this state, the cell transistor T is turned on to redistribute the charge of the cell capacitor C. Then, the source potential of the cell transistor T changes to VSN ′, and the potential of the bit line BL changes to VBL ′. The plate potential VP is kept constant. The total amount of charge QF stored in the cell MC and the bit line BL at this time is
QF = Cs (VSN′−VP) + CBL · VBL ′ (2)
It becomes.

  Since the charge amount is held before and after the conduction of the cell transistor T, the relationship of “QI = QF” is established. Further, in the above formula (2), since VSN ′ = VBL ′, the following formula (3) is obtained.

VBL ′ = (Cs · VSN + CBL · VBL) / (Cs + CBL) (3)
The change in the bit line potential VBL is
ΔVBL = VBL′−VBL
= (VSN−VBL) / (1 + CBL / Cs) (4)
It becomes.

Here, the bit line BL is precharged to VD / 2. Therefore, VSN = VD, VBL = VD / 2, and the above equation (4) is
ΔVBL = VBL′−VBL
= VD / (2 (1 + CBL / Cs)) (5)
It becomes.

  Thus, the change in the bit line potential VBL increases as “CBL / Cs” decreases. Therefore, in the DRAM 40, the use of the 30-degree oblique lead-out wiring 51c is very useful for reducing the capacitance CBL of the bit line BL.

  In the first and second embodiments described above, a method for designing a 30-degree oblique lead-out wiring using parameters (F value, F ′ value, S value, P value, P ′ value) is described. explained. For example, as shown in FIG. 10A, a plurality of block patterns 61a having the same size are arranged stepwise at a predetermined angle to produce wiring pattern data 61 on the mask. At this time, the size and arrangement of the block pattern 61a are set so as to satisfy the conditions (parameters) of the first embodiment described above, for example, as shown in FIG. Also by using such wiring pattern data 61, it is possible to form a 30-degree oblique lead-out wiring.

  In any of the embodiments, the 30-degree oblique lead-out wiring has been described as an example. However, for example, a diagonal lead-out wiring (0 <P ′ <45) having a wiring incident angle P ′ of less than 45 degrees can be easily set. Is possible.

  In the above-described embodiment, the wiring routed between the memory cell array and the row decoder circuit unit and between the memory cell array and the sense amplifier circuit unit has been described as an example. However, the present invention is not limited to this, and the embodiment is similarly applied to a wiring routed between a semiconductor memory device and a peripheral device that controls the semiconductor memory device or between the semiconductor memory device and a peripheral device formed at the same time. it can.

  The embodiments are not limited to NAND flash memories and DRAMs, and can be applied to various semiconductor devices.

  In addition, as an embodiment, it can be used for forming various oblique lead wirings using a polymetal such as polysilicon or WSi and a metal such as Al or Cu as a wiring material.

  As an embodiment, a plurality of oblique lead wires having the same or different wiring incident angles can be mixed in one wiring layer including pitch conversion.

  Furthermore, as an embodiment, it is possible to mix a plurality of wiring layers each having an oblique lead-out wiring having different wiring incident angles in one semiconductor device.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

1 is a diagram showing a layout example of a semiconductor memory device (NAND flash memory) according to a first embodiment of the present invention. FIG. 2 is a diagram showing a configuration example of a memory cell array in the NAND flash memory shown in FIG. 1. FIG. 2 is a diagram showing a configuration example of an oblique lead-out wiring portion of the NAND flash memory shown in FIG. The figure which shows an example of the 30 degree | times diagonal extraction wiring of the diagonal extraction wiring part shown in FIG. The figure which shows an example of wiring pattern data in order to demonstrate the design method of 30 degree | times diagonal extraction wiring. The figure which shows the example of a layout of a semiconductor memory device (DRAM) according to the 2nd Embodiment of this invention. FIG. 7 is a diagram showing an example of wiring routing including pitch conversion in the DRAM shown in FIG. 6. FIG. 7 is a diagram illustrating a configuration example of an oblique lead-out wiring portion of the DRAM illustrated in FIG. 6. The figure shown in order to demonstrate operation | movement of a DRAM cell. The figure which shows the other example of wiring pattern data, in order to demonstrate the design method of 30 degree | times diagonal extraction wiring. The figure which shows the structural example of the diagonal extraction wiring part in a prior art. The figure which expands and shows a part of wiring in order to demonstrate the problem in a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Flash memory, 11 ... Memory cell array, 13 ... Row decoder circuit part, 14 ... Sense amplifier circuit part, 21 ... Diagonal lead wiring part, 22 ... Wiring layer, 22a ... Memory cell array side wiring, 22b ... Row decoder circuit part Side wiring, 22c... 30 degree oblique lead wiring, 31... Wiring pattern data, 40... Flash memory, 41... Memory cell array, 42. ... wiring layer, 51a ... wiring on the memory cell array side, 51b ... wiring on the sense amplifier circuit side, 51c ... 30-degree oblique lead-out wiring, 61 ... wiring pattern data, 61a ... block pattern.

Claims (4)

Are arranged in the memory cell portion in which a plurality of memory elements are formed, a plurality of first wiring layer having a first wiring pitch,
A second wiring layer provided corresponding to the first wiring layer in a peripheral circuit portion where a control circuit for driving the memory element is disposed, and a second wiring layer wider than the first wiring pitch. A second wiring layer having a wiring pitch;
A plurality of third wiring layers provided between the memory cell portion and the peripheral circuit portion and respectively connecting the first wiring layer and the second wiring layer ;
The plurality of third wiring layers are parallel to each other and have a wiring incident angle of less than 45 degrees with respect to the first wiring layer . The semiconductor device according to claim 1, wherein the third wiring layer has the same wiring width as that of the first wiring layer . The second wiring layer, the semiconductor device according to claim 1 or 2, characterized in that it has the wider line width than the first wiring layer. The first wiring layer is a word line, the semiconductor device according to any one of claims 1 to 3, wherein the control circuit is a row decoder circuit.

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