JP4150404B2 - 多数個取り電子装置の製造方法 - Google Patents
多数個取り電子装置の製造方法 Download PDFInfo
- Publication number
- JP4150404B2 JP4150404B2 JP2006068358A JP2006068358A JP4150404B2 JP 4150404 B2 JP4150404 B2 JP 4150404B2 JP 2006068358 A JP2006068358 A JP 2006068358A JP 2006068358 A JP2006068358 A JP 2006068358A JP 4150404 B2 JP4150404 B2 JP 4150404B2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- wiring board
- wiring
- green sheet
- ceramic mother
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structure Of Printed Boards (AREA)
Description
2・・・配線基板領域
2a・・・搭載部
3・・・貫通孔
4・・・配線用メタライズ
5・・・電子部品
Claims (1)
- ドクターブレード法により成形されたセラミックグリーンシートと、配線用メタライズとを備えるとともに、
裏面に電子部品が搭載される搭載部を有する配線基板領域を配列してなる単層且つ平板状の生セラミック成形体を、該生セラミック成形体の全体形状が、裏面側が凸面、表面側が凹面となるように焼成される工程と、
平坦な吸引テーブル上に、前記生セラミック成形体の焼成体を前記凹面が被吸引面側となるように載置させる工程と、を経ることを特徴とする多数個取り電子装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006068358A JP4150404B2 (ja) | 2006-03-13 | 2006-03-13 | 多数個取り電子装置の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006068358A JP4150404B2 (ja) | 2006-03-13 | 2006-03-13 | 多数個取り電子装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002015420A Division JP3793566B2 (ja) | 2002-01-24 | 2002-01-24 | 多数個取り電子装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006196921A JP2006196921A (ja) | 2006-07-27 |
JP4150404B2 true JP4150404B2 (ja) | 2008-09-17 |
Family
ID=36802681
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006068358A Expired - Fee Related JP4150404B2 (ja) | 2006-03-13 | 2006-03-13 | 多数個取り電子装置の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4150404B2 (ja) |
-
2006
- 2006-03-13 JP JP2006068358A patent/JP4150404B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2006196921A (ja) | 2006-07-27 |
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