JP4148626B2 - Digital data reproducing apparatus and reproducing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital data reproducing apparatus and method, and more particularly, to error correction processing.
[0002]
[Prior art]
As an example of a reproducing apparatus for a recording medium on which digital data is recorded, there is one described by Kenji Hayashi “CD-Audio to PC”, Corona, pp. 56-71 (1990). This describes the processing contents and circuit configuration of a CD playback device and a digital signal processing unit included in the device.
[0003]
As a medium for recording digital data subjected to similar modulation processing, there is a DVD (Digital Versatile Disc) having a data capacity (4.7 Gbytes) about eight times that of a CD (Compact Disk). As an example of this DVD playback device, there is one described by Masumi Harada “All about Digital Video Technology”, Denpa Shimbun, pp. 116-124 (1998).
[0004]
In a DVD, like a CD, a continuous spiral track composed of continuous pits is formed, and the center line of the track is the center line of the pit.
[0005]
In such a disc, a track area in which data is recorded is used as an information area. In a single layer track, as shown in FIG. 2, the head of the information area 200 is a lead-in area 201 and the end is a lead-out area 203, and data between the lead-in area 201 and the lead-out area 203 is data. As the area 202, physical sectors to be described later are continuously arranged in the data area 202 with no gap therebetween. The physical sector arranged in the data area 202 has an address of 30000h (Hex: hexadecimal) in the first physical sector in the data area 202, and is assigned a sector number that increases by 1 in the arrangement order.
[0006]
The minimum address that can be independently accessed by a track in the information area 200 on the disc is called a “sector”. As shown in FIG. 3, the sectors are called “data sector” 305, “recording sector” 307, and “physical sector” 308 according to the signal processing process.
[0007]
In the signal processing of digital data, a 2-byte IED (ID Error Detection Code) is added to a 4-byte ID (Identification Data) 301 to form (ID + IED) 302, which is converted into a 6-byte CPR_MAI ( The data 303 is formed by adding it to the 2048-byte main data together with the copyright management information), and the data sector 304 is formed by adding EDC (Error Detecting Code) to the data 303. The data sector 305 is formed by scrambling only the main data.
[0008]
4A and 4B show the ID 301, and FIG. 4C shows the configuration of the data sector 305, respectively.
[0009]
As shown in FIG. 4B, the ID 301 includes a 1-byte (8-bit) sector information (Data Field Information) 401 and a 3-byte sector number (Data Field Number) 402 configured as shown in FIG. It is composed of This sector number 402 is a sector number representing the address of the physical sector sequentially arranged in the data area 202 described with reference to FIG.
[0010]
As shown in FIG. 4C, the data sector 305 includes a 4-byte ID 301, a 2-byte IED, and a 6-byte CPR_MAI at the leading end of the main data of 2048 bytes (= 160 bytes + 172 × 10 bytes + 168 bytes). The 12-byte data is a 2064-byte data string with a 4-byte error detection code (EDC) added to the end, and only the main data portion is scrambled. As described above, the sector number 402 in the ID 301 is a serial number of an address starting from 030000h assigned to the physical sectors in the data area 202 (FIG. 2) in the order of arrangement.
[0011]
The data sector 305 is formed in a format of 172 bytes × 12 rows, and as shown in FIG. 5, a data block 306 (FIG. 3) of a 172 bytes × 192 rows format in which 16 data sectors 305 are overlapped is formed. In addition, a sequence of data arranged in a vertical direction (vertical direction in FIG. 5) orthogonal to a continuous data sequence (horizontal direction in FIG. 5) is RS (208, 192, 17: Reed-Solomon code). , A 16-byte error correction code (external code: PO) 502 is added, and further, a data column (horizontal direction in FIG. 5) of 208 rows of data (= 192 rows + 16 rows) to which this PO 502 is added. 10-byte error correction code (inner code: PI) 501 was added so as to be RS (182, 172, 11), and ECC (Error Correction Code) encoding (FIG. 3) was performed. Obtaining a 82 byte × 208 rows of data blocks 503. Thus, the data block 503 having a product code of RS (208, 192, 17) × RS (182, 172, 11) is referred to as an ECC block.
[0012]
In the ECC block 503, the code of each row viewed in the horizontal direction is hereinafter referred to as a PI code, and the code of each column viewed in the vertical direction is referred to as a PO code.
[0013]
With respect to the ECC block 503 having such a configuration, 16 rows of PO 502 are interleaved into each data sector 305 one row at a time (FIG. 3), and the ECC block having the configuration shown in FIG. 6 is obtained. In this ECC data block, each data sector 305 is added with one row of PO codes 502 to form a 13-row × 182-byte sector structure (that is, a PI code consisting of 12 rows of data sectors 305 and a PI row consisting of 1 row of PO502). The sector of 13 rows is called a recording sector 307 in FIG.
[0014]
The recording sector 307 is subjected to 8/16 modulation while a SYNC (synchronization) code is added to form a physical sector 308 (FIG. 3). FIG. 7 shows the configuration of a recording sector 308 that has been subjected to 8/16 modulation. As shown in FIG. 7, the recording sector 308 includes 13 rows, and each row is one byte before 8/16 modulation (after 16/16 modulation, Bit) is one data, and is composed of 182 data. Each row after 8/16 modulation is composed of 1456 × 2 = 2912 channel bits.
[0015]
In the physical sector 308, for each row, the first (first) data (as described above, 1 byte before 8/16 modulation and 16 channel bits after 8/16 modulation) is the 92nd as before. A 32-bit SYNC code 701 is added to the front of the data. A bit string of 32 + 1456 = 1488 channel bits starting with the SYNC code 701 is hereinafter referred to as a SYNC frame. Therefore, the 8/16 modulated physical sector 308 is a bit string of 38688 channel bits composed of 13 rows × 2 SYNC frames.
[0016]
There are eight types of SYNC codes 701 used for one physical sector 308, and the combination of these SYNC codes 701 is different for each row. In other words, SY0 is used only at the beginning of the first row of the physical sector 308, so that the beginning of the physical sector 308 can be identified. SY1 to SY4 are repeatedly used in order at the head of the second to thirteenth rows, and SY5 is used before the 92nd data (92th byte before 8/16 modulation) of the first to fifth rows. , SY6 is used before the 92nd data in the 6th to 9th rows, and SY7 is used before the 92nd data in the 10th to 13th rows. In this way, the combination of the two SYNC codes 701 used for each row is different, in other words, the combination of the SYNC codes 701 differs depending on the row number corresponding to the row address in the physical sector 308. It will be.
[0017]
The arrangement of the SYNC code 701 as described above is the same in all the physical sectors 308, and the physical sectors 308 having such a configuration are continuously arranged in the data area 202 without a gap in FIG. In the data area of FIG. 3, the boundary of the physical sector 308 is indicated by a broken line, and the boundary of an ECC block composed of 16 physical sectors 308 is indicated by a solid line. In the data area 202, the sector number of ID301 in the first physical sector 308 of the first ECC block is 030000h divisible by 16 (decimal number: 10 in hexadecimal number), and each ECC block is composed of 16 physical sectors 308. Therefore, the sector number of the first physical sector 308 of each ECC block is divisible by 16.
[0018]
The DVD playback apparatus reads the digital data recorded as described above from the disk, and restores the original data by performing processing reverse to the modulation process.
[0019]
However, in reality, there are cases where the digital data read from the disc contains errors or some data is lost due to the shape, scratches, or dust of the disc. In the error correction circuit, even in such a situation, it is necessary to perform data processing without any problem. However, the publicly known documents mentioned above do not specifically describe countermeasures and circuits for such problems.
[0020]
[Problems to be solved by the invention]
In a digital data playback device such as a DVD, even if a lot of errors are included in the digital data to be played back or some data is missing, playback is performed so that demodulation and error correction processing can be performed reliably. It is necessary to improve the reliability of data.
[0021]
In the case of digital data subjected to modulation forming the product code as described above, PI 501 (FIG. 5) is used for correction by PO 502 (FIG. 5) (hereinafter referred to as PO correction) in order to ensure the burst correction length. A position where an error is detected during correction by the above (hereinafter referred to as PI correction) is designated as an error position, and erasure correction is performed to obtain only the error value at this error position. Further, in this erasure correction, when an error position is not correctly specified, an error correction occurs with a high probability. Therefore, the error position must be specified accurately in the erasure correction.
[0022]
By the way, in a conventional reproducing apparatus, a RAM (Randam Access Memory) that temporarily holds data is provided in front of an error correction circuit or PO correction circuit, and data is read from an ECC block repeatedly written on the RAM. In the product code data configuration shown in FIGS. 5 and 6, the PI code sequence (horizontal direction in FIG. 6) is recorded on the disk and read out. Therefore, if a part of the data read from the disk is missing, a data shift in units of lines occurs in the ECC block 503, and the data is written in a different line from the corresponding line in the RAM. There is a situation in which past data that has already been subjected to error correction remains in a line that has been inserted or has not been written in the RAM.
[0023]
Hereinafter, this point will be described with reference to FIG.
[0024]
As described above, when a track jump occurs due to a tracking control malfunction due to the shape, scratch, or dust of the disk, the reading position by the light beam jumps to another position on the track, and the physical sector of the read digital data is read. The arrangement of 308 is discontinuous. FIG. 8A shows the arrangement order of physical sectors of a certain ECC block written on the disk, and FIG. 8B shows the physical data in the digital data read from the disk for the above reasons. An example of a discontinuous portion of the sector 308 is schematically shown.
[0025]
Here, for simplification of description, in FIG. 8A, from the second half of the third physical sector (hereinafter referred to as physical sector 3; the same applies to other physical sectors) to the physical sector 4 As shown in FIG. 8 (b), the data read from the disk is read from the latter half of the physical sector 4 as shown in FIG. 8B. The second half will continue.
[0026]
FIG. 8C is a diagram schematically showing the state of writing the read data in the RAM shown in FIG. 8B, and the write addresses of the physical sectors 1, 2, 3,. Are sector addresses (1), (2), (3),..., Respectively.
[0027]
In FIG. 8C, for the read data shown in FIG. 8B, physical sectors 1 and 2 are written to sector addresses (1) and (2), respectively. When sector 3 is written up to the latter half, the latter half of physical sector 4 is also written. When the latter half of the physical sector 4 is written, the next physical sector 5 is written to the sector address (4), and the next physical sector 6 is further written to the sector address (5). For this reason, these physical sectors 5 and 6 are written at an incorrect sector address in the RAM.
[0028]
On the other hand, as described above, ID 301 (FIG. 4) is added to the top row of each physical sector, and the order in the ECC block can be determined by the sector number of this ID 301. Therefore, the physical sectors 5 and 6 shown in FIG. 8B are the fifth and sixth sectors in the ECC block, and are originally written to the sector addresses (5) and (6) in FIG. 8C. However, the playback device does not immediately correct such a malfunction, but sets a certain judgment period. If a malfunction occurs even after this judgment period has passed, To correct. If this is determined to be a malfunction and the correction is made immediately, the determination that the malfunction has occurred may be incorrect. In such a case, the malfunction may occur despite the malfunction. Because it will be. Here, when there is a possibility of malfunction in three consecutive physical sectors, it is corrected.
[0029]
In this example, when the writing of the sector address of the RAM is completed, the next physical sector 5 is determined as the fifth physical sector from its ID 301. Writing this to the next sector address (4) is clearly an error, but since the determination period has not elapsed, this physical sector 5 is written to the sector address (4) as the fourth physical sector. The same applies to the physical sector 6 and is written in the sector address (5) as the fifth physical sector.
[0030]
However, for the next physical sector 7, the sector number of the ID 301 is 7, and writing to the sector address (6) is an error. Since it has already been determined that the physical sectors 5 and 6 are malfunctioning, it is determined that writing to the next sector address (6) when writing to the physical sector 7 is clearly an error, and the sector address Write to (7). Thereafter, each physical sector is written to the correct sector address in the RAM unless there is a loss in the digital data read from the disk.
[0031]
When such writing is performed, as is apparent from FIG. 8 (c), writing is not performed at the sector address (6), and the physical sector of the past ECC block in which error correction has already been performed for all rows remains. Will be. In addition, each row of the physical sectors 5 and 6 is written in an incorrect selector address (5) and (6), respectively.
[0032]
Further, regarding the sector address (3), there may be a case where the error-corrected row of the physical sector of the past ECC block still remains. This will be described with reference to FIG. 8 (d). In FIG. ₁ , 3 ₂ , 3 _Three , ... and each row of physical sector 4 is 4 ₁ , 4 ₂ , 4 _Three , ..., here, row 3 of physical sector 3 ₉ Row 4 of physical sector 4 from the middle of ₁₁ The middle of this shall continue. In addition, the addresses of each row of sector address 3 are (1), (2), (3),.
[0033]
Therefore, each row 3 of the physical sector 3 is sequentially assigned to the addresses (1) to (8) of the sector address 3. ₁ ~ 3 ₈ Is written, but at address (1), row 3 of physical sector 3 ₉ Row 4 of physical sector 4 from the middle of ₁₁ Is written, followed by line 4 ₁₂ , 4 ₁₃ Are written to the row addresses (10) and (11), respectively. Then, since the next physical sector 5 is written to the next sector address 4, writing is not performed at the row addresses (12) and (13) at the sector address 3, and the past ECC block which has already been error-corrected. The data of the physical sector row remains. Also, row 4 of physical sector 4 ₁₁ ~ 4 ₁₃ Will be written to the wrong row address of the wrong sector address.
[0034]
In the case of PI correction, the digital data written in the RAM is corrected for each row, the position of the error that cannot be corrected is detected, and erasure correction is performed by the PO code based on the position of the error. However, in the sector address (6) shown in FIG. 8 (c) and the row addresses (12) and (13) shown in FIG. 8 (d), the row data in which the error has already been corrected is written. In many cases, it is not detected that the line is in error even though is erroneous. That is, it is unlikely that many errors that make such a row an error position at the time of PO erasure correction are detected from the PI code.
[0035]
From the above, in the conventional reproducing apparatus, there is a problem in determining the position of the PO erasure correction error only from the result of PI correction in terms of the reliability of the data after reproduction, and countermeasures are necessary. It becomes.
[0036]
The present invention has been made in view of the above points, and is a digital data reproduction apparatus and reproduction that can correctly detect an error position for erasure correction even if the above data discontinuity occurs. It is to provide a method.
[0037]
[Means for Solving the Problems]
In order to achieve the above object, the present invention adds a SYNC code regularly added to digital data at the time of modulation and a reliability flag indicating the situation at the time of detection of ID and a digital data after demodulation processing on the RAM. Are combined with the write flag expected value of the write flag added to the digital data read out for error correction from the RAM to determine the error position at the time of erasure correction.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0039]
FIG. 1 is a block diagram showing a first embodiment of a digital data reproducing apparatus and reproducing method according to the present invention, wherein 1 is an optical disk, 2 is an optical pickup, 3 is a spindle motor, 4 is a servo circuit, and 5 is a read channel. Circuit, 6 is a digital data decoder, 7 is a demodulation circuit, 8 is a write flag / write flag expected value count circuit, 8a is a write flag counter, 8b is a write flag expected value counter, 9 is a RAM control circuit, and 9a to 9b are RAM A counter, 10 is a RAM, 11 is an error correction circuit, 12 is a descrambling circuit, 13 is an error detection circuit, 14 is an output circuit, 15 is a RAM, 16 is a microcomputer (hereinafter referred to as a microcomputer), and 17 is an interface.
[0040]
In the figure, the digital data is recorded on the optical disc 1 as described with reference to FIGS. Such an optical disk 1 is rotated by a spindle motor 3 controlled by a servo circuit 4, and digital data is read out from the optical disk 1 as an analog reproduction signal by an optical pickup 2 controlled by the servo circuit 4.
[0041]
The analog reproduction signal read from the disk 1 by the optical pickup 2 is subjected to processing such as waveform equalization processing, binarization, and synchronous clock generation in the read channel circuit 5, and is then supplied to the digital data decoder 6 for data Digital processing such as demodulation and error correction is performed. The digital data decoder 6 inputs and outputs data with a host device (not shown) under the control of the interface 17. The microcomputer 16 controls the entire system.
[0042]
Next, the digital data decoder 6 will be described.
[0043]
The digital data composed of the physical sector 308 shown in FIG. 7 output from the read channel circuit 5 is supplied to the demodulation circuit 7 and the SYNC code 701 added for each SYNC frame is separated and 8/16 inverse modulated. 6 is demodulated into digital data comprising the recording sector 307 shown in FIG. Further, every time the demodulation circuit 7 demodulates to an ECC block of 208 rows × 182 bytes shown in FIG. 6, it generates an ECC block demodulation end signal as shown in FIG. 9C, and write flag / write flag expectation. The value is supplied to the value count circuit 8 and the RAM control circuit 9.
[0044]
The write flag / write flag expected value count circuit 8 includes a write flag counter 8a and a write flag expected value counter 8b, and the value of the write flag counter 8a sequentially changes every time this ECC block demodulation end signal is supplied. A write flag is generated and supplied to the demodulation circuit 7. FIG. 9B shows the operation of the demodulation circuit 7 in units of ECC blocks. _D Represents a demodulation processing period of one ECC block of the demodulation circuit 7.
[0045]
FIG. 10 is a block diagram showing a specific example of the demodulation circuit 7 in FIG. 1, in which 7a is a protection function-equipped SYNC code detection circuit, 7b is an 8/16 inverse modulation circuit, 7c is a protection function-equipped ID detection circuit, and 7d. Is an address generation circuit, and 7e is an output circuit.
[0046]
In the figure, the digital data from the read channel circuit 5 is supplied to the protection function-equipped SYNC code detection circuit 7a, and the SYNC code 701 is separated for each physical sector 308 shown in FIG. The separated SYNC code 701 is supplied to the address generation circuit 7d. Also, the digital data from which the SYNC code 701 has been separated is 8/16 inverse modulated by the 8/16 inverse modulation circuit 7b, demodulated into digital data comprising the recording sector 307 shown in FIG. 6, and output circuit 7e and ID with protection function It is supplied to the detection circuit 7c. In the ID detection circuit with protection function 7c, when the SYNC code 701 of SYNC indicating the head of the physical sector 308 is separated by the SYNC code detection circuit with protection function 7a, 8/16 reverse modulation is performed based on the timing of this SYNC. The ID 301 (FIG. 4) added to the first row of each recording sector 307 is detected from the digital data demodulated by the circuit 7b and supplied to the address generation circuit 7d.
[0047]
By the way, once the SYNC code 701 and ID 301 are detected, the sector structure and the row in the ECC block 503 can be specified from the pattern structure and value. Therefore, if several lines are read, it is possible to predict the position and pattern (value) of the SYNC code 701 in the digital data that is subsequently input using the periodicity of the lines. Similarly to the SYNC code 701, the ID 301 also has continuity in its value and periodicity of appearance (position predicted from the timing of the SYNC code 701 of SYNC (FIG. 7)). The value (sector number) and position can be predicted. Therefore, when the SYNC code 701 or ID 301 is detected, the position and value of the next SYNC code 701 or ID 301 are predicted, so that even if there is an error in the SYNC code 701 or ID 301, these are detected from the digital data. Can do.
[0048]
In the protection function-equipped SYNC code detection circuit 7a, all the patterns of the SYNC code 701 (SYNC 0 to SYNC 7 in FIG. 7) are registered. The SYNC code 7a detected from the input digital data A and these registered patterns Compare with In this case, of the registered patterns, the pattern predicted as described above is used as a reference pattern, and first, the detected pattern is compared with this reference pattern. When they match or when there is a certain degree of mismatch of several bits or less, it is assumed that the predicted SYNC code 701 is detected, and the SYNC code 701 of the reference pattern is sent to the address generation circuit 7d.
[0049]
If the number of bits that do not match between the pattern of the SYNC code detected from the input digital data and the reference pattern is very large or does not match at all, the detected pattern of the SYNC code 701 is used as a reference. Compare with other patterns. When the pattern of the detected SYNC code 701 is a pattern completely different from these patterns, the detected SYNC code 701 is a SYNC code having a predicted pattern, but includes a large error. The SYNC code 701 of the reference pattern is sent to the address generation circuit 7d.
[0050]
The above is the case where the predicted SYNC code 701 is detected from the input digital data A, but the pattern of the SYNC code 701 detected from the input digital data A does not match the reference pattern, and 1 of the other patterns. SYNC code 701 that is different from the predicted SYNC code is detected from the input digital data A.
[0051]
In this way, the SYNC code detection circuit 7a with the protective function detects the SYNC code 701 predicted from the input digital data A so far, but detects the SYNC code 701 different from the suddenly predicted SYNC code. When this occurs, the detected SYNC code 701 is not immediately supplied as correct to the address generation circuit 7d, but a predetermined period of time is set in advance, which may indicate that there is an error in the determination of the detected SYNC code 701. The detected SYNC code 701 corresponds to a pattern other than the predicted reference pattern even after that period, and the SYNC code 701 pattern sequentially detected within the predetermined period changes continuously. The detected SYNC code 701 is correct and the data Such as by determining that that sequence of SYNC code 701 deviates from the sequence shown in FIG. 7 successful, sends the SYNC code of the most matching patterns in the address generating circuit 7d thereto. In this predetermined period, even if the pattern of the detected SYNC code 701 matches with a pattern other than the predicted reference pattern, it is sent to the address generation circuit 7d as the SYNC code of the reference pattern.
[0052]
The predetermined period is set every time the detected SYNC code 701 is determined to be correct in the reference pattern, and the detected SYNC code 701 matches the pattern other than the reference pattern. When it is determined that the predetermined period is set, the predetermined period set at this time is continued as it is. A new predetermined period is set together with the detection and determination of the first SYNC code 701 after the predetermined period has elapsed.
[0053]
In this way, even if an error or a pattern comparison malfunction occurs, and the detected correct SYNC code 701 coincides with a pattern other than the reference pattern, the correct SYNC is generated. A protection function that prevents the code 701 from being overlooked is provided in the protection function-equipped SYNC code detection circuit 7a. For example, even if the first detected SYNC code 701 matches a pattern other than the predicted reference pattern within the predetermined period, the next detected SYNC code 701 is When they match, the SYNC code 701 detected first is also a SYNC code that should have the predicted reference pattern at that time, and a pattern other than the reference pattern due to an error or misjudgment. Is consistent. The protection function prevents the SYNC coat 701 from being overlooked.
[0054]
The predetermined period is hereinafter referred to as a SYNC code detection protection valid period, which is set to an integral multiple of the period length of the SYNC frame (FIG. 7). In the following, the SYNC code detection protection effective period is represented by an integer. For example, “SYNC code detection protection effective period is 2” is a period twice the period length of the SYNC frame. The SYNC code 701 is detected twice from the input digital data A.
[0055]
The protection function-equipped SYNC code detection circuit 7a generates information (SYNC code detection status information) indicating such a detection status of the SYNC code 701, and supplies this to the address generation circuit 7d. This SYNC code detection status information indicates whether or not the SYNC code 701 has been detected using a protection function.
[0056]
The same applies to the protection function-equipped ID detection circuit 7c, in which all ID 301 values (specifically, the sector number 402 (FIG. 4B)) are registered, and the predicted ID 301 value is used as a reference value. / 16 by comparing the ID 301 detected from the digital data B from the inverse modulation circuit 7b with these values, it is determined whether or not the predicted ID 301 has been detected, and in the SYNC code detecting circuit 7a with protection function When the ID detection protection effective period corresponding to the SYNC code detection protection effective period is set and the ID 301 detected from the digital data B from the 8/16 inverse modulation circuit 7b matches a value other than the reference value, this ID 301 is simply It is determined whether the ID 301 is discontinuous due to an error, a determination error, or missing data. And it has a protective function that is to be.
[0057]
Also in this case, the ID detection protection effective period is expressed as an integer multiple of the period of ID 301 (that is, the period length of the recording sector 307 (FIG. 6)). For example, “ID detection protection effective period is 2” Since the detected ID 301 is determined to be correct, the period length is twice the period of the ID 301.
[0058]
The protection function-equipped ID detection circuit 7c supplies the ID 301 to the address generation circuit 7d, creates ID detection status information indicating the detection status of the ID 301 and supplies the ID detection status information to the address generation circuit 7d.
[0059]
Here, each of the SYNC code detection status information and the ID detection status information is whether or not the SYNC code 701 and ID 301 are detected and generated using the protection function, and is detected and generated using the protection function. Sometimes the SYNC code 701 and ID301 are
(I) Whether there is a mismatch of several bits or less with respect to the reference pattern or reference value, or a complete mismatch
(Ii) Whether it matches a pattern or value other than the reference pattern, or there is no matching pattern
This indicates the detection status.
[0060]
The address generation circuit 7d creates a row number C through the ECC block for each row on the basis of the SYNC code 701 from the protection function-equipped SYNC code detection circuit 7a and the ID 301 from the protection function-equipped ID detection circuit 7c, and outputs it. Send to circuit 7e. Here, as described above, since the sector number added to the top row in the top recording sector 307 of the ECC block is divisible by 16, the sector number 402 of ID 301 from the ID detection circuit with protection function 7c is set to 16 When this is divisible, the first line number C is given with the detected line as the first line of the ECC block, and the line head is added each time the supplied SYNC code 701 is supplied. The line number C assigned to this is increased.
[0061]
Further, the address generation circuit 7d generates a reliability flag D for each row based on the SYNC code detection status information from the protection function-equipped SYNC code detection circuit 7a and the ID detection status information from the protection function-equipped ID detection circuit 7c. Is supplied to the output circuit 7e. The reliability flag D corresponds to the detection status indicated by the SYNC code detection status information and the ID detection status information, and is used for PI correction in the error correction circuit 11 (FIG. 1) described later. Here, the reliability flag D is set in accordance with the detection status indicated by the SYNC code detection status information or the ID detection status information in the SYNC code 701 or ID 301 of the protection function-equipped SYNC code detection circuit 7a or the protection function-ID detection circuit 7c. To detect
When many protection functions are used, many protection functions are used.
When a little protection function is used, use protection function (small)
When no protection function is used, protection function is used (none)
To have the information content.
[0062]
As an example, the reliability flag D of protection function use (low) is detected in the same line, and at least one of the protection function-equipped SYNC code detection circuit 7a and the protection function-equipped ID detection circuit 7c uses the protection function to detect. In comparison with the reference pattern or the reference value, as described above, the non-matching of several bits or less represents a certain degree, and the reliability flag D for the use of the protection function (many) is also the SYNC with protection function. At least one of the code detection circuit 7a and the ID detection circuit with protection function 7c performs detection using the protection function, and in comparison with the reference pattern or reference value, it is inconsistent in most bits, or the reference pattern or reference value It shall represent a pattern that matches or does not match any other pattern or value. As another example, the reliability flag D of the protection function use (low) is the same line, and either the protection function-equipped SYNC code detection circuit 7a or the protection function-equipped ID detection circuit 7c (or the protection function-equipped). Only the SYNC code detection circuit 7a) represents a case in which the protection function is used, and the reliability flag D for the use of the protection function (multiple) is the same between the SYNC code detection circuit with protection function 7a and the ID detection circuit with protection function 7c. A case where both (or only the protection function-equipped ID detection circuit 7c) use the protection function may be represented.
[0063]
Based on the former example, when the reliability flag D of each row in the digital data shown in FIGS. 8C and 8D is applied, both the SYNC code detection protection effective period and the ID detection protection effective period are set. 2, in the physical sectors 5 and 6 following the physical sector 3 (because the physical sector 4 between them is from the middle, the SYNC code 701 matches the reference pattern). However, ID 301 does not match the reference value at all (even if it matches the value of ID 301 other than the reference value). Therefore, the reliability flag D in each row of the physical sectors 5 and 6 is the use of the protection function (many). Further, row 4 shown in FIG. ₁₂ , 4 ₁₃ Then, the SYNC code 701 does not match the reference pattern at all. Therefore, these lines 4 ₁₂ , 4 ₁₃ The reliability flags D are used for the protection function (many).
[0064]
Each time the digital data demodulated from the 8/16 inverse modulation circuit 7b is supplied to one row of the recording sector 307, the output circuit 7e supplies the reliability flag D and the write flag / write for this row supplied from the address generation circuit 7d. The demodulated information including the write flag for this row supplied from the expected flag count circuit 8 (FIG. 1) is added, and the demodulated output data E is the RAM control together with the row number C for this row from the address generation circuit 7d. This is supplied to the circuit 9 (FIG. 1).
[0065]
FIG. 11A shows one physical sector 1001 of the input digital data A to the demodulation circuit 7 and has the same configuration as that shown in FIG. However, SY _X Is one of the patterns SYNC0 to SY4 (FIG. 7) of the SYNC code 701, and SY _Z Is one of the patterns SY5 to SY7. FIG. 11B shows the demodulated output data E of one recording sector 307. Demodulation information 1003 consisting of a reliability flag and a write flag is added to row data 1002 consisting of 182 bytes.
[0066]
The output circuit 7e monitors the line number C from the address generation circuit 7d, detects the line number C indicating the last line of the ECC block, and outputs the demodulated output data E of the last line. As described in FIGS. 9B and 9C, the ECC block demodulation processing end signal is output and supplied to the write flag / write flag expected value count circuit 8 and the RAM control circuit 9 in FIG.
[0067]
Next, returning to FIG. 1, the RAM control circuit 9 is supplied with the demodulated output data E, the row number, and the ECC block demodulation processing end signal (FIG. 10) from the demodulating circuit 7, and these row numbers and A write address for each row is created based on the ECC block demodulation processing end signal, and this demodulated output data E is written to the RAM 10 for each row. At the time of this writing, the RAM control circuit 9 cancels the interleaving applied to the PO 502 in units of ECC blocks consisting of 16 recording sectors 307 as shown in FIG. 6, and in the form of the ECC block 503 shown in FIG. Stored in In this case, of course, the demodulation information 1003 shown in FIG. 11 is added to each row.
[0068]
FIG. 12 is a diagram showing a specific example of a data array in the RAM 10.
In the figure, the RAM 10 has n areas 0 to n−1, and ECC blocks to which demodulation information 1003 is added are written one by one. Since each area has an address in units of rows and one ECC block is composed of 208 rows, 208 addresses are set in one area. The preceding and following ECC blocks are stored in adjacent areas, but the address of the area in which the row with the same row number of the preceding and following ECC blocks is stored differs by the value 208 of the number of rows of one ECC block. The ECC blocks are written in the areas 0, 1, 2,... In the order demodulated by the demodulating circuit 7, but the write address for such writing is given by the RAM control circuit 9 to the row number. And the ECC block demodulation processing end signal.
[0069]
The RAM control circuit 9 is provided with a RAM counter 9 a that counts the ECC block demodulation end signal from the demodulation circuit 7 and generates information representing an area in the RAM 10 that is allocated to the ECC block demodulated by the demodulation circuit 7. ing. The area in the RAM 10 is designated by the count value of the RAM counter 9a, and the write address of the row in the area designated by the count value of the RAM counter 9a and the row number from the demodulation circuit 7 is determined. FIG. 9 (h) shows the count value of the RAM counter 9a.
[0070]
In FIG. 9, n is the total number of areas of the RAM 10 shown in FIG. Therefore, the operation in units of ECC blocks of the demodulation circuit 7 shown in FIG. 9B and the count value of the RAM counter 9a shown in FIG. Yes.
[0071]
On the other hand, the write flag of the demodulation information 1003 added to each row and recorded in the RAM 10 indicates that the data in the row is newly written in the RAM 10 and has a continuous value. Is. That is, when data of a certain row is read from the RAM 10, if the write flag read together with the data has a correct value, this data is newly written data in the RAM 10.
[0072]
Returning to FIG. 1, when the ECC block data is written in the RAM 10, the RAM control circuit 9 reads the ECC block in units of rows and supplies it to the error correction circuit 11 to perform PI correction and PO correction. In this case, the PI-corrected row data is once written in the RAM 10, and when the entire ECC block has been subjected to PI correction, the ECC block data is read again from the RAM 10 and the error correction circuit 11 performs PO correction. . The PO-corrected data becomes a data sector 305 having a format as shown in FIG. 4C and is written in the RAM 10 again.
[0073]
FIG. 9D shows the operation of the error correction circuit 11 in units of ECC blocks. The time required for error correction of one ECC block is shorter than the time required for demodulating the input of one ECC block in the demodulation circuit 7. For this reason, when the demodulated data of one ECC block is written into the RAM 10, that is, when the ECC block demodulation processing end signal is supplied from the demodulation circuit 7, the error correction processing of the ECC block is immediately performed. The RAM control circuit 9 generates an ECC block error correction processing end signal as shown in FIG. 9E every time the ECC block error correction processing ends.
[0074]
In addition, the RAM control circuit 9 is provided with a RAM counter 9b indicating which area of the ECC block of the RAM 10 is subjected to error correction processing, and counts up by the ECC block error correction processing end signal. FIG. 9 (i) shows the count value of the RAM counter 9b.
[0075]
The ECC block which has been error-corrected as described above and once written in the RAM 10 is immediately read out from the RAM 10 and processed by the output processing unit including the descrambling circuit 12, the error detection circuit 13, and the output circuit 14, and the interface 17 Is output to the outside. The time required for this output processing unit to process one ECC block is also shorter than the time required for demodulation by the demodulation circuit 7 to input one ECC block. For this reason, as shown in FIG. 9 (f), the ECC block is immediately read from the RAM 10 when the error correction processing is completed and the ECC block error correction processing end signal is generated. Is processed and output to the outside. The RAM control circuit 9 outputs an ECC block output process end signal each time an error-corrected ECC block is read from the RAM 10.
[0076]
Here, the RAM control circuit 9 is further provided with a RAM counter 9c indicating which area of the RAM 10 is being subjected to output processing, and counts up according to the ECC block output processing end signal. FIG. 9 (j) shows the count value of the RAM counter 9c.
[0077]
The RAM control circuit 9 also supplies the generated ECC block error correction processing end signal to the write flag / write flag expected value count circuit 8 in FIG. In the write flag / write flag expected value count circuit 8, the write flag expected value counter 8b counts the ECC block error correction processing end signal, and generates a write flag expected value that continuously increases. The expected value of the write flag is supplied to the error correction circuit 11, and when the data of the row read from the RAM 10 is PI-corrected by the error correction circuit 11, the write flag read from the RAM 10 together with the data of this row. When performing PI correction on the data in this row, in order to determine whether or not the data in this row has been newly written in the RAM 10, that is, it is not old data that has been corrected in the past. Used for.
[0078]
The timing of the write flag expected value generated by the write flag expected value counter 8b is set so as to be the same value as the write flag read from the RAM 10 simultaneously with the ECC block subjected to error correction processing by the error correction circuit 11. . In FIG. 9, it is assumed that an ECC block (hereinafter referred to as ECC block (n−1)) indicated as “n−1” is demodulated by the demodulation circuit 7 and written in the RAM 10 (this ECC block is The value of the write flag added to each row of each recording sector of the ECC block (n−1) is naturally written in the area (n−1) of the RAM 10, and FIG. 9B and FIG. ), It is m + 1. When the entire ECC block (n−1) is demodulated and writing to the RAM 10 is completed and then read from the RAM 10 for error correction (FIG. 9D), the write flag expected value at this time As shown in FIG. 9 (l), m + 1 is equal to the value m + 1 of the write flag added to each row of the ECC block (n-1) subjected to error correction processing. Thus, when they match, it is possible to detect that the demodulated ECC block is correctly written into the RAM 10 and read out from the RAM 10 for error correction processing.
[0079]
Conventionally, the write flag is a 1-bit flag, and the 1-bit write flag is simultaneously written in the RAM together with the writing of the row data. When reading this, the write flag is also read simultaneously. If this write flag can be read, the data in this row is subjected to error correction as newly written data, and the write flag is read and the write flag is erased in the RAM. On the other hand, in this embodiment, the write flag is written in the RAM 10 together with the row data as a multi-bit flag whose value sequentially changes for each ECC block, and the write flag read together with this data is compared with the write flag expected value. Thus, it is determined that this data has been newly written to and read from the RAM 10. In this case, since the value of the write flag and the write flag expected value are successively changed for each ECC block, the write flag having a value older than the current write flag expected value is a past one. It is clear that the data in the row to which this is added is old data. For this reason, even if an old write flag remains in the RAM 10, it can be read and determined as old data, and this does not pose any problem. Therefore, in this embodiment, the operation of erasing the write flag from which row data has been read is not necessary in the RAM 10, and the control operation is simplified.
[0080]
The microcomputer 16 also monitors the processing operation of the digital data decoder 6. If error correction cannot be performed during data processing, the microcomputer 16 returns to the original reading position from the optical disk 1 and performs reading again from there. In such a case, as shown in FIG. 9A, data demodulated by the demodulator circuit 7, data stored in the RAM 10, error correction, etc. The circuit 11 generates a RAM counter reset signal that invalidates the correction and the data therein. Therefore, as shown in FIGS. 9H to 9J, the RAM counters 9a to 9c in the RAM control circuit 9 are reset to 0 by the RAM counter reset signal (however, the RAM counter reset signal does not necessarily The RAM counters 9a to 9c do not need to be reset to 0, and may be reset to other values, in which case rewriting is performed from the area of the RAM 10 corresponding to the value. Here, as described above, the RAM counters 9a to 9c are described as being reset to 0). When the digital data starts to be read from the optical disc 1, the digital data is demodulated by the demodulation circuit 7, and then written from the head area 0 to the RAM 10 in units of ECC blocks. Thereafter, the above operation is performed.
[0081]
Time t in FIG. ₀ Indicates the time when the RAM counter reset signal is generated. Here, the RAM counter reset signal is generated while the demodulated ECC block is being written in the area 2 of the RAM 10. At this time t ₀ Thus, the RAM counters 9 a to 9 c are reset to 0, and a new ECC block demodulated by the demodulation circuit 7 is written in the area 0 of the RAM 10. At this time, the count values of the RAM counters 9b and 9c are 0, but the ECC block demodulation processing end signal is not generated until the ECC block is written in the area 0 of the RAM 10, and the error of the ECC block is not generated. Since the ECC block error correction processing end signal is not generated until the correction is completed, reading from the RAM 10 for error correction and output processing is not performed. Therefore, even if the RAM counters 9a to 9c are reset by the RAM counter reset signal, each ECC block is always processed in the order of demodulation, error correction, and output processing.
[0082]
The RAM counter reset signal generated by the microcomputer 16 is also supplied to the write flag / write flag expected value count circuit 8. This RAM counter reset signal sets the write flag counter 8a to a fixed value (in this case, 0). The operation similar to the operation based on the ECC block demodulation processing end signal from the demodulation circuit 7 is performed instead of resetting to. That is, as shown in FIG. ₀ If the count value (write flag) of the write flag counter 8a is m + 4 immediately before ₀ The count value of the write flag counter 8a becomes the next m + 5 in response to the RAM counter reset signal generated in step S2. As shown in FIG. 9 (l), the write flag expected value counter 8b of the write flag / write flag expected value count circuit 8 has the same value as the count value of the write flag counter 8a at that time (ie, as shown in FIG. 9L). , M + 5). Thereafter, the write flag counter 8a and the write flag expected value counter 8b operate as described above.
[0083]
Time t reset by this RAM counter reset signal ₀ Thereafter, the ECC block demodulation processing end signal (FIG. 9 (c)) is not supplied until the first ECC block is written in area 0 of the RAM 10 with the m + 5 value write flag added, so the error correction processing is performed. Since no error correction processing is performed, no ECC block error correction processing end signal is generated, and no data after error correction is output from the RAM 10. Then, when the ECC block demodulation processing end signal is generated after the demodulation of the ECC block to which the write flag having the value m + 5 is added and the writing to the area 0 of the RAM 10 are completed, the write flag having the next m + 6 value is added. The demodulation of the ECC block and the writing to the area 1 of the RAM 10 are started, and the newly written ECC block is read from the area 0 of the RAM 10 and the error correction circuit 11 performs an error correction process. As described above, the value of the write flag added to the ECC block is m + 5. At this time, the write flag expected value is m + 5 as shown in FIG. Will do. When the error correction of the ECC block ends, as shown in FIG. 9E, an ECC block error correction processing end signal is generated, the write flag expected value becomes m + 6, and the write flag of the ECC block to be error-corrected next. It becomes a thing corresponding to. In this way, the write flag and the write flag expected value change sequentially.
[0084]
By the way, as described above, the write flag counter 8a and the write flag expected value counter 8b are not reset to a fixed value (0 in the specific example shown in FIG. 9) by the RAM counter reset signal. This is for a reason.
[0085]
That is, since the write flag is a flag for indicating that new data demodulated by the demodulation circuit 7 has been written in the RAM 10, the counter value (write flag) of the write flag counter 8a is reset by the RAM counter reset signal. If the RAM counter reset signal is generated twice or more within the time when the data of n ECC blocks are input, after the second and subsequent RAM counter reset signals are generated, the maximum The value of the write flag for n ECC blocks of data becomes the same as the value of the write flag written on the RAM 10 after the first reset, and the write flag becomes ineffective. In order to prevent this, as described above, when the RAM counter reset signal is generated, the write flag is preset to the next value, and the write flag expected value is preset to the same value as the write flag.
[0086]
Returning to FIG. 1, as described above, after the demodulation processing in the demodulation circuit 7, the data written in the format of the ECC block 503 (FIG. 5) together with the demodulation information 1003 in the format of the ECC block 503 (FIG. 5) After being written, when there is no access to the RAM 10 from the demodulation circuit 7 via the RAM control circuit 9, it is read out to the error correction circuit 11 according to the address created by the address generation circuit in the error correction circuit 11, Error correction processing for the ECC block 503 is performed in the order of PI correction and PO correction. As a result, an error of the PI code consisting of 182 byte rows continuously arranged in the order read from the optical disc 1 is corrected up to a maximum of 5 bytes. Further, at the time of this PI correction, demodulation information 1003 (FIG. 11) is read from the RAM 10 together with a PI code composed of 182 bytes and one row of data.
[0087]
13 is a block diagram showing a specific example of the error correction circuit 11 in FIG. 1, in which 11a is an input unit, 11b is an address generation circuit, 11c is an output circuit, 11d is an error position / value arithmetic circuit, 11e, 11f Is an error position pointer generation circuit, 11g is an error position pointer storage unit, and 11h is an error position decoder for erasure correction.
[0088]
In FIG. 11, an ECC block 503 read from the RAM 10 is input to an input unit 11a, and in order to perform PI correction, data corresponding to the PI code shown in FIG. 5 and demodulation information 1003 (FIG. 11). ) And are separated. One row of data corresponding to the PI code is supplied to the error position / value calculation circuit 11d, and error calculation such as syndrome calculation is performed to obtain an error position and value. It is supplied to the pointer generation circuit 11e.
[0089]
The number of errors included in the PI code detected by the error calculation in the error position / value calculation circuit 11d is supplied to the error position pointer generation (error number) circuit 11f, and based on the number of errors. In accordance with a predetermined algorithm, a 2-bit error position pointer P1 used as an error position in PO correction following PI correction or used to specify error data when error correction is impossible by PO correction Is generated.
[0090]
FIG. 14 is a flowchart showing an algorithm for generating the error position pointer P1.
[0091]
In the figure, the number i of errors obtained as a result of the above calculation processing in the error position / value calculation circuit 11d is determined (S (step) 1), and a 2-bit error position pointer P1 corresponding to the number i is obtained. Is set. Now, in PI correction, up to j errors can be corrected, and h <j <k,
When 0 ≦ i <h, P1 = 00 (S2)
When h ≦ i <j, P1 = 01 (S3)
When j ≦ i <k, P1 = 10 (S4)
When k ≦ i, P1 = 11 (S5)
And Here, as described above, when an error of the PI code consisting of a 182 byte line can be corrected up to a maximum of 5 bytes,
h = 4 j = 5 k = 6
And so on. Such processing is performed for each PI code in one row, and the obtained error position pointer P1 is stored in a unit of ECC block in the error position pointer storage unit 11g.
[0092]
Further, in the error position pointer generation (demodulation information) circuit 11e, according to the algorithm shown in FIG. 15, the write flag and write flag / write flag expected value count circuit 8 (FIG. 1) included in the demodulation information 1003 supplied from the input unit 11a. ) And the 2-bit error position pointer P2 is generated according to the comparison result and the demodulation reliability flag included in the demodulation information 1003.
[0093]
FIG. 15 is a flowchart showing an algorithm for generating the error position pointer P2.
[0094]
In the figure, first, the read flag is read from the RAM 10 together with the input PI code of one row, and the write flag is compared with the write flag expected value from the write flag expected value counter 8b (S10). In this case, as described above, the PI code read from the RAM 10 is old data)
Error position pointer P2 = 11 (S15)
And
[0095]
If the write flag matches the write flag expected value, the error position pointer P2 is determined using the reliability flag included in the demodulation information 1003 (FIG. 11). That is, the reliability flag is
When the protection function is used (none), the error position pointer P2 = 00 (S12)
When the protection function is used (low), the error position pointer P2 = 01 (S13)
When the protection function is used (many), the error position pointer P2 = 10 (S14)
And Such processing is for the PI code in the same row calculated by the error position / value calculation circuit 11d, and the error position pointer P2 obtained is stored in association with the error position pointer P1 in the error position pointer storage unit 11g. Is done.
[0096]
FIG. 16 is a diagram schematically showing a storage state of error position pointers P1 and P2 of one ECC block 207 rows in the error position pointer storage circuit 11g, and was obtained under different conditions for each row as shown. Error position pointers P1 and P2 are stored in association with each other.
[0097]
Each PI-corrected row is once written to the original address of the original area of the RAM 10, and when the data of the entire ECC block is PI-corrected and written to this area (at this time, the error position pointer storage circuit 11g The error position pointers P1 and P2 of all the rows of this ECC block are stored), and this ECC block is read again and subjected to PO correction processing by the error correction circuit 11.
[0098]
Therefore, in the error correction circuit 11 shown in FIG. 13, the PO code read from the RAM 10 is supplied from the input unit 11a to the error position / value calculation circuit 11d. This PO code is a 208-byte code in which 1-byte data of the same column is extracted from each row of the ECC block 503 shown in FIG. 5 and combined (this 1-byte data is hereinafter referred to as erasure correction position data). The PO correction is performed according to the algorithm shown in FIG.
[0099]
In FIG. 17, in this PO correction, first, an error in the PO code is detected by the error position / value arithmetic circuit 11d, and the error correction processing is switched according to the number i of detected errors (S30). ). That is, when no error is detected (i = 0), of course, no error correction processing is performed. However, when an error of up to 8 bytes from the PO code is detected, the error position / In the value arithmetic circuit 11d, error correction processing is performed by an arithmetic method for obtaining the position and value of these errors only from the syndrome (S31). If more errors are detected and the number is 9 to 16 bytes, two error position pointers P1 and P2 obtained by PI correction and stored in the error position pointer storage circuit 11g (FIG. 13) are used. An error position is calculated, and the error at that position is subjected to error correction processing by erasure correction (S32). When an error of 17 bytes or more is detected, the error is uncorrectable. As described above, in PO correction, an error of up to 16 bytes can be corrected.
[0100]
FIG. 18 is a flowchart showing a specific example of S32 in FIG.
[0101]
In the algorithm of FIG. 14 for creating the error position pointer P1, in PI correction, it is possible to correct up to j (j bytes) errors.
Although the PI code actually includes an error of i> j, it is erroneously detected as 0 ≦ i <j and j ≦ i <k, and erroneously corrects the data at the wrong position. May end up. In practice, the probability that an error of i> j is erroneously detected as an error of i ≦ j increases as the number increases from i = 0 to i = j. Therefore, the reliability of a PI code that has been subjected to PI correction of j ≦ i <k is generally lower than that of PI codes that have been subjected to other corrections. Therefore, the error position pointer P1 in this case is set to “10”, indicating that the reliability of the PI correction result of this PI code is lower than that of the other. In the specific example of S32 shown in FIG. 18, when there are more errors than the number that can be corrected by the syndrome, the error position pointer P1 = 11 indicating that correction was impossible by the PI correction and this error position pointer. Data included in the PI code (row) of P1 = 10 is a target of error correction using the PO code.
[0102]
Further, in the algorithm of FIG. 15 for creating the error position pointer P2, in a demodulation situation where the reliability flag indicates that the protection function is used (many), the protection function-equipped SYNC detection circuit 7a and the protection function-equipped ID detection circuit 7c (FIG. 10). With this operation, there is a high possibility that the PI code has been written at an incorrect position. Accordingly, in the specific example of S32 shown in FIG. 18, the data on the PO code included in the PI code (row) of the error position pointer P2 = 10 representing this case is old in which the write flag and the write flag expected value do not match. Along with the data on the PI code, the data is subject to correction in S32.
[0103]
In FIG. 18, regarding the error position, the number i of erasure correction position data satisfying either of the error position pointer P1 = 10 or 11 or the error position pointer P2 = 10 or 11 is obtained.
9 ≦ i <17
If this is the case (S40), erasure correction using these i erasure correction position data as errors is performed (S46). Taking FIG. 16 as an example, the erasure correction position data is
1,..., N-4, n-2, n-1, n, n + 1, n + 2,.
When the total number of these is 9 or more and 16 or less, erasure correction is performed using these as errors.
[0104]
When i ≧ 17, the number j of erasure correction position data to which either the error position pointer P1 = 10 or 11 or the error position pointer P2 = 11 is added is
9 ≦ j <17
If this is the case (S41), erasure correction is performed using these j erasure correction position data as error positions (S45). Taking FIG. 16 as an example, the erasure correction position data is
1,..., N-4, n-2, n, n + 1, n + 2,.
When the total number of these is 9 or more and 16 or less, erasure correction using these as error positions is performed.
[0105]
The number k of erasure correction position data to which at least one error position pointer of the PI frame of j ≧ 17 and error position pointer P1 = 11, or error position pointer P2 = 10 or 11 is added is
9 ≦ k <17
(S42), erasure correction is performed using these k erasure correction position data as error positions (S44). Taking FIG. 16 as an example, such a PI frame is:
1,..., N-2, n-1, n, n + 1, n + 2,.
When the total number of these is 9 or more and 16 or less, erasure correction using these as error positions is performed.
[0106]
Further, correction processing is not performed for PO codes that do not satisfy the conditions of S40 to S42 because the error position cannot be specified.
[0107]
As described above, in FIG. 13, the erasure correction of the PO code is performed using the error position pointers P1 and P2 stored in the error position pointer storage unit 11g. However, in the algorithm shown in FIG. Instead of using the value of the error position pointer stored in the pointer storage circuit 11g as it is, in order to determine an error position used in erasure correction, the error position pointer is partially errored by the error position decoder 11h for erasure correction. The value of the position pointer P2 is changed according to the system and then used. As a result, the reliability flag added by the demodulation circuit 7 can be used more efficiently, and more reliable error correction processing can be performed.
[0108]
Hereinafter, a specific example of the erasure correction error position decoder 11h will be described assuming that the error position pointer storage unit 11g stores the error position pointers P1 and P2 shown in FIG.
[0109]
In FIG. 16, in the n-th PI code, the error position pointer P2 = 11, and as is apparent from FIG. 15, the write flag does not match the write flag expected value and is composed of old data. It is. The following can be considered as a cause of occurrence of such a PI frame of the error position pointer P2.
[0110]
That is, as shown in FIG. 19 (a), when the digital data of 1 ECC block of 208 rows starting from the (m-1) row recorded on the optical disc 1 is read out, (m-2 ) Line and (m−1) line are missing, and as shown in FIG. 19B, data of m line, (m + 1) line, (m + 2) line,. Is read out.
[0111]
The demodulating circuit 7 (FIG. 1) demodulates the digital data shown in FIG. 19B as input data A. At this time, the SYNC code detection protection effective set by the protection function-equipped SYNC detecting circuit 7a (FIG. 10) is used. Assuming that the period and the ID detection protection effective period set by the ID detection circuit with protection function 7c (FIG. 10) are 2, respectively, as shown in FIG. 2 rows, i.e., m row and (m + 1) row are regarded as correct (m-2) row and (m-1) row following (m-1) row, respectively, and (m-3 ) Assign line numbers (n-2) and (n-1) following the line number (n-3) assigned to the line. However, when the detection protection effective period has passed and the immediately following line (here, (m + 2) line) is determined, this line is the (n + 2) th line, so this (m + 2) line Is assigned a row number (n + 2), and successive row numbers are assigned to subsequent rows as long as there are no missing rows.
[0112]
In the ECC block, as shown in FIG. 19C, a write flag having the same value X is added to each row.
[0113]
The demodulated ECC block shown in FIG. 19C is written at a row address corresponding to the row number of the designated area of the RAM 10 (FIG. 12) (here, for the sake of clarity, the row address As described with reference to FIG. 19C, since the row numbers (n) and (n + 1) are not used, the row addresses (n) and (n + 1) Data is not written. That is, data up to (m + 1) rows are sequentially written up to row address (n−1) (however, (m−2) and (m−1) rows are missing), from (m + 2) rows. Are written from the row address (n + 2), and the row addresses (n) and (n + 1) are skipped. Therefore, at the row addresses (n) and (n + 1) where the writing is skipped, old data remains, and the write flag in these has a value Y different from X.
[0114]
Thus, when the ECC block thus written in the area of the RAM 10 is subjected to PI correction for each PI code (row), the error position pointer P2 obtained thereby becomes PI frames (n), (n + 1) (that is, Since the write flag value X and the write flag expected value Y do not match in the PI numbers of the line numbers (n) and (n + 1), P2 = 11 as shown in FIG.
[0115]
Also, the PI frames (n-1) and (n-1) are detected because they have been advanced for two row periods by the protection function having the SYNC code detection protection effective period and the ID detection protection effective period of 2 as described above. The SYNC code 701 and the ID 301 are different from the reference pattern or the reference value. Therefore, the reliability flag in these PI frames (n-1) and (n-1) is the use of the protection function (many), and FIG. The error position pointer P2 is P2 = 10.
[0116]
In this way, as shown in FIG. 19F, the error position pointer P2 as shown in FIG. 16 is obtained.
[0117]
The error position pointer P2 obtained in this way is used as described in FIG. 18 to perform erasure correction at the time of PO correction. In FIG. 13, the error position pointer P2 is demodulated by the erasure correction error position decoder 11h. The error position pointer P2 is corrected according to the demodulation status of the circuit 7, and the error position pointer P2 after correction is used for erasure correction of the PO correction shown in FIG.
[0118]
Here, the error position pointer P2 by the erasure correction error position decoder 11h will be described by taking the error position pointer P2 shown in FIGS. 16 and 19F as an example.
[0119]
This is because there is a PI frame in which P2 = 11 due to a mismatch between the write flag and the write flag expected value, and the PI code including this PI frame is referred to by referring to the value of the error position pointer P2 of the PI frame preceding this PI frame. Uses a lot of protection functions of the ID301 or SYNC701 code at the time of demodulation (error position pointer P2 = 10), and if it is determined that the possibility of correct data input is low, this PI frame error The position pointer P2 is corrected by the erasure correction error position decoder 11h.
[0120]
That is, in the error position pointer P2 shown in FIG. 20A (this is the same as the error position pointer P2 shown in FIGS. 16 and 19F), the error position pointer P2 of the PI frame (n) is P2 = 11 and seeing the immediately preceding PI frame (n−1), the error position pointer P2 is P2 = 10. From this, the fact that the error position pointer P2 of the PI frame (n) is P2 = 11 indicates that the write flag and the write flag expected value do not match, and the PI frame (n) is old data, and the optical disk 1 is generated due to the lack of read data from 1. The demodulator 7 does not correctly input data immediately before the PI frame (n). As a result, the PI frame (n immediately before the PI frame (n) is not input. -1), it is expected that P2 = 10 indicating that the error position pointer P2 has used many protection functions is set. This is predicted from the PI frame in which the error position pointer P2 is P2 = 11 at least in the SYNC code or ID detection protection valid period. For the PI frame thus predicted, ( In FIG. 20A, as shown in FIG. 20B, the PI frame (n−1), (n)) and the error position pointer P2 are changed from P2 = 10 to P2 = 11.
[0121]
By correcting the error position pointer P2 in this way, data is lost and read from the optical disc 1, so that demodulation is performed as shown in PI frames (m) and (m + 1) shown in FIG. Although the ID 301 and the SYNC code 701 are correctly input to the circuit 7, due to the protection function of the ID 301 and the SYNC code 701, as shown in FIG. ), The problem that the position of the error cannot be correctly specified at the time of erasure correction can be improved.
[0122]
The above-described operation of the erasure correction error position decoder 11h is performed by the error position pointer P2 of the PI frame in the period length of the SYNC code or ID detection valid period before the PI frame where the error position pointer P2 = 11. When P2 = 10, the error position pointer P2 is changed to P2 = 11. However, the error position pointer P2 = 11 is changed from the PI frame in which the error position pointer P2 = 11 regardless of the length of the detection protection effective period. When the error position pointer P2 of one or more consecutively arranged PI frames is P2 = 10, the error position pointer P2 is changed to P2 = 11 for all of these P2 = 10 PI frames. It may be.
[0123]
Returning to FIG. 1, the corrected ECC block in the area of the RAM 10 designated by the RAM counter 9c of the RAM control circuit 9 is read out, and the data sector 305 having the configuration shown in FIG. The main data is descrambled every time, and the error detection circuit 13 performs error detection with an error detection code (EDC) for each data sector 304 having the configuration shown in FIG. The used processing is performed and output from the interface 17 to the outside.
[0124]
As described above, in the first embodiment, a reliability flag indicating the detection status at the time of demodulation processing of the SYNC code and ID regularly added to the digital data at the time of modulation, and the data after demodulation processing are stored on the RAM. The write flag indicating that the data was correctly written is combined with the flag indicating the result of PI correction, the error position is determined according to the problem occurrence status and system setting status, and the error is determined based on the determined error position. Since correction is performed, the ID and SYNC code protection function can be utilized for demodulation processing, and error correction can be performed while avoiding problems caused by the function.
[0125]
FIG. 21 is a block diagram showing a second embodiment of the digital data reproducing apparatus and reproducing method according to the present invention, in which 7 'is a demodulating circuit, 11A is an error correcting circuit for PI correction, and 11B is an error correcting circuit for PO correction. Therefore, portions corresponding to those in FIG.
[0126]
In the first embodiment, the PI correction and the PO correction are performed by the common error correction circuit 11, but in the second embodiment, these PI correction and PO correction are performed by a dedicated error correction circuit. It is something that is done in.
[0127]
In FIG. 21, a demodulating circuit 7 ′ for demodulating the digital data A from the read channel circuit 5 has the same configuration and function as the demodulating circuit 7 in FIG. 1, but a write flag / write flag expected value counting circuit. No write flag need be supplied from 8. Therefore, as a specific example of the demodulating circuit 7 ′, in the configuration shown in FIG. 10, the write flag is not supplied to the output circuit 7e. Therefore, the demodulated output data E output from the output circuit 7e includes 11 (b), the demodulation information 1003 does not include a write flag. Of course, also in the second embodiment, the write flag may be supplied to the demodulating circuit 7 '. In this case, the demodulating circuit 7' is the same as the demodulating circuit 7 in FIG. Become.
[0128]
Demodulated output data E from the demodulating circuit 7 'is supplied to the error correcting circuit 11a, and PI correction is performed for each PI code (row). In this PI correction, an error position pointer P1 is created according to the algorithm shown in FIG.
[0129]
FIG. 22 is a block diagram showing a specific example of the error correction circuit 11A. Parts corresponding to those in FIG.
[0130]
In this figure, this specific example, as described above, creates only the error position pointer P1 at the time of PI correction. Compared to the configuration shown in FIG. 13, an error position pointer generation circuit 11e, error position pointer storage. The configuration is such that the section 11g and the erasure correction error position decoder 11h are removed.
[0131]
With this configuration, the error position pointer P1 is generated according to the algorithm shown in FIG. 14 based on the number i of errors detected by the error position / value arithmetic circuit 11d, and the PI correction output from the output circuit 11c is performed. Along with the PI code, it is written into the RAM 10 (FIG. 21).
[0132]
When the write flag generated by the write flag / write flag expected value count circuit 8 is supplied to the error correction circuit 11A, the ECC block PI generated upon completion of PI correction in the ECC block by the address generation circuit 11b. The correction processing end signal is supplied to the write flag / write flag expected value count circuit 8 (FIG. 21), and the write flag / write flag expected value count circuit 8 changes in value for each ECC block PI correction processing end signal. A write flag is generated. This write flag is supplied to the output circuit 11c, added to the data after PI correction output from the output circuit 11c, and the RAM 10 (FIG. 21) together with the error position pointer P1 under the control of the RAM control circuit 9. Stored in
[0133]
Further, the ECC block PI correction processing end signal generated by the address generation circuit 11b is replaced by the RAM control instead of the ECC block demodulation processing end signal generated by the demodulation circuit 7 in the first embodiment shown in FIG. It is supplied to the circuit 9. The RAM control circuit 9 is also provided with a RAM counter corresponding to the RAM counter 9a shown in FIG. 1. This RAM counter counts the ECC block PI correction processing end signal, and the PI block of the ECC block whose PI has been corrected. An area in the RAM 10 is designated.
[0134]
Referring back to FIG. 21, when the ECC block after PI correction is written in the RAM 10, this ECC block is read from the RAM 10 under the control of the RAM control circuit 9, and supplied to the error correction circuit 11B for PO correction. Is done. When this PO correction is performed, the write flag expected value is supplied from the write flag / write flag expected value count circuit 8 and the write flag and reliability flag for each PI frame added to the ECC block read from the RAM 10 are displayed. The algorithm shown in FIG. 15 is used to generate an error position pointer P2. This error position pointer P2 and the previous error position pointer P1 are used for erasure correction of the algorithm shown in FIG.
[0135]
FIG. 23 is a block diagram showing a specific example of the error correction circuit 11B. Parts corresponding to those in FIG.
[0136]
In this figure, this specific example uses the error position pointer P1 created by the PI correction at the time of PO correction as described above, and also creates the error position pointer P2, which is shown in FIG. In this configuration, the error position pointer generation circuit 11f is removed.
[0137]
With this configuration, the reliability flag read from the RAM 10 and the error position pointer P1 are separated by the input unit 11a and supplied to the error position pointer generation circuit 11e, and the write flag from the write flag / write flag expected value count circuit 8 is supplied. The error position pointer P2 is generated by executing the algorithm shown in FIG. 15 from the expected value. The error position pointer P2 is supplied to the error position pointer 11g together with the error position pointer P1 read from the RAM 10 and separated by the input unit 11a, and stored in the same manner as in the first embodiment. The erasure correction by the PO correction is performed in the same manner as in the first embodiment.
[0138]
The address generation circuit 11b generates an ECC block PO correction process end signal every time PO correction of the ECC block is completed. In FIG. 21, the RAM control circuit 9 includes a RAM counter similar to the RAM counter 9b in the RAM control circuit 9 in FIG. 1, and this RAM counter counts the ECC block PO correction processing end signal, Next, an area in the RAM 10 of the ECC block to be PO corrected is designated. The ECC block PO correction processing end signal is supplied to the write flag / write flag expected value count circuit 8, and the write flag expected value is changed every time the ECC block PO correction processing end signal is supplied.
[0139]
The subsequent steps are the same as those of the first embodiment shown in FIG. 1, and the same effects as those of the first embodiment can be obtained.
[0140]
In each of the above embodiments, digital data reproduced from an optical disk has been described as an example. However, the present invention is not limited to such an embodiment, and various modifications may be made without departing from the gist of the present invention. Needless to say, it can be implemented.
[0141]
【The invention's effect】
As described above, according to the present invention, a reliability flag indicating the detection status at the time of demodulation processing of a SYNC code or ID regularly added to digital data at the time of modulation, or data on the RAM after demodulation processing A write flag indicating correct writing and a flag (error position pointer) indicating the result of PI correction are combined, and the error position is determined according to the problem occurrence status and system setting status. Since erasure correction is performed based on the error position, it is possible to obtain demodulated data with excellent reliability.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a digital data reproducing apparatus and reproducing method according to the present invention.
FIG. 2 is a diagram showing a configuration of an information area of a single layer DVD.
FIG. 3 is a diagram showing a configuration in the process of forming a sector of digital data to be recorded on a DVD.
FIG. 4 is a diagram showing a configuration of a data sector and an ID added to the data sector.
FIG. 5 is a diagram showing a configuration of an ECC block formed from 16 data sectors shown in FIG. 4;
6 is a diagram showing a configuration of an ECC block composed of 16 recording sectors after interleaving of the ECC block shown in FIG. 5;
7 is a diagram showing a configuration of a physical sector obtained by adding 8/16 modulation and a SYNC code to the recording sector shown in FIG. 6;
FIG. 8 is a diagram schematically showing RAM writing in a conventional digital data reproducing apparatus when there is data loss in digital data read from an optical disc.
FIG. 9 is a timing chart showing the operation of each circuit of the digital data decoder in FIG. 1;
10 is a block diagram showing a specific example of the demodulation circuit in FIG. 1. FIG.
11 is a diagram showing a data configuration of input data and output data in the demodulation circuit shown in FIG.
12 is a diagram showing a specific example of data arrangement on a RAM for error correction in FIG. 1. FIG.
13 is a block diagram showing a specific example of the error correction circuit in FIG. 1. FIG.
14 is a flowchart showing an algorithm of a method for creating an error position pointer P1 at the time of PI correction in the error correction circuit shown in FIG.
15 is a flowchart showing an algorithm of a method for creating an error position pointer P2 at the time of PI correction processing in the error correction circuit shown in FIG.
16 is a diagram showing an arrangement of error position pointers P1 and P2 obtained by the algorithms of FIGS. 14 and 15 in the position pointer storage circuit in FIG.
17 is a flowchart showing an algorithm of PO correction processing in the error correction circuit shown in FIG. 13;
FIG. 18 is a flowchart showing an algorithm for determining the position of the PO erasure correction error in S (step) 32 in FIG. 17;
FIG. 19 is a diagram illustrating a process in which the error position pointer P2 illustrated in FIG. 16 is obtained.
20 is a diagram for explaining an operation example of an erasure correction error position decoder in FIG. 13; FIG.
FIG. 21 is a block diagram showing a second embodiment of a digital data reproducing apparatus and reproducing method according to the present invention.
22 is a block diagram showing a specific example of an error correction circuit for PI correction in FIG. 21. FIG.
23 is a block diagram showing a specific example of an error correction circuit for PO correction in FIG. 21. FIG.
[Explanation of symbols]
1 Optical disc
2 Pickup
3 Spindle motor
4 Servo
5 Read channel
6 Digital data decoder
7 Demodulation circuit
8 Write flag / write flag expected value count circuit
8a Write flag counter
8b Write flag expected value counter
9 RAM control circuit
9a-9c RAM counter
10 RAM
11, 11a, 11b Error correction circuit
12 Descramble circuit
13 Error detection circuit
14 Output circuit
15 RAM
16 Microcomputer
17 Interface

Claims (14)

Demodulating means for demodulating digital data composed of a plurality of data blocks to which an error correction code is added in a data arrangement order different from the data sequence for generating the error correction code; and temporarily storing the demodulated digital data In a digital data reproducing apparatus comprising storage means and error correction means for detecting or correcting an error contained in the digital data using the error correction code for the demodulated digital data,
A first counter whose counter value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction unit corrects one block error of the data block;
The storage means stores the count value of the first counter in association with the data block demodulated by the demodulation means,
The error correction method using the said error Ri correction code said error Ri correction means, disappeared in accordance with the comparison result of the count value and the count value of the second counter of the counter first read from the storage means A digital data reproducing apparatus comprising a process of changing the number of errors to be corrected . Demodulating means for demodulating digital data composed of a plurality of data blocks to which an error correction code is added in a data arrangement order different from the data sequence for generating the error correction code; and temporarily storing the demodulated digital data In a digital data reproducing apparatus comprising storage means and error correction means for detecting or correcting an error contained in the digital data using the error correction code for the demodulated digital data,
A first counter whose counter value changes each time the demodulating means demodulates the data block by one and stores it in the storage means;
A second counter whose count value changes each time the error correction unit corrects one block error of the data block;
The storage means stores the count value of the first counter in association with the data block demodulated by the demodulation means,
The error correction method using the said error Ri correction code said error Ri correction means, disappeared in accordance with the comparison result of the count value and the count value of the second counter of the counter first read from the storage means A digital data reproducing apparatus comprising a process of changing the number of errors to be corrected . The digital data reproducing apparatus according to claim 1 or 2,
Use the error correction code including a process of changing the number of errors erasure correcting in accordance with the comparison result between the count value of the count value and the second counter of the first counter read out from said memory means The digital data reproducing apparatus is characterized in that the error correction method is erasure correction for determining an error position to be erasure corrected in the digital data according to the comparison result. The identification data is added according to a certain rule, and after the error correction code is added, the data sequence is different from the data sequence that generates the error correction code, and the synchronization signal is added according to the certain rule. A sequence of data blocks formed as input digital data, the synchronization signal and the identification data included in the digital data are detected, and the digital data is different from a data sequence for generating the error correction code Demodulation means for demodulating in this order; storage means for temporarily storing the demodulated digital data; and detecting errors contained in the digital data using the error correction code for the demodulated digital data or In a digital data reproducing apparatus provided with error correcting means for correcting,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction means performs one block error correction processing on the data block;
The demodulation means generates information indicating the detection status of the synchronization signal and the identification data in association with the data block,
The storage means stores the data block demodulated by the demodulation means, the information generated by the demodulation means, and the count value of the first counter,
The error correction method using the error correction code of the error correction means includes the detection status of the synchronization signal and the identification data based on the information read from the storage means, and the first status read from the storage means. A digital data reproducing apparatus comprising a process of changing the number of errors to be corrected for erasure in accordance with a comparison result between a count value of one counter and a count value of the second counter. Demodulating means for demodulating digital data composed of a plurality of data blocks to which an error correction code is added in a data arrangement order different from the data sequence for generating the error correction code; and temporarily storing the demodulated digital data A digital data reproduction method for a digital data reproduction apparatus comprising storage means and error correction means for detecting or correcting an error contained in the digital data using the error correction code for the demodulated digital data. And
A first count process for changing a count value every time the demodulating means demodulates one block of the data block;
A second count process for changing a count value each time the error correction unit corrects one block error of the data block;
A process of associating the data block demodulated by the demodulating means with the result of the first counting process;
Using the error correction code for changing the number of errors to be erasure corrected according to the comparison result between the result of the first count process associated with the demodulated data block and the result of the second count process digital data reproducing method, which comprises an error correction process are. After the error correction code is added, the digital data of the sequence of data blocks that are collected in the order of the data arrangement different from the data sequence that generates the error correction code, and to which position information is added according to a certain rule, is sequentially stored In a digital data reproduction method for temporarily storing data in a position predicted from the position information of means, reading out the digital data from the storage means, and detecting or correcting an error contained in the digital data using the error correction code ,
Generating a first variable whose value changes every time the data block is stored in the storage means, and a second variable whose value changes every time the data block is error-corrected;
The first variable is stored in the storage means in association with the corresponding data block together with the digital data,
An error correction method using the error correction code of the data block read from the storage means is based on a comparison result between the first variable and the second variable read from the storage means. digital data reproducing method, which comprises an error correction method to change the number of errors that erasure correction Te. Demodulation means for demodulating digital data comprising a plurality of data blocks to which a first check code and a second check code are added;
Storage means for temporarily storing the demodulated digital data;
In a digital data reproducing apparatus comprising error correction means for detecting or correcting an error contained in the digital data using the first and second check codes for the demodulated digital data,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction means corrects one block error of a data block;
The storage means stores the count value of the first counter in association with the data block demodulated by the demodulation means,
The error correction means performs error correction processing of the data block by the first check code, and in error correction processing of the data block by the second check code, the error correction processing of the data block by the second check code When the number of errors detected in the error correction process is greater than or equal to a preset number, erasure correction is selected, and the count value of the first counter and the count of the second counter read from the storage means A digital data reproducing apparatus, wherein the number of errors for erasure correction is changed according to a comparison result with a value. Demodulation means for demodulating digital data comprising a plurality of data blocks to which a first check code and a second check code are added;
Storage means for temporarily storing the demodulated digital data;
In a digital data reproducing apparatus comprising error correction means for detecting or correcting an error contained in the digital data using the first and second check codes for the demodulated digital data,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction unit corrects one block error of the data block;
The storage means stores the count value of the first counter in association with the data block demodulated by the demodulation means,
The error correction means performs error correction processing using the first check code, then performs error correction processing using the second check code, and performs error correction processing using the second check code. The error position at the time of erasure correction in, the number of errors detected at the time of error correction processing using the first check code, the count value of the first counter read from the storage means, A digital data reproducing apparatus characterized by determining using a comparison result with the count value of the second counter. Detecting the synchronization signal and the identification data from the digital data of a plurality of data block columns to which the identification data and the synchronization signal are added according to a certain rule after the first and second check codes are added; Demodulation means for demodulating the digital data;
Storage means for temporarily storing the demodulated digital data;
In a digital data reproducing apparatus comprising error correction means for detecting or correcting an error contained in the digital data using the first and second check codes for the demodulated digital data,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction unit corrects one block error of the data block;
The demodulation means generates information indicating the detection status of the synchronization signal and the identification data in association with the data block,
The storage means stores the data block demodulated by the demodulation means, the information generated by the demodulation means, and the count value of the first counter,
The error correction means is
An error correction process using the first check code is then performed, and then an error correction process using the second check code is performed, and during the error correction process using the second check code, When the number of errors detected in the error correction processing of the data block by the check code is greater than or equal to a preset number, the information generated by the demodulation unit and the first read from the storage unit A digital data reproducing apparatus, wherein the number of errors to be corrected is changed according to a comparison result between a count value of the counter and a count value of the second counter. Detecting the synchronization signal and the identification data from the digital data of a plurality of data block columns to which the identification data and the synchronization signal are added according to a certain rule after the first and second check codes are added; Demodulation means for demodulating the digital data;
Storage means for temporarily storing the demodulated digital data;
In a digital data reproducing apparatus comprising error correction means for detecting or correcting an error contained in the digital data using the first and second check codes for the demodulated digital data,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block;
A second counter whose count value changes each time the error correction unit corrects one block error of the data block;
The demodulation means generates information indicating the detection status of the synchronization signal and the identification data in association with the data block,
The storage means stores the data block demodulated by the demodulation means, the information generated by the demodulation means, and the count value of the first counter,
The error correction means performs error correction processing using the first check code, then performs error correction processing using the second check code, and performs error correction processing using the second check code. The error position at the time of erasure correction in, the number of errors detected at the time of error correction processing using the first check code, the count value of the first counter read from the storage means, A digital data reproducing apparatus characterized by determining using a comparison result with the count value of the second counter. Demodulating means for demodulating digital data composed of a plurality of data blocks to which first and second check codes are added, and detecting errors contained in the demodulated digital data using the first check code or First error correction means for correcting, storage means for temporarily storing the error-corrected digital data, reading the digital data from the storage means, and using the second check code, included in the data block A digital data reproducing apparatus comprising second error correcting means for detecting or correcting an error generated
A first counter whose count value changes each time the demodulating means demodulates one block of the data block or every time the first error correcting means corrects one block error of the data block;
A second counter whose count value changes each time the second error correction means corrects one block error of the data block;
The storage means indicates the data block error-corrected by the first error correction means and the number of errors detected during error correction processing by the first check code in the first error correction means. Store the flag and the count value of the first counter;
The second error correction means reads from the storage means the number of the flags read from the storage means, the number of errors detected by the error correction processing using the second check code, and the like. A digital data reproducing apparatus, wherein the number of errors to be erasure-corrected is changed according to a comparison result between the count value of the first counter and the count value of the second counter. Demodulating means for demodulating digital data composed of a plurality of data blocks to which first and second check codes are added, and detecting errors contained in the demodulated digital data using the first check code or First error correction means for correcting, storage means for temporarily storing the error-corrected digital data, reading the digital data from the storage means, and using the second check code, included in the data block A digital data reproducing apparatus comprising second error correcting means for detecting or correcting an error generated
A first counter whose count value changes each time the demodulating means demodulates one block of the data block or every time the first error correcting means corrects one block error of the data block;
A second counter whose count value changes each time the second error correction means corrects one block error of the data block;
The storage means indicates the data block error-corrected by the first error correction means and the number of errors detected during error correction processing by the first check code in the first error correction means. Store the flag and the count value of the first counter;
The second error correction means includes the error position when performing error correction processing using the second check code by erasure correction, the number of the flags read from the storage means, and the storage means. A digital data reproducing apparatus, wherein the digital data reproducing apparatus is determined according to a comparison result between the count value of the first counter read from the count value of the second counter and the count value of the second counter. Detecting the synchronization signal and the identification data from the digital data of a plurality of data block columns to which the identification data and the synchronization signal are added according to a certain rule after the first and second check codes are added; Demodulating means for demodulating the digital data, first error correcting means for detecting or correcting an error included in the demodulated digital data using the first check code, and the error-corrected digital data Storage means for temporarily storing data, and second error correction means for reading out the digital data from the storage means and detecting or correcting an error contained in the data block using the second check code In a digital data reproducing device,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block or every time the first error correcting means corrects one block error of the data block;
A second counter whose count value changes each time the second error correction means corrects one block error of the data block;
The demodulation means generates information indicating the detection status of the synchronization signal and the identification data in association with the data block,
The storage means includes the data block error-corrected by the first error correction means, the information indicating the detection status of the synchronization signal and the identification data generated by the demodulation means, and the first error Storing a flag indicating the number of errors detected during error correction processing by the first check code in the correction means, and a count value of the first counter;
The second error correction means reads from the storage means the number of the flags read from the storage means, the number of errors detected by the error correction processing using the second check code, and the like. According to the information indicating the detection status of the synchronization signal and the identification data, and the comparison result between the count value of the first counter and the count value of the second counter read from the storage means And changing the number of errors for erasure correction . The synchronization signal and the identification data are detected from digital data of a plurality of data block columns to which the identification data and the synchronization signal are added according to a certain rule after the first and second check codes are added. Demodulating means for demodulating the digital data; first error correcting means for detecting or correcting an error contained in the demodulated digital data using the first check code; Storage means for temporarily storing data; and second error correction means for reading out the digital data from the storage means and detecting or correcting an error included in the data block using the second check code. In the digital data reproducing apparatus,
A first counter whose count value changes each time the demodulating means demodulates one block of the data block or every time the first error correcting means corrects one block error of the data block;
A second counter whose count value changes each time the second error correction means corrects one block error of the data block;
The demodulation means generates information indicating the detection status of the synchronization signal and the identification data in association with the data block,
The storage means includes the data block error-corrected by the first error correction means, the information indicating the detection status of the synchronization signal and the identification data generated by the demodulation means, and the first error Storing a flag indicating the number of errors detected during error correction processing by the first check code in the correction means, and a count value of the first counter;
The second error correction means includes the error position when performing error correction processing using the second check code by erasure correction, the number of the flags read from the storage means, and the storage means. A comparison result of the information indicating the detection status of the synchronization signal or the identification data read from the first counter and the count value of the second counter read from the storage means A digital data reproducing apparatus characterized by being determined according to the above.

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