JP4147642B2 - Method for manufacturing printed wiring board - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a printed wiring board having at least two conductor circuits laminated via an insulating layer, and more particularly to a method of manufacturing a printed wiring board in which these conductor circuits are electrically connected by vias.
[0002]
[Prior art]
Conventionally, in a multilayer printed circuit board, as shown in FIG. 14, upper and lower conductor circuits 2 and 3 are laminated via an insulating layer 1, and these conductor circuits 2 and 3 are electrically connected by vias 4. ing. The via 4 is formed by forming a hole 5 connected to the upper and lower conductor circuits 2 and 3 in the insulating layer 1 and covering the surface of the insulating layer 1 and the inner surface of the hole 5 with copper plating.
[0003]
[Problems to be solved by the invention]
However, when the conductor circuit 3 is formed by pattern plating, since the plating layer is uniformly coated on the surface of the insulating layer 1 and the inner surface of the hole 5, the hole 5 has a large diameter (100 μm or more). In some cases, the surface of the via 4 has a concave shape 6 as indicated by a two-dot chain line. When the insulating layer 1 is further laminated on the concave surface, particularly in the case of the insulating layer 1 made of a film, there is a problem that voids are generated in the concave portion 6.
[0004]
In order to eliminate this void problem, the surface of the via 4 can be formed flat if electroless plating is applied to the surface of the insulating layer 1 and the inner surface of the hole 5, but it takes a long time for electroless plating. This requires a new problem of high cost.
[0005]
The present invention has been made in view of the above circumstances, and an object thereof is to provide a method of manufacturing a printed wiring board in which vias are formed by pattern plating and the surface can be flattened.
[0006]
[Means for Solving the Problems]
Means taken by the present invention to solve this problem will be described with reference numerals used in the embodiments, and has at least two conductor circuits laminated via an insulating layer. In the printed wiring board electrically connected by via | veer, the following process is included, The manufacturing method of the printed wiring board characterized by the above-mentioned.
Forming an insulating layer on the upper surface of the underlying conductor circuit;
Forming via holes in the insulating layer;
Depositing chemical copper on the surface of the insulating layer and the inner surface of the via hole;
Forming a plating resist on the surface of the insulating layer and forming an opening of substantially the same diameter in communication with the via hole in the plating resist;
Forming a via by applying electrolytic copper plating to the inner surface of the via hole, and projecting the upper surface of the electrolytic copper plating from the insulating layer;
Removing the plating resist.
Forming a panel plating on the surface of the insulating layer and the upper surface of the via;
The process of polishing the upper surface of panel plating and vias to form the entire surface flat.
The process of forming a circuit pattern on panel plating to make a conductor circuit.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to a multilayer circuit printed wiring board will be described with reference to FIGS. In addition, since the manufacturing method of a multilayer board is well-known, especially the process of forming a via | veer is demonstrated mainly.
[0008]
Insulating layer 12 (about 40 μm) is formed on the upper surface of conductor circuit 11 in the first step lower layer (see FIG. 1).
[0009]
Second Step A via hole 13 is formed in the insulating layer 12. There are two types of vias, photo vias and laser vias. The photo via uses a photosensitive resin as an insulating layer, and exposes and develops it to form a tapered hole, and the inner surface of this hole is plated (see FIG. 10). The laser via is formed by forming a cylindrical hole with a laser and plating the inner surface thereof (see FIG. 2). In any case, since the subsequent manufacturing process is the same, the case of laser via will be described.
[0010]
Flash chemical copper plating is performed on the surface of the third step insulating layer 12 and the inner surface of the via hole 13 to deposit chemical copper 14 (2.5 to 5 μm) (see FIG. 3).
[0011]
After forming a plating resist 15 (about 20 μm) on the surface of the fourth step insulating layer 12, exposure and development are performed to form an opening 16 having substantially the same diameter communicating with the via hole 13 (see FIG. 4). .
[0012]
A copper 17 is plated on the inner surface of the fifth process via hole 13 to form a via 17. The upper surface 17a of the electrolytic copper plating is protruded from the insulating layer 12 (see FIG. 5). In this electrolytic copper plating, it is preferable that the upper surface 17a protrudes from the plating resist 15 (the thickness of the copper plating is about 50 μm).
[0013]
Sixth Step Plating resist 15 is removed (see FIG. 6).
[0014]
Panel plating 18 (about 20 μm) is formed on the surface of the seventh step insulating layer 12 and the via 17 (see FIG. 7).
[0015]
Eighth step The panel plating 18 and the upper surface 17a of the via are polished (polishing margin of about 2 to 3 μm) to form the entire surface flatly (see FIG. 8).
[0016]
Ninth step.
A circuit pattern is formed on the panel plating 18 through resist, exposure, development and etching steps to form a conductor circuit 19 (see FIG. 9).
[0017]
In the fourth step, it has been described that the opening 16 having substantially the same shape as the via hole 13 is formed in the plating resist 15. However, the examination result of the photo via regarding the size of the opening 16 will be described.
[0018]
The first case is the case of the opening 16 having the same diameter as the hole 13 (see FIG. 11).
That is, the diameter of the hole 13 is 100 μm, and the opening 16 is circular and has a diameter of 100 μm. In this case, the upper surface 17 a of the via is formed in an arc shape concentric with the opening 16.
[0019]
The second case is a case where the opening 16 is larger than the hole 13 (see FIG. 12). That is, the diameter of the hole 13 is 100 μm, and the opening 16 is circular and has a diameter of 200 μm. In the second case, the surface of the insulating layer 12 is also coated with electrolytic copper plating. In the second case, the polishing time is longer than the first case because the area of the electrolytic copper plating is large.
[0020]
The third case is a case where the opening 16 is smaller than the hole 13 (see FIG. 13). That is, the diameter of the hole 13 is 200 μm, and the opening 16 is circular and the diameter is 150 μm. In this third embodiment, the upper end portion of the hole 13 which is the shadow of the plating resist 15 is sufficiently covered with the electrolytic copper plating, and the inside of the opening portion 16 is raised in an arc shape. When the opening 16 is much smaller than the diameter of the hole 13, the electrolytic copper plating film on the upper end of the hole 13 that is behind the plating resist 15 may be thinned. Since this is covered, this defect is eliminated.
[0021]
In the first to third cases, since the panel plating 18 and the upper surface 17a of the via are polished after the panel plating 18, the surfaces of the conductor circuit 19 and the via 17 can be formed flat.
[0022]
In the first case, it is difficult to completely match the edge of the small-diameter hole 13 and the opening 16, but the second case and the third case described above are combined even in an eccentric state. Therefore, the surface of the conductor circuit 19 and the via 17 can be formed flat.
[0023]
The present invention has the following effects.
(1) Since only the inner surface of the via hole 13 is panel-plated, the upper surface of the conductor circuit 19 can be formed flat regardless of the thickness of the insulating layer 12 (depth of the via 17) or the diameter of the via 17. .
(2) Since the upper surface 17a of the electro copper plating applied to the inner surface of the via hole 13 is protruded from the insulating layer 12, the electroplating management conditions are widened, the electroplating can be easily performed, and the electroless plating can be performed. Cost can be reduced compared to the case of using.
(3) Since the panel plating 18 and the upper surface 17a of the via 17 are polished, the upper surface of the conductor circuit 19 can be formed flat, and no void is generated between the insulating layer 12 and the conductor layer 19 overlying. The insulating layer 12 is also formed flat.
(4) Since the conductor circuits 11 and 19 can be formed flat and there is little variation in plating thickness, a circuit board with high density and high design freedom can be formed.
[0024]
【The invention's effect】
The printed wiring board manufacturing method of the present invention has at least two conductor circuits laminated via an insulating layer, and in the printed wiring board that electrically connects these conductor circuits by vias,
Forming an insulating layer on the upper surface of the underlying conductor circuit;
Forming via holes in the insulating layer;
Depositing chemical copper on the surface of the insulating layer and the inner surface of the via hole;
Forming a plating resist on the surface of the insulating layer and forming an opening of substantially the same diameter in communication with the via hole in the plating resist;
Forming a via by applying electrolytic copper plating to the inner surface of the via hole, and projecting the upper surface of the electrolytic copper plating from the insulating layer;
Removing the plating resist;
Forming a panel plating on the surface of the insulating layer and the upper surface of the via;
The process of polishing the upper surface of panel plating and vias to form the entire surface flat.
The process of forming a circuit pattern on panel plating to make a conductor circuit.
Therefore, the via can be formed by pattern plating at low cost, and the surface can be flattened.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a first manufacturing process in which the present invention is applied to a razor via.
FIG. 2 is a cross-sectional view showing a second manufacturing process.
FIG. 3 is a cross-sectional view showing a third manufacturing process.
FIG. 4 is a cross-sectional view showing a fourth manufacturing process.
FIG. 5 is a cross-sectional view showing a fifth manufacturing process.
FIG. 6 is a cross-sectional view showing a sixth manufacturing process.
FIG. 7 is a cross-sectional view showing a seventh manufacturing process.
FIG. 8 is a cross-sectional view showing an eighth manufacturing process.
FIG. 9 is a cross-sectional view showing a ninth manufacturing process.
FIG. 10 is a cross-sectional view of a photo via.
FIG. 11 is a cross-sectional view of a via in a first case in which the relationship between the size of a resist opening and a via hole is examined in a second manufacturing process;
FIG. 12 is a cross-sectional view of a via in the second case.
FIG. 13 is a sectional view of a via in a third case.
FIG. 14 is a cross-sectional view of a main part in a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 Conductor circuit 12 Insulating layer 13 Via hole 14 Chemical copper 15 Plating resist 16 Opening 17 Via 17a upper surface 18 Panel plating 19 Conductor circuit

Claims (1)

A printed wiring board having at least two conductor circuits laminated via an insulating layer and electrically connecting these conductor circuits with vias, comprising the following steps: .
Forming an insulating layer on the upper surface of the underlying conductor circuit;
Forming via holes in the insulating layer;
Depositing chemical copper on the surface of the insulating layer and the inner surface of the via hole;
Forming a plating resist on the surface of the insulating layer and forming an opening of substantially the same diameter in communication with the via hole in the plating resist;
Forming a via by applying electrolytic copper plating to the inner surface of the via hole, and projecting the upper surface of the electrolytic copper plating from the insulating layer;
Removing the plating resist;
Forming a panel plating on the surface of the insulating layer and the upper surface of the via;
The process of polishing the upper surface of panel plating and vias to form the entire surface flat.
The process of forming a circuit pattern on panel plating to make a conductor circuit.

Images