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JP4141789B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP4141789B2
JP4141789B2 JP2002298629A JP2002298629A JP4141789B2 JP 4141789 B2 JP4141789 B2 JP 4141789B2 JP 2002298629 A JP2002298629 A JP 2002298629A JP 2002298629 A JP2002298629 A JP 2002298629A JP 4141789 B2 JP4141789 B2 JP 4141789B2
Authority
JP
Japan
Prior art keywords
case
electrode
semiconductor device
wire bonding
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002298629A
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Japanese (ja)
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JP2004134624A5 (en
JP2004134624A (en
Inventor
慶久 小栗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2002298629A priority Critical patent/JP4141789B2/en
Publication of JP2004134624A publication Critical patent/JP2004134624A/en
Publication of JP2004134624A5 publication Critical patent/JP2004134624A5/ja
Application granted granted Critical
Publication of JP4141789B2 publication Critical patent/JP4141789B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires

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  • Lead Frames For Integrated Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は、電力用半導体素子を有し、その電極がケースにインサート成型されている電力用半導体装置に関するものである。
【0002】
【従来の技術】
この種の半導体装置は、公知の放熱板上にはんだを介して、導電性の板材を上面に有した絶縁性のセラミック基板が構成されたものであり、基板導電材上にはんだを介してスイッチング用素子が構成され、各素子は、公知のワイヤー配線を用いて結線されている。そして、半導体装置を構成するケース外からケースへ貫通して設けられる電極(出力および接続用電極)のケース内側の端部は、ケース内の底面に形成した“ピンガイド”や“電極つぶし構造”により、保持されている。
【0003】
また、ケース内に位置する電極を長手方向に2分し、一方の部分に対して段差を形成し、その段差部に樹脂を形成することで電極を固定しているが(例えば、特許文献1参照)、電極に微細な加工が必要となる。
【0004】
【特許文献1】
特開2000−349219号「電力用半導体装置」(実施の形態1、図3)
【0005】
【発明が解決しようとする課題】
前記内部電極は、ケース成型時にピンガイド構造や電極つぶし構造が形成されるため、ケース成型用金型の構造が複雑となり、高価となった。また、ピンガイド構造では、成型後に残るピン穴からの気泡流出により、絶縁不具合を発生させていた。また、電極つぶし構造では十分な電極保持ができないためにワイヤーボンドで不具合を起こしていた。更に、従来のケース内部前面と、電極内部前面が同一面で構成されていたため、電極底面とケース樹脂間に生じたスキマの空気が電極内部前面より気泡として発生し品質の安定化が困難であった。
【0006】
この発明は、ケース成形用金型構造を単純にでき、また、電極面への加工をなくし、かつ気泡発生の要因となる空気溜まりをなくした半導体装置を提供するものである。
【0007】
【課題を解決するための手段】
基板およびこれに実装した半導体装置をケースに収納後、ケース内部をゲル状樹脂で充填してなる電力用半導体装置において、
ケースに貫通するようにして設けられた電極のケース内側に位置する内部リードを固定用ベッドで埋め込み固定するにあたり
前記内部リードワイヤボンディング面(2c)が露出するようにし、
前記内部リードの端面 ( 2e ) を、固定用ベッドの端面 ( 7e ) から退避させ、かつ、
ケース成型時に金型の一部が入り込んで形成された前記固定用ベッドの切り欠き内に、前記端面 ( 2e ) の、ワイヤボンディング面(2c)側の一部が露出したことを特徴とする。
【0008】
【発明の実施の形態】
実施の形態1.
図1に半導体装置の平面図を示し、ケース1内に収納した回路基板4上に、半導体素子5が設けられ、その半導体素子5はワイヤ6により他のデバイスなどに接続されている。放熱板3はケース1の底板を兼ねる。外部引き出し用の電極2部分の拡大斜視図を図2に示し、その電極2の全体図を図3に示す。また、図2中のA−B方向およびC−D方向での垂直断面図を図4および図5に示す。
【0009】
L字形状の電極2は、ケース1を貫通するようにして設けられ、外部リード2aはケース外に引き出され、内部リード2bは、ケース内にて固定用ベッド7に埋め込まれることにより保持されるが、その内部リード2bの上面部であるワイヤボンディング面2cは、固定用ベッド7の上面と同一平面にされ、ワイヤボンディング面2cが露出される。
【0010】
電極2のケース内側の端面2e(図3)は、図2、図4に示すように、固定用ベッド7の端面7eより退避しており、かつ、端面2eの一部が露出するように、固定用ベッド7の上端面部に切り欠き7aが形成されている。
【0011】
図4において示した矢印(→)は、電極2をケース1および固定用ベッド7に埋め込み成型する際の金型(不図示)による押圧面を示している。切り欠き7aで示した個所に対しても金型が入り込むことによって、そのような切り欠き7aが固定用ベッド7に形成される。このとき、切り欠き7aに入り込んだ金型の端面が、電極2の端面2eに当接するため、前記埋め込み成型の際に、電極2が正確な位置で保持されるようになる。
【0012】
ここで用いた金型の形状もシンプルなため、金型を安価に形成できる。また、成型の際に、金型内面と、電極2を含むケース1および固定用ベッド7との間に隙間が生じないため、上述したような気泡発生も生じない。
【0013】
更に図3に示したように、電極2のワイヤボンディング面2cの周囲に、プレス加工時の塑性変形である“ダレ”2dが生じている。このような電極2を、ワイヤボンディング面2cのみが露出するように、固定用ベッド7に埋め込んだ時、図2中のA−B方向での垂直断面図である図4に示されるように、ダレ2dの部分が樹脂で覆われることにより、ダレ2dが無い場合に比べて電極2の保持強度が増す。
【0014】
【発明の効果】
この発明は、ケース内の固定用ベッドに電極を成型固定する際、電極の端面を金型で保持するようにしたので、金型の形状もシンプルなため、金型を安価に形成でき、また、成型の際に、金型内面と、電極を含むケースおよび固定用ベッドとの間に隙間が生じないため、上述したような気泡発生も生じない。
【図面の簡単な説明】
【図1】 本発明の1実施形態を示した電力用半導体装置の内部平面図
【図2】 電極における内部リード部の詳細斜視図
【図3】 電極の全体斜視図
【図4】 図2中のA−B方向での垂直断面を示した図
【図5】 図2中のC−D方向での垂直断面を示した図
【符号の説明】
1 ケース、2 電極、2a 外部リード、2b 内部リード、2c ワイヤボンディング面、2d ダレ、2e 端面、3 放熱板、4 回路基板、5 半導体素子、6 ワイヤ、7 固定用ベッド、7a 切り欠き
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device having a power semiconductor element and an electrode of which is insert-molded in a case.
[0002]
[Prior art]
In this type of semiconductor device, an insulating ceramic substrate having a conductive plate material on its upper surface is formed on a known heat sink via solder, and switching is performed on the substrate conductive material via solder. The elements are configured, and each element is connected using a known wire wiring. The inner end of the electrode (output and connection electrode) provided through the case from the outside of the case constituting the semiconductor device is a “pin guide” or “electrode crushing structure” formed on the bottom surface inside the case. Is held by.
[0003]
Moreover, although the electrode located in a case is divided into 2 to a longitudinal direction, a level | step difference is formed in one part, and the electrode is fixed by forming resin in the level | step-difference part (for example, patent document 1). See), and the electrode needs fine processing.
[0004]
[Patent Document 1]
Japanese Unexamined Patent Publication No. 2000-349219 “Power Semiconductor Device” (Embodiment 1, FIG. 3)
[0005]
[Problems to be solved by the invention]
Since the internal electrode is formed with a pin guide structure or an electrode crushing structure when the case is molded, the structure of the case molding die is complicated and expensive. Further, in the pin guide structure, an insulation failure occurs due to air bubbles flowing out from the pin holes remaining after molding. In addition, since the electrode crushing structure cannot hold the electrode sufficiently, a problem has occurred in the wire bond. In addition, since the front surface inside the case and the front surface inside the electrode are configured on the same surface, gap air generated between the bottom surface of the electrode and the case resin is generated as bubbles from the front surface inside the electrode, making it difficult to stabilize the quality. It was.
[0006]
The present invention provides a semiconductor device in which the case-molding mold structure can be simplified, the processing on the electrode surface is eliminated, and air pockets that cause bubbles are eliminated.
[0007]
[Means for Solving the Problems]
In a power semiconductor device in which a case and a semiconductor device mounted thereon are stored in a case, and the inside of the case is filled with a gel resin,
Per the inner leads located inside the case of electrodes provided so as to penetrate the case to the embedded fixed by fixing bed,
The wire bonding surface (2c) of the internal lead is exposed,
Retracting the end face ( 2e ) of the internal lead from the end face ( 7e ) of the fixed bed ; and
A part of the end face ( 2e ) on the wire bonding surface (2c) side is exposed in a notch of the fixing bed formed by partly entering a mold when molding the case .
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a plan view of a semiconductor device. A semiconductor element 5 is provided on a circuit board 4 housed in the case 1, and the semiconductor element 5 is connected to other devices by wires 6. The heat radiating plate 3 also serves as the bottom plate of the case 1. FIG. 2 shows an enlarged perspective view of the external electrode 2 portion, and FIG. 3 shows an overall view of the electrode 2. Moreover, the vertical sectional view in the AB direction and CD direction in FIG. 2 is shown in FIG. 4 and FIG.
[0009]
The L-shaped electrode 2 is provided so as to penetrate the case 1, the external lead 2 a is drawn out of the case, and the internal lead 2 b is held by being embedded in the fixing bed 7 in the case. However, the wire bonding surface 2c which is the upper surface portion of the internal lead 2b is flush with the upper surface of the fixing bed 7, and the wire bonding surface 2c is exposed.
[0010]
As shown in FIGS. 2 and 4, the end surface 2 e (FIG. 3) inside the case of the electrode 2 is retracted from the end surface 7 e of the fixing bed 7, and a part of the end surface 2 e is exposed. A notch 7 a is formed in the upper end surface portion of the fixing bed 7.
[0011]
An arrow (→) shown in FIG. 4 indicates a pressing surface by a mold (not shown) when the electrode 2 is embedded in the case 1 and the fixing bed 7. The notch 7a is formed in the fixing bed 7 by the mold entering the portion indicated by the notch 7a. At this time, since the end surface of the mold that has entered the notch 7a comes into contact with the end surface 2e of the electrode 2, the electrode 2 is held at an accurate position during the embedding molding.
[0012]
Since the shape of the mold used here is simple, the mold can be formed at low cost. Further, since no gap is generated between the inner surface of the mold and the case 1 including the electrode 2 and the fixing bed 7 during molding, the generation of bubbles as described above does not occur.
[0013]
Further, as shown in FIG. 3, “sag” 2 d which is plastic deformation at the time of press working is generated around the wire bonding surface 2 c of the electrode 2. When such an electrode 2 is embedded in the fixing bed 7 so that only the wire bonding surface 2c is exposed, as shown in FIG. 4 which is a vertical sectional view in the direction AB in FIG. Since the sagging portion 2d is covered with the resin, the holding strength of the electrode 2 is increased as compared with the case where there is no sagging 2d.
[0014]
【The invention's effect】
In the present invention, when the electrode is molded and fixed to the fixing bed in the case, the end face of the electrode is held by the mold, so the mold shape is simple, and the mold can be formed at low cost. In the molding, since no gap is generated between the inner surface of the mold and the case including the electrode and the fixing bed, the generation of bubbles as described above does not occur.
[Brief description of the drawings]
FIG. 1 is an internal plan view of a power semiconductor device showing an embodiment of the present invention. FIG. 2 is a detailed perspective view of an internal lead portion of an electrode. FIG. 3 is an overall perspective view of an electrode. The figure which showed the vertical cross section in the AB direction of FIG. 5 [FIG. 5] The figure which showed the vertical cross section in the CD direction in FIG.
1 case, 2 electrodes, 2a external lead, 2b internal lead, 2c wire bonding surface, 2d sag, 2e end surface, 3 heat sink, 4 circuit board, 5 semiconductor element, 6 wire, 7 fixing bed, 7a notch

Claims (3)

基板およびこれに実装した半導体装置をケースに収納後、ケース内部をゲル状樹脂で充填してなる電力用半導体装置において、
ケースに貫通するようにして設けられた電極のケース内側に位置する内部リードを固定用ベッドで埋め込み固定するにあたり
前記内部リードワイヤボンディング面(2c)が露出するようにし、
前記内部リードの端面 ( 2e ) を、固定用ベッドの端面 ( 7e ) から退避させ、かつ、
ケース成型時に金型の一部が入り込んで形成された前記固定用ベッドの切り欠き内に、前記端面 ( 2e ) の、ワイヤボンディング面(2c)側の一部が露出したことを特徴とする電力用半導体装置。
In a power semiconductor device in which a case and a semiconductor device mounted thereon are stored in a case, and the inside of the case is filled with a gel resin,
Per the inner leads located inside the case of electrodes provided so as to penetrate the case to the embedded fixed by fixing bed,
The wire bonding surface (2c) of the internal lead is exposed,
Retracting the end face ( 2e ) of the internal lead from the end face ( 7e ) of the fixed bed ; and
Electric power characterized in that a part of the end face ( 2e ) on the wire bonding surface (2c) side is exposed in a notch of the fixing bed formed by partly entering a mold during case molding. Semiconductor device.
前記ワイヤボンディング面と前記固定用ベッドの上面とを同一面として、前記内部リードにおける前記ワイヤボンディング面が露出するようにした請求項1記載の電力用半導体装置。  The power semiconductor device according to claim 1, wherein the wire bonding surface and the upper surface of the fixing bed are the same surface, and the wire bonding surface of the internal lead is exposed. 上記電極をプレス加工したときに生じる電極の上縁のダレの個所が、固定用ベッドの樹脂で覆われることにより、電極の固定強度を高めた請求項2記載の電力用半導体装置。  The power semiconductor device according to claim 2, wherein a portion of a sag at the upper edge of the electrode that is produced when the electrode is pressed is covered with a resin of the fixing bed, thereby increasing the fixing strength of the electrode.
JP2002298629A 2002-10-11 2002-10-11 Power semiconductor device Expired - Fee Related JP4141789B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP2002298629A JP4141789B2 (en) 2002-10-11 2002-10-11 Power semiconductor device

Publications (3)

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JP2004134624A JP2004134624A (en) 2004-04-30
JP2004134624A5 JP2004134624A5 (en) 2005-07-21
JP4141789B2 true JP4141789B2 (en) 2008-08-27

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JP6107362B2 (en) * 2013-04-18 2017-04-05 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device
JP6841199B2 (en) * 2017-09-29 2021-03-10 三菱電機株式会社 Semiconductor device
JP7183551B2 (en) 2018-03-15 2022-12-06 富士電機株式会社 semiconductor equipment
JP7318238B2 (en) 2019-03-11 2023-08-01 富士電機株式会社 semiconductor equipment
CN113496965A (en) * 2021-07-08 2021-10-12 广东汇芯半导体有限公司 Semiconductor circuit and method for manufacturing semiconductor circuit

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JP3505908B2 (en) * 1996-03-15 2004-03-15 アイシン・エィ・ダブリュ株式会社 Conductive wire connection terminal
JP3681922B2 (en) * 1999-06-03 2005-08-10 三菱電機株式会社 Drawer terminal, power semiconductor device case, and power semiconductor device

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