JP4141433B2 - Differential amplifier circuit - Google Patents

Description

  The present invention relates to a differential amplifier circuit, and more particularly to a differential amplifier circuit capable of controlling an amplification factor.

  In the fields of wireless communication and wired communication in recent years, communication systems have become more sophisticated and complicated, as represented by code division multiple access (CDMA) and orthogonal frequency division multiple communication (OFDM). Along with this, the characteristics required for analog circuits used in transceivers are becoming stricter. Furthermore, in the field of wireless communication, multiband / multimode wireless devices corresponding to various and various communication methods and services have been developed. As such an analog circuit for multiband / multimode communication, an amplifier circuit having a variable amplification factor, a filter circuit having a variable passband, and the like are important.

  FIG. 7 is a circuit diagram showing a configuration of a Gm amplifier 71 having a variable mutual conductance Gm (see, for example, Non-Patent Document 1). In FIG. 7, this Gm amplifier includes differential input terminals T71 and T72, differential output terminals T73 and T74, P channel MOS transistors 72 and 73, N channel MOS transistors 74 to 77, resistance elements 78 and 79, and a sub Gm amplifier. 80. Differential input voltages VIP and VIM are applied to the differential input terminals T71 and T72, respectively. Differential output voltages VOP and VOM are output to the differential output terminals T73 and T74.

  The sources of P-channel MOS transistors 72 and 73 are both connected to the line of power supply voltage VDD, their drains are connected to differential output terminals T74 and T73, respectively, and their gates receive a predetermined voltage VFB1.

  MOS transistor 74, resistance element 78, and MOS transistor 76 are connected in series between differential output terminal T74 and the ground voltage GND line. MOS transistor 75, resistance element 79, and MOS transistor 77 are connected in series between differential output terminal T73 and the line of ground voltage GND. The gates of N channel MOS transistors 74 and 75 are connected to differential input terminals T71 and T72, respectively. N channel MOS transistors 76 and 77 have their gates receiving a predetermined voltage VFB2.

  Both the differential input terminal and the differential output terminal on the + side of the sub Gm amplifier 80 are connected to the source of the N-channel MOS transistor 74. The negative differential input terminal and differential output terminal of the sub Gm amplifier 80 are both connected to the source of the N-channel MOS transistor 75. The Gm amplifier 80 is used as a negative source degeneration resistor (NSDR).

  If the mutual conductance of the sub Gm amplifier 80 is gmn and the resistance value obtained by adding the resistance value of the resistance element 78 and the resistance value of the N-channel MOS transistor 76 is Rs, the source of the N-channel MOS transistor 74 and the line of the ground voltage GND Is R = Rs / (1−gmn · Rs).

  If the mutual conductance of the N-channel MOS transistor 74 is gm74, the GM amplifier 70 operates when gm74 · R >> 1 is established, and the mutual conductance Gm of the Gm amplifier 70 is Gm = 1 / Rs−gmn. When 1 / Rs = gmn, Gm has a minimum value of 0. Further, when gmn = 0, Gm has the maximum value 1 / Rs.

Next, the operation of this Gm amplifier 71 will be described. A constant current corresponding to gate voltage VFB1 adjusted in advance flows through each of P channel MOS transistors 72 and 73. When differential input voltage VIP is higher than VIM, the current flowing through N channel MOS transistor 74 is larger than the current flowing through N channel MOS transistor 75, and differential output voltage VOP is higher than VOM. When differential input voltage VIP is lower than VIM, the current flowing through N channel MOS transistor 74 is smaller than the current flowing through N channel MOS transistor 75, and differential output voltage VOP is lower than VOM.
S. Hori, T. Maeda, H. Yano, N. Matsuno, K. Numata, N. Yoshida, Y. Takahashi, T. Yamase, R. Walkington, and H, Hida, “A Widely Tunable CMOS Gm-C Filter With a Negative Source Degeneration Resistor Transconductor, ”Proc. 29-th European Solid-State Circuits Conference, pp. 449-452, Sep. 2003.

  As described above, in this Gm amplifier 71, Gm has the maximum value 1 / Rs when gmn = 0, so that the maximum value 1 / Rs of Gm can be increased by decreasing Rs.

  However, if Rs is decreased, the basic condition gm74 · R >> 1 for operating the Gm amplifier 71 is not satisfied, so that Rs cannot be reduced so much and the maximum value 1 / Rs of Gm is increased so much. I can't.

  In Non-Patent Document 1, the Gm amplifier 71 is applied to a sixth-order elliptic low-pass filter to realize a variable range of a cutoff frequency of 2 MHz to 12 MHz. However, in order to sufficiently cope with future communication methods and diversification of services, it is necessary to change the frequency characteristics by one digit or more. For this purpose, it is necessary to further increase the bandwidth of the Gm amplifier.

  Therefore, a main object of the present invention is to provide a differential amplifier circuit having a wide variable range of amplification factor.

The differential amplifier circuit according to the present invention has a mutual conductance of outputting a current or voltage at a level corresponding to the voltage applied to the first and second differential input terminals to the first and second differential output terminals. A controllable differential amplifier circuit, the first and second load elements respectively connected between the first power supply voltage line and the first and second differential output terminals, and their first Are connected to first and second differential output terminals, their control electrodes are connected to second and first differential input terminals, respectively, and their second electrodes are connected to each other. The first and second transistors, the third transistor connected between the second electrode of the first and second transistors and the second power supply voltage line, and the first electrode of the third transistor connected to the first power supply voltage line, respectively. Connected to the 1st and 2nd differential output terminals The control electrodes are connected to the first and second differential input terminals, respectively, and the fourth and fifth transistors are connected to each other, and the fourth and fifth transistors are connected to each other. A sixth transistor connected between the second electrode and the second power supply voltage line, and a current flowing through the third and sixth transistors connected to the control electrodes of the third and sixth transistors, respectively. And the first and second control terminals for controlling the amplification factor, and the sum of the square root of the current value of the third transistor and the square root of the current value of the sixth transistor is constant. And a control circuit for controlling the voltages of the first and second control terminals .

  Preferably, each of the first to sixth transistors is a MOS transistor.

  Preferably, each of the first and second load elements includes a MOS transistor whose gate receives a predetermined voltage and operates in a saturation region.

  Preferably, each of the first and second load elements includes a MOS transistor which has a gate receiving a predetermined voltage and operates in a linear region.

  Preferably, each of the first and second load elements includes a resistance element.

The differential amplifier circuit according to the invention, the maximum value of the amplification factor is proportional to the current flowing through the third transistor. Therefore, unlike the conventional Gm amplifier, the maximum value of the amplification factor is not limited by the resistance value of the resistance element, so that the variable range of the amplification factor can be made wider than the conventional one.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of a Gm amplifier 1 according to Embodiment 1 of the present invention. In FIG. 1, this Gm amplifier 1 includes differential input terminals T1, T2, differential output terminals T3, T4, control terminals T5, T6, P channel MOS transistors 2, 3 and N channel MOS transistors 4-9.

  Differential input voltages VIP and VIM are applied to the differential input terminals T1 and T2, respectively. Differential output voltages VOP and VOM are output to the differential output terminals T3 and T4, respectively. Control voltages VB1 and VB2 are applied to the control terminals T5 and T6, respectively.

  The sources of P channel MOS transistors 2 and 3 are both connected to the line of power supply voltage VDD, their drains are connected to differential output terminals T4 and T3, respectively, and their gates both receive a predetermined voltage VFB. P-channel MOS transistors 2 and 3 operate in a saturation region and pass currents at levels proportional to differential input voltages VIP and VIM, respectively.

  N channel MOS transistors 4 and 5 have their drains connected to differential output terminals T4 and T3, their gates connected to differential input terminals T1 and T2, respectively, and their sources connected to each other. N channel MOS transistor 6 has its drain connected to the sources of N channel MOS transistors 4 and 5, its source connected to the line of ground voltage GND, and its gate connected to control terminal T5.

  N channel MOS transistors 7 and 8 have their drains connected to differential output terminals T4 and T3, their gates connected to differential input terminals T2 and T1, respectively, and their sources connected to each other. N channel MOS transistor 9 has its drain connected to the sources of N channel MOS transistors 7 and 8, its source connected to the ground voltage GND line, and its gate connected to control terminal T6.

  The MOS transistors 2 to 6 constitute a first sub Gm amplifier, and the MOS transistors 2, 3, 7 to 9 constitute a second sub Gm amplifier. The first and second sub Gm amplifiers share the load elements 2 and 3. The drains of the N-channel MOS transistors 4 and 8 to which the differential input voltage VIP is input are connected to the differential output terminals T4 and T3, respectively, and the drains of the N-channel MOS transistors 5 and 7 to which the differential input voltage VIM is input are These are connected to differential output terminals T3 and T4, respectively.

  That is, the differential output node pairs of the first and second sub-Gm amplifiers are connected in reverse to each other. Therefore, the combined mutual conductance gmt of the Gm amplifier 1 is represented by a difference gm1−gm2 between the mutual conductance gm1 of the first sub Gm amplifier and the mutual conductance gm2 of the second sub Gm amplifier.

  Here, currents flowing in N channel MOS transistors 6 and 9 which are tail current sources of the first and second sub-Gm amplifiers are I1 and I2, respectively, and the gate width and gate length of each of N channel MOS transistors 4 and 5 are set. Are W1 and L1, respectively, the gate width and gate length of each of the N channel MOS transistors 7 and 8 are W2 and L2, respectively, and the transconductance parameter depending on the manufacturing process of the N channel MOS transistors 4 to 9 is K. , Gm1, gm2, gmt = gm1-gm2 are represented by the following formulas (1) to (3), respectively.

gm1 = (K · W1 · I1 / L1) ^1/2 (1)
gm2 = (K · W2 · I2 / L2) ^1/2 (2)
gmt = (K · W1 · I1 / L1) ^1/2 − (K · W2 · I2 / L2) ^1/2 (3)
From equation (3), it can be seen that the combined mutual conductance gmt of the Gm amplifier 1 can be changed by changing the currents I1 and I2 flowing through the N-channel MOS transistors 6 and 9. When W1 · I1 / L1 = W2 · I2 / L2, gmt has a minimum value of 0. When I2 = 0, gmt is the maximum value (K · W1 · I1 / L1) ^1/2 , and the value depends on I1.

  Next, the operation of the Gm amplifier 1 will be described. First, the case where I2 = 0 will be described. When the voltage VB2 at the control terminal T6 is set to 0V, the N-channel MOS transistor 9 becomes non-conductive and I2 = 0. A constant current corresponding to gate voltage VFB adjusted in advance flows through each of P channel MOS transistors 2 and 3. When differential input voltage VIP is higher than VIM, the current flowing through N channel MOS transistor 4 is larger than the current flowing through N channel MOS transistor 5, and differential output voltage VOP is higher than VOM. When differential input voltage VIP is lower than VIM, the current flowing through N channel MOS transistor 4 is smaller than the current flowing through N channel MOS transistor 5, and differential output voltage VOP is lower than VOM.

  At this time, the combined mutual conductance gmt of the Gm amplifier 1 is the maximum value gm1. When the voltage VB1 of the control terminal T5 is increased, gmt = gm1 is increased. When a load circuit is connected to each of the differential output terminals T3 and T4, a current having a level corresponding to the differential output voltages VOP and VOM is output.

  When the voltage VB2 at the control terminal T6 is increased, I2 increases, current flows in both N-channel MOS transistors 4 and 8 in response to VIP, and current flows in both N-channel MOS transistors 5 and 7 in response to VIM. Flows, the voltage between the differential output terminals T3 and T4 becomes small. When W1 · I1 / L1 = W2 · I2 / L2, the currents flowing through the N-channel MOS transistors 4, 5, 7, and 8 become equal, and the voltage between the differential output terminals T3 and T4 becomes zero. At this time, gmt is zero.

In the first embodiment, the combined mutual conductance gmt of the Gm amplifier 1 can be changed from 0 to (K · W1 · I1 / L1) ^1/2 . Therefore, unlike the conventional Gm amplifier 71, the maximum value of the mutual conductance is not limited by the resistance value Rs of the resistance element 78 and the like, so that the variable range of gmt can be made wider than before.

  FIG. 2 is a circuit diagram showing a modification of the first embodiment. 2, the Gm amplifier 10 is obtained by replacing the N channel MOS transistors 2 and 3 of the Gm amplifier 1 of FIG. The Gm amplifier 11 can obtain differential output voltages VOP and VOM proportional to the differential input voltages VIP and VIM. Further, even if the predetermined voltage VFB of FIG. 1 is adjusted and the N-channel MOS transistors 2 and 3 are used in the linear region, the differential output voltages VOP and VOM proportional to the differential input voltages VIP and VIM can be obtained. .

  Needless to say, the P-channel MOS transistor and the N-channel MOS transistor may be interchanged, and the power supply voltage VDD line and the ground voltage GND line may be interchanged. Further, the N-channel MOS transistors 2 and 3 are connected in a plurality of stages of cascodes between the power supply voltage VDD line and the differential output terminals 2 and 3, and the gate voltages of the N-channel MOS transistors 2 and 3 at each stage are controlled separately. May be.

[Embodiment 2]
In the first embodiment, when I2 = 0, gmt is the maximum value (K · W1 · I1 / L1) ^1/2 and the value depends on I1. However, the maximum value of gmt is proportional to the square root of I1, and the rate of increase of gmt decreases as I1 increases. In order to avoid this, in the second embodiment, I1 and I2 are changed under the condition of the following expression (4).

(K · W1 · I1 / L1) ^1/2 + (K · W2 · I2 / L2) ^1/2 = A (4)
However, A is a constant value. At this time, gmt is expressed by the following equation (5).

gmt = (K ^1/2 / A) (W 1 · I 1 / L 1 −W 2 · I 2 / L 2) (5)
In Equation (5), gmt is proportional to I1. Thereby, the increase rate of gmt can be kept constant, and the band variable range of the Gm-C filter using the Gm amplifier 1 can be expanded.

  FIG. 3 is a circuit diagram showing a configuration of the control circuit 20 for changing I1 and I2 under the condition of the formula (4). In FIG. 3, control circuit 20 includes P channel MOS transistors 21 to 26, constant current sources 27 and 28, and N channel MOS transistors 29 to 33. The MOS transistors 21 and 31, the constant current source 27 and the MOS transistor 29, the MOS transistors 22 and 25, the constant current source 28 and the MOS transistors 26 and 32, the MOS transistors 23 and 30, and the MOS transistors 24 and 33 are respectively connected to the power supply voltage VDD. The line is connected in series between the line and the line of the ground voltage GND.

  The gates of the MOS transistors 21 and 22 are both connected to the drain of the MOS transistor 21. The gates of the MOS transistors 23 and 24 are both connected to the drain of the MOS transistor 24. The gates of the MOS transistors 31 and 32 are both connected to the drain of the MOS transistor 32. MOS transistors 21 and 22, 23 and 24, and 31 and 32 constitute current mirror circuits, respectively.

  The gates of the MOS transistors 29 and 25 are both connected to the drain of the MOS transistor 29. The gates of MOS transistors 26 and 30 are both connected to the drain of MOS transistor 30. The sources of the MOS transistors 25 and 26 are connected to each other. A control voltage VC is applied to the gate of N channel MOS transistor 33. Gate voltages VB1 and VB2 of N channel MOS transistors 30 and 32 are applied to control terminals T5 and T6 of differential amplifier circuit 1 in FIG. 1, respectively.

  Here, assuming that the currents flowing through the constant current sources 27 and 28 are I11 and I12, respectively, the currents I11 and I12 flow through the MOS transistors 29 and 25, respectively. The current flowing through the MOS transistors 26, 32, 31, 21, 22 is I13, and the current flowing through the MOS transistors 33, 24, 23, 30 is I14. The source voltages of the MOS transistors 25 and 26 are Vx, and the gate-source voltages of the MOS transistors 29, 25, 26, and 30 are Vgs11, Vgs12, Vgs13, and Vgs14, respectively. When the transconductor parameters of the P channel MOS transistor and the N channel MOS transistor are βp and βn, respectively, and the threshold voltages of the P channel MOS transistor and the N channel MOS transistor are Vthp and Vthn, respectively, Thus, Equations (7) and (8) are derived from Equation (6).

Vx = Vgs11 + Vgs12 = Vgs13 + Vgs14 (6)
(2 · I11 / βn) ^1/2 + Vthn + (2 · I12 / βp) ^1/2 + Vthp
= (2 · I13 / βp) ^1/2 + Vthp + (2 · I14 / βn) ^1/2 + Vthn (7)
(2 · βp · I11) ^1/2 + (2 · βn · I12) ^1/2
= (2 · βn · I13) ^1/2 + (2 · βp · I14) ^1/2 (8)
The left side of Equation (8) is a constant value. Since the MOS transistors 30 and 6, 32, and 9 constitute current mirror circuits, I1 and I2 are currents at levels corresponding to I14 and I13, respectively. From Equation (8), the square root of I14 and the square root of I13 are constant values, and therefore the square root of I1 and the square root of I2 are constant values. Thereby, the condition of Formula (4) is satisfied.

  FIG. 4 is a block diagram showing a configuration of the Gm-C filter 40 using the Gm amplifier 1 shown in FIG. In FIG. 4, the Gm-C filter 40 includes a plurality of stages of Gm amplifiers 1 and capacitors 41 provided corresponding to the differential output terminals of the Gm amplifier 1. Capacitor 41 is connected between a corresponding differential output terminal and a line of ground voltage GND. A control circuit 20 and a tuning circuit 43 are provided in common for the multiple stages of Gm amplifiers 1. The control circuit 20 generates VB1 and VB2 in response to the control voltage VC and supplies the generated VB1 and VB2 to each Gm amplifier 1. Tuning circuit 43 includes Gm filter 1 and capacitor 41, generates control voltage VC that compensates for manufacturing variations of Gm filter 1 and capacitor 41, and supplies the control voltage VC to control circuit 20. In the Gm-C filter 40, the Gm amplifier 1 and the control circuit 20 shown in FIGS. 1 and 3 are used, so that a wide band variable range can be realized.

FIG. 5 is a circuit block diagram showing a configuration of a second-order Gm-C low-pass filter 50 that is a specific example of the Gm-C filter 40. In FIG. 5, the second-order Gm-C low-pass filter 50 includes a four-stage Gm amplifier 1, a capacitor 51 provided corresponding to each differential output terminal of the first-stage Gm amplifier 1, and a second-stage Gm. And a capacitor 52 provided corresponding to each differential output terminal of the amplifier 1. Each of capacitors 51 and 52 is connected between a corresponding differential output terminal and a line of ground voltage GND. When the mutual conductance of the Gm amplifier 1 is g _m and the capacitance values of the capacitors 51 and 52 are C ₁ and C ₂ , respectively, the transfer function H of the second-order Gm-C low-pass filter 50 is expressed by the following equation (9). .

FIG. 6 is a circuit block diagram showing a configuration of a fifth-order Gm-C low-pass filter 60 which is another specific example of the Gm-C filter 40. In FIG. 6, the fifth-order Gm-C low-pass filter 60 includes a 10th stage Gm amplifier 1, a capacitor 61 provided corresponding to each differential output terminal of the first stage Gm amplifier 1, and a third stage Gm. The capacitor 62 provided corresponding to each differential output terminal of the amplifier 1, the capacitor 63 provided corresponding to each differential output terminal of the four-stage Gm amplifier 1, and the seventh stage Gm amplifier 1 A capacitor 64 provided corresponding to each differential output terminal and a capacitor 65 provided corresponding to each differential output terminal of the 8-stage Gm amplifier 1 are included. Each of capacitors 61 to 65 is connected between a corresponding differential output terminal and a line of ground voltage GND. When the transconductance of the Gm amplifier 1 is g _m and the capacitance values of the capacitors 61 to 65 are C _{1 to} C ₅ , the transfer function H of the second order Gm-C low-pass filter 60 is expressed by the following equation (10). .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a circuit diagram which shows the structure of Gm amplifier by Embodiment 1 of this invention. FIG. 6 is a circuit diagram showing a modification of the first embodiment. It is a circuit diagram which shows the structure of the control circuit of Gm amplifier by Embodiment 2 of this invention. It is a circuit block diagram which shows the structure of the Gm-C filter using Gm amplifier shown in FIG. FIG. 5 is a circuit block diagram illustrating a specific example of the Gm-C filter illustrated in FIG. 4. FIG. 5 is a circuit block diagram illustrating another specific example of the Gm-C filter illustrated in FIG. 4. It is a circuit diagram which shows the structure of the conventional Gm amplifier.

Explanation of symbols

  1, 11, 71 Gm amplifier, 2, 3, 21-26, 72, 73 P-channel MOS transistor, 4-9, 29-33, 74-77 N-channel MOS transistor, T1, T2, T71, T72 Differential input Terminal, T3, T4, T73, T74 differential output terminal, 12, 13, 78, 79 resistance element, 20 control circuit, 27, 28 constant current source, 40 Gm-C filter, 41, 51, 52, 61-65 Capacitor, 43 Tuning circuit, 50, 60 Low pass filter, 80 Sub Gm amplifier.

Claims (5)

A differential amplifier circuit capable of controlling an amplification factor for outputting a current or a voltage at a level corresponding to a voltage applied to the first and second differential input terminals to the first and second differential output terminals. And
First and second load elements respectively connected between a first power supply voltage line and the first and second differential output terminals;
The first electrodes are connected to the first and second differential output terminals, respectively, the control electrodes are connected to the second and first differential input terminals, respectively, and the second electrodes First and second transistors connected to each other;
A third transistor connected between a second electrode of the first and second transistors and a second power supply voltage line;
The first electrodes are connected to the first and second differential output terminals, respectively, the control electrodes are connected to the first and second differential input terminals, respectively, and the second electrodes Fourth and fifth transistors connected to each other;
A sixth transistor connected between a second electrode of the fourth and fifth transistors and a line of the second power supply voltage;
First and second control terminals connected to the control electrodes of the third and sixth transistors, respectively, for controlling the current flowing through the third and sixth transistors to control the amplification factor ;
A control circuit that controls the voltages of the first and second control terminals so that the sum of the square root of the current value of the third transistor and the square root of the current value of the sixth transistor is constant . Differential amplifier circuit. The differential amplifier circuit according to claim 1, wherein each of the first to sixth transistors is a MOS transistor. Wherein each of the first and second load element, a gate thereof receives a predetermined voltage, including a MOS transistor operating in the saturation region, the differential amplifier circuit according to claim 1 or claim 2. Wherein each of the first and second load element, a gate thereof receives a predetermined voltage, including a MOS transistor operating in the linear region, the differential amplifier circuit according to claim 1 or claim 2. Wherein each of the first and second load elements includes a resistive element, a differential amplifier circuit according to claim 1 or claim 2.

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