JP4034227B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a metal wiring such as a Cu wiring and a manufacturing method thereof.
[0002]
[Prior art]
In the field of semiconductor device manufacturing, device design rules are being reduced along with the increase in device speed and integration. As devices are reduced in size, the wiring size and the wiring interval are also reduced, so that the wiring resistance and the inter-wiring parasitic capacitance tend to increase. When the wiring resistance and the inter-wiring parasitic capacitance increase, the time constant increases, and a decrease in the signal propagation speed becomes a problem in increasing the device speed.
[0003]
Therefore, as a method for reducing the wiring resistance, techniques and products using Cu (copper), which has a smaller specific resistance than Al (aluminum), which has been widely used as a wiring material, have become widespread. When Cu is used as a wiring material, since it is difficult to finely process Cu by dry etching, conventionally, a groove wiring called a damascene wiring formed by using a CMP (Chemical Mechanical Polishing) method is generally used. Widely used in
[0004]
FIG. 34 is a sectional view showing the structure of a conventional trench wiring.
[0005]
As shown in FIG. 34, the trench wiring is formed on the base insulating film 101 formed on the semiconductor substrate (not shown).₂A barrier metal 105 for preventing diffusion of Cu is formed in the groove portion of the insulating film 102, and a Cu wiring 107 whose bottom and side surfaces are covered with the barrier metal 105 is formed. In the structure shown in the figure, the SiN film 112 on the Cu wiring 107 and the upper layer wiring not shown in the figure and SiO for ensuring the insulation of the Cu wiring 107 are shown.₂An interlayer insulating film 110 is formed in order.
[0006]
In the process of forming the structure shown in the figure, after the formation of the trench wiring, the SiO wiring is formed on the Cu wiring 107.₂When the interlayer insulating film 110 is formed, Cu becomes SiO.₂Reacts easily with SiO₂Since it diffuses into the film, a SiN film 112 by the plasma CVD method is deposited on the Cu wiring 107 as a Cu diffusion preventing film by about 50 to 150 nm, and then SiO 2₂An interlayer insulating film 110 is formed.
[0007]
By the way, with the spread of Cu as a wiring material, improvement of electromigration resistance of Cu wiring has been demanded, and as one of the methods for that purpose, the oxidation resistance around Cu wiring is improved. The structure and its method are disclosed in the literature (see, for example, Patent Document 1 and Non-Patent Document 1). These documents include SiH while heating a Si substrate having Cu wiring._FourCu and SiH exposed to gas atmosphere_FourIt has been proposed to improve the electromigration resistance of the Cu wiring by reacting with Si (silicon) in the gas and forming a Cu silicide layer on the surface of the Cu wiring.
[0008]
In addition, when a SiN film is formed as a Cu diffusion prevention film on the Cu wiring, SiH is used as a reaction gas for film formation._FourIt is known that the electromigration (EM) resistance of the Cu wiring is improved by forming a SiN film after forming a Cu silicide layer using a gas.
[0009]
In recent years, in order to further reduce the parasitic capacitance between wirings, it has been studied to use a SiC film or a SiCN film having a relative dielectric constant lower than that of the SiN film 112 instead of the SiN film 112. In recent years, in order to reduce costs and to reduce the resistance of vias serving as connection holes, dual damascene structure wirings in which vias and wirings are simultaneously formed have been studied.
[0010]
Currently, the following three methods are known for forming a wiring with a dual damascene structure. First, after forming a different interlayer insulation film to insulate wires of different layers and a wiring interlayer insulation film to insulate wires of the same layer, first etch the vias, and then groove wiring Is a via first method (hereinafter referred to as VF method) in which vias and wirings are formed. Second, after forming a different interlayer insulating film, a via etching mask insulating film is formed thereon, etched into a via pattern, then a wiring interlayer insulating film is formed, and wiring trench etching is performed. At this time, the middle first method (hereinafter referred to as MF method) is performed in which the wiring trench and the via are simultaneously etched through the mask insulating film for via etching. Third, after forming the different interlayer insulating film and the wiring interlayer insulating film, the trench is first etched, then the via is processed, and the trench first method (hereinafter referred to as the TF method) for forming the via and the wiring. Called).
[0011]
Currently, mainly from the viewpoint of the photoresist process, the VF method is used in the lower wiring portion with many fine wiring structures, and the TF method or MF method is used in the upper wiring layer while the wiring width and via diameter are relatively large. It has been.
[0012]
[Patent Document 1]
JP 2000-150517 A
[Non-Patent Document 1]
1995 IEICE Electronics Society Conference Proceedings 2, Lecture number C-418, pp115-116
[0013]
[Problems to be solved by the invention]
The problems of the conventional trench wiring structure using the above-described SiC film or SiCN film as the Cu diffusion prevention film will be described separately.
[0014]
1. When forming a SiN film as a Cu diffusion prevention film on a Cu wiring, the reaction gas for film formation by the CVD method is SiH._Four, NH_ThreeAnd N₂Is generally used. Therefore, when forming a SiN film, SiH is placed in a processing chamber for film formation in a CVD apparatus._Four, NH_ThreeAnd N₂While the gas is introduced and the temperature of the semiconductor substrate on which the Cu wiring is formed and the pressure in the processing chamber is stabilized, SiH is formed on the Cu wiring._FourAs a result, a Cu silicide layer is formed, and the electromigration resistance of the Cu wiring is improved.
[0015]
However, when a SiC film or a SiCN film is formed as a Cu diffusion preventing film on the Cu wiring, the reaction gas is SiH (CH_Three)_ThreeAnd Si (CH_Three)_FourIs widely used, SiH_FourIs not used. The Si compound gas containing these organic groups has a bond energy between Si and organic groups larger than the bond energy between Si and H, and the thermal decomposition is SiH._FourLess likely to occur. Therefore, Cu wiring is replaced by SiH (CH_Three)_ThreeOr Si (CH_Three)_FourEven when exposed to a gas atmosphere of_FourCompared with the case where it exposes to atmosphere, the reactivity of Cu and Si becomes low. Therefore, when a SiC film or a SiCN film is formed on the Cu wiring, a Cu silicide layer is not easily formed on the Cu surface by a reaction gas for film formation as compared with a case where a SiN film is formed.
[0016]
In addition, if a Cu silicide layer is not formed on the surface of the Cu wiring, the adhesion between the Cu wiring and the SiC film or the SiCN film is lowered, and Cu crystal grains in the Cu wiring cannot be stabilized, and the electromigration of the Cu wiring is not possible. It will lead to deterioration of resistance. Furthermore, the stress migration resistance is also deteriorated, and the Cu wiring is easily disconnected due to the stress of the protective film formed in the upper layer.
[0017]
2. Since the Cu silicide layer has a higher specific resistance than Cu, there is a problem that the wiring resistance is increased. Further, since the Cu silicide layer is formed only on the outermost surface of the copper wiring, when the connection hole with the upper wiring layer is further opened, the Cu silicide layer is removed by etching of the connection hole. In order to improve stress migration, it is necessary to form the Cu silicide layer sufficiently thick. As a result, there is a problem that the wiring resistance further increases.
[0018]
3. Cu wiring to SiH_FourWhen a Cu silicide layer is formed by exposure to a gas atmosphere, if the Cu surface is oxidized to form a Cu oxide layer, the Cu oxide layer on the surface reacts with Si to form a mixture of Cu, Si and O Abnormal growth occurs. This abnormal growth not only causes an increase in wiring resistance, but also tends to occur near the interface between Cu and the barrier metal at the upper end of the Cu wiring. appear.
[0019]
4). As a Cu anticorrosion method, a method is known in which a Cu oxide layer and BTA (benzotriazole) are reacted to form a BTA layer on the Cu surface to stop the progress of oxidation. Therefore, after forming the Cu wiring by the CMP method, the oxidation of Cu can be prevented by adding a process of anticorrosion treatment by BTA. However, with the BTA layer still formed, Cu and SiH_FourIs also suppressed, so a step of removing the BTA layer is required. Moreover, even if the process of removing the BTA layer is introduced, when the Cu wiring is exposed to the atmosphere after the BTA layer is removed, oxygen in the atmosphere reacts with Cu to form a Cu oxide layer on the surface of the Cu wiring. The Cu oxide layer causes the abnormal growth described above.
[0020]
5. NH is a method for removing the Cu oxide layer._ThreeAnd H₂Plasma processing using a reducing gas such as is generally known. However, when such a plasma treatment is used, the oxide layer on the Cu surface can be removed, but it is difficult to remove even the oxide layer formed in the depth direction along the Cu crystal grain interface. In addition, during the plasma treatment, the Cu wiring is heated and hillock growth due to migration proceeds, which causes a problem that the morphology of the Cu wiring surface is deteriorated.
[0021]
Next, in order to explain the problems in forming the damascene structure, a dual damascene forming method by the VF method will be briefly described. 35 to 37 are cross-sectional views showing the manufacturing process of the two-layer wiring by the dual damascene forming method using the VF method.
[0022]
First, after forming the first copper wiring 330, the Cu diffusion prevention film SiCN film 311 and the different interlayer insulating film SiO₂The film 312, the SiCN film 313 which is an etching stopper film, and the SiO which is a second wiring interlayer insulating film₂A film 317 is formed, and a via portion photoresist process is performed first (FIG. 35A). Next, etching is performed up to the SiCN film 311 which is a diffusion prevention film provided on the first copper wiring 330, and the via photoresist 314 is changed to O₂After removing by dry ashing and wet peeling (FIG. 35B), the antireflection film 325 is embedded in the via, and a photoresist process for the second groove wiring is performed (FIG. 36C), and the second groove is formed. Etch the wiring. After that, the photoresist of the second trench wiring is O₂It is removed by dry ashing or wet peeling (FIG. 36D). Subsequently, the SiCN film 311 on the first copper wiring 330 is removed by etch-back, and a connection hole with the lower layer wiring is formed (FIG. 36E). Then, a laminated film (hereinafter referred to as “Ta / TaN film”) in which tantalum (Ta) is formed on tantalum nitride (TaN), and a Cu film 321 are used as a via and a groove for the second groove wiring. At the same time (FIG. 37 (f)), SiO is obtained by CMP.₂The Ta / TaN film 320 and the Cu film 321 on the film 317 are removed to form the second copper wiring 332, and the SiCN film 322 is formed (FIG. 37 (g)).
[0023]
6). In the case of the VF method described above, as shown in FIG. 35B, etching is performed up to the SiCN film 311 which is a diffusion prevention film in the via etching process. Due to this problem, it is very difficult to stop the etching of vias with the SiCN film 311 which is a diffusion prevention film in all vias. For this reason, in the via in which the SiCN film 311 that is the diffusion prevention film has been removed during the via etching, the copper wiring at the bottom of the via is formed by the etching of the via and the second groove wiring.₂It will be exposed to dry ashing and wet stripping solution, and its surface will be oxidized and corroded to form a copper oxide layer 331, leading to lower yield of vias and lower reliability represented by via EM. become.
[0024]
Furthermore, when rework that is redo due to dimensional deviation or positional deviation is performed in the photolithography process of the second trench wiring, the copper wiring at the bottom of the via becomes O₂Exposure to dry ashing and wet stripping solution will lead to oxidation and corrosion of the Cu surface.
[0025]
Here, the relationship between the number of rework in the photolithography process of the second trench wiring and the via chain yield will be described.
[0026]
FIG. 38 is a graph showing the results of evaluating the via chain yield. Note that the via chain used for the evaluation is for calculating the defect rate of the via and has a configuration capable of measuring the via resistance value. When the measured resistance value deviated from a predetermined standard, it was determined that the via had a defect.
[0027]
As shown in FIG. 38, as the number of rework increases, the via chain yield decreases due to oxidation and corrosion of the copper surface in the via. For this reason, rework in the photolithography process leads to a decrease in reliability represented by the via EM. This problem is not limited to the VF method, and is commonly seen when etching the insulating film on the upper layer of the Cu wiring in all the damascene wiring forming methods.
[0028]
7. In general, when etching an interlayer insulating film formed on a copper wiring, in the photolithography process, when the photoresist is exposed, interference due to reflection of the lower copper wiring becomes a problem. A photoresist is applied after an antireflection film for suppressing the above is formed. However, when forming a dual damascene wiring, in the MF method, since the underlying insulating film is subjected to etching damage when the antireflection film is removed, the mask insulating film processing for via etching and the photolithography process for upper layer groove wiring processing are performed. There is a problem that an antireflection film cannot be used. In addition, in the TF method, when the insulating film under the formed wiring groove is etched, the insulating film cannot be etched if the antireflection film is embedded in the wiring groove. Therefore, the antireflection film is formed in the via photolithography process. There is a problem that can not be used.
[0029]
The present invention has been made in order to solve the above-described problems of the prior art. For metal wiring such as Cu wiring, the adhesion between the metal wiring and the metal diffusion prevention film is improved, and the metal wiring is improved. An object of the present invention is to provide a semiconductor device that has a long metal wiring lifetime and suppresses an increase in wiring resistance by improving the electromigration resistance, and a method for manufacturing the same.
[0030]
[Means for Solving the Problems]
  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a metal wiring containing at least one of copper and an alloy of copper whose upper surface is exposed in a groove portion of an insulating film formed on a semiconductor substrate. Forming a step;
  On the upper surface of the metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming an antioxidant layer;
  Removing the antioxidant layer by heating in a sealed processing chamber;
  In the sealed processing chamber, silicon is diffused from the upper surface of the metal wiring using inorganic silane gas without exposing the upper surface of the metal wiring to oxygen, thereby forming a silicon-containing metal wiring that does not contain a metal silicide layer. Process,
  On the exposed surface of the silicon-containing metal wiring and the insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a metal diffusion prevention film;
It is what has.
[0031]
  Further, according to the method of manufacturing a semiconductor device of the present invention, the first metal containing at least one of copper and a copper alloy whose upper surface is exposed in the groove portion of the first insulating film formed on the semiconductor substrate. Forming a wiring; and
  On the upper surface of the first metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a first antioxidant layer;
  Removing the first antioxidant layer by heating in a sealed processing chamber;
  In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
  An exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a first metal diffusion prevention film;
  Forming a second insulating film and a third insulating film in order on the first metal diffusion preventing film;
  Forming an opening communicating the first metal diffusion prevention film, the second insulating film, and the third insulating film until the upper surface of the first metal wiring is exposed;
  Forming a first groove connected to the opening in the third insulating film;
  A metal embedded in the opening and the first groove, a second metal wiring containing at least one of copper and a copper alloy formed in the first groove, and the first metal wiring; Forming a via plug containing at least one of copper and a copper alloy for connecting
  On the upper surface of the second metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a second antioxidant layer;
  Removing the second antioxidant layer by heating in the sealed processing chamber;
  In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
  An exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a second metal diffusion barrier film;
It is what has.
[0032]
  Further, according to the method of manufacturing a semiconductor device of the present invention, the first metal containing at least one of copper and a copper alloy whose upper surface is exposed in the groove portion of the first insulating film formed on the semiconductor substrate. Forming a wiring; and
  On the upper surface of the first metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a first antioxidant layer;
  Removing the first antioxidant layer by heating in a sealed processing chamber;
  In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
  An exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a first metal diffusion prevention film;
  Forming a second insulating film and a third insulating film in order on the first metal diffusion preventing film;
  Selectively etching the third insulating film to form a first groove;
  Opening that connects the first metal diffusion prevention film, the second insulating film, and the third insulating film and is connected to the first groove until the upper surface of the first metal wiring is exposed. Forming, and
  A metal embedded in the first groove and the opening, a second metal wiring containing at least one of copper and a copper alloy formed in the first groove, and the first metal wiring; Forming a via plug containing at least one of copper and a copper alloy for connecting
  On the upper surface of the second metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a second antioxidant layer;
  Removing the second antioxidant layer by heating in the sealed processing chamber;
  In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
  An exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a second metal diffusion barrier film;
It is what has.
[0033]
  Further, according to the method of manufacturing a semiconductor device of the present invention, the first metal containing at least one of copper and a copper alloy whose upper surface is exposed in the groove portion of the first insulating film formed on the semiconductor substrate. Forming a wiring; and
  On the upper surface of the first metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a first antioxidant layer;
  Removing the first antioxidant layer by heating in a sealed processing chamber;
  In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
  An exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a first metal diffusion prevention film;
  Forming a second insulating film and an etching stopper film in order on the first metal diffusion prevention film;
  Selectively etching the etching stopper film until the second insulating film is exposed to form a first opening;
  Forming a third insulating film on the exposed surfaces of the second insulating film and the etching stopper film;
  Forming a first groove in the third insulating film having a width equal to or greater than that of the first opening and connected to the first opening;
  A second communicating the first metal diffusion prevention film, the second insulating film, and the third insulating film until the first metal wiring is exposed at a position including the first opening. Forming an aperture;
  A second metal containing at least one of copper and a copper alloy formed in the first groove by embedding metal in the first groove, the first opening, and the second opening. Forming a via plug containing at least one of copper and a copper alloy for connecting the metal wiring and the first metal wiring;
  On the upper surface of the second metal wiring, Containing at least one of benzotriazole and benzotriazole derivativesForming a second antioxidant layer;
  Removing the second antioxidant layer by heating in the sealed processing chamber;
  In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
  An exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a second metal diffusion barrier film;
It is what has.
[0034]
  Further, according to the method of manufacturing a semiconductor device of the present invention, the first metal containing at least one of copper and a copper alloy whose upper surface is exposed in the groove portion of the first insulating film formed on the semiconductor substrate. Forming a wiring; and
  Forming a first antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the first metal wiring;
  Removing the first antioxidant layer by heating in a sealed processing chamber;
  In the sealed processing chamber,Forming a first silicon-containing metal wiring not containing a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas;,
  The exposed surface of the first silicon-containing metal wiring and the first insulating film is exposed in the sealed processing chamber without exposing the upper surface of the first metal wiring to oxygen., Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a first metal diffusion prevention film;
  Forming a second insulating film on the first metal diffusion prevention film;
  Forming an opening communicating the first metal diffusion prevention film and the second insulating film until the first metal wiring is exposed;
  Forming a via plug containing at least one of copper and a copper alloy by embedding a metal in the opening;
  Forming a second antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the top surface of the via plug;
  Removing the second antioxidant layer by heating in a sealed processing chamber;
  Forming a silicon-containing via plug that does not contain a metal silicide layer by diffusing silicon from the upper surface of the via plug using an inorganic silane gas without exposing the upper surface of the via plug to oxygen in the sealed processing chamber;
  In the sealed processing chamber,On the exposed surfaces of the via plug and the second insulating film, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a second metal diffusion barrier film;
  Forming a third insulating film on the second metal diffusion preventing film;
  Selectively etching the third insulating film until the second insulating film is exposed to form a first groove connected to the via plug;
  Forming a second metal wiring containing at least one of copper and a copper alloy by embedding a metal in the first groove portion;
  On the upper surface of the second metal wiringA third containing at least one of benzotriazole and a benzotriazole derivativeForming an antioxidant layer;
  In the sealed processing chamber,ThirdRemoving the antioxidant layer by heating;
  In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
  In the sealed processing chamber,On the exposed surfaces of the second silicon-containing metal wiring and the third insulating film, Including at least one of SiCN film, SiC film, SiOC film, and organic filmForming a third metal diffusion preventing film;
It is what has.
[0035]
  In the method for manufacturing a semiconductor device of the present invention,The step of forming the second silicon-containing metal wiring not containing the metal silicide layer by diffusing silicon from the upper surface of the second metal wiring using an inorganic silane gas diffuses the silicon into the via plug.It is good as well.
[0037]
  In the method for manufacturing a semiconductor device of the present invention,A step of nitriding the surface of the silicon-containing metal wiring and the exposed insulating film may be included between the step of forming the silicon-containing metal wiring and the step of forming the metal diffusion prevention film. Also,Silicon may be diffused throughout the wiring of the metal wiring, the metal wiring may have the highest silicon concentration on the upper surface, and the metal wiring may have a silicon concentration of 8 atoms% or less.
[0039]
In the method of manufacturing a semiconductor device according to the present invention, silicon may be diffused throughout the wiring of the first metal wiring, and the silicon concentration of the first metal wiring may be highest on the upper surface. The first metal wiring may have a silicon concentration of 8 atoms% or less.
[0041]
In the method for manufacturing a semiconductor device according to the present invention, silicon may be diffused throughout the second metal wiring, and the second metal wiring may have the highest silicon concentration on the upper surface. The second metal wiring may have a silicon concentration of 8 atoms% or less.
[0043]
In the method of manufacturing a semiconductor device according to the present invention, the via plug may have the highest silicon concentration on the upper surface, and the via plug may have a silicon concentration of 8 atoms% or less.
[0045]
In the method for manufacturing a semiconductor device of the present invention, the insulating film is made of SiO.₂, SiOC, and an organic film may be included, and the insulating film may include at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane.
[0046]
In the method for manufacturing a semiconductor device of the present invention, the insulating film has a laminated film composed of a lower film and an upper film formed on the lower film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0047]
In the method for manufacturing a semiconductor device of the present invention, the first insulating film is made of SiO.₂The first insulating film may include at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane. Also good.
[0048]
In the method of manufacturing a semiconductor device according to the present invention, the first insulating film has a laminated film including a lower film and an upper film formed on the lower film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0049]
In the method for manufacturing a semiconductor device according to the present invention, the third insulating film is made of SiO.₂, SiOC, and organic film may be included, and the third insulating film may include at least one of ladder-type hydrogen siloxane and porous ladder-type siloxane siloxane. Also good.
[0050]
In the method for manufacturing a semiconductor device of the present invention, the third insulating film has a multilayer film including a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0052]
In the method for manufacturing a semiconductor device of the present invention, the second insulating film is made of SiO.₂, SiOC, and organic film may be included, and the second insulating film includes at least one of ladder-type hydrogenated siloxane and porous ladder-type hydrogenated siloxane. It is good.
[0053]
In the method for manufacturing a semiconductor device of the present invention, the second insulating film has a lower layer film and a laminated film formed of an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0054]
  In the method of manufacturing a semiconductor device according to the present invention,,The ladder-type hydrogenated siloxane has a film density of 1.50 g / cm.^Three1.58 g / cm^ThreeThe ladder-type hydrogenated siloxane may have a film refractive index of 1.38 or more and 1.40 or less at a wavelength of 633 nm.
[0055]
In the method for manufacturing a semiconductor device of the present invention, the second insulating film may have an etching stopper film. In this case, the etching stopper film may include at least one of a SiCN film, a SiC film, a SiOC film, and an organic film.
[0060]
In the method for manufacturing a semiconductor device of the present invention, the temperature of the step of removing the antioxidant layer may be 250 ° C. or more and 400 ° C. or less, and the temperature of the step of diffusing the silicon is 250 ° C. or more and 400 ° C. It is good also as being below ° C. In this case, the temperature of the step of removing the antioxidant layer and the step of diffusing the silicon may be equal.
[0061]
In the method of manufacturing a semiconductor device according to the present invention, SiH is diffused in the step of diffusing the silicon._Four, Si₂H₆And SiH₂Cl₂At least one of these gases may be used.
[0062]
  In the method of manufacturing a semiconductor device according to the present invention,,The metal wiring may contain hydrogen. Furthermore, the metal wiring may contain carbon.
[0063]
In the method for manufacturing a semiconductor device of the present invention, the metal wiring may have a barrier metal.
[0064]
  In the method of manufacturing a semiconductor device according to the present invention,,The first metal wiring may contain hydrogen. Furthermore, the first metal wiring may contain carbon.
[0065]
In the method for manufacturing a semiconductor device of the present invention, the first metal wiring may have a barrier metal.
[0066]
  In the method of manufacturing a semiconductor device according to the present invention,,The second metal wiring and the via plug may contain hydrogen. Furthermore, the second metal wiring and the via plug may contain carbon.
[0067]
In the method for manufacturing a semiconductor device of the present invention, the second metal wiring and the via plug may have a barrier metal.
[0068]
Furthermore, in the method for manufacturing a semiconductor device of the present invention, the copper alloy includes Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and The barrier metal may include at least one of Fe, and the barrier metal may include at least one of Ti, TiN, TiSiN, Ta, TaN, and TaSiN.
[0069]
To achieve the above object, a semiconductor device of the present invention is provided in a groove in a first insulating film formed on a semiconductor substrate, and a first metal wiring in which silicon is diffused,
A first metal diffusion prevention film covering an exposed surface of the first metal wiring;
It is the structure which has.
[0070]
In the semiconductor device of the present invention, the first metal diffusion prevention film and the second insulating film formed on the first metal diffusion prevention film are connected to the top surface of the first metal wiring. Via plugs provided in the
A second metal wiring connected to the via plug and provided in a third insulating film formed on the second insulating film, in which silicon is diffused;
A second metal diffusion prevention film covering an exposed surface of the second metal wiring;
It is good also as having.
[0071]
In this case, a barrier metal that separates the via plug and the second metal wiring may be provided between the via plug and the second metal wiring, and silicon is diffused in the via plug. Also good.
[0072]
In addition, the semiconductor device of the present invention includes a first metal wiring provided in a groove in the first insulating film formed on the semiconductor substrate,
A via plug connected to an upper surface of the first metal wiring and provided in a second insulating film formed on the first insulating film, in which silicon is diffused;
A second metal wiring connected to the via plug and provided in a third insulating film formed on the second insulating film;
It is the structure which has.
[0073]
In this case, the via plug and the second metal wiring may be integrated.
[0074]
In the semiconductor device of the present invention, silicon may be diffused throughout the via plug, the via plug may have the highest silicon concentration on the upper surface, and the via plug may have a silicon concentration of 8 atoms% or less. It may be there.
[0075]
In the semiconductor device of the present invention, the via plug may be a silicon-containing metal via plug that does not contain a metal silicide layer.
[0076]
In the semiconductor device of the present invention, silicon may be diffused throughout the first metal wiring, and the first metal wiring may have the highest silicon concentration on the upper surface. The first metal wiring may have a silicon concentration of 8 atoms% or less.
[0077]
In the semiconductor device of the present invention, the first metal wiring may be a silicon-containing metal wiring that does not contain a metal silicide layer.
[0078]
In the semiconductor device of the present invention, silicon may be diffused throughout the wiring of the second metal wiring, and the second metal wiring may have the highest silicon concentration on the upper surface, The second metal wiring may have a silicon concentration of 8 atoms% or less.
[0079]
In the semiconductor device of the present invention, the second metal wiring may be a silicon-containing metal wiring that does not contain a metal silicide layer.
[0080]
In the semiconductor device of the present invention, the first metal diffusion prevention film may include at least one of a SiCN film, a SiC film, a SiOC film, and an organic film, and the second metal diffusion prevention film. The film may include at least one of a SiCN film, a SiC film, a SiOC film, and an organic film.
[0081]
In the semiconductor device of the present invention, the first insulating film is made of SiO.₂The first insulating film may include at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane. It is good.
[0082]
In the semiconductor device of the present invention, the first insulating film has a laminated film including a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0083]
In the semiconductor device of the present invention, the second insulating film is made of SiO.₂, SiOC, and organic film may be included, and the second insulating film includes at least one of ladder-type hydrogenated siloxane and porous ladder-type hydrogenated siloxane. It is good.
[0084]
In the semiconductor device of the present invention, the second insulating film has a laminated film including a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0085]
In the semiconductor device of the present invention, the third insulating film is made of SiO.₂, SiOC, and organic film may be included, and the third insulating film may include at least one of ladder-type hydrogen siloxane and porous ladder-type siloxane siloxane. Also good.
[0086]
Further, in the semiconductor device of the present invention, the third insulating film has a laminated film composed of a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film is made of SiO.₂It is good also as having.
[0087]
In the semiconductor device of the present invention, the ladder-type hydrogenated siloxane may be L-Ox, and the ladder-type hydrogenated siloxane has a film density of 1.50 g / cm.^Three1.58 g / cm^ThreeThe ladder-type hydrogenated siloxane may have a film refractive index of 1.38 or more and 1.40 or less at a wavelength of 633 nm.
[0088]
In the semiconductor device of the present invention, the first metal wiring may contain at least one of copper and a copper alloy. In this case, the first metal wiring may contain hydrogen. Furthermore, the first metal wiring may contain carbon.
[0089]
In the semiconductor device of the present invention, the first metal wiring may have a barrier metal.
[0090]
In the semiconductor device of the present invention, the second metal wiring and the via plug may contain at least one of copper and a copper alloy. In this case, the second metal wiring and the via plug may contain hydrogen. Furthermore, the second metal wiring and the via plug may contain carbon.
[0091]
In the semiconductor device of the present invention, the second metal wiring and the via plug may have a barrier metal.
[0092]
Furthermore, in the semiconductor device of the present invention, the copper alloy is selected from Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and Fe. The barrier metal may contain at least one, and the barrier metal may include at least one of Ti, TiN, TiSiN, Ta, TaN, and TaSiN.
[0093]
(Function)
In the present invention configured as described above, since silicon is diffused in the metal wiring, the adhesion with the metal diffusion preventing film is improved as compared with the case where silicon is not diffused. Further, since silicon is diffused, migration during the manufacturing process is suppressed. In addition, the resistance to electromigration and stress migration of the wiring is improved. Furthermore, since the metal wiring in which silicon is diffused has high oxidation resistance, deterioration of the wiring surface during etching is suppressed.
[0094]
In the present invention, since silicon is also diffused in the via plug, the effect of suppressing migration during the manufacturing process is further improved. In addition, the resistance to electromigration and stress migration of the wiring is further improved.
[0095]
Further, in the present invention, since the silicon concentration is high on the upper surface of the metal wiring, the adhesion with the metal diffusion prevention film as an upper layer is further improved.
[0096]
Further, in the present invention, since the silicon concentration in the metal wiring is 8 atoms% or less, it is possible to suppress the wiring resistance from becoming larger than that of the silicide layer.
[0097]
In the present invention, the metal wiring is not exposed to the oxygen atmosphere until the metal diffusion prevention film is formed on the metal wiring after the oxidation prevention layer formed on the metal wiring surface is removed. Oxidation of the metal generated along the metal crystal grain interface is suppressed. Therefore, silicon can be diffused not only in the wiring surface but also in the depth direction along the crystal grains, and a silicon-containing metal wiring containing silicon can be formed up to the wiring bottom.
[0098]
In the present invention, since the heat treatment for removing the antioxidant layer is performed in the temperature range of 250 ° C. to 400 ° C., only the wiring surface heated by the plasma in the case of the plasma treatment reacts with silicon. Formation of the silicide layer can be prevented.
[0099]
In the present invention, since the silicon diffusion process is performed in a temperature range of 250 ° C. to 400 ° C., silicon is diffused into the metal wiring without forming a silicide layer on the surface of the metal wiring.
[0100]
Further, in the present invention, since the temperature of the step of removing the antioxidant layer and the step of diffusing silicon are equal, the waiting time until temperature stabilization required when the temperature conditions are different can be reduced. Throughput is improved.
[0101]
In the present invention, the insulating film for insulating the wirings in the same layer contains ladder-type hydrogen siloxane or porous ladder-type hydrogen siloxane, so that the wiring capacity can be reduced as compared with the oxide film. The film density is 1.50 g / cm.^Three1.58 g / cm^ThreeWhen the refractive index of the film at a wavelength of 633 nm is 1.38 or more and 1.40 or less, the dielectric constant is further reduced.
[0102]
In the present invention, since at least one of a SiCN film, a SiC film, a SiOC film, and an organic film is used for the metal diffusion prevention film, the adhesion between the metal wiring in which silicon is diffused and the metal diffusion prevention film is good.
[0103]
In the present invention, since the etching stopper film is used, over-etching is prevented and the shape of the groove formed for each etching process becomes constant.
[0104]
In the present invention, the insulating film for insulating different wiring layers is made of SiO.₂Since at least one of SiOC and organic film is used, the inter-wiring capacitance can be reduced as compared with the nitride film.
[0105]
In the present invention, since at least one of the SiCN film, the SiC film, the SiOC film, and the organic film is used as the etching stopper film, the inter-wiring capacitance can be reduced as compared with the nitride film.
[0106]
In the present invention, since a film containing benzotriazole or a benzotriazole derivative is used, the effect of preventing corrosion of metal is high.
[0107]
In the present invention, since the metal wiring is a wiring containing at least one of copper and a copper alloy, the wiring resistance is reduced and the electromigration resistance is improved.
[0108]
Furthermore, in the present invention, since the metal wiring contains hydrogen, oxidation of the metal wiring is suppressed, and precipitation of metal silicide is prevented.
[0109]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
The configuration of the semiconductor device according to the first embodiment of the present invention will be described.
[0110]
FIG. 1 is a cross-sectional view showing the structure of a semiconductor device of the present invention.
[0111]
As shown in FIG. 1, the semiconductor device according to the present embodiment has a silicon-containing copper (Cu) wiring 8 in which silicon is diffused in a Cu wiring, on a base insulating film 1 formed on a semiconductor substrate (not shown). SiO₂This is a configuration provided in a groove formed in the insulating film 2. The side and bottom surfaces of the silicon-containing Cu wiring 8 are covered with the Ta / TaN film 5, and the upper surface of the silicon-containing Cu wiring 8 is covered with the SiCN film 9 which is a Cu diffusion preventing film and to ensure insulation between the wiring layers. SiO₂Interlayer insulating film 10 is formed in order. In addition to the silicon-containing Cu wiring 8 shown in FIG. 1, a semiconductor device is composed of transistors (not shown), diodes, resistors, capacitors, and the like.
[0112]
Next, a parallel plate type plasma CVD apparatus used for forming the silicon-containing Cu wiring 8 and the SiCN film 9 in the manufacturing process of the semiconductor device of the first embodiment will be described. Here, the case where a film is formed over a semiconductor substrate will be described.
[0113]
FIG. 2 is a cross-sectional view schematically showing one embodiment of the configuration of the parallel plate type plasma CVD apparatus used in the first embodiment.
[0114]
The plasma CVD apparatus includes a processing chamber 30 for performing a film forming process on the semiconductor substrate 100, a heater 32 for keeping the temperature of the semiconductor substrate 100 placed in the processing chamber 30 constant, and the semiconductor substrate 100. Is supplied to the processing chamber 30, a conveying means (not shown) for carrying out the processing chamber 30, an exhaust means 34 for keeping the pressure in the processing chamber 30 constant, and a plurality of types of reaction gases are supplied to the processing chamber 30. A gas supply unit 36 for generating a high frequency in the processing chamber 30, a heater 32, a conveying unit (not shown), an exhaust unit 34, a gas supply unit 36, and a high frequency generator 42. And a computer 38 to be controlled.
[0115]
The gas supply unit 36 is connected to the processing chamber 30 via a plurality of gas pipes 35 for supplying several kinds of reaction gases and a gas flow rate control means 37.
[0116]
An upper plate electrode 40 and a lower plate electrode 41 are provided opposite to each other in the processing chamber 30, and the upper plate electrode 40 and the lower plate electrode 41 are connected to the high frequency generator 42. The lower plate electrode 41 has the heater 32 built therein. The high frequency generator 42 generates a high frequency of a predetermined frequency and high frequency power (RF power) between the upper plate electrode 40 and the lower plate electrode 41.
[0117]
For example, when the SiCN film 9 is formed by the plasma CVD apparatus having the above configuration, the semiconductor substrate 100 placed on the lower plate electrode 41 is brought to a desired temperature by the heater 32, and the type and flow rate of the reaction gas are adjusted. A plasma of a reactive gas is generated in the processing chamber 30 by applying a desired high-frequency RF power in the processing chamber 30 to a desired processing pressure in a desired gas atmosphere, and the SiCN film 9 is formed on the semiconductor substrate 100. Form.
[0118]
In the plasma CVD apparatus, not only the silicon diffusion for forming the silicon-containing Cu wiring 8 and the film formation of the SiCN film 9 but also the processing conditions such as the gas atmosphere, the processing pressure, the processing temperature, and the RF power are set. By adjusting, the film formed on the semiconductor substrate 100 can be removed. In order to enable removal of a film formed on the semiconductor substrate 100, the plasma CVD apparatus is a single-sheet type that processes the semiconductor substrates 100 one by one.
[0119]
Next, a method for manufacturing the semiconductor device of the first embodiment using the plasma CVD apparatus will be described.
[0120]
FIG. 3 is a cross-sectional view showing a manufacturing process procedure of the semiconductor device of the first embodiment.
[0121]
An SiO film having a film thickness of 500 nm is formed by plasma CVD on a base insulating film 1 on a semiconductor substrate (not shown) on which semiconductor elements such as transistors and capacitors are formed.₂An insulating film 2 is formed. Deposited SiO₂A photoresist 3 is applied on the insulating film 2, and a resist pattern 4 for trench wiring is formed on the photoresist 3 by using a photolithography technique (FIG. 3A).
[0122]
Next, from the trench wiring resist pattern 4 to the SiO 2 by dry etching technique.₂Insulating film 2 is etched to form SiO₂A trench wiring pattern is formed in the insulating film 2. Thereafter, oxygen plasma treatment is performed.₂The photoresist 3 is removed by dry ashing and wet stripping for removing resist residues.
[0123]
Next, as shown in FIG. 3B, the exposed base insulating film 1 and SiO 2₂A Ta / TaN film 5 having a film thickness of 30 nm is formed on the insulating film 2 as a barrier metal, and a Cu layer serving as a cathode-side underlayer for electrolytic plating is formed on the formed Ta / TaN film 5 with a film thickness of 100 nm. The film is formed by sputtering. Thereafter, the Cu layer 6 is embedded in the groove wiring pattern by electrolytic plating, and then heat treatment at 400 ° C. is performed for crystallization.
[0124]
Subsequently, SiO is obtained by CMP.₂The Cu layer 6 and the Ta / TaN film 5 on the insulating film 2 are removed, and a Cu wiring 7 is formed. After the CMP process, when the abrasive grains adhering to the upper surface of the Cu wiring 7 are removed by the cleaning process, a Cu oxide layer is formed on the upper surface of the Cu wiring 7 by the water used for the cleaning process. Thereafter, when the exposed surface of the Cu oxide layer is exposed to a 1% diluted solution of BTA, the BTA and the Cu oxide layer react to form the BTA layer 11 serving as an antioxidant layer (FIG. 3C).
[0125]
In some cases, an unreacted Cu oxide layer may remain in the lower layer of the BTA layer 11, but before forming the BTA layer 11, the Cu oxide layer is reduced to several nm or less by removing the Cu oxide layer with oxalic acid or the like. Can be controlled. In this embodiment, as shown in the figure, the case where the BTA layer 11 is formed on the Cu wiring 7 will be described.
[0126]
Next, in order to remove the BTA layer 11 on the Cu wiring 7 by thermal decomposition, a processing temperature of 250 to 400 ° C., N₂Heat treatment is performed for 2 minutes under conditions of a gas flow rate of 100 to 5000 sccm and a processing pressure of 20 Torr or less.
[0127]
Next, in the plasma CVD apparatus, the exposed surface of the Cu wiring 7 from which the Cu oxide layer has been removed is not exposed to oxygen._FourGas flow rate 10-500sccm, N₂A heat treatment is performed on the Cu wiring 7 for 120 seconds under conditions of a gas flow rate of 100 to 5000 sccm and a processing pressure of 20 Torr or less to form a silicon-containing Cu wiring 8. Here, when the silicon-containing Cu wiring 8 is formed, SiH_FourDepending on the heat treatment conditions, SiO₂There is a possibility that Si is deposited on the insulating film 2 and the deposited Si causes a short circuit between the Cu wirings 7. Therefore, after the formation of the silicon-containing Cu wiring 8, NH is exposed in the plasma CVD apparatus without exposing the exposed surface of the silicon-containing Cu wiring 8 to oxygen._ThreeGas flow rate 50-1000sccm, N₂Plasma treatment is performed for 3 seconds under conditions of a gas flow rate of 100 to 5000 sccm, a processing pressure of 20 Torr or less, and an RF power of 50 to 500 W, and the silicon-containing Cu wiring 8 and SiO₂Si deposited on the surface of the insulating film 2 is nitrided.
[0128]
Next, after the nitriding treatment, without exposing the silicon-containing Cu wiring 8 to oxygen, SiH (CH_Three)_Three, NH_ThreeAnd a silicon-containing Cu wiring 8 having a surface of nitrided SiCN film 9 having a film thickness of 50 nm as a Cu diffusion preventing film and a SiO 3 film by a plasma CVD method using a reactive gas of He and SiO₂A film is formed on the insulating film 2.
[0129]
Thereafter, SiO 2 as an interlayer insulating film is formed by the plasma CVD apparatus.₂An interlayer insulating film 10 is formed on the SiCN film 9 with a film thickness of 500 nm, and an interlayer insulating film on the silicon-containing Cu wiring 8 is formed. (FIG. 3 (d)).
[0130]
For the formation of the silicon-containing Cu wiring 8, the source gas is SiH._FourWas used, but Si₂H₆And SiH₂Cl₂Inorganic silane gas such as₂In a gas atmosphere that does not contain, and a processing temperature of 250 ° C. to 400 ° C. and a processing pressure of 20 Torr or less.
[0131]
Further, since silicon is diffused in the Cu wiring 7, the adhesion with the upper Cu diffusion preventing film is improved. In order to further improve the adhesion with the Cu diffusion preventing film, it is desirable that the silicon concentration of the silicon-containing Cu wiring 8 is highest on the upper surface of the wiring. Further, in order to suppress an increase in wiring resistance, it is desirable that the silicon concentration in the silicon-containing Cu wiring 8 is 8 atoms% or less.
[0132]
Here, the difference between Cu silicide and silicon-containing Cu wiring will be described.
[0133]
FIG. 4 is a phase diagram showing states of silicon and Cu. From the phase diagram of Cu and Si shown in FIG. 4, Cu silicide is not formed and a silicon-containing Cu layer is formed when the Si content is 92: 8 or less. Wiring by this silicon-containing Cu layer becomes silicon-containing Cu wiring.
[0134]
Next, the difference between the Cu silicide formation method and the silicon-containing Cu film formation method will be described.
[0135]
A method for forming Cu silicide is disclosed in Japanese Patent Laid-Open No. 2000-150517 as follows. In this publication, as a method for manufacturing a semiconductor integrated circuit device, (a) a step of forming a groove pattern in an interlayer insulating film formed on a semiconductor substrate, and (b) a barrier layer and Cu on the interlayer insulating film are formed. Sequentially forming a film, and (c) planarizing the surface of the Cu film and the exposed surface of the barrier layer by a chemical mechanical polishing method, and embedding the Cu film and the barrier layer in the groove pattern; And (d) performing a heat treatment on the semiconductor substrate in a silane gas atmosphere in a reduced pressure state of 0.1 Torr or less to silicidize the surface of the Cu film. Cu silicide can be easily formed by this method.
[0136]
On the other hand, it is difficult to form a silicon-containing Cu film in which the silicon concentration in Cu is 8 atoms% or less with respect to the Cu silicide by the method disclosed in the above publication. As described above, the method for forming a silicon-containing Cu film in the present invention includes (d) an antioxidant layer on the surface of the Cu film after the steps (a) to (c) of JP-A-2000-150517. A step of forming, (e) a step of performing a heat treatment to remove the antioxidant layer, and (f) a step of performing a heat treatment on the semiconductor substrate in a silane-based gas atmosphere under reduced pressure without being exposed to the oxidizing atmosphere, And forming a silicon-containing Cu film. Hereinafter, the processing conditions of the steps (e) ′ and (f) ′ will be described in detail. SiH as the silane gas_FourSiH_FourSiH treatment with gas_FourThis is called processing.
[0137]
FIG. 5 shows the removal of the antioxidant layer and SiH._FourThe result of the experiment about the process conditions of a process is shown. 5A is a graph showing the heat treatment temperature dependence of Cu silicide deposition, FIG. 5B is a graph showing the heat treatment temperature dependence of BTA desorption, and FIG. It is a table | surface which shows the heat processing temperature dependence of silicon diffusion.
[0138]
The graph of FIG. 5A shows a chamber serving as a processing chamber of the CVD apparatus when BTA is formed on the Cu film as an antioxidation layer of the Cu film (● mark) and when BTA is not formed (□ mark). Heat treatment for removing the anti-oxidation layer in the chamber, and further SiH_FourThe number of Cu silicide deposits in the fine Cu wiring part after the processing is shown.
In the experiment, SiH_FourMultiple temperature conditions were provided for the treatment. Regarding the temperature range of 200 ° C. to 450 ° C., there were 11 conditions for the sample in which BTA was formed, and 4 conditions for the sample in which BTA was not formed. The number of Cu silicide precipitates was measured with an optical microscope in an observation area having an area of about 500 μm □. The horizontal axis of the graph is SiH_FourThe temperature of the treatment, and the vertical axis is the number of Cu silicide precipitates.
[0139]
When BTA is formed as shown in FIG._FourCu silicide deposition did not occur at a treatment temperature of 400 ° C. or lower, and a silicon-containing Cu film could be formed. At 425 ° C. or higher, Cu silicide precipitates were partially generated on the upper surface of the Cu wiring, and at 450 ° C., 2000 or more Cu silicide precipitates were generated. Therefore, when BTA is used, the temperature when the Cu film is exposed to the silane-based gas is preferably 400 ° C. or lower.
[0140]
On the other hand, when BTA is not formed, SiH_FourCu silicide was deposited even at a treatment temperature of 250 ° C. Therefore, if an antioxidant layer is not formed on the Cu film, SiH_FourIt was found that Cu silicide was formed when the processing temperature was 250 ° C. or higher.
[0141]
FIG. 5B is a graph showing a result of measuring a temperature-programmed desorption spectrum having a mass number of 119 corresponding to BTA by an API-MS method while performing heat treatment on a sample in which BTA is formed on a Cu film. . The horizontal axis of the graph represents the processing temperature, and the vertical axis represents the desorption strength.
[0142]
As shown in FIG. 5 (b), as the processing temperature is increased, BTA desorption begins at 180 ° C. and has a peak at which the desorption intensity is maximum at 250 ° C., and the peak decreases at 270 ° C. or higher. start. From this result, SiH at 180 ° C. or higher where BTA desorption begins._FourSince it was confirmed whether or not silicon diffuses into the Cu film by the treatment, the following will be described.
[0143]
FIG. 5C is a table showing the presence or absence of silicon in the Cu film. As shown in FIG. 5 (c), almost corresponding to the measurement result by the API-MS (Atmospheric Pressure Ion-Mass Spectroscopy) method shown in FIG. 5 (b), in the Cu film at processing temperatures of 200 ° C. and 225 ° C. Although the silicon content in the film was not confirmed, the silicon content in the Cu film was confirmed at 250 ° C. or higher.
[0144]
From the above experimental results, BTA can be sufficiently desorbed if heat treatment is performed at a temperature of 250 ° C. or higher, and SiH having a temperature of 250 ° C. or higher and 400 ° C. or lower._FourIn the case of treatment, it is possible to diffuse silicon into the Cu film without depositing Cu silicide.
[0145]
Therefore, when BTA is used for the antioxidant layer, it is preferable to form a BTA layer on the surface of the (d) ′ Cu film after the steps (a) to (c) of JP-A-2000-150517. And (e) a process of removing the antioxidant layer by performing a heat treatment at a temperature of 250 ° C. to 400 ° C. in a chamber of the CVD apparatus, and (f) an oxidizing atmosphere at the same temperature as the “antioxidant layer removing process”. A step of converting the Cu film into a silicon-containing Cu film by subjecting the semiconductor substrate to heat treatment in a silane-based gas atmosphere under reduced pressure without exposure. If the temperatures of the steps (e) ′ and (f) ′ are made equal, the waiting time until temperature stabilization required when the temperature conditions are different can be reduced, and the throughput from oxide layer removal to silicon diffusion is improved. To do.
[0146]
Although not shown here as data, when BTA is used, SiH_FourIf plasma treatment using a reducing gas is performed before the treatment, only the surface of the wiring heated by the plasma reacts with silicon, and Cu silicide abnormal precipitation is formed, which is not preferable. SiH_FourPerforming plasma treatment using a reducing gas after the gas treatment is not related to Cu silicide deposition, so there is no problem.
[0147]
In the manufacturing process procedure shown in FIG. 3, after the silicon-containing Cu wiring 8 is formed, the silicon-containing Cu wiring 8 and SiO₂Although Si deposited on the surface of the insulating film 2 is nitrided by plasma treatment, Si etching may be performed to remove Si precipitation by etching the surface by plasma treatment using He gas or Ar gas. If there is no precipitation, the nitriding treatment and the Si etching treatment may be omitted.
[0148]
Further, although the SiCN film 9 is used as the Cu diffusion preventing film, an SiC film or an organic film may be used. The organic film is, for example, a Teflon organic polymer film or an amorphous carbon film that can be formed by a plasma CVD method.
[0149]
In addition, since the silicon-containing Cu wiring 8 also has an antioxidant effect, an insulating film containing O, such as a SiOC film, may be used instead of the SiC film and the SiCN film as the Cu diffusion preventing film.
[0150]
Further, a heat treatment for removing the BTA layer 11 on the surface of the Cu wiring 7 is performed with N.₂Although it is performed in a gas atmosphere, the reaction gas is NH_Three, H₂, He, Ar and SiH_FourAt least one gas and O₂The heat treatment may be performed in an atmosphere that does not contain a gas. Furthermore, heat treatment under vacuum may be performed without flowing any gas. In this heat treatment, the BTA layer 11 can be removed if the temperature is 250 ° C. or more and 400 ° C. or less and the pressure is 20 Torr or less.
[0151]
In this example, after the formation of the antioxidant layer on the exposed surface of the Cu oxide layer on the Cu wiring 7, the processing from the removal of the antioxidant layer to the formation of the Cu diffusion prevention film is performed in a sealed processing chamber. Since the Cu wiring and the silicon-containing Cu wiring are not exposed to oxygen, an oxide layer is not formed on the upper surfaces of the Cu wiring and the silicon-containing Cu wiring. Therefore, the adhesion between the silicon-containing Cu wiring 8 and the Cu diffusion preventing film is improved, the Cu particles in the silicon-containing Cu wiring 8 are prevented from moving, and the electromigration resistance is improved. Further, disconnection of the silicon-containing Cu wiring 8 due to stress such as a protective film formed in the upper layer is prevented, and resistance to stress migration is improved. Therefore, a wiring having a long wiring life can be formed.
[0152]
The Cu layer 6 is preferably a hydrogen-containing Cu layer. That is, after the Cu-CMP process which is a CMP process to the Cu layer, the SiH film before the deposition of the SiCN film 9 serving as a barrier insulating film._FourThis is because it is desirable that hydrogen is desorbed from the Cu wiring during the gas exposure. The reason will be described in detail.
[0153]
If there is a small amount of residual oxygen in the plasma CVD apparatus that is the film forming apparatus for the SiCN film 9, oxidation proceeds at the grain interface in the Cu wiring, and SiH after the Cu-CMP treatment._FourWhen exposed to gas, the metal oxide formed unevenly on the surface of the Cu wiring tends to generate Cu silicide precipitates. On the other hand, if the Cu layer contains hydrogen, BTA removal before the formation of the SiCN film after Cu-CMP treatment and SiH_FourEven if a small amount of residual oxygen is present in the plasma CVD apparatus, hydrogen is desorbed from the Cu wiring, so that the oxidation of the grain interface in the Cu wiring does not proceed, the surface state of the Cu wiring becomes uniform, and the Cu silicide Thus, a silicon-containing Cu wiring is formed. This applies not only to the Cu layer containing hydrogen but also to the hydrogen-containing Cu alloy layer. The inclusion of hydrogen in the Cu layer could be confirmed as the desorption of a gas having a mass number of 2 by TDS (Temperature Desorption Gas Method). Further, when hydrogen in the Cu layer was analyzed by SIMS (secondary ion mass spectrometry), a count number two orders of magnitude greater than the background level was confirmed.
[0154]
Strictly speaking, in order to improve the embedding property of the Cu layer 6, a Cu plating solution to which an organic component is added (100 ppm or less) is used when the Cu layer 6 is formed. Therefore, a trace amount of carbon is contained in the Cu layer 6, and the Cu layer 6 may be a carbon-containing Cu layer.
[0155]
(Second embodiment)
The second embodiment of the present invention is characterized in that a silicon-containing copper wiring is applied to a dual damascene double-layer wiring by a VF method, and a low dielectric constant interlayer insulating film is applied to the wiring interlayer insulating film.
[0156]
The configuration of the second embodiment will be described.
[0157]
FIG. 6 is a cross-sectional view showing the structure of the semiconductor device of this example.
[0158]
As shown in FIG. 6, the semiconductor device of this example has a configuration in which a first silicon-containing copper wiring 210 is connected to a second silicon-containing copper wiring 223 through a via plug.
[0159]
The first silicon-containing copper wiring 210 is provided in a groove formed in the laminated film. The trenches include a base insulating film 201, a SiCN film 202, a ladder oxide hydride (Ladder Oxide film) 203 formed on a semiconductor substrate (not shown), and SiO.₂The film 204 is formed in a laminated film. The side and bottom surfaces of the first silicon-containing copper wiring 210 are covered with a Ta / TaN film 208. Hereinafter, Ladder Oxide will be referred to as L-Ox (NEC Electronics Co., Ltd. trademark (pending)).
[0160]
Via plug is SiO₂SiCN film 211 and SiO on film 204₂It is provided in a hole formed in the laminated film made of the film 212. The side and bottom surfaces of the hole are covered with a Ta / TaN film 220, and the inside thereof is embedded with silicon-containing copper.
[0161]
The second silicon-containing copper wiring 223 is provided in a groove formed in the laminated film. The groove is made of SiO.₂Film 212, SiCN film 213, L-Ox film 216, and SiO₂The film 217 is formed in a laminated film. A side surface of the second silicon-containing copper wiring 223 is covered with a Ta / TaN film 220, and a SiCN film 222 is formed on the upper surface of the second silicon-containing copper wiring 223.
[0162]
In addition to the first silicon-containing copper wiring 210, the via plug, and the second silicon-containing copper wiring 223, a semiconductor device includes a transistor, a diode, a resistor, a capacitor, and the like (not shown).
[0163]
Next, a method for manufacturing the semiconductor device of this example will be described.
[0164]
7 to 10 are cross-sectional views showing the manufacturing steps of the semiconductor device of the second embodiment. Detailed description of the same steps as those in the first embodiment will be omitted.
[0165]
In the manufacturing method of the semiconductor device of this embodiment, the SiCN film 202 is formed on the base insulating film 201 formed on the substrate having the semiconductor element as the etching stopper film for forming the groove portion of the first groove wiring by the plasma CVD method. To 50 nm. Next, an L-Ox film 203 which is a low dielectric constant interlayer insulating film is formed as an interlayer insulating film of the first copper trench wiring by a coating method to a thickness of 300 nm, and baking at 400 ° C. is performed by N₂30 minutes in atmosphere.
Next, SiO₂A film 204 is formed to a thickness of 100 nm by plasma CVD. Next, the deposited SiO₂A first trench wiring resist pattern 206 is formed on the film 204 (FIG. 7A).
[0166]
In addition, the first trench wiring resist pattern is SiO 2 by dry etching technology.₂The film 204 and the L-Ox film 203 are etched to form the first groove wiring pattern 207. Then O₂The photoresist 205 and the antireflection film 225 are removed by dry ashing (FIG. 7B).
[0167]
Next, the SiCN film 202, which is an etching stopper film, is etched back by dry etching, a conductive surface with the underlying semiconductor element is opened, wet stripping is performed to remove etching residues, and a first groove wiring pattern 207 is formed. To do. Next, a Ta / TaN film 208 is formed as a barrier metal by a 30 nm sputtering method, and then a Cu film 209 is formed on the Ta / TaN film 208 by a sputtering method with a film thickness of 100 nm. Thereafter, a Cu film 209 is formed to a thickness of 700 nm by electrolytic plating, and the first groove wiring pattern 207 is buried, and then N for crystallization.₂Heat treatment is performed in an atmosphere at 400 ° C. for 30 minutes (FIG. 7C).
[0168]
Next, SiO₂The Cu film 209 and the Ta / TaN film 208 on the film 204 are removed by a CMP method, and further, a surface treatment with a BTA solution is performed to form a first copper trench wiring in which the Cu surface is subjected to an oxidation treatment with a BTA layer. (FIG. 7D).
[0169]
Next, in order to remove the BTA layer on the first copper trench wiring by thermal decomposition, in the same manner as in the first embodiment, a processing temperature of 250 to 400 ° C., N₂Heat treatment is performed for 2 minutes under conditions of a gas flow rate of 100 to 5000 sccm and a processing pressure of 20 Torr or less. Further, after removing the BTA layer, the first copper trench wiring is not exposed to oxygen, and the SiH_FourGas flow rate 10-500sccm, N₂The first copper trench wiring is heat treated for 240 seconds under conditions of a gas flow rate of 100 to 5000 sccm and a processing pressure of 20 Torr or less to form a first silicon-containing copper wiring 210, and a SiCN film 211 as a Cu diffusion prevention film is formed to a thickness of 50 nm. Form a film.
[0170]
Here, the measurement result of the silicon concentration in the first silicon-containing copper wiring 210 is shown. FIG. 11 is a graph showing the silicon concentration in the depth direction of the first silicon-containing copper wiring 210. As shown in FIG. 11, the silicon concentration is highest on the surface of the wiring and decreases as it becomes deeper in the bottom surface direction.
[0171]
Next, SiO2 as an inter-layer insulating film₂A SiCN film 213 is deposited to a thickness of 400 nm using the film 212 as an etching stopper film. An L-Ox film 216 is applied and baked thereon as an interlayer insulating film for the second trench wiring, and then SiO 2 is formed thereon.₂A film 217 is formed to a thickness of 100 nm. Next, an antireflection film 225 and a photoresist 214 are applied, and a via resist pattern 215 is formed on the photoresist by using a photolithography technique (FIG. 8E).
[0172]
Next, from the via resist pattern 215 to the interlayer insulating film and the different interlayer insulating film are etched by a dry etching technique and stopped on the SiCN film 211 on the first silicon-containing copper wiring 210 (FIG. 8F). )). At this time, if there was a via where etching stopped at the SiCN film 211, there was also a via where the first silicon-containing copper wiring 210 was exposed at the via bottom without stopping etching at the SiCN film 211.
[0173]
Then O₂The antireflection film 225, the photoresist 214, and the resist residue are removed by dry ashing and wet peeling. At this time, in the via from which the SiCN film 211 has been removed, the first silicon-containing copper wiring 210 at the bottom of the via is oxidized or corroded. However, in the case of the silicon-containing copper wiring, silicon is different from the difference in electronegativity. First oxidized and stable SiO₂Since the film 224 is formed in a self-aligned manner, copper oxidation and corrosion are prevented.
[0174]
Next, an antireflection film 225 is applied and baked, a photoresist 218 is applied, and a resist pattern 219 for second groove wiring is formed on the photoresist using a photolithography technique (FIG. 9G).
[0175]
Subsequently, from the second trench wiring resist pattern 219 by dry etching technology, SiO 2₂The film 217, the L-Ox film 216, and the antireflection film 225 are etched up to the SiCN film 213 serving as an etching stopper film. Then O₂Dry ashing is performed to remove the second trench wiring photoresist 218 and antireflection film 225, etch back is performed, and the SiCN film 211 at the bottom of the via is removed. Next, the etching residue is removed by wet peeling (FIG. 9 (h)). At this time, in the via in which the SiCN film 211 is removed in the via etching process, the first silicon-containing copper wiring 210 at the bottom of the via is further oxidized or corroded. However, as described above, in the case of the silicon-containing copper wiring Because of the difference in electronegativity, silicon is oxidized first, and stable SiO₂Is formed in a self-aligned manner, so that copper oxidation and corrosion are prevented.
[0176]
Thereafter, SiO formed in a self-aligned manner at the bottom of the via.₂Is removed by RF etching before barrier sputtering, and a Ta / TaN film 220 is deposited to 30 nm by sputtering without being exposed to the atmosphere. A seed Cu film 221 is formed on the Ta / TaN film 220 to a thickness of 100 nm. Film. Thereafter, a Cu film 221 is formed to 700 nm by electrolytic plating (FIG. 9I). Next, as shown in FIG. 10J, a second copper trench wiring and a via plug are formed by CMP.
[0177]
Next, in the same manner as the first copper trench wiring, the BTA layer is removed and SiH is removed._FourTo form a second silicon-containing copper wiring 223, and a SiCN film 222 having a thickness of 50 nm was formed as a Cu diffusion prevention film (FIG. 10 (k)). At this time, as described above, the silicon concentration is highest on the surface of the wiring, and decreases as the depth increases toward the bottom surface.
[0178]
As described above, the silicon-containing copper wiring formed in this example has a stable SiO2 due to the oxidation of silicon first due to the difference in electronegativity.₂Is formed in a self-aligned manner, so that oxidation and corrosion of copper in the etching process can be prevented. Furthermore, since silicon is diffused in the film as compared with the case where Cu silicide is formed, even if the wiring surface is etched, the effect of preventing oxidation of copper is high.
[0179]
Next, the evaluation results of the via chain yield of the semiconductor device according to this example will be described.
[0180]
FIG. 12 is a graph showing the evaluation results of the via chain yield by the two-layer wiring.
[0181]
From the graph shown in FIG. 12, it can be seen that a yield better than that of pure copper wiring was obtained as in the case of copper wiring with Cu silicide (hereinafter referred to as silicide copper wiring). An example of the silicide copper wiring is disclosed in US Pat. No. 6,110,844.
[0182]
Next, evaluation results of resistance to electromigration and stress migration will be described.
[0183]
FIG. 13 is a graph showing the results of evaluating the resistance to electromigration and stress migration.
[0184]
From the graph shown in FIG. 13, it can be seen that the silicon-containing copper wiring is one digit higher in resistance to electromigration and stress migration than pure copper wiring and silicide copper wiring.
[0185]
As shown in the above evaluation results, the silicon-containing copper wiring formed in this example forms a silicide layer only on the outermost surface by diffusing silicon throughout the wiring to form a silicon-containing metal wiring. As compared with the case, the effect of suppressing the movement of the metal particles of the metal wiring is improved.
[0186]
Here, the physical properties of the L-Ox will be described.
[0187]
Various low dielectric constant materials can be used as a wiring interlayer insulating film for insulating the wirings of the same layer and a different interlayer insulating film between the lower layer wiring and the upper layer wiring, from the viewpoint of preventing wiring delay, The dielectric constant is preferably 2.9 or less, and the film density is preferably low. For example, the film density is 1.50 g / cm^Three1.58 g / cm^ThreeHereinafter, the refractive index at a wavelength of 633 nm is desirably 1.38 or more and 1.40 or less. Specific examples of such an insulating film material include the above-described L-Ox.
[0188]
FIG. 14 is a table showing physical property data of L-Ox.
[0189]
As shown in FIG. 14, the dielectric constant of L-Ox is 2.9 and the refractive index is 1.39. This indicates that L-Ox is a preferable material for the wiring interlayer insulating film and the different interlayer insulating film. As an insulating film, not only L-Ox is used alone but also SiO.₂A laminated film with a film or the like may be used. SiO₂This is because the film has a lower dielectric constant than the nitride film.
[0190]
Next, the structure of the ladder type hydrogenated siloxane will be described.
[0191]
FIG. 15 is a schematic diagram showing the structure of L-Ox having a ladder-type hydrogenated siloxane structure. N shown in FIG. 15 is a positive number of 1 or more.
[0192]
L-Ox is a polymer having a ladder-type molecular structure as shown in FIG. Thus, the fact that L-Ox has the structure shown in FIG. 15 will be described using observation results of FT-IR for performing substance identification and qualitative analysis.
[0193]
FIG. 16 is a graph showing the FT-IR observation results.
[0194]
The chart shown in FIG. 16 is characterized by a wave number of about 830 cm.^-1Is a spectrum of a sharp Si—H bond appearing in FIG. This steepness of the spectrum suggests that L-Ox has a two-dimensional structure. Also, the wave number 870 cm on the high wave number side of this steep spectrum^-1There is what is supposed to be another Si-H bond peak in the vicinity, but this spectrum is extremely small. This is also considered to indicate that the substance to be measured has a two-dimensional structure.
[0195]
Next, the dependency of the physical properties of L-Ox on the firing temperature condition will be described.
[0196]
FIG. 17 is a graph showing changes in physical properties accompanying changes in firing conditions. R. shown by a black circle in FIG. I. Indicates the refractive index at a wavelength of 633 nm, and the white square mark indicates the density. In the experiment, firing was performed in an inert gas atmosphere such as nitrogen and at a temperature of 200 ° C. to 450 ° C.
[0197]
The refractive index is a parameter that directly affects the dielectric constant, and changes between 1.38 and 1.40. The refractive index showed values exceeding 1.40 at temperatures below 200 ° C. and temperatures above 400 ° C.
[0198]
The density is 1.50 to 1.58 g / cm for L-Ox fired at 200 ° C. or more and 400 ° C. or less.^Threeshowed that. At temperatures above 400 ° C., 1.60 g / cm^ThreeA value exceeding. At a firing temperature exceeding 400 ° C., the increase in density becomes significant.
[0199]
It was not possible to measure below 200 ° C. Below 200 ° C., the wave number is about 3650 cm from the FT-IR chart not shown in the figure.^-1The spectrum of the bond assumed to be Si—OH (silanol) appearing in FIG. 6 is observed, and it is considered that Si—OH (silanol) has an influence on the physical properties.
[0200]
As described above, when an insulating film containing L-Ox is formed, L-Ox having excellent characteristics with a low dielectric constant can be stably obtained by firing at an atmospheric temperature of 200 ° C. or higher and 400 ° C. or lower. I understand that.
[0201]
Next, a difference in structure between a conventionally known three-dimensional hydrogenated silsesquioxane structure HSQ (Hydrogen Silsesquioxane; hereinafter referred to as HSQ) and L-Ox will be described.
[0202]
FIG. 18 is a schematic diagram showing the molecular skeleton of HSQ (quoted from “semiconductor technology outlook 1998: p. 431-435”).
[0203]
The materials having the above two structures are greatly different in film stability in the manufacturing process, and L-Ox shows remarkably superior film stability. This is thought to be due to the fact that L-Ox has a smaller amount of Si-H reduction than HSQ. It is also considered that this is caused by the difference in the bonding mode of hydrogen atoms in the insulating film. That is, in HSQ, hydrogen atoms are bonded to the corners of the cubic structure, whereas in L-Ox, hydrogen atoms are bonded to the side surfaces of the ladder structure. Therefore, it is considered that HSQ has a lower density around hydrogen atoms, and the hydrogen bond of HSQ has a structure richer in reactivity than L-Ox.
[0204]
Next, the difference in film stability between L-Ox and HSQ will be described.
[0205]
Two types of wiring structures are fabricated using L-Ox and HSQ, and SiH_FourWhen the silicon addition process by irradiation was performed, it was confirmed that the film quality tolerances differed greatly. Hereinafter, description will be made based on experimental data.
[0206]
SiH_FourIrradiation is performed in a chamber of a plasma CVD apparatus. Irradiation conditions are a processing temperature of 250 to 400 ° C., a processing pressure of 20 Torr or less, and a gas flow rate of SiH._Four= 10 to 500 sccm, N₂= 100-5000 sccm. HSQ and L-Ox used in the experiment were baked on a hot plate at about 200 ° C. after coating, and then baked in a diffusion furnace at 350 ° C. for 30 minutes in a diffusion furnace. A wafer was used. The film thickness and refractive index were measured with a spectroscopic ellipsometer. The dielectric constant was calculated using the capacitor value measured with the mercury probe apparatus and the film thickness value measured with the spectroscopic ellipsometer.
[0207]
FIG. 19A shows SiH._FourGraph showing film thickness shrinkage rate change with respect to irradiation time, (b) is SiH_FourGraph showing refractive index change with respect to irradiation time, (c) is SiH_FourIt is a graph which shows the dielectric constant variation | change_quantity with respect to irradiation time.
[0208]
Regarding the film thickness shrinkage rate, as shown in FIG. 19A, the film thickness of L-Ox is SiH from 0 s to 120 s._FourRegardless of the irradiation time, there was almost no change at 99% of the initial value. On the other hand, the film thickness of HSQ is SiH._FourIt decreased as the irradiation time increased, and decreased to about 80% of the initial value at the irradiation time of 120 s.
[0209]
As for the refractive index change, as shown in FIG. 19B, the refractive index changed from the initial value of 1.39 to 1.42 when irradiated with HSQ for 120 s, as measured at a wavelength of 633 nm. On the other hand, in L-Ox, the refractive index did not change from the initial value of 1.39 from the irradiation time of 0 s to 120 s.
[0210]
As for the change in dielectric constant, as shown in FIG._FourWhen the irradiation process is performed, the initial value increases from 2.9 to 3.4 with 120s irradiation. On the other hand, L-Ox did not change from the initial value of 2.9 even after irradiation for 120 s.
[0211]
From the above results, it can be seen that all of the film thickness, refractive index, and dielectric constant are SiH._FourIt became clear that L-Ox was superior in resistance to irradiation. Such SiH_FourThe difference in irradiation treatment resistance is considered to be due to the above-described difference in hydrogen bond reactivity.
[0212]
From the above, SiH_FourIn the case of performing irradiation treatment, L-Ox is preferable to HSQ as the interlayer film. In addition, even with porous L-Ox having a dielectric constant of 2.5, this L-Ox is porous._FourIt was confirmed that the resistance of the irradiation treatment was the same as that of L-Ox.
[0213]
Furthermore, since the comparative experiment was carried out about the chemical | medical solution tolerance of L-Ox and HSQ, the result is demonstrated.
[0214]
FIG. 20A is a table showing the film thickness after a certain amount of etching, and FIG. 20B is a schematic diagram showing the measurement position in the wafer. In the experiment, after immersing the wafer in an etching solution composed of ammonium fluoride and diluted HF for a certain period of time, the amount of etching at positions 5 to 5 shown in FIG. 20B was measured. The unit of numerical values in the table is angstrom (× 10^-8cm).
[0215]
As shown in FIG. 20, when the etching rates for ammonium fluoride and diluted HF were compared, it was found that L-Ox had a higher etching rate than HSQ.
[0216]
Next, the HSQ film and the L-Ox film are applied to the wiring interlayer insulating film of the actual damascene wiring structure, and SiH_FourThe result of the irradiation process will be described.
[0217]
In places where the wiring density is high, the polishing rate of the CMP process is high, so that after the CMP process, the mask SiO₂The film was missing or thinned. Therefore, the wiring is SiH_FourWhen irradiated, plasma SiO₂SiH is also applied to the HSQ film and L-Ox film below the film._FourIrradiation processing will be performed. SiH in the wiring structure of line / space = 0.2 / 0.2 micrometer_FourComparing the inter-wiring capacitance with the irradiation treatment, in HSQ, SiO₂However, L-Ox reduces SiO2 to 2-3%.₂As a result, a sufficient reduction of 8 to 12% was confirmed. Furthermore, in the case of porous L-Ox (k = 2.5), SiO₂A reduction of about 15 to 20% with respect to the film was confirmed.
[0218]
From the above, it was confirmed that L-Ox or porous L-Ox is preferable to HSQ in the actual wiring structure.
[0219]
In addition, MSQ (methyl silsesquioxane), which is a material containing carbon, and organic polymer having carbon as a main structure, are also used for an L-Ox film and a porous L-Ox film using an actual damascene structure. Compared with. In a damascene structure using a material containing carbon, such as MSQ and Organic Polymer, a thin copper oxide film was confirmed at the interface between the copper wiring and the SiCN film as the cap film, whereas L No copper oxide film was observed between the -Ox film layers or porous L-Ox. This is probably because a small amount of hydrogen was desorbed from L-Ox by the heat in the chamber before the SiCN film was formed, and this hydrogen reduced the copper oxide layer originally present after CMP.
[0220]
In addition, the carbon-containing film has a smaller amount of hydrogen alone and a larger amount of hydrocarbon gas degas than L-Ox in the heat in the chamber before the SiCN film is formed. It is expected that the layer could not be reduced sufficiently. Furthermore, when copper oxide is present in the film, it is expected that the resistance to electromigration, stress migration, and the like will deteriorate due to this. That is, it is preferable to use an L-Ox film or a porous L-Ox film as an interlayer film rather than a carbon-containing insulating film.
[0221]
(Third embodiment)
The third embodiment of the present invention is characterized in that a silicon-containing copper wiring is applied to a two-layer wiring having a dual damascene structure by the MF method, and a low dielectric constant interlayer insulating film is applied to the wiring interlayer insulating film. The configuration of the semiconductor device according to the present embodiment is the same as that of the second embodiment, and thus detailed description thereof is omitted.
[0222]
A method for manufacturing the semiconductor device of this embodiment will be described.
[0223]
21 to 23 are cross-sectional views showing the manufacturing process of the semiconductor device of the third embodiment. Detailed description of the same steps as those in the first and second embodiments will be omitted.
[0224]
In the method of manufacturing the semiconductor device according to this embodiment, first, the first silicon-containing copper wiring 210 is formed in the same manner as in the second embodiment. At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction. Next, in the same manner as in the second embodiment, the SiCN film 211 and SiO which is a different interlayer insulating film are used.₂The layers up to the film 212 are formed in order. Further, a SiCN film 213 having a thickness of 50 nm is formed thereon as a second etching stopper film (FIG. 21A).
[0225]
Next, in order to etch only the SiCN film 213 as the second etching stopper film into a via pattern, a photoresist 214 is applied, and a via resist pattern 215 is formed in the photoresist 214 by using a photolithography technique. (FIG. 21 (b)).
[0226]
Next, using the photoresist 214 as a mask, the SiCN film 213 is etched by a dry etching technique. Then O₂Dry ashing and wet stripping are performed to remove the photoresist 214 and etching residues. Next, an L-Ox film 216 is applied and baked as an interlayer insulating film of the second trench wiring, and then SiO 2 is deposited thereon.₂A film 217 is formed to a thickness of 100 nm (FIG. 21C). Next, a photoresist 218 is applied, and a second trench wiring resist pattern 219 is formed on the photoresist 218 by using a photolithography technique (FIG. 22D).
[0227]
Next, by dry etching technique, using the photoresist 218 as a mask, the interlayer insulating film of the second trench wiring is SiO.₂Using the film 217, the L-Ox film 216, and the SiCN film 213, which is the second etching stopper film in which the via-shaped pattern is formed, as the etching mask, the SiO 2 film of the different interlayer insulating film₂The film 212 was etched and stopped on the SiCN film 211 on the first silicon-containing copper wiring 210. Then O₂After the photoresist 218 is removed by dry ashing, etch back is performed to remove the SiCN film 211 on the first silicon-containing copper wiring 210 and the SiCN film 213 as the second etching stopper film. Thereafter, wet peeling was performed to remove etching residues (FIG. 22E).
[0228]
At this time, at the bottom of the via, as described in the second embodiment, SiO 2₂In the via in which the SiCN film 211 is removed in the etching process of the film 212, the copper wiring at the bottom of the via is further oxidized or corroded. However, in the case of the silicon-containing copper wiring, the silicon is first due to the difference in electronegativity. Oxidized and stable SiO₂Since the film is formed in a self-aligned manner, copper oxidation and corrosion are prevented.
[0229]
Thereafter, SiO formed in a self-aligned manner at the bottom of the via.₂The film is removed by RF etching before barrier sputtering, and a Ta / TaN film 220 is formed to 30 nm by sputtering without being exposed to the atmosphere. A seed Cu film 221 is formed on the Ta / TaN film 220 to a thickness of 100 nm. Form a film. Thereafter, a Cu film 221 is formed to 700 nm by electrolytic plating (FIG. 22F). Next, as shown in FIG. 23G, a second copper trench wiring and a via plug are formed by CMP.
[0230]
Next, in the same manner as the first copper trench wiring, the BTA layer is removed and SiH is removed._FourTo form a second silicon-containing copper wiring 223, and a SiCN film 222 having a thickness of 50 nm was formed as a Cu diffusion preventing film (FIG. 23 (h)). At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction.
[0231]
In the case of the MF method according to the present embodiment, it is necessary to perform a photolithography process on the SiCN film which is an etching stopper film. However, since the surface of the SiCN film is hydrophobic, the wettability of the antireflection film which is a coating film is high. The antireflection film cannot be used because the coating unevenness easily occurs and the SiCN film is damaged by etching when the antireflection film on the SiCN film is removed. Further, in the second groove wiring photolithography process, a thick antireflection film is deposited on the etching step portion of the etching stopper film, which hinders the dry etching process. Therefore, the second groove wiring photolithography process also prevents reflection. The membrane cannot be used. For this reason, in the conventional copper wiring, reflection of the Cu film from the lower layer cannot be suppressed, and the depth of focus (DOF: Depth of Focus) of the via is lowered, which is a problem. However, since the silicon-containing copper wiring formed in this example has a higher antireflection effect in the photolithography process than the conventional copper wiring, the photolithography process of the etching stopper film in the MF method is improved. Product yield and reliability can be improved.
[0232]
Here, the relationship between the silicon content and the reflectance will be described.
[0233]
FIG. 24 is a graph showing the relationship between the silicon-containing concentration and the reflectance. In the reflectance measurement, a Cu film not containing silicon was used as a standard sample, and samples containing silicon with various amounts of Cu were used as samples containing silicon. The measurement was performed using a spectrophotometer for the reflectance obtained when a laser having a wavelength of 260 nm was irradiated.
[0234]
From the graph shown in FIG. 24, the reflectance of the copper surface not containing silicon is 32%, but the reflectance decreases as the silicon content increases, and the reflectance is up to 2% when the silicon content is about 0.05%. Declined. Further, the reflectance hardly changed even when silicon was further contained. From this result, it was found that if the silicon content is 0.05% or more, there is an effect.
[0235]
In the second embodiment and the present embodiment, as a method of forming the groove, after dry etching of the interlayer insulating film, O₂After removing the resist by dry ashing, the SiCN film is etched back, and then etching residues are removed by wet stripping.₂The SiCN film may be etched back after resist removal and etching residue removal by dry ashing and wet stripping.
[0236]
(Fourth embodiment)
The fourth embodiment of the present invention is characterized in that a silicon-containing copper wiring is applied to a two-layer wiring having a dual damascene structure by the TF method, and a low dielectric constant interlayer insulating film is applied to the wiring interlayer insulating film. The configuration of the semiconductor device according to the present embodiment is the same as that of the second embodiment, and thus detailed description thereof is omitted.
[0237]
A method for manufacturing the semiconductor device of this embodiment will be described.
[0238]
25 to 27 are cross-sectional views showing the manufacturing steps of the semiconductor device of the fourth embodiment. Detailed description of steps similar to those in the first to third embodiments will be omitted.
[0239]
In the semiconductor device manufacturing method of this embodiment, first, the first silicon-containing copper wiring 210 is formed in the same manner as in the second embodiment. At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction. Next, in the same manner as in the second embodiment, the SiCN film 211 and SiO which is a different interlayer insulating film are used.₂The layers up to the film 212 are formed in order. Further, an SiCN film 213 having a thickness of 50 nm is formed thereon as a second etching stopper film.
[0240]
Next, an L-Ox film 216 is applied and baked as an interlayer insulating film of the second groove wiring thereon, and then SiO 2 is deposited thereon.₂A film 217 is formed to a thickness of 100 nm. Next, an antireflection film 225 and a photoresist 218 are applied, and a second groove wiring resist pattern 219 is formed on the photoresist 218 by using a photolithography technique (FIG. 25A).
[0241]
Next, by dry etching technique, using the photoresist 218 as a mask, the interlayer insulating film of the second trench wiring is SiO.₂The film 217 and the L-Ox film 216 are etched. Next, O₂The photoresist 218, the antireflection film 225, and the etching residue are removed by dry ashing and wet peeling (FIG. 25B). Next, the SiCN film 213 as the second etching stopper film is removed by the entire surface etch back (FIG. 25C).
[0242]
Next, a photoresist 214 is applied, and a via resist pattern 215 is formed on the photoresist 214 by using a photolithography technique (FIG. 26D).
[0243]
Next, by dry etching technique, using the photoresist 214 as a mask, the interlayer insulating film SiO 2₂The film 212 was etched and stopped on the SiCN film 211 on the first silicon-containing copper wiring 210. Then O₂The photoresist is removed by dry ashing (FIG. 26E). Next, the SiCN film 211 on the first silicon-containing copper wiring 210 was etched back. Thereafter, wet peeling was performed to remove etching residues (FIG. 26 (f)).
[0244]
At this time, at the bottom of the via, as described in the third embodiment, SiO 2₂In the via in which the SiCN film 211 is removed in the etching process of the film 212, the copper wiring at the bottom of the via is further oxidized or corroded. However, in the case of the silicon-containing copper wiring, the silicon is first due to the difference in electronegativity. Oxidized and stable SiO₂Since the film 224 is formed in a self-aligned manner, copper oxidation and corrosion are prevented.
[0245]
Thereafter, SiO formed in a self-aligned manner at the bottom of the via.₂The film 224 is removed by an RF etching process before barrier sputtering, and a Ta / TaN film 220 is formed to a thickness of 30 nm by a sputtering method without being exposed to the atmosphere. A seed Cu film 221 is formed on the Ta / TaN film 220. A 100 nm film is formed. Thereafter, a Cu film 221 is formed to 700 nm by electrolytic plating (FIG. 27G). Next, as shown in FIG. 27H, a second copper trench wiring and a via plug are formed by CMP.
[0246]
Next, in the same manner as the first copper trench wiring, the BTA layer is removed and SiH is removed._FourTo form a second silicon-containing copper wiring 223, and a SiCN film 222 having a thickness of 50 nm was formed as a Cu diffusion preventing film (FIG. 27 (i)). At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction.
[0247]
In the case of the TF method according to the present embodiment, it is necessary to perform a via photolithography process after forming the groove portion of the second groove wiring. However, when the antireflection film is used, the wiring groove portion is embedded with the antireflection film. SiO, which is a lower interlayer insulating film₂Since the film cannot be etched, an antireflection film cannot be used. For this reason, in the conventional copper wiring, the reflection of the Cu film from the lower layer cannot be suppressed, and the DOF of the via is lowered, which is a problem. However, since the silicon-containing copper wiring formed in this example has a higher antireflection effect in the lithography process than the conventional copper wiring, the via lithography process in the TF method is improved, and the product yield and reliability are improved. Can be improved.
[0248]
In addition, the etching stopper film is used for the second embodiment to the present embodiment, but in the etching process of the upper layer film of the etching stopper film, the etching time is controlled by controlling the processing time so as not to etch the lower layer film. The stopper film may be omitted. By omitting the etching stopper film, the inter-wiring capacitance can be reduced.
[0249]
(5th Example)
The fifth embodiment of the present invention is characterized in that a silicon-containing copper wiring is applied to a two-layer wiring having a single damascene structure, and a low dielectric constant interlayer insulating film is applied to the wiring interlayer insulating film.
[0250]
The configuration of the fifth embodiment will be described.
[0251]
FIG. 28 is a cross-sectional view showing the structure of the semiconductor device of this example.
[0252]
As shown in FIG. 28, the semiconductor device of this example has a configuration in which a first silicon-containing copper wiring 210 is connected to a second silicon-containing copper wiring 223 via a silicon-containing copper plug 228.
[0253]
The first silicon-containing copper wiring 210 is provided in a groove formed in the laminated film. The trenches are formed by a base insulating film 201, a SiCN film 202, an L-Ox film 203, and a SiO film formed on a semiconductor substrate (not shown).₂The film 204 is formed in a laminated film. The side and bottom surfaces of the first silicon-containing copper wiring 210 are covered with a Ta / TaN film 208.
[0254]
The silicon-containing copper plug 228 is made of SiO.₂SiCN film 211 and SiO on film 204₂It is provided in a hole formed in the laminated film made of the film 212. The side and bottom surfaces of the hole are covered with a Ta / TaN film 226.
[0255]
The second silicon-containing copper wiring 223 is provided in a groove formed in the laminated film. The groove portions are SiCN film 213, L-Ox film 216, and SiO.₂The film 217 is formed in a laminated film. Side and bottom surfaces of the second silicon-containing copper wiring 223 are covered with a Ta / TaN film 220, and a SiCN film 222 is formed on the upper surface of the second silicon-containing copper wiring 223.
[0256]
Note that a semiconductor device includes a transistor, a diode, a resistor, and a capacitor (not shown) in addition to the first silicon-containing copper wiring 210, the silicon-containing copper plug 228, and the second silicon-containing copper wiring 223.
[0257]
Next, a method for manufacturing the semiconductor device of this example will be described.
[0258]
29 to 32 are cross-sectional views showing the manufacturing steps of the semiconductor device of the fifth embodiment. Detailed description of the same steps as those in the first to fourth embodiments will be omitted.
[0259]
In the semiconductor device manufacturing method of this embodiment, first, the first silicon-containing copper wiring 210 is formed in the same manner as in the second embodiment. At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction.
[0260]
Next, in the same manner as in the second embodiment, the SiCN film 211 and SiO which is a different interlayer insulating film are used.₂The layers up to the film 212 are sequentially formed (FIG. 29A).
[0261]
Next, the deposited SiO₂An antireflection film 225 and a photoresist 214 are applied on the film 212, and a via resist pattern 215 is formed by using a photolithography technique (FIG. 29B).
[0262]
In addition, via etching pattern from via resist pattern by dry etching technology₂The film 212 is etched to form a via pattern. Then O₂Dry ashing is performed to remove the photoresist 214 and the antireflection film 225 (FIG. 29C). Next, the SiCN film 211 at the bottom of the via is etched back. Next, the etching residue is removed by wet peeling (FIG. 29D).
[0263]
At this time, in the via etching process, the copper wiring at the bottom of the via from which the SiCN film 211 has been removed is further oxidized or corroded. However, in the case of a silicon-containing copper wiring, silicon is first oxidized due to the difference in electronegativity. , Stable SiO₂Since the film 224 is formed in a self-aligned manner, copper oxidation and corrosion are prevented.
[0264]
Thereafter, SiO formed in a self-aligned manner at the bottom of the via.₂The film 224 is removed by an RF etching process before barrier sputtering, and a Ta / TaN film 226 is formed to a thickness of 30 nm by a sputtering method without being exposed to the atmosphere. A seed Cu film 227 is formed on the Ta / TaN film 226. A 100 nm film is formed. Thereafter, a Cu film 227 having a thickness of 700 nm is formed by electrolytic plating and embedded in the via pattern, and then heat treatment is performed at 400 ° C. for crystallization (FIG. 30E).
[0265]
Next, SiO₂The Cu film 227 and the Ta / TaN film 226 on the film 212 were removed by a CMP method, and further a surface treatment with a BTA solution was performed to form a copper via plug in which the Cu surface was oxidized with a BTA layer (FIG. 30 ( f)).
[0266]
Next, a silicon-containing copper plug 228 is formed by the same process as that for forming the first silicon-containing copper wiring 210 in the second embodiment, and a SiCN film 213 is formed to a thickness of 50 nm as a second Cu diffusion preventing film ( FIG. 30 (g)).
[0267]
Next, an L-Ox film 216 is applied and baked as a second interlayer insulating film to a thickness of 300 nm, and an SiO 2 film is formed thereon.₂A film 217 is formed to a thickness of 100 nm. Next, an antireflection film 225 and a photoresist 218 are applied, and a second groove wiring resist pattern 219 is formed on the photoresist 218 by using a photolithography technique (FIG. 31H).
[0268]
Next, by dry etching technique, using the photoresist 218 as a mask, the interlayer insulating film of the second trench wiring is SiO.₂The film 217 and the L-Ox film 216 are etched. Next, O₂The photoresist 218 and the antireflection film 225 are removed by dry ashing. Next, the SiCN film 213 of the second Cu diffusion prevention film is removed by whole surface etch back. Next, the etching residue is removed by wet peeling (FIG. 31 (i)).
[0269]
At this time, if the SiCN film is removed in the dry etching process and the via plug is exposed at the bottom of the second trench wiring in the dry etching process, it is oxidized or corroded. Due to the difference in electronegativity, silicon is oxidized first, and stable SiO₂Since the film is formed in a self-aligned manner, copper oxidation and corrosion are prevented.
[0270]
After that, SiO formed in a self-aligned manner on the upper surface of the via plug₂The film is removed by RF etching before barrier sputtering, and a Ta / TaN film 220 is formed to 30 nm by sputtering without being exposed to the atmosphere. A seed Cu film 221 is formed on the Ta / TaN film 220 to a thickness of 100 nm. Form a film. Next, a Cu film 221 is formed to 700 nm by electrolytic plating (FIG. 31 (j)). Next, a second copper trench wiring was formed by CMP, and surface treatment with a BTA solution was performed (FIG. 32 (k)).
[0271]
Next, in the same manner as the first silicon-containing copper wiring 210 and the silicon-containing copper plug 228, the BTA layer is removed and SiH_FourTo form a second silicon-containing copper wiring 223, and a SiCN film 222 having a film thickness of 50 nm is formed as a Cu diffusion preventing film (FIG. 32L). At this time, the silicon concentration is highest on the surface of the wiring, and decreases as it deepens in the bottom direction.
[0272]
As described above, the wiring formed in the present example has a metal wiring more diffused than the case where a silicide layer is formed only on the outermost surface by diffusing silicon throughout the wiring to form a silicon-containing metal wiring. The effect of suppressing the movement of the metal particles can be improved.
[0273]
In addition, the silicon-containing copper wiring formed in this example has a stable SiO2 due to the oxidation of silicon first due to the difference in electronegativity.₂Is formed in a self-aligned manner, so that oxidation and corrosion of copper in the etching process can be prevented, so that the product yield can be improved as compared with pure copper wiring.
[0274]
Further, in this embodiment, since the silicon-containing copper wiring having a high silicon concentration is formed on the upper surfaces of the first groove wiring, the second groove wiring, and the via plug by the single damascene structure, the silicon-containing copper has a dual damascene structure. The silicon concentration inside the via can be made higher than when the wiring is formed.
[0275]
Here, the result of resistance evaluation of electromigration and stress migration will be described.
[0276]
FIG. 33 is a graph showing the results of evaluating the resistance to electromigration and stress migration.
[0277]
As shown in FIG. 33, the silicon-containing copper wiring according to the present example has further improved resistance to electromigration and stress migration than the silicon-containing copper wiring formed in the dual damascene structure.
[0278]
In the fourth embodiment and the present embodiment, the groove and via are formed by dry etching the interlayer insulating film,₂After removing the resist by dry ashing, the SiCN film is etched back, and then etching residues are removed by wet stripping.₂The SiCN film may be etched back after resist removal and etching residue removal by dry ashing and wet stripping.
[0279]
From the second embodiment to the present embodiment, the interlayer insulating film is made of SiO.₂Although the film is used, the L-Ox film and SiO₂A laminated structure of films may be used. In addition, as a mask insulating film of the L-Ox film, SiO₂Although a film is used, it has excellent etching selectivity with L-Ox, and O₂An insulating film such as a SiC film, a SiCN film, and a SiOC film may be used as long as the resistance to dry ashing and wet stripping solution is excellent. Furthermore, although L-Ox is used as the low dielectric constant interlayer insulating film, SiOF such as SiOF film, SiOC film, and organic film can be used.₂Any insulating film having a relative dielectric constant lower than that of the film may be used.
[0280]
Although copper wiring was used in the first to fifth embodiments, Al, Ag (silver), W (tungsten), Mg (magnesium), Be (beryllium), Zn (zinc), Pd ( Palladium), Cd (cadmium), Au (gold), Hg (mercury), Pt (platinum), Zr (zirconium), Ti (titanium), Sn (tin), Ni (nickel) and Fe (iron) It may be a wiring containing another metal in copper, such as a metal wiring containing an alloy of copper formed with an alloy of at least one of them, and can also be applied to wiring of other metals. Even in this case, the resistance to electromigration and stress migration in the metal wiring is not reduced.
[0281]
Although the Ta / TaN film is used as the barrier metal in the first to fifth embodiments, the barrier metal may be any structure as long as it has at least one of Ti, TiN, TiSiN, Ta, TaN, and TaSiN. . Even in this case, the resistance to electromigration and stress migration in the metal wiring is not reduced.
[0282]
Further, although BTA is used to form an antioxidant film on the wiring surface, a BTA derivative having higher solubility than BTA may be used.
[0283]
Further, the semiconductor device of the present invention is a semiconductor device having a copper wiring, but may not have a transistor, a diode, a resistor, a capacitor, or the like.
[0284]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0285]
The semiconductor device manufacturing method of the present invention has good adhesion between the silicon-containing metal wiring and the metal diffusion prevention film, so that the metal particles of the metal wiring are stabilized to prevent the metal particles from moving and the electromigration resistance is improved. . Further, disconnection of the metal wiring due to stress such as a protective film formed in the upper layer is prevented, and resistance to stress migration is improved. Therefore, a metal wiring having a long wiring life can be formed.
[0286]
In addition, as in the present invention, by forming silicon-containing metal wiring by diffusing silicon throughout the wiring, the effect of suppressing the movement of metal particles in the metal wiring is improved compared to the case where a silicide layer is formed only on the outermost surface. In addition, since the silicon content of the entire wiring can be made lower than when the silicide layer is formed, an increase in wiring resistance can be suppressed.
[0287]
Further, since silicon can be diffused not only in the wiring surface but also in the depth direction along the crystal grains, a silicon-containing metal wiring containing silicon can be formed up to the wiring bottom.
[0288]
In addition, the silicon-containing copper wiring of the present invention can prevent copper oxidation and corrosion in the etching process. Compared with the case where a Cu silicide layer is formed, silicon is diffused in the film. Therefore, even if the wiring surface is etched, the copper is highly effective in preventing oxidation, and the deterioration of wiring due to etching can be suppressed. Can be improved.
[0289]
In addition, since the silicon-containing copper wiring of the present invention has a high antireflection effect in the lithography process, the product yield and reliability can be improved even in a lithography process in which an antireflection film cannot be used.
[0290]
Furthermore, by using Cu wiring as the metal wiring, an increase in wiring resistance is suppressed even when the wiring size is reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment.
FIG. 2 is a cross-sectional view schematically showing one embodiment of the configuration of a parallel plate type plasma CVD apparatus used in the first embodiment.
FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device of the first embodiment.
FIG. 4 is a phase diagram showing states of silicon and copper.
FIG. 5 shows removal of an antioxidant layer and SiH._FourIt is a graph and table | surface which show the result of the experiment about the process conditions of a process.
FIG. 6 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.
FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.
FIG. 8 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.
FIG. 9 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.
FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device of the second embodiment.
FIG. 11 is an experimental data diagram showing that the silicon-containing copper wiring of the present invention is subjected to SIMS analysis from the semiconductor substrate side and silicon is diffused in the copper wiring.
FIG. 12 is an experimental data diagram comparing the via chain yield of a product formed according to the second embodiment of the present invention and a product of a conventional structure.
FIG. 13 is an experimental data diagram comparing a via EM of a product formed according to the second embodiment of the present invention and a product having a conventional structure.
FIG. 14 is a table showing physical property data of L-Ox.
FIG. 15 is a schematic diagram showing the structure of L-Ox.
FIG. 16 is a graph showing observation results of FT-IR.
FIG. 17 is a graph showing changes in physical properties accompanying changes in firing conditions.
FIG. 18 is a schematic diagram showing the structure of HSQ.
FIG. 19 shows SiH of the present invention._FourIt is an experimental data figure about the film thickness shrinkage | contraction rate variation | change_quantity, refractive index variation | change_quantity, and relative dielectric constant variation | change_quantity of HSQ and L-Ox with respect to irradiation processing time.
FIG. 20 is a table showing a film thickness measurement result after etching a certain amount, and a schematic diagram showing measurement points.
FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment;
FIG. 22 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment.
FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device of the third embodiment.
FIG. 24 is an experimental data diagram in which the relationship between the silicon concentration and the reflectance is examined in the silicon-containing copper wiring of the present invention.
FIG. 25 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fourth embodiment;
FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fourth embodiment;
FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fourth embodiment;
FIG. 28 is a sectional view showing the structure of a semiconductor device according to a fifth embodiment;
FIG. 29 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fifth embodiment;
30 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fifth embodiment; FIG.
FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fifth embodiment;
32 is a cross-sectional view showing a manufacturing step of the semiconductor device of the fifth embodiment; FIG.
FIG. 33 is an experimental data diagram comparing a via EM of a product having a dual damascene structure and a single damascene structure using a silicon-containing copper wiring according to the present invention.
FIG. 34 is a cross-sectional view showing an example of the structure of a conventional trench wiring.
FIG. 35 is a cross-sectional view showing a manufacturing process of a conventional VF method.
FIG. 36 is a cross-sectional view showing a manufacturing process of a conventional VF method.
FIG. 37 is a cross-sectional view showing a manufacturing process of a conventional VF method.
FIG. 38 is an experimental data diagram showing the relationship between the via chain yield and the number of reworks in the photolithography process for the second trench wiring for a product formed by the conventional VF method.
[Explanation of symbols]
1, 101, 201, 301 Base insulating film
2,102 SiO₂Insulation film
3, 205, 214, 218, 314, 318 photoresist
4 Resist pattern for groove wiring
5, 208, 220, 226, 320 Ta / TaN film
6 Cu layer
7, 107 Cu wiring
8 Silicon-containing Cu wiring
9, 202, 211, 213, 222, 302, 311, 313, 322 SiCN film
10, 110 SiO₂Interlayer insulation film
11 BTA layer
12, 112 SiN film
30 treatment room
32 Heater
34 Exhaust means
35 Gas piping
36 Gas supply section
37 Gas flow rate control means
38 computers
40 Upper plate electrode
41 Lower plate electrode
42 High frequency generator
100 Semiconductor substrate
105 barrier metal
204, 212, 217, 304, 312, 317 SiO₂film
209, 221, 227, 321 Cu film
203, 216 L-Ox
206 First groove wiring resist pattern
207 First groove wiring pattern
215, 315 Via resist pattern
210 First silicon-containing copper wiring
219, 319 Second groove wiring resist pattern
223 Second silicon-containing copper wiring
224 Self-aligned SiO₂film
225, 325 Antireflection film
228 Silicon-containing copper plug
330 First copper wiring
331 Copper oxide layer
332 Second copper wiring

Claims (49)

Forming a metal wiring containing at least one of copper and an alloy of copper, the upper surface of which is exposed in the groove portion of the insulating film formed on the semiconductor substrate;
Forming an antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the metal wiring;
Removing the antioxidant layer by heating in a sealed processing chamber;
In the sealed processing chamber, silicon is diffused from the upper surface of the metal wiring using inorganic silane gas without exposing the upper surface of the metal wiring to oxygen, thereby forming a silicon-containing metal wiring that does not contain a metal silicide layer. Process,
Forming a metal diffusion prevention film including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on the exposed surface of the silicon-containing metal wiring and the insulating film in the sealed processing chamber;
A method for manufacturing a semiconductor device comprising: Forming a first metal wiring containing at least one of copper and an alloy of copper, the upper surface of which is exposed, in a groove of the first insulating film formed on the semiconductor substrate;
Forming a first antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the first metal wiring;
Removing the first antioxidant layer by heating in a sealed processing chamber;
In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
A first metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on an exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber. Forming a prevention film;
Forming a second insulating film and a third insulating film in order on the first metal diffusion preventing film;
Forming an opening communicating the first metal diffusion prevention film, the second insulating film, and the third insulating film until the upper surface of the first metal wiring is exposed;
Forming a first groove connected to the opening in the third insulating film;
A metal embedded in the opening and the first groove, a second metal wiring containing at least one of copper and a copper alloy formed in the first groove, and the first metal wiring; Forming a via plug containing at least one of copper and a copper alloy for connecting
Forming a second antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the second metal wiring;
Removing the second antioxidant layer by heating in the sealed processing chamber;
In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
Second metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on the exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber Forming a prevention film;
A method for manufacturing a semiconductor device comprising: Forming a first metal wiring containing at least one of copper and an alloy of copper, the upper surface of which is exposed, in a groove of the first insulating film formed on the semiconductor substrate;
The first metal interconnection top, forming a first anti-oxidation layer comprising at least one Chi sac benzotriazole and benzotriazole derivatives,
Removing the first antioxidant layer by heating in a sealed processing chamber;
In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
A first metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on an exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber. Forming a prevention film;
Forming a second insulating film and a third insulating film in order on the first metal diffusion preventing film;
Selectively etching the third insulating film to form a first groove;
Opening that connects the first metal diffusion prevention film, the second insulating film, and the third insulating film and is connected to the first groove until the upper surface of the first metal wiring is exposed. Forming, and
A metal embedded in the first groove and the opening, a second metal wiring containing at least one of copper and a copper alloy formed in the first groove, and the first metal wiring; Forming a via plug containing at least one of copper and a copper alloy for connecting
Forming a second antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the second metal wiring;
Removing the second antioxidant layer by heating in the sealed processing chamber;
In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
Second metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on the exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber Forming a prevention film;
A method for manufacturing a semiconductor device comprising: Forming a first metal wiring containing at least one of copper and an alloy of copper, the upper surface of which is exposed, in a groove of the first insulating film formed on the semiconductor substrate;
Forming a first antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the first metal wiring;
Removing the first antioxidant layer by heating in a sealed processing chamber;
In the sealed processing chamber, the first metal wiring does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas without exposing the upper surface of the first metal wiring to oxygen. Forming a silicon-containing metal wiring of
A first metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on an exposed surface of the first silicon-containing metal wiring and the first insulating film in the sealed processing chamber. Forming a prevention film;
Forming a second insulating film and an etching stopper film in order on the first metal diffusion prevention film;
Selectively etching the etching stopper film until the second insulating film is exposed to form a first opening;
Forming a third insulating film on the exposed surfaces of the second insulating film and the etching stopper film;
Forming a first groove in the third insulating film having a width equal to or greater than that of the first opening and connected to the first opening;
A second communicating the first metal diffusion prevention film, the second insulating film, and the third insulating film until the first metal wiring is exposed at a position including the first opening. Forming an aperture;
A second metal containing at least one of copper and a copper alloy formed in the first groove by embedding metal in the first groove, the first opening, and the second opening. Forming a via plug containing at least one of copper and a copper alloy for connecting the metal wiring and the first metal wiring;
Forming a second antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the second metal wiring;
Removing the second antioxidant layer by heating in the sealed processing chamber;
In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
Second metal diffusion including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on the exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber Forming a prevention film;
A method for manufacturing a semiconductor device comprising: Forming a first metal wiring containing at least one of copper and an alloy of copper, the upper surface of which is exposed, in a groove of the first insulating film formed on the semiconductor substrate;
Forming a first antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the upper surface of the first metal wiring;
Removing the first antioxidant layer by heating in a sealed processing chamber;
Forming a first silicon-containing metal wiring that does not contain a metal silicide layer by diffusing silicon from the upper surface of the first metal wiring using an inorganic silane gas in the sealed processing chamber ;
An SiCN film, a SiC film, and a SiOC film are exposed on the exposed surfaces of the first silicon-containing metal wiring and the first insulating film without exposing the upper surface of the first metal wiring to oxygen in the sealed processing chamber. Forming a first metal diffusion barrier film including at least one of a film and an organic film ;
Forming a second insulating film on the first metal diffusion prevention film;
Forming an opening communicating the first metal diffusion prevention film and the second insulating film until the first metal wiring is exposed;
Forming a via plug containing at least one of copper and a copper alloy by embedding a metal in the opening;
Forming a second antioxidant layer containing at least one of benzotriazole and a benzotriazole derivative on the top surface of the via plug;
Removing the second antioxidant layer by heating in a sealed processing chamber;
Forming a silicon-containing via plug that does not contain a metal silicide layer by diffusing silicon from the upper surface of the via plug using an inorganic silane gas without exposing the upper surface of the via plug to oxygen in the sealed processing chamber;
A second metal diffusion prevention film including at least one of a SiCN film, a SiC film, a SiOC film, and an organic film is formed on the exposed surface of the via plug and the second insulating film in the sealed processing chamber. Process,
Forming a third insulating film on the second metal diffusion preventing film;
Selectively etching the third insulating film until the second insulating film is exposed to form a first groove connected to the via plug;
Forming a second metal wiring containing at least one of copper and a copper alloy by embedding a metal in the first groove portion;
The second metal interconnection top, forming a third oxide prevention layer containing at least one Chi sac benzotriazole and benzotriazole derivatives,
Removing the third antioxidant layer by heating in the sealed processing chamber;
In the sealed processing chamber, a silicon silicide layer is not contained by diffusing silicon using inorganic silane gas from the upper surface of the second metal wiring without exposing the upper surface of the second metal wiring to oxygen. Forming a silicon-containing metal wiring of 2;
A third metal containing at least one of a SiCN film, a SiC film, a SiOC film, and an organic film on the exposed surface of the second silicon-containing metal wiring and the third insulating film in the sealed processing chamber. Forming a diffusion barrier film;
A method for manufacturing a semiconductor device comprising: 3. The step of forming a second silicon-containing metal wiring not containing a metal silicide layer by diffusing silicon from an upper surface of the second metal wiring using an inorganic silane gas diffuses silicon into the via plug. The method for manufacturing a semiconductor device according to any one of claims 1 to 4 .   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of nitriding the surface of the silicon-containing metal wiring and the exposed insulating film between the step of forming the silicon-containing metal wiring and the step of forming the metal diffusion prevention film. Method.   The method of manufacturing a semiconductor device according to claim 1, wherein silicon is diffused throughout the wiring of the metal wiring. 9. The method of manufacturing a semiconductor device according to claim 8 , wherein the metal wiring has the highest silicon concentration on the upper surface. 10. The method of manufacturing a semiconductor device according to claim 8 , wherein the metal wiring has a silicon concentration of 8 atoms% or less.   The method for manufacturing a semiconductor device according to claim 2, wherein silicon is diffused throughout the wiring of the first metal wiring. 12. The method of manufacturing a semiconductor device according to claim 11 , wherein the first metal wiring has the highest silicon concentration on the upper surface. The method of manufacturing a semiconductor device according to claim 11 , wherein the first metal wiring has a silicon concentration of 8 atoms% or less.   The method for manufacturing a semiconductor device according to claim 2, wherein silicon is diffused throughout the wiring of the second metal wiring. The method of manufacturing a semiconductor device according to claim 14 , wherein the second metal wiring has the highest silicon concentration on the upper surface. 16. The method of manufacturing a semiconductor device according to claim 14 , wherein the second metal wiring has a silicon concentration of 8 atoms% or less. 7. The method of manufacturing a semiconductor device according to claim 5 , wherein the via plug has the highest silicon concentration on the upper surface. The method of manufacturing a semiconductor device according to claim 17 , wherein the via plug has a silicon concentration of 8 atoms% or less. The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film includes at least one of SiO ₂ , SiOC, and an organic film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film contains at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane. The insulating film has a laminated film composed of a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The method of manufacturing a semiconductor device according to claim 1, wherein the upper layer film includes SiO ₂ . The first insulating film, SiO _2, SiOC, and the manufacturing method of at least claim includes one claim 2 or semiconductor device according to any one of 6 in the organic film. The first insulating film, a manufacturing method of a ladder-type siloxane hydride and porous ladder-type hydrogenated semiconductor device of any one of claims 2 to 6 containing at least one siloxane. The first insulating film has a laminated film composed of a lower layer film and an upper layer film formed on the lower layer film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The upper layer film manufacturing method of a semiconductor device according to any one of claims 2 to 6 having a SiO _2. The method for manufacturing a semiconductor device according to claim ₂ , wherein the third insulating film includes at least one of SiO ₂ , SiOC, and an organic film.   The method for manufacturing a semiconductor device according to claim 2, wherein the third insulating film contains at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane. The third insulating film has a laminated film composed of a lower film and an upper film formed on the lower film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The method for manufacturing a semiconductor device according to claim ₂ , wherein the upper layer film includes SiO ₂ . The second insulating film, SiO _2, SiOC, and the manufacturing method of at least claim includes one claim 2 or semiconductor device according to any one of 6 in the organic film. The second insulating film, a manufacturing method of a ladder-type siloxane hydride and porous ladder-type hydrogenated semiconductor device of any one of claims 2 to 6 containing at least one siloxane. The second insulating film has a laminated film composed of a lower film and an upper film formed on the lower film,
The underlayer has at least one of a ladder-type hydrogenated siloxane and a porous ladder-type hydrogenated siloxane;
The method for manufacturing a semiconductor device according to claim ₂ , wherein the upper layer film includes SiO ₂ . The ladder-type hydrogenated siloxane film density set forth in any one 1.50 g / cm ³ or more 1.58 g / cm ³ claims 20,21,23,24,26,27,29 and 30 or less Manufacturing method of the semiconductor device. 31. The ladder-type hydrogenated siloxane according to any one of claims 20, 21, 23, 24, 26, 27, 29 , and 30 , wherein a film has a refractive index of 1.38 or more and 1.40 or less at a wavelength of 633 nm. Manufacturing method of the semiconductor device.   6. The method of manufacturing a semiconductor device according to claim 2, wherein the second insulating film has an etching stopper film. 34. The method of manufacturing a semiconductor device according to claim 4, wherein the etching stopper film includes at least one of a SiCN film, a SiC film, a SiOC film, and an organic film. The method for manufacturing a semiconductor device according to claim 1 , wherein a temperature in the step of removing the antioxidant layer is 250 ° C. or higher and 400 ° C. or lower. 36. The method of manufacturing a semiconductor device according to claim 1 or 35 , wherein a temperature of the step of diffusing the silicon is 250 ° C. or higher and 400 ° C. or lower. 37. The method of manufacturing a semiconductor device according to claim 36 , wherein the temperatures of the step of removing the antioxidant layer and the step of diffusing the silicon are equal. In the step of diffusing the silicon, SiH _4, Si ₂ H ₆ and a manufacturing method of a semiconductor device according to any one of claims 1 to 37 using at least one of the gas SiH ₂ Cl _2.   The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring contains hydrogen. 40. The method of manufacturing a semiconductor device according to claim 39 , wherein the metal wiring contains carbon.   The method of manufacturing a semiconductor device according to claim 1, wherein the metal wiring has a barrier metal. The method of manufacturing a semiconductor device according to any one of claims 2 to 6 wherein the first metal wiring contains hydrogen. 43. The method of manufacturing a semiconductor device according to claim 42, wherein the first metal wiring contains carbon. The method of manufacturing a semiconductor device according to any one of claims 2 to 6 wherein the first metal wiring have a barrier metal. Manufacturing method of the second metal wiring and the via plug semiconductor device according to any one of claims 2 to 6 containing hydrogen. 46. The method of manufacturing a semiconductor device according to claim 45, wherein the second metal wiring and the via plug contain carbon. Manufacturing method of the second metal wiring and the via plug semiconductor device according to any one of claims 2 to 6 having a barrier metal. The copper alloy contains at least one of Al, Ag, W, Mg, Be, Zn, Pd, Cd, Au, Hg, Pt, Zr, Ti, Sn, Ni, and Fe. the method of manufacturing a semiconductor device according to any one of the 5. 48. The method of manufacturing a semiconductor device according to claim 41 , wherein the barrier metal includes at least one of Ti, TiN, TiSiN, Ta, TaN, and TaSiN.

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