JP4021806B2 - Nonvolatile semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device using electrically rewritable nonvolatile memory cells.
[0002]
[Prior art]
In recent years, NAND cell type EEPROMs have been proposed as one of nonvolatile semiconductor memory devices (EEPROMs) that can be electrically rewritten and achieve high integration. In this NAND cell type EEPROM, for example, a floating gate as a charge storage layer and a plurality of memory cells of an n-channel FETMOS structure in which a control gate is stacked via an insulating film on the floating gate, and their sources and drains are arranged. Adjacent ones are connected in series so that they are shared with each other, and this is connected as a unit to a bit line.
[0003]
The drain side of the NAND cell is connected to the bit line via a first selection MOS transistor having a first selection gate as a gate electrode, and the source side is a second selection MOS transistor having a second selection gate as a gate electrode. Connected to the source line. The control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction. Usually, a set of memory cells connected to the control gate is called one page, and a set of pages sandwiched by one set of drain-side and source-side selection MOS transistors is called one NAND block or simply one block. The memory cell array is usually formed in a p-type well formed in an n-type semiconductor substrate.
[0004]
The operation of the NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell far from the bit line. A boosted write voltage Vpp (= about 20V) is applied to the control gate of the selected memory cell, and an intermediate potential (= about 10V) is applied to the control gate of the other non-selected memory cells and the first selection gate. Then, 0V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data. At this time, the potential of the bit line is transmitted to the selected memory cell. When the data is “0”, a high voltage is applied between the floating gate and the substrate of the selected memory cell, electrons are tunneled from the substrate to the floating gate, and the threshold value moves in the positive direction. When the data is “1”, the threshold value does not change.
[0005]
Data erasure is performed almost simultaneously on all the memory cells in the NAND cell. That is, all control gates and select gates are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate. As a result, in all the memory cells, the electrons of the floating gate are released to the well, and the threshold value moves in the negative direction.
[0006]
In the data read operation, the control gate of the selected memory cell is set to 0 V, and the control gates of other memory cells are set to the power supply voltage Vcc (for example, 3 V) to detect whether or not a current flows in the selected memory cell. Done. In the NAND cell type EEPROM, since a plurality of memory cells are connected in cascade, the cell current at the time of reading is small. In addition, since the control gate and the first and second selection gates of the memory cell are continuously arranged in the row direction, data for one page is simultaneously read out to the bit line.
[0007]
(Problem 1)
A circuit example of a sense amplifier of a conventional NAND cell type EEPROM is shown in FIG. The bit line potential is detected by this sense amplifier as follows. First, when the address is set and the read mode is set, the bit line precharge control signal PREB is changed from Vcc to Vss, and the bit line BLj and the node N2 are charged to the power supply potential Vcc. Further, the sense amplifier SA is reset by setting the node N2 to Vcc and the node N1 to Vss. After selection of the word line, if the cell data is "0", the bit line potential is kept at Vcc, and if the cell data is "1", the bit line potential is discharged toward Vss. After the bit line potential is determined, the bit line potential is transferred to the node N2.
[0008]
Next, SENB changes from Vcc to Vss, SEN changes from Vss to Vcc, and the clocked inverter INV1 is activated. If the potential of the node N2 is larger than the circuit threshold value of the clocked inverter INV1, the node N1 is kept at Vss. If the potential of the node N2 is smaller than the circuit threshold value of the clocked inverter INV2, the node N1 is kept at Vcc. Thus, the potential of the bit line BLj is detected. Thereafter, the clocked inverter INV2 is activated and the detected data is latched. When the column selection signal CSLj changes from Vss to Vcc, the latched data is output to I / O and I / O '.
[0009]
In this method, as described above, cell data is detected depending on whether the potential of the floating bit line is larger or smaller than the circuit threshold value of the clocked inverter. Due to the capacitive coupling between the two, the state changes depending on the state of the adjacent bit line. For example, when "0" data is written in the cell, no read current is passed, and the potential of the bit line BLj should be kept at the precharge potential Vcc. On the other hand, when "1" data is written in a cell connected to the adjacent bit line BLi and a read current is passed, the potential of the bit line BLi drops from Vcc to Vss. Then, the potential of the bit line BLj that should be kept at Vcc is pulled down to the potential of the adjacent bit line BLi that drops from Vcc to Vss.
[0010]
Therefore, in order to correctly detect the bit line BLj as "0" data, the circuit threshold value of the clocked inverter INV1 is set low in consideration of the change in the bit line potential due to capacitive coupling between the bit lines. Must be set to In order to read the bit line BLi as "1" data, the potential of the bit line BLi must be lowered from Vcc to the circuit threshold value of the clocked inverter INV1, considering that the read current of the NAND cell is small. If the circuit threshold value of the clocked inverter INV1 is set low, the time required for detecting the bit line becomes long.
[0011]
In the sense amplifier using the clocked inverter as shown in FIG. 30, it takes a long time to detect the bit line potential. This will be exemplified below using numerical values. Assuming that the capacity between adjacent bit lines occupies 1/2 of the total capacity of the bit lines, the bit line BLj that should maintain Vcc is pulled down to Vcc / 2 in accordance with the adjacent bit line BLi. If the power supply voltage Vcc is 3V, for example, BLj is lowered to 1.5V. Therefore, the circuit threshold value of the clocked inverter INV1 is set to 1.2 V, for example, with a margin. When the read current of the NAND cell is the smallest, that is, when “1” is written in the selected cell and “0” is written in the non-selected cell, the cell current is 1 μA. If the bit line capacitance is 3 pF, the potential of the bit line BLi can be discharged to the circuit threshold.
3 pF × (3-1.2) V / 1 μA = 5.4 μs
It will take.
[0012]
As a method for solving the above-mentioned problems, the folded bit line method used in DRAM is used, and the input to the sense amplifier is set to the bit line pair BLj, / BLj, and these are operated differentially to operate at high speed. It is conceivable to read it out. Taking the case of reading a cell connected to the bit line BLj as an example, the time for discharging the bit line is estimated. If the potential of the bit line / BLj is kept at 1.5V, for example, and the potential of the bit line BLj is precharged to 1.7V, if the cell information connected to the bit line BLj is "0", the bit line BLj will be 1.7V. If it is "1", the bit line should be discharged to 1.3V. If the cell current is 1 μA and the bit line capacitance is 3 pF, the time required to discharge the bit line is:
3 pF × (1.7−1.3) / 1 μA = 1.2 μs
Thus, the reading speed is faster than the conventional single-ended method.
[0013]
In the folded bit line system, when reading a cell connected to the bit line BLj, the bit line / BLj must not be discharged. However, in the conventional NAND cell type EEPROM, the control gate of the memory cell and the first and second gates Since the selection gates are continuously arranged in the row direction, if both the cells connected to the adjacent bit lines BLj and / BLj are both written with "1", the bit lines BLj and / BLj are simultaneously discharged. Will be.
[0014]
As a method of not discharging the bit line / BLj when reading a cell connected to the bit line BLj, for example, the bit line BLj and the drain side selection gate (or the source side selection gate) of the bit line / BLj are operated at different timings. A method is conceivable. For example, in order to operate the drain side selection gate at different timings for the bit line BLj and the bit line / BLj, the control signal SGD1 for selecting the selection gate of the bit line BLj and the control signal SGD2 for selecting the bit line / BLj. Is required. Assuming that 8 memory cells are connected in series between the bit line contact and the source line, in the conventional cell array, 10 wires (8 control gates and 2 select gates) in the row direction per block. However, in this method, since 11 wirings (8 control gates and 3 selection gates) are required, the area of the cell array increases, and as a result, the chip area increases.
[0015]
(Problem 2)
As described above, in the NAND cell type EEPROM, since the memory cells are connected in series, the cell current is small, the discharge of the bit line takes several μs, and the random read takes about 10 μs. Data for one page is simultaneously detected and latched by the sense amplifier. The page read can be read in about 100 ns because it only reads the latch data. For example, when the page length is 256 bytes and one page of data is read, random read once and page read 255 times.
10 + 0.1 × 255-35μs
Takes time. Therefore, when reading data over a plurality of pages, a random read operation of 10 μs is required at the page switching unit.
[0016]
As a method of reading out data of a plurality of pages in an apparent page read cycle without the random read operation at the time of page switching, for example, there is a method of dividing the memory cell array and the sense amplifier into two and performing random read and page read simultaneously. By performing the random read operation on one side of the memory cell array divided into two while performing the random read operation on the other side, a plurality of page read timings can be maintained without interposing the random read operation at the page switching point. Data across pages can be read.
[0017]
In the conventional memory cell array, it is necessary to increase the number of peripheral circuits (such as row decoders) that transmit voltage to the word lines in order to operate the memory cell array divided into two with the random read timing shifted. In particular, in EEPROM, since a high voltage of about 20 V is applied to a word line at the time of writing, the area of a transistor constituting a peripheral circuit (such as a row decoder) that transmits the voltage to the word line is large. Therefore, when this high-speed page reading method is employed in the conventional memory cell array, there is a problem that the chip area increases due to an increase in peripheral circuits (such as row decoders) that transmit voltage to the word lines.
[0018]
(Problem 3)
As the degree of integration increases and the distance between bit lines decreases, the capacitive coupling between bit lines increases. As a result, the potential of the bit line that should maintain the “H; High” state at the time of reading is dragged to the adjacent bit line that discharges to the “L; Low” state and falls from the “H” state. In order to reduce the noise caused by the capacitive coupling between the bit lines, a method (bit line shield) for maintaining every other bit line at a constant potential during reading has been proposed (Japanese Patent Laid-Open No. 4-276393). Since reading is performed on every other bit line in the bit line shield, data writing is also performed on every other bit line.
[0019]
In the open bit line method and the single-ended method using the conventional cell array, the adjacent bit lines share the selection gate and the control gate. Therefore, when reading cell data to one bit line, the adjacent bit line is also a cell. Data is read and consequently discharged. Therefore, when using a method (bit line shield) in which every other bit line is kept at the reference potential in order to reduce noise due to the capacitive coupling between the bit lines, the reference potential must be set to 0V. As a result, when reading data written over a plurality of pages, for example, when reading data of memory cells connected to odd-numbered bit lines after reading data of memory cells connected to even-numbered bit lines The even-numbered bit lines read out first are discharged to 0V, and the odd-numbered bit lines read out second are precharged from 0V.
[0020]
That is, after reading the memory cells of the even-numbered bit lines, the next even-numbered bit lines are read after the page switching when reading the data of the odd-numbered bit lines and after reading the memory cells of the odd-numbered bit lines. It is necessary to discharge all the previously read bit lines and precharge all the bit lines to be read next from 0V when the page is switched when reading the data of this bit line. As described above, when the bit line shield is applied to the open bit line method and the single end method using a conventional cell array, there is a problem that precharge time is required for page switching and power consumption is large.
[0021]
Next, a problem that occurs at the time of writing when the bit line shield is applied to an open bit line system or a single end system using a conventional memory cell array will be described. When the bit line shield is applied as described above, writing is also performed separately for the memory cells connected to the even-numbered bit lines and the memory cells connected to the odd-numbered bit lines. Therefore, for example, when writing to a memory cell connected to an even-numbered bit line, since writing is not performed to a memory cell connected to an odd-numbered bit line, an intermediate potential (10 V) is applied to the odd-numbered bit line. Degree). That is, at the time of writing, at least half of the bit lines must be charged to the intermediate potential.
[0022]
In the write operation, first write is performed, and then verify read is performed to check whether the write is sufficiently performed. Then, additional writing is not performed on cells that are sufficiently written, and additional writing is performed only on cells that are insufficiently written. In the conventional memory cell array, when the verify read is performed after writing the memory cell connected to the even-numbered bit line, the odd-numbered bit line is also discharged from the intermediate potential, so that the memory cell connected to the even-numbered bit line, for example Is written, the odd-numbered bit lines must be charged / discharged to an intermediate potential every write-verify read cycle, and there is a problem that write time increases and power consumption also increases.
[0023]
As described above (Problem 1), if the selection gate for controlling the selection MOS transistor is changed by the adjacent bit line, the above (Problem 3) can be solved, but the source and the bit line are sandwiched instead. One extra MOS transistor area is required per NAND string, resulting in an increase in chip area.
[0024]
[Problems to be solved by the invention]
(Problem 1)
As described above, the single-ended sense amplifier used in the conventional nonvolatile semiconductor memory device has a problem that the reading time is slow. In addition, when the folded bit line method used in a so-called DRAM, which is high-speed reading, is realized in a nonvolatile semiconductor memory device, the area of the cell array increases in the conventional nonvolatile semiconductor memory device, and as a result, There was a problem that the chip area increased.
[0025]
(Problem 2)
As described above, in the conventional nonvolatile semiconductor memory device, when reading data over a plurality of pages, random read is required at the time of switching word lines. There is. In order to solve this problem, a method has been proposed in which the memory cell array and the sense amplifier are divided into two, and random read and page read are performed simultaneously. However, when this method is applied to a conventional nonvolatile semiconductor memory device, the chip area is reduced. There is a problem of increasing.
[0026]
(Problem 3)
In order to reduce noise caused by coupling capacitance between bit lines, a bit line shield that keeps every other bit line at the reference potential during reading is applied to conventional open bit line type and single-ended type memory cell arrays. Then, since writing and reading are performed on every other bit line, it is necessary to charge and discharge the non-selected bit line to an intermediate potential (about 10 V) for each write-verify read cycle. Further, when reading data over a plurality of pages, it is necessary to discharge the bit line to be shielded when the page is switched and to precharge the bit line to be selected next. For this reason, there is a problem that power consumption is large during writing and reading, and writing and reading are slow by the precharge time.
[0027]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory having a memory cell array and a sense amplifier circuit capable of high-speed random reading without increasing the chip area. To provide an apparatus.
[0028]
Another object of the present invention is to provide a non-volatile semiconductor device capable of performing a page read operation at a high speed without increasing the chip area, eliminating the dead time generated when switching word lines.
[0029]
Still another object of the present invention is to read and write data over a plurality of pages when a bit line shield is applied to an open bit line system or a single end system using a conventional cell array. An object of the present invention is to provide a semiconductor memory device that can prevent an increase in power consumption, read time, and write time.
[0030]
[Means for Solving the Problems]
In order to solve the above problems, the present invention adopts the following configuration.
[0031]
In one aspect of the present invention, a NAND cell unit in which a plurality of nonvolatile memory cells are connected in series, one end is connected to a bit line and the other end is connected to a source line, and a memory cell array including the plurality of NAND cell units; A read circuit that precharges the bit line and reads data stored in the NAND cell unit according to whether the NAND cell unit passes a current from the bit line to the source line, and is connected to each bit line A plurality of latch circuits for temporarily storing data read from the NAND cell unit and a data output circuit for outputting the data of the latch circuit to the outside, and outputting the data of the latch circuit to the outside from the data output circuit At the same time, data is read from the NAND cell unit. In the nonvolatile semiconductor memory device, the following embodiments are preferable.
(1) The latch circuit further includes a function of sensing the potential of the bit line.
[0032]
(2) A MOS transistor for controlling connection between the bit line and the latch circuit is provided between the bit line and the latch circuit.
[0033]
(3) The data of the plurality of latch circuits is divided into a plurality of times and output from the data output circuit to the outside.
[0034]
According to one aspect of the present invention, in a nonvolatile semiconductor memory device, a nonvolatile memory unit including one or a plurality of nonvolatile memory cells, and the nonvolatile memory unit are electrically connected to a first common signal line. And a second selection MOS transistor that conducts the non-volatile memory portion and the second common signal line and has a threshold value different from that of the first selection MOS transistor. The memory cell unit includes a memory cell array arranged in a matrix.
[0035]
According to one aspect of the present invention, in a nonvolatile semiconductor memory device, a nonvolatile memory unit including one or a plurality of nonvolatile memory cells and a first selection for electrically connecting the nonvolatile memory unit to a bit line A memory cell unit including a MOS transistor, a non-volatile memory unit, and a second selection MOS transistor that conducts a source line and has a threshold value different from that of the first selection MOS transistor is arranged in a matrix. And a memory cell array.
[0036]
In one aspect of the present invention, a non-volatile memory unit composed of a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory unit to a bit line, a non-volatile memory unit and a source In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a line are arranged in a matrix, the first selection MOS transistor is a first threshold value. A first memory cell unit having Vth1 and a second selection MOS transistor having a second threshold Vth2, and a first selection MOS transistor having a third threshold Vth3 and a second selection MOS. A second memory cell unit having a fourth threshold voltage Vth4; and a gate electrode of the first selection MOS transistor and The sub-array is configured by sharing the gate electrode of the second selection MOS transistor as the first and second selection gates, respectively, and the magnitude relationship between the first and third threshold values Vth1 and Vth3 and the second and fourth thresholds. This is characterized in that the relationship between the threshold values Vth2 and Vth4 is opposite.
[0037]
Further, according to one aspect of the present invention, a nonvolatile memory unit including a plurality of nonvolatile memory cells, a first selection MOS transistor that makes the nonvolatile memory unit electrically connected to a bit line, the nonvolatile memory unit, In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a source line are arranged in a matrix, the first selection MOS transistor is a first threshold. A first memory cell unit having a value Vth1, a second selection MOS transistor having a second threshold value Vth2, and a first selection MOS transistor having a third threshold value Vth3; The second memory cell unit in which the MOS transistor has the fourth threshold value Vth4 is connected to the gate electrode of the first selection MOS transistor. And the gate electrode of the second selection MOS transistor is shared as the first and second selection gates respectively to form a subarray,
The magnitude relationship between the first and third threshold values Vth1 and Vth3 is opposite to the magnitude relationship between the second and fourth threshold values Vth2 and Vth4, and the second threshold value and the second threshold value are the same. 3 is different in threshold value.
[0038]
In one aspect of the present invention, a non-volatile memory unit composed of a plurality of non-volatile memory cells, a first selection MOS transistor for electrically connecting the non-volatile memory unit to a bit line, a non-volatile memory unit and a source In a nonvolatile semiconductor memory device having a memory cell array in which memory cell units each including a second selection MOS transistor for conducting a line are arranged in a matrix, the first selection MOS transistor is a first threshold value. A first memory cell unit having Vth1 and a second selection MOS transistor having a second threshold Vth2, and a first selection MOS transistor having a third threshold Vth3 and a second selection MOS. A second memory cell unit having a fourth threshold voltage Vth4; and a gate electrode of the first selection MOS transistor and The sub-array is configured by sharing the gate electrode of the second selection MOS transistor as the first and second selection gates, respectively, and the magnitude relationship between the first and third threshold values Vth1 and Vth3 and the second and fourth thresholds. The data is stored in the nonvolatile memory portion of one of the memory cell units in the first and second memory cell units in the sub-array, which is opposite to the magnitude relationship between the threshold values Vth2 and Vth4. It is characterized by having timing means for page-reading data stored in the nonvolatile memory portion in the other memory cell unit during random reading.
[0039]
Here, preferred embodiments of the present invention include the following.
[0040]
(1) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.
[0041]
(2) The first memory cell unit and the second memory cell unit are alternately arranged to form a subarray.
[0042]
(3) When reading the non-volatile memory portion of the first memory cell unit, both the first and second selection MOS transistors of the first memory cell unit are made conductive, and the first memory cell unit first When one of the second selection MOS transistors is turned off and the nonvolatile memory portion of the second memory cell unit is read, one of the first and second selection MOS transistors of the first memory cell unit is turned off. A read selection gate voltage is applied to the first and second selection MOS transistors in the selected sub-array so that both the first and second selection MOS transistors of the second memory cell unit are turned on. Provided with means for applying.
[0043]
(4) In (3), when the data stored in the nonvolatile memory portion in one of the first memory cell unit and the second memory cell unit in the subarray is read out to the bit line In addition, the bit line connected to the other memory cell unit is kept at the unselected read bit line potential.
[0044]
(5) In (4), using the non-selected read bit line potential as a reference potential, the first bit line potential to which the first memory cell unit at the time of reading is connected and the second memory cell unit are connected. Bit line voltage detection means for differentially detecting a potential difference between the second bit line potential and the second bit line potential.
[0045]
(6) The non-volatile memory section is composed of a plurality of electrically rewritable non-volatile memory cells.
[0046]
(7) A nonvolatile memory cell is formed by laminating a charge storage layer and a control gate on a semiconductor layer, and a plurality of adjacent nonvolatile memory cells are connected in series so as to share a source and a drain. Configure a non-volatile memory unit.
[0047]
(8) A nonvolatile memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer, and one or a plurality of nonvolatile memory cells are all connected in parallel so as to share a source and a drain. A volatile memory unit.
[0048]
(9) The first, second, third and fourth threshold values are selected by controlling the impurity concentration of the channel of the nonvolatile memory cell.
[0049]
(10) The first and second selection MOS transistors are configured by stacking a charge storage layer and a selection gate on a semiconductor layer.
[0050]
(11) The gate lengths of the first selection MOS transistor and the second selection MOS transistor are different.
[0051]
(12) When performing a verify operation for checking whether writing to and writing to the nonvolatile memory portion in one of the first memory cell unit and the second memory cell unit in the subarray is sufficient Alternatively, the bit line connected to the other memory cell unit is kept at a constant potential through write, write verify, rewrite, and write verify operations.
[0052]
(13) The memory cell array is composed of a first sub-memory cell array and a second sub-memory cell array, and each of the sub-memory cell arrays is composed of first and second memory cell units, respectively. A voltage to be applied to the gate of the first selection MOS transistor is applied to the gate of the second MOS transistor of the second sub-memory cell array, and a voltage to be applied to the gate of the second MOS transistor of the first sub-memory cell array Apply to the gate of the first MOS transistor of the second sub-memory cell array.
[0053]
Further, according to one aspect of the present invention, a nonvolatile memory unit including a plurality of nonvolatile memory cells, a first selection MOS transistor that makes the nonvolatile memory unit conductive with a first common signal line, and the nonvolatile memory unit In a non-volatile semiconductor memory device having a memory cell array in which memory cell units each composed of a conductive memory portion and a second selection MOS transistor that conducts a second common signal line are arranged in a matrix, While reading or writing to a memory cell connected to one or a plurality of bit lines, among the remaining bit lines in the memory cell array, within a bit line group composed of a plurality of bit lines, It has a means for connecting / cutting off bit lines.
[0054]
Here, preferred embodiments of the present invention include the following.
[0055]
(1) The means for connecting / cutting between the bit lines is a MOS transistor provided between the bit lines.
[0056]
(2) The bit line group is composed of bit line pairs connected to the same sense amplifier circuit.
[0057]
(3) A plurality of bit lines are connected to the same sense amplifier circuit, and the sense amplifier circuit constitutes an open bit line type memory cell array disposed between the bit lines connected to the circuit.
[0058]
(4) An open bit line type memory cell array having a shared sense amplifier type in which the first bit line pair and the second bit line pair share a sense amplifier, and memory cells connected to the first bit line pair are provided. Means for connecting between the bit lines constituting the second bit line pair when reading or writing is provided.
[0059]
(5) The memory cell array includes a non-volatile memory unit including one or a plurality of non-volatile memory cells, a first selection MOS transistor that makes the non-volatile memory unit conductive with a first common signal line, A memory cell unit comprising a non-volatile memory portion and a second common signal line that are conductive and a second selection MOS transistor having a threshold value different from that of the first selection MOS transistor is arranged in a matrix. It is.
[0060]
(6) A first memory cell unit in which the first selection MOS transistor has the first threshold value Vth1, the second selection MOS transistor has the second threshold value Vth2, and the first selection MOS transistor Has a third threshold value Vth3 and the second selection MOS transistor has a fourth threshold value Vth4. The second memory cell unit includes the gate electrode of the first selection MOS transistor and the second selection MOS transistor. The gate electrode of the MOS transistor is shared as the first and second selection gates, respectively, to form a subarray. The magnitude relationship between the first and third threshold values Vth1 and Vth3 and the second and fourth threshold values Vth2 , Vth4 must be opposite in magnitude.
[0061]
(7) The first threshold value and the fourth threshold value are equal, and the second threshold value and the third threshold value are equal.
[0062]
(8) The first memory cell unit and the second memory cell unit are alternately arranged to form a subarray.
[0063]
(9) In (4), in the sub-array, the first memory cell unit is connected to the first bit line pair, and the second memory cell unit is connected to the second bit line pair.
[0064]
[Action]
In the present invention, a selection MOS transistor sharing one selection gate can be made conductive and non-conductive, and the same selection can be made by preparing two such selection gates. A memory cell in a selected state and a memory cell in a non-selected state in a memory cell having a gate Easy Can be realized. Specifically, for example, a memory connected to an even-numbered bit line by changing the threshold value of the selection gate on the source side and the selection gate on the drain side and changing the threshold value of the selection gate between adjacent memory cells. When reading the cell to the bit line, the memory cell connected to the odd-numbered bit line can be deselected. As a result, the folded bit line system can be realized without increasing the chip area, and high-speed random reading is possible.
[0065]
Further, according to the present invention, when one of the first memory cell unit and the second memory cell unit is randomly read, the other is page-read, so that the word line can be switched without increasing the chip area. It is possible to perform a page read operation at a high speed by eliminating the generated dead time. Furthermore, according to the present invention, since the precharge associated with the bit line shield or the like can be omitted, there is a problem that occurs when the bit line shield is applied to the open bit line method and the single end method using a conventional cell array, that is, It is possible to reduce the increase in power consumption and the increase in reading and writing time when reading and writing data over a plurality of pages.
[0066]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0067]
Example 1
Hereinafter, an embodiment for solving (Problem 1) will be described.
[0068]
FIG. 1 is a block diagram showing the overall configuration of a NAND cell type EEPROM according to the first embodiment of the present invention. In the figure, 1 is a memory cell array, 2 is a sense amplifier / latch circuit as latch means for writing and reading data, 3 is a row decoder for selecting word lines, 4 is a column decoder for selecting bit lines, and 5 is An address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0069]
FIG. 2 is a diagram showing a configuration of the memory cell array, where BL and / BL are bit lines, WL is a word line, STD is a first selection MOS transistor connected to the drain side of the NAND cell, and STS is a source side of the NAND cell. Second selection MOS transistor connected to, SGD is a selection gate for driving the selection MOS transistor STD, SGS is a selection gate for driving the selection MOS transistor STS, SA is a sense amplifier, TG is a sense amplifier SA and a bit line A control signal for driving a gate for connecting BL is shown.
[0070]
As shown in FIG. 2, the sense amplifier SA receives adjacent bit line pairs BLj and / BLj. This is a folded bit line system used in DRAM. In order to realize the folded bit line system, when one bit line of a bit line pair is discharged, the other bit line must not be discharged. A difference is applied to the threshold values of the selection MOS transistors (for example, STS00 and STS10, STD00 and STD10 in FIG. 2) sharing the same selection gate, and different voltages are applied to the drain side selection gate and the source side selection gate. It is realized by doing.
[0071]
In FIG. 2, a selection MOS transistor having a high threshold Vt1 (for example, 2V) is denoted as E-type, and a selection MOS transistor having a low threshold Vt2 (for example, 0.5V) (Vt1> Vt2) is denoted as I-type. ing. The voltages applied to the gates (selection gates) of the two types of selection MOS transistors are a voltage Vsgh (for example, 3 V) (Vsgh> Vt1, Vt2) that turns on both the I-type transistor and the E-type transistor, and an I-type transistor. Is a voltage Vsgl (for example, 1.5 V) (Vt1>Vsgl> Vt2) at which the E-type transistor is turned off.
[0072]
Here, the memory cell is an electrically rewritable nonvolatile memory cell in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate. A plurality of memory cells are connected in series to form a NAND cell (nonvolatile memory cell). Memory section). A first memory cell unit is configured by connecting an I-type STS and an E-type STD to the NAND cell, and an E-type STS and an I-type STD are connected to the NAND cell. The memory cell unit is configured, and the first and second memory cell units are alternately arranged. A sub-array is composed of a plurality of first and second memory cell units sharing a word line.
[0073]
A method for applying the voltage of the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00, WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source side select gate SGS0 is set to Vsgh, and the drain side select gate SGD0 is set to Vsgl. SGS1 and SGD1 are set to 0V. In this case, the source side select MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off. Therefore, if the data in the memory cell MC000 is "1", the bit line BL0 is Although it is discharged, the bit line / BL0 is not discharged regardless of the data in the memory cell MC100.
[0074]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, both the drain side selection MOS transistors STD00 and STD10 are turned on. Since the source-side selection MOS transistor STS10 is turned on, the bit line / BL0 is discharged if the data in the memory cell MC100 is "1", but the selection MOS transistor STS00 is turned off so that the bit line BL0 is not discharged.
[0075]
The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 and STS01 in FIG. 2). What is necessary is just to give a difference to the threshold value of STS11), and the method of setting the threshold value is arbitrary. For example, as shown in FIG. 3, the selection MOS transistor STD00 of the bit line BLj may be E-type, STS00 may be I-type, the selection MOS transistor STD10 of the bit line / BLj may be I-type, and STS10 may be E-type.
[0076]
In FIG. 2, the selection MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type and the selection MOS transistors on the source side are E-type. For example, as shown in FIG. 4, the bit line contact is shared. In two NAND blocks, one of the drain side selection MOS transistors may be I-type and the other may be E-type. 2 to 4, the alternately arranged bit lines BLj are simultaneously selected and read. For example, as shown in FIG. 5, the threshold value of the selection MOS transistor is set to select the bit line BL0. When this is done, the bit line / BL1 may be selected.
[0077]
In the present invention, not only this (Embodiment 1) but also all the embodiments up to (Embodiment 5) described later, among the selection MOS transistors sharing one selection gate, those in the conductive state, A conductive state can be generated, and by preparing two such select gates, a memory cell in a selected state and a memory cell in a non-selected state can be easily selected in a memory cell having the same select gate. Utilizes what can be realized.
[0078]
Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. The drain side selection MOS transistor has two threshold values of Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to the drain side selection gate is Vsghd (Vsghd> Vtd1), Vsgld (Vtd1>Vsgld> Vtd2). The source-side selection MOS transistor has two threshold values of Vts1, Vts2 (Vts1> Vts2), and voltages applied to the source-side selection gate are Vsghs (Vsghs> Vts1), Vsgls ( Vts1>Vsgls> Vts2), and Vtd1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, and Vsgld = Vsgls are not necessary.
[0079]
For example, the drain side selection MOS transistor has two threshold values of 2V and 0.5V, and the source side selection MOS transistor has two threshold values of 2.5V and 1V. The applied voltage may be Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the source side selection gate may be Vsgh = 3V, Vsgl = 1.2V.
[0080]
If Vsgh is larger than Vcc, the conductance of the selection MOS transistor is increased (that is, the resistance is decreased), and the cell current flowing through the NAND cell column is increased during reading, resulting in a shorter bit line discharge time. , Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0081]
The selection gate voltage Vsgh for making all the selection MOS transistors sharing one selection gate conductive is preferably equal to or lower than the power supply voltage Vcc. When Vsgh is larger than Vcc, a booster circuit is required in the chip, leading to an increase in chip area.
[0082]
Further, the smaller threshold value Vt2 of the selection MOS transistor may be a negative threshold value (for example, -1 V). At the time of writing, 0 V is applied to the bit line to which the cell to be written is connected, and an intermediate potential (about 10 V) is applied to the bit line to which the cell not to be written is connected. The source side select gate must be turned off so that no current flows. Therefore, when Vt2 is set to a negative threshold value of about -1V, a negative voltage (for example, -1.5V) is applied to the selection gate on the source side to turn off the selection gate having a negative threshold value at the time of writing. That's fine.
[0083]
The larger value Vt1 of the threshold values of the selection gate may be set to a voltage (for example, 3.5 V) that is equal to or higher than the power supply voltage Vcc. In this case, in order to turn on the selection MOS transistor having the threshold value Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate using a booster circuit inside the chip.
[0084]
Here, the operation for reading the memory cell MC000 connected to the bit line BLj of FIG. 6 will be described using the timing chart of FIG. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.
[0085]
First, the control signal TG changes from Vcc (for example, 3 V) to Vss, and the CMOS flip-flop FF and the bit lines BLj and / BLj are disconnected. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BLj is precharged to VA (eg, 1.7 V), and the bit line / BLj is precharged to VB (eg, 1.5 V) ( Time t1). When the precharge is finished, φpA and φpB become Vss, and the bit lines BLj and / BLj are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and selection gate (time t2).
[0086]
When reading the memory cell MC000 of FIG. 6, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V (Vsgh), and SGS0 is 1.5V (Vsgl). When the data written in the memory cell MC000 is “0”, the threshold value of the memory cell MC000 is positive, so the cell current does not flow, and the potential of the bit line BLj remains 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLj is lowered to 1.5 V or less. Since the select gate SGS0 is 1.5V, the select transistor STS10 is turned off, and the bit line / BLj is not discharged regardless of the data written in the memory cell MC100, and is kept at the precharge potential 1.5V. .
[0087]
Thereafter, SAP becomes 3V and SAN becomes 0V at time t3, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). At time t5, TG becomes 3V, and after the bit line and the sense amplifier are connected (time t6), SAN changes from 0V to 3V, and the potential difference between the bit lines BLj and / BLj is amplified. Thereafter, at time t7, the SAP is changed from 3V to 0V, and the data is latched.
[0088]
That is, if “0” is written in the memory cell MC000, the node N1 is 3V and the node N2 is 0V. If “1” is written in MC000, the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSLj changes from 0V to 3V, the data latched in the CMOS flip-flop is output to I / O and I / O '(time t8).
[0089]
Next, FIG. 10 shows a timing chart when reading the memory cell MC100 connected to the bit line / BLj in FIG. In this case, 1.5V is precharged to the bit line BLj and 1.7V is precharged to the bit line / BLj (time t1). The voltage applied to the control gate (word line) from the row decoder 3 when reading the cell data to the bit line is the same as that for reading the memory cell MC000, but the voltage applied to the selection gate is 1.5 V for SGD0 and SGS0. Is 3V (time t2).
[0090]
When the data written in the memory cell MC100 is "0", the threshold value of the memory cell MC100 is positive, so that no cell current flows and the potential of the bit line / BLj remains 1.7V. When the data is "1", a cell current flows and the potential of the bit line / BLj is lowered to 1.5 V or less. Since the selection gate SGD0 is 1.5V, the selection MOS transistor STD00 is turned off, and the bit line BLj is not discharged regardless of the data written in the memory cell MC000 and is kept at the precharge potential 1.5V. . After that, the data read out to the bit line / BLj is sensed and latched by the sense amplifier as in the case of reading out the memory cell MC000 and output to I / O and I / O ′.
[0091]
The timing of the read operation is arbitrary. For example, at time t5, as shown in FIG. 9, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BLj and / BLj to the nodes N1 and N2, and then the transfer gate may be turned off. . Accordingly, since the load capacity of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.
[0092]
8 to 10, in the sense operation of the sense amplifier, first, SAN is changed from 0V to 3V, the N-channel transistor of the CMOS flip-flop FF is turned on, and then SAP is changed from 3V to 0V. The P channel transistor is turned on, but the SAP may be changed from 3V to 0V almost simultaneously with the change of SAN from 0V to 3V.
[0093]
When the data of the cell connected to the bit line BLj is sensed and latched by the sense amplifier, one of the potentials of the bit lines BLj and / BLj is 0V and the other is Vcc (for example, 3V). After the cell data of the bit line BLj is output from the sense amplifier to I / O and I / O ', if φE is set to 3V, the bit lines BLj and / BLj are connected (equalized), and the bit line BLj is not precharged. , / BLj becomes 1.5V. Thereafter, for example, when reading the bit line / BLj, the bit line / BLj may be precharged to 1.7 V by setting φPB to 3 V and VB to 1.7 V. Thus, by connecting the bit lines BLj and / BLj after sensing the bit line BLj, the precharge time for the next read can be shortened, and the power consumption required for the precharge can be reduced.
[0094]
Further, as shown in FIG. 7, a circuit for performing verification after writing to the sense amplifier may be added.
[0095]
As a method of precharging different potentials to the bit line pair, dummy cells may be provided as shown in FIG. 11, for example, in addition to the method of transferring the potentials VA and VB from the peripheral circuit as shown in FIG. In this case, the bit lines BLj and / BLj are precharged to the same potential VPR. The current flowing in the dummy cell is set smaller than the worst read current of the cell. For example, a dummy NAND type cell connected in series is a depletion type transistor, the channel length L is increased, and the channel width W is decreased.
[0096]
If the threshold value of the dummy selection MOS transistor is set as shown in FIG. 11, when the data of the memory cell connected to the bit line BLj is read to the bit line BLj, the bit line / BLj is discharged through the dummy cell, and the bit line When reading data from the memory cell connected to / BLj, the bit line BLj is discharged through the dummy cell.
[0097]
The operation of this embodiment will be described by taking the case of reading the memory cell MC000 as an example. First, the precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to a precharge potential VPR (for example, 1.7V). Thereafter, the control gate line and selection gate of the memory cell are selected, 0V is applied to the dummy word line DWL, and substantially the same voltage as that applied to the selection gates SGS and SGD of the selection MOS transistor is applied to the dummy selection gates DSGS and DSGD. Is done.
[0098]
If “0” is written in the memory cell MC000, the bit line BLj is not discharged and maintains the precharge potential of 1.7V. If “1” is written in MC000, the bit line BLj is discharged to 1.3 V, for example. When the bit line BLj on which "1" is written is discharged to 1.3V, the bit line / BLj may be discharged to 1.5V through the dummy cell. Thereafter, the operation of differentially amplifying the potential of the bit line pair with the sense amplifier is the same as that of the embodiment of FIG.
[0099]
As a method of precharging different potentials to the bit line pair, the dummy cell may be composed of one transistor and one capacitor as shown in FIG. First, the bit line precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to the same potential VPR. When the data of the memory cell MC000 is read out to the bit line BLj after the control signal PRE becomes 0V and the bit line enters the floating state, φPB becomes 3V and the capacitor C1 is charged. The bit line / BLj drops from the precharge potential VPR by the amount of charge charged in the capacitor C1. This may be used as a reference potential when the bit line pair is differentially amplified.
[0100]
When data in the memory cell MC100 is read out to the bit line / BLj, the capacitor C0 is charged when .phi.PA becomes 3V, and the bit line BLj falls from the precharge potential VPR. The bit line BLj may be set as a reference potential.
[0101]
6 to 10, the other bit line (for example, the memory shown in FIG. 6) of the bit line pair connected to the sense amplifier is discharged while discharging the bit line to which the memory cell to be read is connected. The bit line / BLj is read when reading the cell MC000, and the bit line BLj is read when reading the memory cell MC100. However, while the bit line (for example, bit line BLj) is precharged to 1.7V and the data of the memory cell is read thereafter, the precharge control signal φPB is maintained at 3V, so that the reference bit line (for example, It is also possible to fix the bit line / BLj) to a reference potential of 1.5V.
[0102]
By maintaining the bit line / BLj at the reference potential in this way, it is possible to reduce noise due to capacitive coupling between adjacent bit lines during bit line discharge. Similarly to the case of the above-described reading, the bit line is charged / discharged according to the data written in the cell during the verify read after writing (described in detail in the fourth embodiment), but the bit line / BLj that is not read is used as the reference potential. If this is maintained, noise caused by capacitive coupling between bit lines can be reduced.
[0103]
In order to reduce noise due to capacitive coupling between adjacent bit lines when sensing and latching memory cell data read to the bit line, the twisted bit line method proposed in the DRAM as shown in FIG. It may be. A twisted bit line system as shown in FIG. 14 may be used.
[0104]
The selection MOS transistor may be composed of a cell having a selection gate and a floating gate as shown in FIG. In this embodiment, the threshold value of the selection MOS transistor can be determined by injecting electrons into the floating gate of the selection MOS transistor before shipping the semiconductor memory device. Electrons may be injected into the floating gate of the drain-side selection MOS transistor (for example, STD00 in FIG. 15) by tunneling from the substrate.
[0105]
That is, the word lines WL00 to WL07 are at an intermediate potential (about 10V) or 0V, the selection gate SGD0 is Vpp (about 20V), the selection gate SGD0 is 0V, the bit line BL0 is 0V, and the bit lines / BL0, BL1, and / BL1 are intermediate. What is necessary is just to set it as an electric potential (about 10V). Further, in order to determine the threshold value of the source-side selection MOS transistor, the selection gates SGD0 and SGS0 and the word lines WL00 to WL07 are all set to "H" to turn on all the NAND cell columns, and the bit line BL0 has Vpp or Hot electrons may be injected by applying 0 V to the intermediate potential and the bit lines / BL0, BL1, and / BL1.
[0106]
As described above, according to the present invention, by changing the threshold value of the selection MOS transistor and the voltage applied to the selection gate, a folded bit line system can be realized without increasing the chip area, and high-speed random reading can be performed. It becomes possible. As a method of changing the threshold value, it is conceivable to change the gate oxide film thickness of the selection MOS transistor, or to change the concentration of impurities doped in the channel of the selection MOS transistor. Alternatively, the threshold value may be made different depending on whether or not the selection MOS transistor is channel-doped with impurities. The threshold value can also be changed by changing the channel length of the selection MOS transistor. In other words, a transistor having a short channel length has a small threshold value due to the short channel effect, and may be an I-type transistor.
[0107]
Also, as a method of changing the gate oxide film thickness and the channel impurity concentration, other manufacturing processes such as channel doping of peripheral circuits may be used without introducing a new manufacturing process. In any method, it is sufficient to make a difference in the threshold value of the selection MOS transistor, and if the threshold value is made different, a predetermined threshold value can be obtained by a substrate bias or the like.
[0108]
In the conventional NAND cell type EEPROM, 0V is applied to the source side selection gate of the write block. However, when the source side selection MOS transistor is I-type and the threshold value Vt2 is about 0.1V (or negative) In the case of the threshold value), the source-side selection MOS transistor is not completely cut off, and the cell line flows, for example, 0.1 μA, and the bit line not written is discharged from the intermediate potential (about 10 V).
[0109]
For example, if writing is not performed to memory cells connected to 200 bit lines and the bit lines are charged to an intermediate potential, a total cell current of 200 × 0.1 μA = 20 μA flows. In order to improve the cut-off characteristics of the I-type transistor, a voltage of about 0.5 V, for example, may be applied to the common source line at the time of writing. If 0.5V is applied to the source, the potential difference between the source and the substrate becomes -0.5V, and the threshold value of the I-type transistor increases due to the substrate bias effect. Therefore, 0V is applied to the gate of the I-type transistor. The cut-off characteristic at the time is improved, and the cell current at the time of reading can be reduced.
[0110]
In order to set the smaller threshold value (I-type) of the selection gate thresholds to 0.5 V, for example, a method of reducing the substrate concentration is conceivable. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate spreads. As a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are formed. There is a problem of being connected and easy (punch through). In order to increase the punch-through breakdown voltage of the I-type selection MOS transistor, the channel length L of the I-type selection MOS transistor may be increased.
[0111]
Although the NAND cell type EEPROM has been described in the above embodiments, the nonvolatile semiconductor memory in which the drain side of the memory cell is connected to the bit line via the selection gate and the source side of the memory cell is also connected to the source line via the selection gate. The present invention is effective if it is an apparatus. For example, the present invention is also effective in an AND cell type EEPROM (H. Kume el al .; IEDM Tech. Digi., Dec. 1992, pp. 991-993) as shown in FIG. It is also effective in a NOR type EEPROM or mask ROM having one memory cell between the source gate and the source side selection gate.
[0112]
(Example 2)
Hereinafter, an embodiment for solving (Problem 2) will be described.
[0113]
FIG. 17 is a block diagram showing the configuration of the NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means. Since the open bit line system is used, the memory cell is divided into two parts, 1A and 1B. The memory cell arrays 1A and 1B are each divided into at least two predetermined units.
[0114]
In this embodiment, one page is 256 bits, and the memory cell arrays 1A and 1B are divided into 1A1, 1A2 and 1B1, 1B2 by 128 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch means for performing data writing and reading, and is divided into at least two for each predetermined unit as in the memory cell arrays 1A and 1B. In FIG. 17, the sense amplifier is divided into 2A and 2B. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0115]
The memory cell array 1A1 is shown in FIG. 18, 1B1 in FIG. 19, 1A2 in FIG. 20, and 1B2 in FIG. In FIG. 18 to FIG. 21, the threshold value of the selection MOS transistor of the memory cell array has two types of values as in the first embodiment. The threshold value of the selection MOS transistor indicated as E-type is 2 V, and the threshold value of the selection MOS transistor indicated as I-type is 0.5 V. Therefore, when both the E-type selection MOS transistor and the I-type selection MOS transistor are turned on, Vcc (for example, 3 V) is applied to the selection gate, and when only the I-type is turned on, 1. is applied to the selection gate. Apply 5V.
[0116]
When reading data from the memory cell array 1A1 to the bit lines BL0A to BL127A, the drain side select gate SGD is set to 3V, and the source side select gate SGS is set to 1.5V. On the other hand, when reading data from the memory cell array 1A2 to the bit lines BL128A to BL255A, the drain side selection gate SGD is set to 1.5V, and the source side selection gate SGS is set to 3V. When simultaneously reading data from the memory cell arrays 1A1 and 1A2, both SGS and SGD may be set to 3V.
[0117]
The sense amplifier is a differential sense amplifier in the same manner as the folded bit line system of the above (Embodiment 1). FIG. 22 shows the sense amplifier 2A (SA1) connected to the memory cell arrays 1A1 and 1B1, and FIG. 23 shows the sense amplifier 2B (SA2) connected to the memory cell arrays 1A2 and 1B2.
[0118]
Here, taking the case of reading data written in two pages as an example, the read operation of this embodiment will be described using the timing charts of FIGS. First, on the first page, the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) operate simultaneously. The control signals TG1, TG2 change from 3V to 0V, and the CMOS flip-flops FF1, FF2 and the bit lines BLjA, BLjB (j = 0, 1,..., 255) are disconnected.
[0119]
Next, the precharge signals φpA1, φpB1, φpA2, and φpB2 are changed from 0V to 3V, the bit line BLjA (j = 0, 1,..., 255) is changed to, for example, 1.7V, and the bit line BLjB (j = 0, 1). ,..., 255) are precharged to 1.5V, for example. When the precharge is finished, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 255) are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate.
[0120]
18 and 19, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V, and SGS0 is 3V. When the data written in the memory cell selected by the word line WL00 is “0”, the threshold of the memory cell is positive, so the cell current does not flow and the potential of the bit line BLjA remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BLjA decreases to 1.5 V or less. Further, the bit line BLjB is not discharged and is kept at the precharge potential of 1.5V.
[0121]
Thereafter, SAP1 and SAP2 are 3V, SAN1 and SAN2 are 0V, CMOS flip-flops FF1 and FF2 are inactivated, and φE1 and φE2 are 3V, thereby resetting CMOS flip-flops FF1 and FF2. After TG1 and TG2 become 3V and the bit lines and the sense amplifier are connected, SAN1 and SAN2 change from 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 255) is amplified. The Thereafter, SAP1 and SAN2 change from 0V to 3V, and data is latched. Then, the column selection signal CSLj (j = 0, 1,..., 255) is selected one after another, and the data latched in the CMOS flip-flop is output to I / O and I / O ′ (page read).
[0122]
After page reading of the first half of the first page (column addresses 0 to 127), the first half of the row address of the second page (bit line BLjA; j = 0, 1,..., 127. This may be performed by detecting that the column address is 128, for example.
[0123]
First, the precharge signals φpA1, φpB1, φpA2, φpB2 are changed from 0V to 3V, the bit line BLjA (j = 0, 1,..., 127) is changed to 1.7V, and the bit line BLjB (j = 0, 1,. 127) is precharged to 1.5V. When the precharge is finished, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00, WL02 to WL07 is 3V, SGD0 is 3V, and SGS0 is 1.5V.
[0124]
When the data written in the memory cell selected by the word line WL01 is “0”, the memory cell threshold value is positive, so that no cell current flows, and the bit line BLjA (j = 0, 1,..., 127). Remains at 1.7V. When the data is “1”, a cell current flows, and the potential of the bit line BLjA (j = 0, 1,..., 127) decreases to 1.5 V or less. Further, the bit line BLjB (j = 0, 1,..., 127) is not discharged and the precharge potential of 1.5 V is maintained.
[0125]
Thereafter, SAP1 becomes 3V, SAN1 becomes 0V, the CMOS flip-flop FF1 is inactivated, and φE1 becomes 3V, so that the CMOS flip-flop FF1 is equalized. After TG1 becomes 3V and the bit line and the sense amplifier are connected, SAN1 becomes 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 127) is amplified. Thereafter, SAP1 and SAN2 are changed from 0V to 3V, and the data is latched in the sense amplifier 2A (SA1).
[0126]
When page read of the first page has advanced by 256 column addresses, data for 128 column addresses of the next second page has already been latched in the sense amplifier 2A (SA1), so there is no need to perform a random read operation. . While the page read from the sense amplifier 2A (SA1) to the column addresses 0 to 127 of the second page is performed, a random read operation is performed on the column addresses 128 to 255 of the second half of the second page. That is, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00, WL02 to WL07 are 3V, SGD0 is 1.5V, and SGS0 is 3V.
[0127]
When the data written in the memory cell selected by the word line WL01 is “0”, the memory cell threshold value is positive, so that the cell current does not flow, and the potential of the bit line BLjA remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BLjA (j = 128, 129,..., 255) decreases to 1.5 V or less.
[0128]
Further, the bit line BLjB (j = 128, 129,..., 255) is not discharged and is kept at the precharge potential of 1.5V. Then, SAP2 becomes 3V, SAN2 becomes 0V, the CMOS flip-flop FF2 is inactivated, and φE2 becomes 3V, thereby resetting the CMOS flip-flop FF2. Then, after TG2 becomes 3V and the bit line and the sense amplifier are connected, SAN2 changes from 0V to 3V, and the potential difference between the bit lines BLjA, BLjB (j = 128, 129,..., 255) is amplified. Thereafter, SAP2 changes from 3V to 0V, and the data is latched in the sense amplifier 2B (SA2).
[0129]
When the page read of the second page has advanced by 128 column addresses, data for the 128 column addresses of the second half of the next second page has already been latched in the sense amplifier 2B (SA2), and therefore a random read operation is performed. There is no need to serially read data for the 128 column addresses in the second half of the second page.
[0130]
The present invention is not limited to the above embodiment. In the above embodiment, the memory cell is divided into two, but it may be divided into four, for example, or may be divided into an arbitrary number.
[0131]
The timing charts of FIGS. 24 and 25 are merely examples. In the timing charts of FIGS. 24 and 25, random reading of the data of the first page is simultaneously performed by the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2). As shown in the timing charts of FIGS. First, random reading of the memory cell corresponding to the first half column address of the first page is performed, and then the second half of the first page is randomly read while the first half of the first page is being page read. Good.
[0132]
24 and 25, bit lines are precharged simultaneously by random read of the first half of the second page and random read of the second half of the second page. However, as shown in FIGS. The bit line precharge timing may be changed between the case of random reading with 2A (SA1) and the case of random reading with the sense amplifier 2B (SA2).
[0133]
Further, the memory cell array may not be divided into physically continuous units as one division unit. For example, as shown in FIGS. 28 and 29, the bit lines connected to the sense amplifier SA1 and the bit lines connected to the sense amplifier SA2 may be alternately arranged. While the bit line connected to the sense amplifier SA1 is randomly read, the bit line connected to the sense amplifier SA2 can be grounded to 0V. In this case, the distance between the bit lines connected to the sense amplifier SA1 is as shown in FIGS. Therefore, noise caused by bit line capacitive coupling can be reduced during random reading.
[0134]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. In FIG. 31, the memory cell array connected to the bit line BLj (j = 0, 1,..., 255) is the same as the memory cell array connected to the bit line BLjA (j = 0, 1,..., 255) of FIG. Good.
[0135]
(Example 3)
Hereinafter, an embodiment for solving (Problem 3) will be described.
[0136]
In the conventional memory cell array, when a word line which is the row decoder 3 is selected at the time of reading and writing, all the memory cells arranged at the intersection of the selected word line and the bit line are selected. Therefore, one of the memory cells connected to the adjacent bit line cannot be selected and the other cannot be selected.
[0137]
As described in the above (Embodiment 1) and (Embodiment 2), according to the present invention, the threshold values of the selection MOS transistor on the source side and the selection MOS transistor on the drain side of the NAND block are changed, and further the source By changing the voltage applied to the select gate on the side and the select gate on the drain side, one of the adjacent bit lines can be selected and the other bit line can be deselected. As a result, by omitting the precharge to the bit line at the time of reading and writing, the precharge time can be shortened and the power consumption can be reduced.
[0138]
Therefore, in this embodiment (third embodiment), an embodiment will be described in which the precharge time is shortened during reading and the power consumption is reduced. An example of shortening the precharge time and reducing power consumption at the time of writing will be described in the next embodiment (embodiment 4).
[0139]
FIG. 32 is a block diagram showing the configuration of the NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as memory means, which is divided into 1A and 1B because it is an open bit line system. In this embodiment, one page is 256 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch means for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0140]
The memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) of FIG. 28 arranged in the memory cell arrays 1A and 1B is not FIG. 22 but FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) of FIG. 29 arranged in the memory cell arrays 1A, 1B is not FIG. 23 but FIG. In the sense amplifiers SA1 and SA2 in FIGS. 33 and 34, transistors are added to the sense amplifiers SA1 and SA2 in FIGS. 22 and 23 to equalize the bit lines BLjA and BLjB by the control signals φEQ1 and φEQ2 (to have the same potential). Has been.
[0141]
At the time of reading, every other bit line is kept at the reference potential (bit line shield) in order to reduce noise due to capacitive coupling between the bit lines. In this case, the write operation is first performed on, for example, a cell connected to the bit line BLjA (j = 0, 1,..., 127) and then connected to the bit line BLjA (j = 128, 129,..., 255). Writing to the cell to be performed. Here, data (first page data) written to the bit line BLjA (j = 0, 1,..., 127) is read first, and then to the bit line BLjA (j = 128, 129,..., 255). The present embodiment will be described by taking as an example the case of reading written data (second page data).
[0142]
When reading data from the bit line BLjA (j = 0, 1,..., 127), the bit line BLjA (j = 128, 129,..., 255) to be shielded is kept at a reference potential (for example, 1.5 V). In the conventional memory cell array, since adjacent bit lines are simultaneously selected and discharged, the shielded bit line can only have 0V. The timing chart of FIG. 35 is divided into the case where the data of the first page is read to the bit line, the case where the data read to the bit line is sensed by the sense amplifier, and the case where the data of the second page is read to the bit line. Will be described.
[0143]
<When reading the first page of data to the bit line>
When reading a memory cell selected by the word line WL00 and connected to the bit line BLjA (j = 0, 1,..., 127) in the memory cell array of FIG. 28, first, the bit line BLjA (j = 0, 1,. 127) is precharged to 1.7V, and the bit line BLjB (j = 128, 129,..., 255) is precharged to 1.5V and shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) Is precharged to a reference potential (eg, 1.5 V).
[0144]
After the bit line precharge, the control gate WL00 is set to 0V, WL01 to WL07 is set to 3V, the selection gate SGS0 is set to 1.5V, and SGD0 is set to 3V. In this case, the source side selection MOS transistors of the bit line BLjA (j = 0, 1,..., 127) are turned on, but the source side selection MOS transistors of the bit line BLjA (j = 128, 129,..., 255). Turn off. Therefore, the bit line BLjA (j = 0, 1,..., 127) is discharged if the data of the memory cell selected by the word line WL00 is “1”, but the bit line BLjA (j = 128, 129,. 255) does not discharge.
[0145]
When the bit line BLjA (j = 0, 1,..., 127) is discharged, the potential of the bit line BLjA (j = 128, 129,..., 255) drops from the reference potential due to capacitive coupling between the bit lines. While the line BLjA (j = 0, 1,..., 127) is discharged, for example, by setting VA2 and VB2 to the reference potential 1.5V and the control signals φPA2 and φPB2 to 3V, the bit lines BLjA and BLjB ( If j = 128, 129,..., 255) is continuously precharged to 1.5 V, the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) can be kept at the reference potential.
[0146]
After the cell data is read out to the bit line BLjA (j = 0, 1,..., 127), the control signals φPA2, φPB2 become 0 V, the bit lines BLjB (j = 0, 1,..., 127), and Bit lines BLjA and BLjB (j = 128, 129,..., 255) are floating.
[0147]
At the time of reading cell data to the bit line, the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) may be equalized by setting the control signal φEQ2 to 3 V, or the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) may be independently precharged to the reference potential 1.5V without being connected (without equalization).
[0148]
<When the first page data read to the bit line is amplified and sensed>
After the potential of the bit line BLjA (j = 0, 1,..., 127) is determined reflecting the data of the memory cell selected by the word line WL00, the potential of the bit line will be described in (Example 2). It senses differentially as it does. At this time, the bit lines BLjA, BLjB (j = 128, 129,..., 255) to be shielded are in a floating state, but are equalized by keeping the control signal φEQ2 at 3V to the same potential (1.5V). Yes. By differentially sensing, if the cell data read to the bit line BLjA (j = 0, 1,..., 127) is “0”, the bit line BLjA becomes 3V, and the bit line BLjB (j = 0, 1, ..., 127) becomes 0V.
[0149]
Therefore, as shown in FIG. 36 (a), the bit line BLjA (j = 128, 129,..., 255) shielded by sense is connected to the bit line BLjA (j = 0, 1,..., 127). The potential rises from the reference potential by δ by coupling. On the other hand, the potential of the shielded bit line BLjB (j = 128, 129,..., 255) drops from the reference potential by −δ due to capacitive coupling with the bit line BLjB (j = 0, 1,..., 127). . However, since the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are equalized, the bit line capacitive coupling noise δ applied to the bit line BLjA and the bit line capacitive coupled noise applied to the bit line BLjB. -Δ cancel each other, and as a result, the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are kept at the reference potential of 1.5V.
[0150]
Similarly, when the data read to the bit line BLjA (j = 0, 1,..., 127) is “1”, the bit line BLjA (j = 0, 1, 1, as shown in FIG. 36B). .., 127) and BLjB (j = 0, 1,..., 127) are connected (equalized) so that the shielded bit line can maintain the reference potential.
[0151]
<When reading the second page data>
As described above, after reading the data of the memory cells connected to the bit line BLjA (j = 0, 1,..., 127), the bit lines BLjA, BLjB (j = 128, 129,..., 255) Is already precharged to 1.5V. In addition, the bit line BLjA (j = 0, 1,..., 127) and the bit line BLjB (j = 0, 1,..., 127) read out first are one after 0 V and the other is 3 V after the sensing operation. Therefore, when data to be connected to the bit line BLjA (j = 128, 129,..., 255) is read next, if φEQ1 is set to 3V (φE1 may be set to 3V), precharge is performed. The bit lines BLjA, BLjB (j = 0, 1,..., 127) to be shielded can be set to the reference potential 1.5V without performing the above.
[0152]
Accordingly, the memory cell connected to the bit line BLjA (j = 128, 129,..., 255) is read after one page of data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) is read. In the case of reading out the data, the precharge for the second time only needs to change the read bit line BLjA (128, 129,..., 255) from 1.5V to 1.7V.
[0153]
When reading is performed using the bit line shield in this way, the bit line to be shielded can be set to a reference potential other than 0 V by applying the memory cell array and the sense amplifier of the present invention. As a result, when reading data over a plurality of pages, precharge can be shortened, reading speed can be increased, and power consumption can be reduced.
[0154]
In this embodiment, the bit lines BLjA and BLjB are equalized by the control signals φEQ1 and φEQ2, but may be equalized by the control signals φE1 and φE2. In FIG. 33 and FIG. 34, the node connecting the source and drain of the two transistors selected by the control signal φE1 (φE2) is fixed at Vcc / 2 potential (for example, 1.5 V). When reading the cell data to the bit line, the state shown in FIGS. 33 and 34 may be maintained. However, when the bit line is sensed, the shielded bit line is floated, so that the terminal connected to this node is in a floating state. There is a need.
[0155]
In this embodiment, after reading the data of the memory cells connected to the bit line BLjA (j = 0, 1,..., 127), the memory cells connected to the bit line BLjA (j = 128, 129,..., 255). However, the bit line to be read is arbitrary. Any bit line may be used as long as the bit line connected to the sense amplifier SA2 is read after reading the bit line connected to the sense amplifier SA1. Alternatively, the bit line connected to the sense amplifier SA1 may be read after reading the bit line connected to the sense amplifier SA2.
[0156]
The present invention is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. A memory cell array when this shared sense amplifier system is employed is shown in FIGS. FIG. 39 is a diagram showing a specific configuration of the sense amplifier SA3. Connected to the bit line BLjA (j = 0, 1,..., 127) and connected to the bit line BLjA (j = 128, 129,..., 255) after reading the data of the memory cell selected by the word line WL00. FIG. 40 is a timing chart when reading data from the memory cell selected by the word line WL00. The read operation is almost the same as that in the above embodiment having one sense amplifier per bit line.
[0157]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. The memory cell array connected to the bit line BLj in FIG. 31 may be the memory cell array connected to the bit line BLjA in FIG.
[0158]
In this embodiment, after sensing the cell data on the bit line, when sensing the potential of the read bit line, the two bit lines to be shielded are connected (equalized) to the reference potential. I kept it. When sensing the potential of the bit line, the two bit lines to be shielded may be connected to the terminal to which the reference potential is applied without being equalized. For example, when the bit line connected to the sense amplifier of FIG. 23 or FIG. 33 is shielded (maintained at a reference potential), φPA1 and φPB1 are 3 V, TG1 and TG2 are 0 V, and VA1 and VB1 are reference potentials (for example, 1.. 5V).
[0159]
(Example 4)
Subsequently to (Embodiment 3), an embodiment for solving (Problem 3) will be described below.
[0160]
The block diagram showing the configuration of the NAND cell type EEPROM according to the present embodiment is FIG. 32 as in the third embodiment. The memory cell array is the same as that in the third embodiment. That is, the memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) in the memory cell arrays 1A and 1B may be either FIG. 22 or FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) in the memory cell arrays 1A, 1B may be either FIG. 23 or FIG.
[0161]
When the bit line shield method is used in which every other bit line is maintained at the reference potential at the time of reading in order to reduce the capacitive coupling between the bit lines, as described in the third embodiment, the write operation is performed by, for example, the bit line BLjA (j = 0, 1,..., 127) and then writing to the cells connected to the bit line BLjA (j = 128, 129,..., 255). In the write operation, first write is performed, and then verify read is performed to check whether the write is sufficiently performed. Further, additional writing is not performed on cells that are sufficiently written, and additional writing is performed only on cells that are insufficiently written. Here, the present embodiment will be described by taking as an example a case where a memory cell selected by the word line WL00 is written to the bit line BLjA (j = 0, 1,..., 127) of the memory cell array 1A of FIG.
[0162]
FIG. 41 shows a write / write verify read operation excluding a data load operation of write data from the data input / output buffer 7 to the sense amplifier 2. Prior to writing, the memory cell array is erased all at once by setting all control gates to 0 V and the p substrate (or p-type well and n substrate) on which the memory cells are formed as the high voltage Vpp (about 20 V). After the write data is latched from the data input / output buffer 7 to the CMOS flip-flop FF via the input / output lines I / O and I / O ′, first, the control signals φPA1, φPA2, φPB1, and φPB2 become 3V. The bit line is reset.
[0163]
Thereafter, when the transfer gate control signals TGA1, VSW for connecting the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier become an intermediate potential (about 10V), the bit line BLjA (j = 0, 1, .., 127) according to data, the potential is an intermediate potential when it is "1" and 0V when it is "0". Since the bit line BLjA (j = 128, 129,..., 255) does not perform writing, it is charged to the intermediate potential from the terminal VA2. When the word line WL00 is selected by the row decoder 3, WL00 becomes Vpp, WL01 to WL07, SGD0 becomes an intermediate potential, and SGS0 becomes 0V.
[0164]
After the control gate and selection gate are reset to 0V after a certain time (˜20 μs), the transfer gate control signal TGA1 becomes 0V, and the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier are turned on. Disconnected. Thereafter, the control signal φPA1 becomes 3V, and the bit line BLjA (j = 0, 1,..., 127) is reset to 0V. VSW is also 3V. During this time, the bit line BLjA (j = 128, 129,..., 255) remains precharged to the intermediate potential.
[0165]
Next, a verify read operation is performed. First, φPA1 and φPB1 become 3V, the bit line BLjA (j = 0, 1,..., 127) is charged to 1.7V, and the bit line BLjB (j = 0, 1,..., 127) is charged to 1.5V. After that, φPA1 and φPB1 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) enter a floating state. Next, for example, 0.5V is applied to the control gate WL00, the word lines WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and SGD0 is set to 3V. In normal reading, “0” is read if the threshold value of the memory cell is 0 V or higher, but “0” is not read if it is not 0.5 V or higher in verify reading.
[0166]
After the bit line is discharged, the verify signal φAV becomes 3V, and when the bit line BLjA (j = 0, 1,..., 127) is written “1”, it is charged near 3V. Here, the voltage level of the precharge performed by the verify signal may be a precharge voltage of 1.5 V or higher for the bit line BLjB (j = 0, 1,..., 127). Thereafter, the equalize signal φE becomes 3V and the sense amplifier is reset. Then, the transfer gate control signals TGA1, TGB1 become 3V, and the data of the bit line BLjA (j = 0, 1,..., 127) is read. The read data is latched by the sense amplifier and becomes the next rewritten data.
[0167]
During the verify read, the bit line BLjA (j = 128, 129,..., 255) is not discharged and maintains an intermediate potential, so that when the bit line BLjA (j = 0, 1,. This reduces the coupling capacitance noise between bit lines.
[0168]
When rewriting the bit line BLjA (j = 0, 1,..., 127), the bit line BLjA (j = 128, 129,..., 255) is already precharged to the intermediate potential, so there is no need to recharge it. , Charging time can be omitted. In addition, since the booster circuit that charges the intermediate potential consumes a large amount of power when starting to boost, according to the present embodiment, the power consumption during writing can be reduced.
[0169]
In this embodiment, at the time of verify read, the unselected bit line BLjA (j = 128, 129,..., 255) is continuously charged to the intermediate potential, but the unselected bit line is set to the intermediate potential by, for example, setting φPA2 to 0V. May be in a floating state.
[0170]
This embodiment is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. 37 and 38 show memory cell arrays when the shared sense amplifier method is employed. The block diagram showing the configuration of the NAND cell type EEPROM when the shared sense amplifier system is adopted is also FIG. 32 as in the third embodiment. FIG. 39 shows the sense amplifier SA3 when the shared sense amplifier system is adopted. The timing chart when the shared sense amplifier system is adopted is almost the same as that in FIG.
[0171]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. The memory cell array connected to the bit line BLj in FIG. 31 may be the memory cell array connected to the bit line BLjA in FIG.
[0172]
The present invention can also be applied to a folded bit line system as shown in FIG. While writing to a memory cell connected to one of the two bit lines connected to the sense amplifier (for example, BL0 in FIG. 42), the other bit line BL1 sets the transfer gate control signal TG2 to 0 V and the terminal What is necessary is just to continue charging from VB to an intermediate potential (about 10V). Since the bit line BL1 is kept at the intermediate potential while the verify read of the memory cell connected to the written bit line BL0 is being performed, the verify read of the memory cell connected to the bit line BL0 cannot be performed differentially.
[0173]
However, for example, normal reading is differentially performed by the folded bit line method as described in the first embodiment, and at the time of verify reading, as described in the section of [Prior Art], One of the two inverters constituting the flip-flop of the sense amplifier is inactivated, and the read data is “0” depending on whether the potential of the bit line is larger than the circuit threshold value of the inverter as shown in FIG. It may be determined whether it is “1” or not.
[0174]
(Example 5)
In this embodiment, SGD0 is applied to the selection MOS transistor on the drain side of the half of the memory cell units in one block selected by the row decoder 3 at the time of verify-reading of writing and normal reading. When SGS0 is applied to the selection MOS transistor, SGS0 is applied to the drain-side selection MOS transistor and SGD0 is applied to the source-side selection MOS transistor in the remaining half of the memory cell units.
[0175]
As a method of applying a voltage to the selection gate, for example, as shown in FIG. 43, a signal applied to the selection gate of the memory cell connected to the bit lines BL0 to BL127 and a selection gate of the memory cell connected to the bit lines BL128 to BL255. A signal to be applied to may be provided separately. As shown in FIG. 44, the source side select gate and the drain side select gate may be interchanged in the middle of the memory cell array.
[0176]
43 and 44, for example, when a memory cell selected by the word line WL00 is read, if the selection gate SGS0 is 3V and SGD0 is 1.5V, it is connected to the bit line BLj (j; even number). A memory cell is read. In this case, among the unselected bit lines BLj (j; odd number) that are not read, the unselected bit lines BLj (j = 1, 3, 5,..., 125, 127) are turned off by the source side selection MOS transistors. For the unselected bit lines BLj (j = 129, 131, 133,..., 253, 255), the drain side selection MOS transistors are turned off. In other words, half of the unselected bit lines are stopped when the drain side selection MOS transistors are turned off, and the other half of the unselected bit lines are turned off by turning off the source side selection MOS transistors. Is stopped.
[0177]
On the other hand, when reading the memory cell connected to the bit line BLj (j; odd number) in FIGS. 43 and 44, the selection gate SGS0 may be set to 1.5V, and SGD0 may be set to 3V. In this case, among the unselected bit lines BLj (j; even number) that are not read, the drain-side selection MOS transistors of the unselected bit lines BLj (j = 0, 2, 4,..., 124, 126) are turned off. For the unselected bit lines BLj (j = 128, 130, 132,..., 252 and 254), the source-side selection MOS transistors are turned off. In other words, half of the unselected bit lines are stopped when the drain side selection MOS transistors are turned off, and the other half of the unselected bit lines are turned off by turning off the source side selection MOS transistors. Is stopped.
[0178]
In this way, during reading, whether the odd-numbered bit lines or even-numbered bit lines are read, half of the unselected bit lines are stopped when the drain-side selection MOS transistor is turned off. The remaining half of the unselected bit lines are turned off when the source-side selection MOS transistors are turned off. Therefore, the capacity of the entire unselected bit line is the same whether the odd-numbered bit line is read or the even-numbered bit line is read, and the bit line BLj (j) is read when the bit line BLj (j; odd number) is read. ; Even number) can be read, the precharge time and the read time can be made the same.
[0179]
Although the case of reading has been described here, the capacity of the entire bit line is equal in the case of reading the odd-numbered bit line and the case of reading the even-numbered bit line even in the case of the verify read after writing.
[0180]
43 and 44, the folded bit line method is taken as an example. However, the open bit line method described in the first embodiment to the fourth embodiment may be used, or a single end method may be used. A so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier may be used.
[0181]
(Example 6)
Next, another embodiment will be described. This embodiment is basically the same as the first embodiment, and is different from the first embodiment in that the type of the selection MOS transistor is changed.
[0182]
FIG. 45 is a diagram showing the configuration of the memory cell array in the present embodiment. 2 is different from FIG. 2 in that part of the I-type selection MOS transistor is D-type.
[0183]
In FIG. 45, a selection MOS transistor having a high threshold Vt1 (for example, 2V) is an E-type, and a selection MOS having a low threshold Vt2, Vt3 (for example, 0.5V, -1V) (Vt1>Vt2> Vt3). Transistors are indicated as I-type and D-type. The voltage applied to the selection gate is the voltage Vsgh (for example, 3V) (Vsgh> Vt1, Vt2, Vt3) at which all of the I-type transistor, D-type and E-type transistors are turned on, and the I-type transistor is turned on. E-type transistor turns off voltage Vsgl1 (eg, 1.5 V) (Vt1>Vsgl1> Vt2), and D-type transistor turns on, but E-type transistor turns off voltage Vsgl2 (eg, 0 V) (Vt1> Vsgl2) > Vt3).
[0184]
A method for applying the voltage of the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00, WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source side select gate SGS0 is set to Vsgh, and the drain side select gate SGD0 is set to Vsgl1. SGS1 and SGD1 are set to 0V. In this case, the source side select MOS transistors STS00 and STS10 are both turned on. On the other hand, although the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off, so that the bit line BL0 is discharged but the bit line / BL0 is not discharged. .
[0185]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl2, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, both the drain side selection MOS transistors STD00 and STD10 are turned on. Since the source-side selection MOS transistor STS10 is turned on, the bit line / BL0 is discharged, but the selection MOS transistor STS00 is turned off so that the bit line BL0 is not discharged.
[0186]
The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 in FIG. 45). What is necessary is just to give a difference to the threshold value of STS11), and the method of setting the threshold value is arbitrary. In FIG. 45, the selection MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type and the selection MOS transistors on the source side are E-type. For example, two NAND blocks sharing the bit line contact are connected on the drain side. One of the selection MOS transistors may be I-type and the other may be E-type.
[0187]
In the present invention, among the selection MOS transistors that share one selection gate, one that is conductive and one that is non-conductive can be generated, and two such selection gates are prepared. This utilizes the fact that a memory cell in a selected state and a memory cell in a non-selected state can be easily realized in memory cells having the same selection gate.
[0188]
As shown in FIG. 46, the selection MOS transistor connected to the drain side may be E-type or D-type, and the selection MOS transistor connected to the source side may be E-type or I-type. In this case, when a memory cell (for example, MC000) in the memory cell unit 2 is selected, SGS0 is set to Vsgh (for example, 3V), SGD0 is set to Vsgl2 (for example, 0V), and SGD1 and SGS1 are set to 0V. When selecting a memory cell (for example, MC100) in the memory cell unit 1, SGS0 may be set to Vsgl1 (for example, 1.5V), SGD0 to Vsgh (for example, 3V), and SGS1 and SGD1 to 0V.
[0189]
If Vsgh is made larger than Vcc, the conductance of the selection MOS transistor is increased (that is, the resistance is decreased), and the current flowing through the NAND cell string is increased during reading, so that the bit line discharge time is shortened. Reading and writing verify reading are speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0190]
The threshold values of the I-type selection MOS transistor and the D-type selection MOS transistor may be negative threshold values (for example, -1V and -2V).
[0191]
The larger value Vt1 of the threshold values of the selection gates may also be set to a voltage (for example, 3.5 V) equal to or higher than the power supply voltage Vcc. In this case, in order to turn on the selection MOS transistor having the threshold value Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate using a booster circuit inside the chip.
[0192]
Here, the operation for reading the memory cell MC000 connected to the bit line BL1 in FIG. 48 will be described with reference to the timing chart in FIG. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.
[0193]
First, the control signals φA and φB become Vss, and the CMOS flip-flop FF and the bit lines BL0 and BL1 are disconnected. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BL1 is precharged to VB (for example, 1.7 V) and the dummy bit line BL0 is precharged to VA (for example, 1.5 V) (time). t1). When the precharge is finished, φpA and φpB become Vss, and the bit lines BL0 and BL1 are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the control gate (time t2).
[0194]
When reading the memory cell MC000 in FIG. 48, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V, and SGS0 is 1.5V. When the data written in the memory cell MC000 is “0”, the threshold value of the memory cell MC000 is positive, so the cell current does not flow, and the potential of the bit line BL1 remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BL1 decreases to 1.5V or less. Since the select gate SGS0 is 1.5V, the select gate transistor STS10 is turned off, and the bit line BL0 is not discharged regardless of the data written in the memory cell MC100, and is kept at the precharge potential 1.5V. .
[0195]
Thereafter, SAP becomes 3V and SAN becomes 0V at time t3, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2. (For example, 1.5V). At time t5, .phi.A and .phi.B become 3V, and after the bit line and the sense amplifier are connected (time t6), SAN changes from 0V to 3V and the potential difference between the bit lines BL0 and BL1 is amplified. Thereafter, at time t7, the SAP is changed from 3V to 0V, and the data is latched. That is, if "0" is written in the memory cell MC000, the node N1 is 3V and the node N2 is 0V. If "1" is written in the MC000, the node N1 is 0V and the node N2 is 3V. Become. Thereafter, when the column selection signal CSL1 changes from 0V to 3V, the data latched in the CMOS flip-flop is output to I / O and I / O '(time t8).
[0196]
The timing of the read operation is arbitrary. For example, at time t5, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BL1 and BL2 to the nodes N1 and N2, and then the transfer gate may be turned off. Accordingly, since the load capacity of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.
[0197]
Also, during the sense operation of the sense amplifier, first, SAN is changed from 0 V to 3 V, the N-channel transistor of the CMOS flip-flop FF is turned on, and then SAP is changed from 3 V to 0 V, and the P-channel transistor of the CMOS flip-flop FF is turned on. However, the SAP may be changed from 3V to 0V at the same time as the SAN is changed from 0V to 3V.
[0198]
In the above embodiment, while the bit line to which the memory cell to be read is connected is discharged, the other dummy bit line (for example, the memory cell MC000 in FIG. 48) of the bit line pair connected to the sense amplifier is read. In the case of reading the bit line BL0 and the memory cell MC100, the bit line BL1) is in a floating state. However, while the bit line BL1 is precharged and the data in the memory cell MC000 is read thereafter, the precharge control signal φpA is kept at 3V to fix the reference dummy bit line BL0 to the reference potential of 1.5V. You can also.
[0199]
By maintaining the dummy bit line at the reference potential in this way, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. As in the case of the above read, the bit line is charged / discharged according to the data written in the cell at the time of verify read after writing, but if the dummy bit line not to be read is kept at the reference potential, it is caused by capacitive coupling between the bit lines. Noise can be reduced.
[0200]
<Write>
A write procedure in this embodiment, for example, when writing to the memory cell MC000 of FIG. 48 will be described below.
[0201]
The selection gate SGD0 and the control gates WL01 to WL07 are set to the intermediate potential Vm (about 10V), WL00 is set to Vpp (about 20V), and the bit line BL0 is charged from VA to Vm8 (about 8V). When "1" is written to the memory cell MC000, Vm8 is applied from the flip-flop FF, and when "0" is written, 0 V is applied to the bit line BL1. Then, electrons are not injected into the memory cell MC100 that is not written and the floating gate of the memory cell MC000 when "1" is written, and electrons are injected from the channel into the floating gate of the memory cell MC000 that is written "0". Is done.
[0202]
After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation is finished.
[0203]
When writing to MC000 of the memory cell array as shown in FIG. 45, a voltage (eg, −3 V) at which the D-type selection MOS transistor STS10 is turned off may be applied to the selection gate SGS0.
[0204]
After the writing is completed, a write verify operation is performed to check whether the writing has been sufficiently performed.
[0205]
First, .phi.A and .phi.B become Vcc, the precharge signals .phi.pB and .phi.pA become Vcc, and the bit line BL1 is precharged to 1.7 V, for example, (dummy) bit line BL0 to 1.5 V, for example.
[0206]
When the precharge is finished, φpA and φpB become Vss, and the bit lines BL1 and BL0 are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate. The control gate WL00 is a verify voltage (for example, 0.5V), WL01 to WL07 are Vcc (for example, 3V), SGS0 is 1.5V, and SGD0 is 3V. When "0" is sufficiently written in the memory cell MC000, the memory cell does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit line BL1 remains 1.7V. When "1" write or "0" write is insufficient, the cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. The dummy bit line BL0 may be left floating during this time, or may be fixed at 1.5V by setting φpA to Vcc. If the dummy bit line is kept at a constant voltage, the capacitive coupling noise between the bit lines during the bit line discharge can be significantly reduced.
[0207]
After the bit line is discharged, when the verify signal φBV becomes 3V and the data written in the memory cell MC000 is “1”, the bit line BL1 is charged close to 3V. Here, the voltage level of the charge performed by the verify signal may be a precharge voltage of 1.5 V or higher for the dummy bit line BL0.
[0208]
Thereafter, SAP becomes 3V, SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). become. Thereafter, φA and φB become 3V, and after the bit line and the sense amplifier are connected, SAN is changed from 0V to 3V, SAP is changed from 3V to 0V, and the potential difference between the bit line BL1 and the dummy bit line BL0 is amplified, The sense data is latched by the write data.
[0209]
As described above, according to this embodiment, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line can be increased without increasing the chip area as in the first embodiment. The system can be realized and high-speed random reading is possible. As a method for changing the threshold value, various methods described in the first embodiment can be employed.
[0210]
【The invention's effect】
Embodiments of the present invention will be described below with reference to the drawings.
[0211]
Example 1
Hereinafter, an embodiment for solving (Problem 1) will be described.
[0212]
FIG. 1 is a block diagram showing the overall configuration of a NAND cell type EEPROM according to the first embodiment of the present invention. In the figure, 1 is a memory cell array, 2 is a sense amplifier / latch circuit as latch means for writing and reading data, 3 is a row decoder for selecting word lines, 4 is a column decoder for selecting bit lines, and 5 is An address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0213]
FIG. 2 is a diagram showing a configuration of the memory cell array, where BL and / BL are bit lines, WL is a word line, STD is a first selection MOS transistor connected to the drain side of the NAND cell, and STS is a source side of the NAND cell. Second selection MOS transistor connected to, SGD is a selection gate for driving the selection MOS transistor STD, SGS is a selection gate for driving the selection MOS transistor STS, SA is a sense amplifier, TG is a sense amplifier SA and a bit line A control signal for driving a gate for connecting BL is shown.
[0214]
As shown in FIG. 2, the sense amplifier SA receives adjacent bit line pairs BLj and / BLj. This is a folded bit line system used in DRAM. In order to realize the folded bit line system, when one bit line of a bit line pair is discharged, the other bit line must not be discharged. A difference is applied to the threshold values of the selection MOS transistors (for example, STS00 and STS10, STD00 and STD10 in FIG. 2) sharing the same selection gate, and different voltages are applied to the drain side selection gate and the source side selection gate. It is realized by doing.
[0215]
In FIG. 2, a selection MOS transistor having a high threshold Vt1 (for example, 2V) is denoted as E-type, and a selection MOS transistor having a low threshold Vt2 (for example, 0.5V) (Vt1> Vt2) is denoted as I-type. ing. The voltages applied to the gates (selection gates) of the two types of selection MOS transistors are a voltage Vsgh (for example, 3 V) (Vsgh> Vt1, Vt2) that turns on both the I-type transistor and the E-type transistor, and an I-type transistor. Is a voltage Vsgl (for example, 1.5 V) (Vt1>Vsgl> Vt2) at which the E-type transistor is turned off.
[0216]
Here, the memory cell is an electrically rewritable nonvolatile memory cell in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate. A plurality of memory cells are connected in series to form a NAND cell (nonvolatile memory cell). Memory section). A first memory cell unit is configured by connecting an I-type STS and an E-type STD to the NAND cell, and an E-type STS and an I-type STD are connected to the NAND cell. The memory cell unit is configured, and the first and second memory cell units are alternately arranged. A sub-array is composed of a plurality of first and second memory cell units sharing a word line.
[0217]
A method for applying the voltage of the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00, WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source side select gate SGS0 is set to Vsgh, and the drain side select gate SGD0 is set to Vsgl. SGS1 and SGD1 are set to 0V. In this case, the source side select MOS transistors STS00 and STS10 are both turned on. On the other hand, the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, but the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off. Therefore, if the data in the memory cell MC000 is "1", the bit line BL0 is Although it is discharged, the bit line / BL0 is not discharged regardless of the data in the memory cell MC100.
[0218]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, both the drain side selection MOS transistors STD00 and STD10 are turned on. Since the source-side selection MOS transistor STS10 is turned on, the bit line / BL0 is discharged if the data in the memory cell MC100 is "1", but the selection MOS transistor STS00 is turned off so that the bit line BL0 is not discharged.
[0219]
The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 and STS01 in FIG. 2). What is necessary is just to give a difference to the threshold value of STS11), and the method of setting the threshold value is arbitrary. For example, as shown in FIG. 3, the selection MOS transistor STD00 of the bit line BLj may be E-type, STS00 may be I-type, the selection MOS transistor STD10 of the bit line / BLj may be I-type, and STS10 may be E-type.
[0220]
In FIG. 2, the selection MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type and the selection MOS transistors on the source side are E-type. For example, as shown in FIG. 4, the bit line contact is shared. In two NAND blocks, one of the drain side selection MOS transistors may be I-type and the other may be E-type. 2 to 4, the alternately arranged bit lines BLj are simultaneously selected and read. For example, as shown in FIG. 5, the threshold value of the selection MOS transistor is set to select the bit line BL0. When this is done, the bit line / BL1 may be selected.
[0221]
In the present invention, not only this (Embodiment 1) but also all the embodiments up to (Embodiment 5) described later, among the selection MOS transistors sharing one selection gate, those in the conductive state, A conductive state can be generated, and by preparing two such select gates, a memory cell in a selected state and a memory cell in a non-selected state can be easily selected in a memory cell having the same select gate. Utilizes what can be realized.
[0222]
Therefore, the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate are arbitrary. The drain side selection MOS transistor has two threshold values of Vtd1 and Vtd2 (Vtd1> Vtd2), and the voltage applied to the drain side selection gate is Vsghd (Vsghd> Vtd1), Vsgld (Vtd1>Vsgld> Vtd2). The source-side selection MOS transistor has two threshold values of Vts1, Vts2 (Vts1> Vts2), and voltages applied to the source-side selection gate are Vsghs (Vsghs> Vts1), Vsgls ( Vts1>Vsgls> Vts2), and Vtd1 = Vts1, Vtd2 = Vts2, Vsghd = Vsghs, and Vsgld = Vsgls are not necessary.
[0223]
For example, the drain side selection MOS transistor has two threshold values of 2V and 0.5V, and the source side selection MOS transistor has two threshold values of 2.5V and 1V. The applied voltage may be Vsgh = 3V, Vsgl = 1.5V, and the voltage applied to the source side selection gate may be Vsgh = 3V, Vsgl = 1.2V.
[0224]
If Vsgh is larger than Vcc, the conductance of the selection MOS transistor is increased (that is, the resistance is decreased), and the cell current flowing through the NAND cell column is increased during reading, resulting in a shorter bit line discharge time. , Read and write verify reading is speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0225]
The selection gate voltage Vsgh for making all the selection MOS transistors sharing one selection gate conductive is preferably equal to or lower than the power supply voltage Vcc. When Vsgh is larger than Vcc, a booster circuit is required in the chip, leading to an increase in chip area.
[0226]
Further, the smaller threshold value Vt2 of the selection MOS transistor may be a negative threshold value (for example, -1 V). At the time of writing, 0 V is applied to the bit line to which the cell to be written is connected, and an intermediate potential (about 10 V) is applied to the bit line to which the cell not to be written is connected. The source side select gate must be turned off so that no current flows. Therefore, when Vt2 is set to a negative threshold value of about -1V, a negative voltage (for example, -1.5V) is applied to the selection gate on the source side to turn off the selection gate having a negative threshold value at the time of writing. That's fine.
[0227]
The larger value Vt1 of the threshold values of the selection gate may be set to a voltage (for example, 3.5 V) that is equal to or higher than the power supply voltage Vcc. In this case, in order to turn on the selection MOS transistor having the threshold value Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate using a booster circuit inside the chip.
[0228]
Here, the operation for reading the memory cell MC000 connected to the bit line BLj of FIG. 6 will be described using the timing chart of FIG. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.
[0229]
First, the control signal TG changes from Vcc (for example, 3 V) to Vss, and the CMOS flip-flop FF and the bit lines BLj and / BLj are disconnected. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BLj is precharged to VA (eg, 1.7 V), and the bit line / BLj is precharged to VB (eg, 1.5 V) ( Time t1). When the precharge is finished, φpA and φpB become Vss, and the bit lines BLj and / BLj are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and selection gate (time t2).
[0230]
When reading the memory cell MC000 of FIG. 6, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V (Vsgh), and SGS0 is 1.5V (Vsgl). When the data written in the memory cell MC000 is “0”, the threshold value of the memory cell MC000 is positive, so the cell current does not flow, and the potential of the bit line BLj remains 1.7V. When the data is "1", a cell current flows and the potential of the bit line BLj is lowered to 1.5 V or less. Since the select gate SGS0 is 1.5V, the select transistor STS10 is turned off, and the bit line / BLj is not discharged regardless of the data written in the memory cell MC100, and is kept at the precharge potential 1.5V. .
[0231]
Thereafter, SAP becomes 3V and SAN becomes 0V at time t3, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5 V). At time t5, TG becomes 3V, and after the bit line and the sense amplifier are connected (time t6), SAN changes from 0V to 3V, and the potential difference between the bit lines BLj and / BLj is amplified. Thereafter, at time t7, the SAP is changed from 3V to 0V, and the data is latched.
[0232]
That is, if “0” is written in the memory cell MC000, the node N1 is 3V and the node N2 is 0V. If “1” is written in MC000, the node N1 becomes 0V and the node N2 becomes 3V. Thereafter, when the column selection signal CSLj changes from 0V to 3V, the data latched in the CMOS flip-flop is output to I / O and I / O '(time t8).
[0233]
Next, FIG. 10 shows a timing chart when reading the memory cell MC100 connected to the bit line / BLj in FIG. In this case, 1.5V is precharged to the bit line BLj and 1.7V is precharged to the bit line / BLj (time t1). The voltage applied to the control gate (word line) from the row decoder 3 when reading the cell data to the bit line is the same as that for reading the memory cell MC000, but the voltage applied to the selection gate is 1.5 V for SGD0 and SGS0. Is 3V (time t2).
[0234]
When the data written in the memory cell MC100 is "0", the threshold value of the memory cell MC100 is positive, so that no cell current flows and the potential of the bit line / BLj remains 1.7V. When the data is "1", a cell current flows and the potential of the bit line / BLj is lowered to 1.5 V or less. Since the selection gate SGD0 is 1.5V, the selection MOS transistor STD00 is turned off, and the bit line BLj is not discharged regardless of the data written in the memory cell MC000 and is kept at the precharge potential 1.5V. . After that, the data read out to the bit line / BLj is sensed and latched by the sense amplifier as in the case of reading out the memory cell MC000 and output to I / O and I / O ′.
[0235]
The timing of the read operation is arbitrary. For example, at time t5, as shown in FIG. 9, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BLj and / BLj to the nodes N1 and N2, and then the transfer gate may be turned off. . Accordingly, since the load capacity of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.
[0236]
8 to 10, in the sense operation of the sense amplifier, first, SAN is changed from 0V to 3V, the N-channel transistor of the CMOS flip-flop FF is turned on, and then SAP is changed from 3V to 0V. The P channel transistor is turned on, but the SAP may be changed from 3V to 0V almost simultaneously with the change of SAN from 0V to 3V.
[0237]
When the data of the cell connected to the bit line BLj is sensed and latched by the sense amplifier, one of the potentials of the bit lines BLj and / BLj is 0V and the other is Vcc (for example, 3V). After the cell data of the bit line BLj is output from the sense amplifier to I / O and I / O ', if φE is set to 3V, the bit lines BLj and / BLj are connected (equalized), and the bit line BLj is not precharged. , / BLj becomes 1.5V. Thereafter, for example, when reading the bit line / BLj, the bit line / BLj may be precharged to 1.7 V by setting φPB to 3 V and VB to 1.7 V. Thus, by connecting the bit lines BLj and / BLj after sensing the bit line BLj, the precharge time for the next read can be shortened, and the power consumption required for the precharge can be reduced.
[0238]
Further, as shown in FIG. 7, a circuit for performing verification after writing to the sense amplifier may be added.
[0239]
As a method of precharging different potentials to the bit line pair, dummy cells may be provided as shown in FIG. 11, for example, in addition to the method of transferring the potentials VA and VB from the peripheral circuit as shown in FIG. In this case, the bit lines BLj and / BLj are precharged to the same potential VPR. The current flowing in the dummy cell is set smaller than the worst read current of the cell. For example, a dummy NAND type cell connected in series is a depletion type transistor, the channel length L is increased, and the channel width W is decreased.
[0240]
If the threshold value of the dummy selection MOS transistor is set as shown in FIG. 11, when the data of the memory cell connected to the bit line BLj is read to the bit line BLj, the bit line / BLj is discharged through the dummy cell, and the bit line When reading data from the memory cell connected to / BLj, the bit line BLj is discharged through the dummy cell.
[0241]
The operation of this embodiment will be described by taking the case of reading the memory cell MC000 as an example. First, the precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to a precharge potential VPR (for example, 1.7V). Thereafter, the control gate line and selection gate of the memory cell are selected, 0V is applied to the dummy word line DWL, and substantially the same voltage as that applied to the selection gates SGS and SGD of the selection MOS transistor is applied to the dummy selection gates DSGS and DSGD. Is done.
[0242]
If “0” is written in the memory cell MC000, the bit line BLj is not discharged and maintains the precharge potential of 1.7V. If “1” is written in MC000, the bit line BLj is discharged to 1.3 V, for example. When the bit line BLj on which "1" is written is discharged to 1.3V, the bit line / BLj may be discharged to 1.5V through the dummy cell. Thereafter, the operation of differentially amplifying the potential of the bit line pair with the sense amplifier is the same as that of the embodiment of FIG.
[0243]
As a method of precharging different potentials to the bit line pair, the dummy cell may be composed of one transistor and one capacitor as shown in FIG. First, the bit line precharge control signal PRE becomes 3V, and the bit lines BLj and / BLj are precharged to the same potential VPR. When the data of the memory cell MC000 is read out to the bit line BLj after the control signal PRE becomes 0V and the bit line enters the floating state, φPB becomes 3V and the capacitor C1 is charged. The bit line / BLj drops from the precharge potential VPR by the amount of charge charged in the capacitor C1. This may be used as a reference potential when the bit line pair is differentially amplified.
[0244]
When data in the memory cell MC100 is read out to the bit line / BLj, the capacitor C0 is charged when .phi.PA becomes 3V, and the bit line BLj falls from the precharge potential VPR. The bit line BLj may be set as a reference potential.
[0245]
6 to 10, the other bit line (for example, the memory shown in FIG. 6) of the bit line pair connected to the sense amplifier is discharged while discharging the bit line to which the memory cell to be read is connected. The bit line / BLj is read when reading the cell MC000, and the bit line BLj is read when reading the memory cell MC100. However, while the bit line (for example, bit line BLj) is precharged to 1.7V and the data of the memory cell is read thereafter, the precharge control signal φPB is maintained at 3V, so that the reference bit line (for example, It is also possible to fix the bit line / BLj) to a reference potential of 1.5V.
[0246]
By maintaining the bit line / BLj at the reference potential in this way, it is possible to reduce noise due to capacitive coupling between adjacent bit lines during bit line discharge. Similarly to the case of the above-described reading, the bit line is charged / discharged according to the data written in the cell during the verify read after writing (described in detail in the fourth embodiment), but the bit line / BLj that is not read is used as the reference potential. If this is maintained, noise caused by capacitive coupling between bit lines can be reduced.
[0247]
In order to reduce noise due to capacitive coupling between adjacent bit lines when sensing and latching memory cell data read to the bit line, the twisted bit line method proposed in the DRAM as shown in FIG. It may be. A twisted bit line system as shown in FIG. 14 may be used.
[0248]
The selection MOS transistor may be composed of a cell having a selection gate and a floating gate as shown in FIG. In this embodiment, the threshold value of the selection MOS transistor can be determined by injecting electrons into the floating gate of the selection MOS transistor before shipping the semiconductor memory device. Electrons may be injected into the floating gate of the drain-side selection MOS transistor (for example, STD00 in FIG. 15) by tunneling from the substrate.
[0249]
That is, the word lines WL00 to WL07 are at an intermediate potential (about 10V) or 0V, the selection gate SGD0 is Vpp (about 20V), the selection gate SGD0 is 0V, the bit line BL0 is 0V, and the bit lines / BL0, BL1, and / BL1 are intermediate. What is necessary is just to set it as an electric potential (about 10V). Further, in order to determine the threshold value of the source-side selection MOS transistor, the selection gates SGD0 and SGS0 and the word lines WL00 to WL07 are all set to "H" to turn on all the NAND cell columns, and the bit line BL0 has Vpp or Hot electrons may be injected by applying 0 V to the intermediate potential and the bit lines / BL0, BL1, and / BL1.
[0250]
As described above, according to the present invention, by changing the threshold value of the selection MOS transistor and the voltage applied to the selection gate, a folded bit line system can be realized without increasing the chip area, and high-speed random reading can be performed. It becomes possible. As a method of changing the threshold value, it is conceivable to change the gate oxide film thickness of the selection MOS transistor, or to change the concentration of impurities doped in the channel of the selection MOS transistor. Alternatively, the threshold value may be made different depending on whether or not the selection MOS transistor is channel-doped with impurities. The threshold value can also be changed by changing the channel length of the selection MOS transistor. In other words, a transistor having a short channel length has a small threshold value due to the short channel effect, and may be an I-type transistor.
[0251]
Also, as a method of changing the gate oxide film thickness and the channel impurity concentration, other manufacturing processes such as channel doping of peripheral circuits may be used without introducing a new manufacturing process. In any method, it is sufficient to make a difference in the threshold value of the selection MOS transistor, and if the threshold value is made different, a predetermined threshold value can be obtained by a substrate bias or the like.
[0252]
In the conventional NAND cell type EEPROM, 0V is applied to the source side selection gate of the write block. However, when the source side selection MOS transistor is I-type and the threshold value Vt2 is about 0.1V (or negative) In the case of the threshold value), the source-side selection MOS transistor is not completely cut off, and the cell line flows, for example, 0.1 μA, and the bit line not written is discharged from the intermediate potential (about 10 V).
[0253]
For example, if writing is not performed to memory cells connected to 200 bit lines and the bit lines are charged to an intermediate potential, a total cell current of 200 × 0.1 μA = 20 μA flows. In order to improve the cut-off characteristics of the I-type transistor, a voltage of about 0.5 V, for example, may be applied to the common source line at the time of writing. If 0.5V is applied to the source, the potential difference between the source and the substrate becomes -0.5V, and the threshold value of the I-type transistor increases due to the substrate bias effect. Therefore, 0V is applied to the gate of the I-type transistor. The cut-off characteristic at the time is improved, and the cell current at the time of reading can be reduced.
[0254]
In order to set the smaller threshold value (I-type) of the selection gate thresholds to 0.5 V, for example, a method of reducing the substrate concentration is conceivable. In an I-type transistor having a low substrate concentration, when a drain voltage is applied without applying a gate voltage, a depletion layer between the drain and the substrate spreads. As a result, a depletion layer between the drain and the substrate and a depletion layer between the source and the substrate are formed. There is a problem of being connected and easy (punch through). In order to increase the punch-through breakdown voltage of the I-type selection MOS transistor, the channel length L of the I-type selection MOS transistor may be increased.
[0255]
Although the NAND cell type EEPROM has been described in the above embodiments, the nonvolatile semiconductor memory in which the drain side of the memory cell is connected to the bit line via the selection gate and the source side of the memory cell is also connected to the source line via the selection gate. The present invention is effective if it is an apparatus. For example, the present invention is also effective in an AND cell type EEPROM (H. Kume el al .; IEDM Tech. Digi., Dec. 1992, pp. 991-993) as shown in FIG. It is also effective in a NOR type EEPROM or mask ROM having one memory cell between the source gate and the source side selection gate.
[0256]
(Example 2)
Hereinafter, an embodiment for solving (Problem 2) will be described.
[0257]
FIG. 17 is a block diagram showing the configuration of the NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as a memory means. Since the open bit line system is used, the memory cell is divided into two parts, 1A and 1B. The memory cell arrays 1A and 1B are each divided into at least two predetermined units.
[0258]
In this embodiment, one page is 256 bits, and the memory cell arrays 1A and 1B are divided into 1A1, 1A2 and 1B1, 1B2 by 128 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch means for performing data writing and reading, and is divided into at least two for each predetermined unit as in the memory cell arrays 1A and 1B. In FIG. 17, the sense amplifier is divided into 2A and 2B. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0259]
The memory cell array 1A1 is shown in FIG. 18, 1B1 in FIG. 19, 1A2 in FIG. 20, and 1B2 in FIG. In FIG. 18 to FIG. 21, the threshold value of the selection MOS transistor of the memory cell array has two types of values as in the first embodiment. The threshold value of the selection MOS transistor indicated as E-type is 2 V, and the threshold value of the selection MOS transistor indicated as I-type is 0.5 V. Therefore, when both the E-type selection MOS transistor and the I-type selection MOS transistor are turned on, Vcc (for example, 3 V) is applied to the selection gate, and when only the I-type is turned on, 1. is applied to the selection gate. Apply 5V.
[0260]
When reading data from the memory cell array 1A1 to the bit lines BL0A to BL127A, the drain side select gate SGD is set to 3V, and the source side select gate SGS is set to 1.5V. On the other hand, when reading data from the memory cell array 1A2 to the bit lines BL128A to BL255A, the drain side selection gate SGD is set to 1.5V, and the source side selection gate SGS is set to 3V. When simultaneously reading data from the memory cell arrays 1A1 and 1A2, both SGS and SGD may be set to 3V.
[0261]
The sense amplifier is a differential sense amplifier in the same manner as the folded bit line system of the above (Embodiment 1). FIG. 22 shows the sense amplifier 2A (SA1) connected to the memory cell arrays 1A1 and 1B1, and FIG. 23 shows the sense amplifier 2B (SA2) connected to the memory cell arrays 1A2 and 1B2.
[0262]
Here, taking the case of reading data written in two pages as an example, the read operation of this embodiment will be described using the timing charts of FIGS. First, on the first page, the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2) operate simultaneously. The control signals TG1, TG2 change from 3V to 0V, and the CMOS flip-flops FF1, FF2 and the bit lines BLjA, BLjB (j = 0, 1,..., 255) are disconnected.
[0263]
Next, the precharge signals φpA1, φpB1, φpA2, and φpB2 are changed from 0V to 3V, the bit line BLjA (j = 0, 1,..., 255) is changed to, for example, 1.7V, and the bit line BLjB (j = 0, 1). ,..., 255) are precharged to 1.5V, for example. When the precharge is finished, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 255) are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate.
[0264]
18 and 19, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V, and SGS0 is 3V. When the data written in the memory cell selected by the word line WL00 is “0”, the threshold of the memory cell is positive, so the cell current does not flow and the potential of the bit line BLjA remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BLjA decreases to 1.5 V or less. Further, the bit line BLjB is not discharged and is kept at the precharge potential of 1.5V.
[0265]
Thereafter, SAP1 and SAP2 are 3V, SAN1 and SAN2 are 0V, CMOS flip-flops FF1 and FF2 are inactivated, and φE1 and φE2 are 3V, thereby resetting CMOS flip-flops FF1 and FF2. After TG1 and TG2 become 3V and the bit lines and the sense amplifier are connected, SAN1 and SAN2 change from 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 255) is amplified. The Thereafter, SAP1 and SAN2 change from 0V to 3V, and data is latched. Then, the column selection signal CSLj (j = 0, 1,..., 255) is selected one after another, and the data latched in the CMOS flip-flop is output to I / O and I / O ′ (page read).
[0266]
After page reading of the first half of the first page (column addresses 0 to 127), the first half of the row address of the second page (bit line BLjA; j = 0, 1,..., 127. This may be performed by detecting that the column address is 128, for example.
[0267]
First, the precharge signals φpA1, φpB1, φpA2, φpB2 are changed from 0V to 3V, the bit line BLjA (j = 0, 1,..., 127) is changed to 1.7V, and the bit line BLjB (j = 0, 1,. 127) is precharged to 1.5V. When the precharge is finished, φpA1, φpB1, φpA2, and φpB2 become 0 V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00, WL02 to WL07 is 3V, SGD0 is 3V, and SGS0 is 1.5V.
[0268]
When the data written in the memory cell selected by the word line WL01 is “0”, the memory cell threshold value is positive, so that no cell current flows, and the bit line BLjA (j = 0, 1,..., 127). Remains at 1.7V. When the data is “1”, a cell current flows, and the potential of the bit line BLjA (j = 0, 1,..., 127) decreases to 1.5 V or less. Further, the bit line BLjB (j = 0, 1,..., 127) is not discharged and the precharge potential of 1.5 V is maintained.
[0269]
Thereafter, SAP1 becomes 3V, SAN1 becomes 0V, the CMOS flip-flop FF1 is inactivated, and φE1 becomes 3V, so that the CMOS flip-flop FF1 is equalized. After TG1 becomes 3V and the bit line and the sense amplifier are connected, SAN1 becomes 3V to 0V, and the potential difference between the bit lines BLjA, BLjB (j = 0, 1,..., 127) is amplified. Thereafter, SAP1 and SAN2 are changed from 0V to 3V, and the data is latched in the sense amplifier 2A (SA1).
[0270]
When page read of the first page has advanced by 256 column addresses, data for 128 column addresses of the next second page has already been latched in the sense amplifier 2A (SA1), so there is no need to perform a random read operation. . While the page read from the sense amplifier 2A (SA1) to the column addresses 0 to 127 of the second page is performed, a random read operation is performed on the column addresses 128 to 255 of the second half of the second page. That is, a desired voltage is applied from the row decoder 3 to the control gate and the selection gate. WL01 is 0V, WL00, WL02 to WL07 are 3V, SGD0 is 1.5V, and SGS0 is 3V.
[0271]
When the data written in the memory cell selected by the word line WL01 is “0”, the memory cell threshold value is positive, so that the cell current does not flow, and the potential of the bit line BLjA remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BLjA (j = 128, 129,..., 255) decreases to 1.5 V or less.
[0272]
Further, the bit line BLjB (j = 128, 129,..., 255) is not discharged and is kept at the precharge potential of 1.5V. Then, SAP2 becomes 3V, SAN2 becomes 0V, the CMOS flip-flop FF2 is inactivated, and φE2 becomes 3V, thereby resetting the CMOS flip-flop FF2. Then, after TG2 becomes 3V and the bit line and the sense amplifier are connected, SAN2 changes from 0V to 3V, and the potential difference between the bit lines BLjA, BLjB (j = 128, 129,..., 255) is amplified. Thereafter, SAP2 changes from 3V to 0V, and the data is latched in the sense amplifier 2B (SA2).
[0273]
When the page read of the second page has advanced by 128 column addresses, data for the 128 column addresses of the second half of the next second page has already been latched in the sense amplifier 2B (SA2), and therefore a random read operation is performed. There is no need to serially read data for the 128 column addresses in the second half of the second page.
[0274]
The present invention is not limited to the above embodiment. In the above embodiment, the memory cell is divided into two, but it may be divided into four, for example, or may be divided into an arbitrary number.
[0275]
The timing charts of FIGS. 24 and 25 are merely examples. In the timing charts of FIGS. 24 and 25, random reading of the data of the first page is simultaneously performed by the sense amplifier 2A (SA1) and the sense amplifier 2B (SA2). As shown in the timing charts of FIGS. First, random reading of the memory cell corresponding to the first half column address of the first page is performed, and then the second half of the first page is randomly read while the first half of the first page is being page read. Good.
[0276]
24 and 25, bit lines are precharged simultaneously by random read of the first half of the second page and random read of the second half of the second page. However, as shown in FIGS. The bit line precharge timing may be changed between the case of random reading with 2A (SA1) and the case of random reading with the sense amplifier 2B (SA2).
[0277]
Further, the memory cell array may not be divided into physically continuous units as one division unit. For example, as shown in FIGS. 28 and 29, the bit lines connected to the sense amplifier SA1 and the bit lines connected to the sense amplifier SA2 may be alternately arranged. While the bit line connected to the sense amplifier SA1 is randomly read, the bit line connected to the sense amplifier SA2 can be grounded to 0V. In this case, the distance between the bit lines connected to the sense amplifier SA1 is as shown in FIGS. Therefore, noise caused by bit line capacitive coupling can be reduced during random reading.
[0278]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. In FIG. 31, the memory cell array connected to the bit line BLj (j = 0, 1,..., 255) is the same as the memory cell array connected to the bit line BLjA (j = 0, 1,..., 255) of FIG. Good.
[0279]
(Example 3)
Hereinafter, an embodiment for solving (Problem 3) will be described.
[0280]
In the conventional memory cell array, when a word line which is the row decoder 3 is selected at the time of reading and writing, all the memory cells arranged at the intersection of the selected word line and the bit line are selected. Therefore, one of the memory cells connected to the adjacent bit line cannot be selected and the other cannot be selected.
[0281]
As described in the above (Embodiment 1) and (Embodiment 2), according to the present invention, the threshold values of the selection MOS transistor on the source side and the selection MOS transistor on the drain side of the NAND block are changed, and further the source By changing the voltage applied to the select gate on the side and the select gate on the drain side, one of the adjacent bit lines can be selected and the other bit line can be deselected. As a result, by omitting the precharge to the bit line at the time of reading and writing, the precharge time can be shortened and the power consumption can be reduced.
[0282]
Therefore, in this embodiment (third embodiment), an embodiment will be described in which the precharge time is shortened during reading and the power consumption is reduced. An example of shortening the precharge time and reducing power consumption at the time of writing will be described in the next embodiment (embodiment 4).
[0283]
FIG. 32 is a block diagram showing the configuration of the NAND cell type EEPROM according to this embodiment. In the figure, reference numeral 1 denotes a memory cell array as memory means, which is divided into 1A and 1B because it is an open bit line system. In this embodiment, one page is 256 bits. Reference numeral 2 denotes a sense amplifier circuit as a latch means for writing and reading data. 3 is a row decoder for selecting a word line, 4 is a column decoder for selecting a bit line, 5 is an address buffer, 6 is an I / O sense amplifier, 7 is a data input / output buffer, and 8 is a substrate potential control circuit.
[0284]
The memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) of FIG. 28 arranged in the memory cell arrays 1A and 1B is not FIG. 22 but FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) of FIG. 29 arranged in the memory cell arrays 1A, 1B is not FIG. 23 but FIG. In the sense amplifiers SA1 and SA2 in FIGS. 33 and 34, transistors are added to the sense amplifiers SA1 and SA2 in FIGS. 22 and 23 to equalize the bit lines BLjA and BLjB by the control signals φEQ1 and φEQ2 (to have the same potential). Has been.
[0285]
At the time of reading, every other bit line is kept at the reference potential (bit line shield) in order to reduce noise due to capacitive coupling between the bit lines. In this case, the write operation is first performed on, for example, a cell connected to the bit line BLjA (j = 0, 1,..., 127) and then connected to the bit line BLjA (j = 128, 129,..., 255). Writing to the cell to be performed. Here, data (first page data) written to the bit line BLjA (j = 0, 1,..., 127) is read first, and then to the bit line BLjA (j = 128, 129,..., 255). The present embodiment will be described by taking as an example the case of reading written data (second page data).
[0286]
When reading data from the bit line BLjA (j = 0, 1,..., 127), the bit line BLjA (j = 128, 129,..., 255) to be shielded is kept at a reference potential (for example, 1.5 V). In the conventional memory cell array, since adjacent bit lines are simultaneously selected and discharged, the shielded bit line can only have 0V. The timing chart of FIG. 35 is divided into the case where the data of the first page is read to the bit line, the case where the data read to the bit line is sensed by the sense amplifier, and the case where the data of the second page is read to the bit line. Will be described.
[0287]
<When reading the first page of data to the bit line>
When reading a memory cell selected by the word line WL00 and connected to the bit line BLjA (j = 0, 1,..., 127) in the memory cell array of FIG. 28, first, the bit line BLjA (j = 0, 1,. 127) is precharged to 1.7V, and the bit line BLjB (j = 128, 129,..., 255) is precharged to 1.5V and shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) Is precharged to a reference potential (eg, 1.5 V).
[0288]
After the bit line precharge, the control gate WL00 is set to 0V, WL01 to WL07 is set to 3V, the selection gate SGS0 is set to 1.5V, and SGD0 is set to 3V. In this case, the source side selection MOS transistors of the bit line BLjA (j = 0, 1,..., 127) are turned on, but the source side selection MOS transistors of the bit line BLjA (j = 128, 129,..., 255). Turn off. Therefore, the bit line BLjA (j = 0, 1,..., 127) is discharged if the data of the memory cell selected by the word line WL00 is “1”, but the bit line BLjA (j = 128, 129,. 255) does not discharge.
[0289]
When the bit line BLjA (j = 0, 1,..., 127) is discharged, the potential of the bit line BLjA (j = 128, 129,..., 255) drops from the reference potential due to capacitive coupling between the bit lines. While the line BLjA (j = 0, 1,..., 127) is discharged, for example, by setting VA2 and VB2 to the reference potential 1.5V and the control signals φPA2 and φPB2 to 3V, the bit lines BLjA and BLjB ( If j = 128, 129,..., 255) is continuously precharged to 1.5 V, the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) can be kept at the reference potential.
[0290]
After the cell data is read out to the bit line BLjA (j = 0, 1,..., 127), the control signals φPA2, φPB2 become 0 V, the bit lines BLjB (j = 0, 1,..., 127), and Bit lines BLjA and BLjB (j = 128, 129,..., 255) are floating.
[0291]
At the time of reading cell data to the bit line, the shielded bit lines BLjA, BLjB (j = 128, 129,..., 255) may be equalized by setting the control signal φEQ2 to 3 V, or the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) may be independently precharged to the reference potential 1.5V without being connected (without equalization).
[0292]
<When the first page data read to the bit line is amplified and sensed>
After the potential of the bit line BLjA (j = 0, 1,..., 127) is determined reflecting the data of the memory cell selected by the word line WL00, the potential of the bit line will be described in (Example 2). It senses differentially as it does. At this time, the bit lines BLjA, BLjB (j = 128, 129,..., 255) to be shielded are in a floating state, but are equalized by keeping the control signal φEQ2 at 3V to the same potential (1.5V). Yes. By differentially sensing, if the cell data read to the bit line BLjA (j = 0, 1,..., 127) is “0”, the bit line BLjA becomes 3V, and the bit line BLjB (j = 0, 1, ..., 127) becomes 0V.
[0293]
Therefore, as shown in FIG. 36 (a), the bit line BLjA (j = 128, 129,..., 255) shielded by sense is connected to the bit line BLjA (j = 0, 1,..., 127). The potential rises from the reference potential by δ by coupling. On the other hand, the potential of the shielded bit line BLjB (j = 128, 129,..., 255) drops from the reference potential by −δ due to capacitive coupling with the bit line BLjB (j = 0, 1,..., 127). . However, since the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are equalized, the bit line capacitive coupling noise δ applied to the bit line BLjA and the bit line capacitive coupled noise applied to the bit line BLjB. -Δ cancel each other, and as a result, the shielded bit lines BLjA and BLjB (j = 128, 129,..., 255) are kept at the reference potential of 1.5V.
[0294]
Similarly, when the data read to the bit line BLjA (j = 0, 1,..., 127) is “1”, the bit line BLjA (j = 0, 1, 1, as shown in FIG. 36B). .., 127) and BLjB (j = 0, 1,..., 127) are connected (equalized) so that the shielded bit line can maintain the reference potential.
[0295]
<When reading the second page data>
As described above, after reading the data of the memory cells connected to the bit line BLjA (j = 0, 1,..., 127), the bit lines BLjA, BLjB (j = 128, 129,..., 255) Is already precharged to 1.5V. In addition, the bit line BLjA (j = 0, 1,..., 127) and the bit line BLjB (j = 0, 1,..., 127) read out first are one after 0 V and the other is 3 V after the sensing operation. Therefore, when data to be connected to the bit line BLjA (j = 128, 129,..., 255) is read next, if φEQ1 is set to 3V (φE1 may be set to 3V), precharge is performed. The bit lines BLjA, BLjB (j = 0, 1,..., 127) to be shielded can be set to the reference potential 1.5V without performing the above.
[0296]
Accordingly, the memory cell connected to the bit line BLjA (j = 128, 129,..., 255) is read after one page of data of the memory cell connected to the bit line BLjA (j = 0, 1,..., 127) is read. In the case of reading out the data, the precharge for the second time only needs to change the read bit line BLjA (128, 129,..., 255) from 1.5V to 1.7V.
[0297]
When reading is performed using the bit line shield in this way, the bit line to be shielded can be set to a reference potential other than 0 V by applying the memory cell array and the sense amplifier of the present invention. As a result, when reading data over a plurality of pages, precharge can be shortened, reading speed can be increased, and power consumption can be reduced.
[0298]
In this embodiment, the bit lines BLjA and BLjB are equalized by the control signals φEQ1 and φEQ2, but may be equalized by the control signals φE1 and φE2. In FIG. 33 and FIG. 34, the node connecting the source and drain of the two transistors selected by the control signal φE1 (φE2) is fixed at Vcc / 2 potential (for example, 1.5 V). When reading the cell data to the bit line, the state shown in FIGS. 33 and 34 may be maintained. However, when the bit line is sensed, the shielded bit line is floated, so that the terminal connected to this node is in a floating state. There is a need.
[0299]
In this embodiment, after reading the data of the memory cells connected to the bit line BLjA (j = 0, 1,..., 127), the memory cells connected to the bit line BLjA (j = 128, 129,..., 255). However, the bit line to be read is arbitrary. Any bit line may be used as long as the bit line connected to the sense amplifier SA2 is read after reading the bit line connected to the sense amplifier SA1. Alternatively, the bit line connected to the sense amplifier SA1 may be read after reading the bit line connected to the sense amplifier SA2.
[0300]
The present invention is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. A memory cell array when this shared sense amplifier system is employed is shown in FIGS. FIG. 39 is a diagram showing a specific configuration of the sense amplifier SA3. Connected to the bit line BLjA (j = 0, 1,..., 127) and connected to the bit line BLjA (j = 128, 129,..., 255) after reading the data of the memory cell selected by the word line WL00. FIG. 40 is a timing chart when reading data from the memory cell selected by the word line WL00. The read operation is almost the same as that in the above embodiment having one sense amplifier per bit line.
[0301]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. The memory cell array connected to the bit line BLj in FIG. 31 may be the memory cell array connected to the bit line BLjA in FIG.
[0302]
In this embodiment, after sensing the cell data on the bit line, when sensing the potential of the read bit line, the two bit lines to be shielded are connected (equalized) to the reference potential. I kept it. When sensing the potential of the bit line, the two bit lines to be shielded may be connected to the terminal to which the reference potential is applied without being equalized. For example, when the bit line connected to the sense amplifier of FIG. 23 or FIG. 33 is shielded (maintained at a reference potential), φPA1 and φPB1 are 3 V, TG1 and TG2 are 0 V, and VA1 and VB1 are reference potentials (for example, 1.. 5V).
[0303]
(Example 4)
Subsequently to (Embodiment 3), an embodiment for solving (Problem 3) will be described below.
[0304]
The block diagram showing the configuration of the NAND cell type EEPROM according to the present embodiment is FIG. 32 as in the third embodiment. The memory cell array is the same as that in the third embodiment. That is, the memory cell array 1A is the same as FIG. 28, and the memory cell array 1B is the same as FIG. However, the sense amplifier SA1 connected to the bit lines BLjA, BLjB (j = 0, 1,..., 127) in the memory cell arrays 1A and 1B may be either FIG. 22 or FIG. Similarly, the sense amplifier SA2 connected to the bit lines BLjA, BLjB (j = 128, 129,..., 255) in the memory cell arrays 1A, 1B may be either FIG. 23 or FIG.
[0305]
When the bit line shield method is used in which every other bit line is maintained at the reference potential at the time of reading in order to reduce the capacitive coupling between the bit lines, as described in the third embodiment, the write operation is performed by, for example, the bit line BLjA (j = 0, 1,..., 127) and then writing to the cells connected to the bit line BLjA (j = 128, 129,..., 255). In the write operation, first write is performed, and then verify read is performed to check whether the write is sufficiently performed. Further, additional writing is not performed on cells that are sufficiently written, and additional writing is performed only on cells that are insufficiently written. Here, the present embodiment will be described by taking as an example a case where a memory cell selected by the word line WL00 is written to the bit line BLjA (j = 0, 1,..., 127) of the memory cell array 1A of FIG.
[0306]
FIG. 41 shows a write / write verify read operation excluding a data load operation of write data from the data input / output buffer 7 to the sense amplifier 2. Prior to writing, the memory cell array is erased all at once by setting all control gates to 0 V and the p substrate (or p-type well and n substrate) on which the memory cells are formed as the high voltage Vpp (about 20 V). After the write data is latched from the data input / output buffer 7 to the CMOS flip-flop FF via the input / output lines I / O and I / O ′, first, the control signals φPA1, φPA2, φPB1, and φPB2 become 3V. The bit line is reset.
[0307]
Thereafter, when the transfer gate control signals TGA1, VSW for connecting the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier become an intermediate potential (about 10V), the bit line BLjA (j = 0, 1, .., 127) according to data, the potential is an intermediate potential when it is "1" and 0V when it is "0". Since the bit line BLjA (j = 128, 129,..., 255) does not perform writing, it is charged to the intermediate potential from the terminal VA2. When the word line WL00 is selected by the row decoder 3, WL00 becomes Vpp, WL01 to WL07, SGD0 becomes an intermediate potential, and SGS0 becomes 0V.
[0308]
After the control gate and selection gate are reset to 0V after a certain time (˜20 μs), the transfer gate control signal TGA1 becomes 0V, and the bit line BLjA (j = 0, 1,..., 127) and the sense amplifier are turned on. Disconnected. Thereafter, the control signal φPA1 becomes 3V, and the bit line BLjA (j = 0, 1,..., 127) is reset to 0V. VSW is also 3V. During this time, the bit line BLjA (j = 128, 129,..., 255) remains precharged to the intermediate potential.
[0309]
Next, a verify read operation is performed. First, φPA1 and φPB1 become 3V, the bit line BLjA (j = 0, 1,..., 127) is charged to 1.7V, and the bit line BLjB (j = 0, 1,..., 127) is charged to 1.5V. After that, φPA1 and φPB1 become 0V, and the bit lines BLjA, BLjB (j = 0, 1,..., 127) enter a floating state. Next, for example, 0.5V is applied to the control gate WL00, the word lines WL01 to WL07 are set to 3V, the selection gate SGS0 is set to 1.5V, and SGD0 is set to 3V. In normal reading, “0” is read if the threshold value of the memory cell is 0 V or higher, but “0” is not read if it is not 0.5 V or higher in verify reading.
[0310]
After the bit line is discharged, the verify signal φAV becomes 3V, and when the bit line BLjA (j = 0, 1,..., 127) is written “1”, it is charged near 3V. Here, the voltage level of the precharge performed by the verify signal may be a precharge voltage of 1.5 V or higher for the bit line BLjB (j = 0, 1,..., 127). Thereafter, the equalize signal φE becomes 3V and the sense amplifier is reset. Then, the transfer gate control signals TGA1, TGB1 become 3V, and the data of the bit line BLjA (j = 0, 1,..., 127) is read. The read data is latched by the sense amplifier and becomes the next rewritten data.
[0311]
During the verify read, the bit line BLjA (j = 128, 129,..., 255) is not discharged and maintains an intermediate potential, so that when the bit line BLjA (j = 0, 1,. This reduces the coupling capacitance noise between bit lines.
[0312]
When rewriting the bit line BLjA (j = 0, 1,..., 127), the bit line BLjA (j = 128, 129,..., 255) is already precharged to the intermediate potential, so there is no need to recharge it. , Charging time can be omitted. In addition, since the booster circuit that charges the intermediate potential consumes a large amount of power when starting to boost, according to the present embodiment, the power consumption during writing can be reduced.
[0313]
In this embodiment, at the time of verify read, the unselected bit line BLjA (j = 128, 129,..., 255) is continuously charged to the intermediate potential, but the unselected bit line is set to the intermediate potential by, for example, setting φPA2 to 0V. May be in a floating state.
[0314]
This embodiment is also effective in a so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier. 37 and 38 show memory cell arrays when the shared sense amplifier method is employed. The block diagram showing the configuration of the NAND cell type EEPROM when the shared sense amplifier system is adopted is also FIG. 32 as in the third embodiment. FIG. 39 shows the sense amplifier SA3 when the shared sense amplifier system is adopted. The timing chart when the shared sense amplifier system is adopted is almost the same as that in FIG.
[0315]
The present invention is not limited to a memory cell array having an open bit line arrangement. For example, a single-ended memory cell arrangement as shown in FIG. 31 having an inverter type sense amplifier as shown in FIG. 30 may be used. The memory cell array connected to the bit line BLj in FIG. 31 may be the memory cell array connected to the bit line BLjA in FIG.
[0316]
The present invention can also be applied to a folded bit line system as shown in FIG. While writing to a memory cell connected to one of the two bit lines connected to the sense amplifier (for example, BL0 in FIG. 42), the other bit line BL1 sets the transfer gate control signal TG2 to 0 V and the terminal What is necessary is just to continue charging from VB to an intermediate potential (about 10V). Since the bit line BL1 is kept at the intermediate potential while the verify read of the memory cell connected to the written bit line BL0 is being performed, the verify read of the memory cell connected to the bit line BL0 cannot be performed differentially.
[0317]
However, for example, normal reading is differentially performed by the folded bit line method as described in the first embodiment, and at the time of verify reading, as described in the section of [Prior Art], One of the two inverters constituting the flip-flop of the sense amplifier is inactivated, and the read data is “0” depending on whether the potential of the bit line is larger than the circuit threshold value of the inverter as shown in FIG. It may be determined whether it is “1” or not.
[0318]
(Example 5)
In this embodiment, SGD0 is applied to the selection MOS transistor on the drain side of the half of the memory cell units in one block selected by the row decoder 3 at the time of verify-reading of writing and normal reading. When SGS0 is applied to the selection MOS transistor, SGS0 is applied to the drain-side selection MOS transistor and SGD0 is applied to the source-side selection MOS transistor in the remaining half of the memory cell units.
[0319]
As a method of applying a voltage to the selection gate, for example, as shown in FIG. 43, a signal applied to the selection gate of the memory cell connected to the bit lines BL0 to BL127 and a selection gate of the memory cell connected to the bit lines BL128 to BL255. A signal to be applied to may be provided separately. As shown in FIG. 44, the source side select gate and the drain side select gate may be interchanged in the middle of the memory cell array.
[0320]
43 and 44, for example, when a memory cell selected by the word line WL00 is read, if the selection gate SGS0 is 3V and SGD0 is 1.5V, it is connected to the bit line BLj (j; even number). A memory cell is read. In this case, among the unselected bit lines BLj (j; odd number) that are not read, the unselected bit lines BLj (j = 1, 3, 5,..., 125, 127) are turned off by the source side selection MOS transistors. For the unselected bit lines BLj (j = 129, 131, 133,..., 253, 255), the drain side selection MOS transistors are turned off. In other words, half of the unselected bit lines are stopped when the drain side selection MOS transistors are turned off, and the other half of the unselected bit lines are turned off by turning off the source side selection MOS transistors. Is stopped.
[0321]
On the other hand, when reading the memory cell connected to the bit line BLj (j; odd number) in FIGS. 43 and 44, the selection gate SGS0 may be set to 1.5V, and SGD0 may be set to 3V. In this case, among the unselected bit lines BLj (j; even number) that are not read, the drain-side selection MOS transistors of the unselected bit lines BLj (j = 0, 2, 4,..., 124, 126) are turned off. For the unselected bit lines BLj (j = 128, 130, 132,..., 252 and 254), the source-side selection MOS transistors are turned off. In other words, half of the unselected bit lines are stopped when the drain side selection MOS transistors are turned off, and the other half of the unselected bit lines are turned off by turning off the source side selection MOS transistors. Is stopped.
[0322]
In this way, during reading, whether the odd-numbered bit lines or even-numbered bit lines are read, half of the unselected bit lines are stopped when the drain-side selection MOS transistor is turned off. The remaining half of the unselected bit lines are turned off when the source-side selection MOS transistors are turned off. Therefore, the capacity of the entire unselected bit line is the same whether the odd-numbered bit line is read or the even-numbered bit line is read, and the bit line BLj (j) is read when the bit line BLj (j; odd number) is read. ; Even number) can be read, the precharge time and the read time can be made the same.
[0323]
Although the case of reading has been described here, the capacity of the entire bit line is equal in the case of reading the odd-numbered bit line and the case of reading the even-numbered bit line even in the case of the verify read after writing.
[0324]
43 and 44, the folded bit line method is taken as an example. However, the open bit line method described in the first embodiment to the fourth embodiment may be used, or a single end method may be used. A so-called shared sense amplifier system in which a plurality of bit lines are shared by one sense amplifier may be used.
[0325]
(Example 6)
Next, another embodiment will be described. This embodiment is basically the same as the first embodiment, and is different from the first embodiment in that the type of the selection MOS transistor is changed.
[0326]
FIG. 45 is a diagram showing the configuration of the memory cell array in the present embodiment. 2 is different from FIG. 2 in that part of the I-type selection MOS transistor is D-type.
[0327]
In FIG. 45, a selection MOS transistor having a high threshold Vt1 (for example, 2V) is an E-type, and a selection MOS having a low threshold Vt2, Vt3 (for example, 0.5V, -1V) (Vt1>Vt2> Vt3). Transistors are indicated as I-type and D-type. The voltage applied to the selection gate is the voltage Vsgh (for example, 3V) (Vsgh> Vt1, Vt2, Vt3) at which all of the I-type transistor, D-type and E-type transistors are turned on, and the I-type transistor is turned on. E-type transistor turns off voltage Vsgl1 (eg, 1.5 V) (Vt1>Vsgl1> Vt2), and D-type transistor turns on, but E-type transistor turns off voltage Vsgl2 (eg, 0 V) (Vt1> Vsgl2) > Vt3).
[0328]
A method for applying the voltage of the selection gate will be specifically described with reference to FIG. For example, when reading data from the memory cell MC000, the word lines WL00, WL08 to WL15 are set to 0V, and the word lines WL01 to WL07 are set to Vcc (for example, 3V). The source side select gate SGS0 is set to Vsgh, and the drain side select gate SGD0 is set to Vsgl1. SGS1 and SGD1 are set to 0V. In this case, the source side select MOS transistors STS00 and STS10 are both turned on. On the other hand, although the selection MOS transistor STD00 on the drain side of the bit line BL0 is turned on, the selection MOS transistor STD10 on the drain side of the bit line / BL0 is turned off, so that the bit line BL0 is discharged but the bit line / BL0 is not discharged. .
[0329]
On the other hand, when reading data from the memory cell MC100, the word lines WL00, WL08 to WL15 are set to 0 V, and the word lines WL01 to WL07 are set to Vcc, as in the case of reading the memory cell MC000. The source side select gate SGS0 is set to Vsgl2, and the drain side select gate SGD0 is set to Vsgh. SGS1 and SGD1 are set to 0V. In this case, both the drain side selection MOS transistors STD00 and STD10 are turned on. Since the source-side selection MOS transistor STS10 is turned on, the bit line / BL0 is discharged, but the selection MOS transistor STS00 is turned off so that the bit line BL0 is not discharged.
[0330]
The present invention is a selection MOS transistor connected to the bit line pair BLj, / BLj and controlled by the same selection gates SGS, SGD (for example, STD00 and STD10, STS00 and STS10, STD01 and STD11, STS01 in FIG. 45). What is necessary is just to give a difference to the threshold value of STS11), and the method of setting the threshold value is arbitrary. In FIG. 45, the selection MOS transistors on the drain side of the cell connected to the bit line BLj are all I-type and the selection MOS transistors on the source side are E-type. For example, two NAND blocks sharing the bit line contact are connected on the drain side. One of the selection MOS transistors may be I-type and the other may be E-type.
[0331]
In the present invention, among the selection MOS transistors that share one selection gate, one that is conductive and one that is non-conductive can be generated, and two such selection gates are prepared. This utilizes the fact that a memory cell in a selected state and a memory cell in a non-selected state can be easily realized in memory cells having the same selection gate.
[0332]
As shown in FIG. 46, the selection MOS transistor connected to the drain side may be E-type or D-type, and the selection MOS transistor connected to the source side may be E-type or I-type. In this case, when a memory cell (for example, MC000) in the memory cell unit 2 is selected, SGS0 is set to Vsgh (for example, 3V), SGD0 is set to Vsgl2 (for example, 0V), and SGD1 and SGS1 are set to 0V. When selecting a memory cell (for example, MC100) in the memory cell unit 1, SGS0 may be set to Vsgl1 (for example, 1.5V), SGD0 to Vsgh (for example, 3V), and SGS1 and SGD1 to 0V.
[0333]
If Vsgh is made larger than Vcc, the conductance of the selection MOS transistor is increased (that is, the resistance is decreased), and the current flowing through the NAND cell string is increased during reading, so that the bit line discharge time is shortened. Reading and writing verify reading are speeded up. Vsgh may be boosted from Vcc by a booster circuit in the chip, for example.
[0334]
The threshold values of the I-type selection MOS transistor and the D-type selection MOS transistor may be negative threshold values (for example, -1V and -2V).
[0335]
The larger value Vt1 of the threshold values of the selection gates may also be set to a voltage (for example, 3.5 V) equal to or higher than the power supply voltage Vcc. In this case, in order to turn on the selection MOS transistor having the threshold value Vt1 at the time of reading or verify reading, for example, 4V may be applied to the selection gate using a booster circuit inside the chip.
[0336]
Here, the operation for reading the memory cell MC000 connected to the bit line BL1 in FIG. 48 will be described with reference to the timing chart in FIG. The sense amplifier is formed of a CMOS flip-flop controlled by control signals SAN and SAP.
[0337]
First, the control signals φA and φB become Vss, and the CMOS flip-flop FF and the bit lines BL0 and BL1 are disconnected. Next, the precharge signals φpA and φpB change from Vss to Vcc (time t0), the bit line BL1 is precharged to VB (for example, 1.7 V) and the dummy bit line BL0 is precharged to VA (for example, 1.5 V) (time). t1). When the precharge is finished, φpA and φpB become Vss, and the bit lines BL0 and BL1 are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the control gate (word line) and the control gate (time t2).
[0338]
When reading the memory cell MC000 in FIG. 48, WL00 is 0V, WL01 to WL07 is 3V, SGD0 is 3V, and SGS0 is 1.5V. When the data written in the memory cell MC000 is “0”, the threshold value of the memory cell MC000 is positive, so the cell current does not flow, and the potential of the bit line BL1 remains 1.7V. When the data is “1”, a cell current flows and the potential of the bit line BL1 decreases to 1.5V or less. Since the select gate SGS0 is 1.5V, the select gate transistor STS10 is turned off, and the bit line BL0 is not discharged regardless of the data written in the memory cell MC100, and is kept at the precharge potential 1.5V. .
[0339]
Thereafter, SAP becomes 3V and SAN becomes 0V at time t3, the CMOS flip-flop FF is inactivated, and φE becomes 3V at time t4, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2. (For example, 1.5V). At time t5, .phi.A and .phi.B become 3V, and after the bit line and the sense amplifier are connected (time t6), SAN changes from 0V to 3V and the potential difference between the bit lines BL0 and BL1 is amplified. Thereafter, at time t7, the SAP is changed from 3V to 0V, and the data is latched. That is, if "0" is written in the memory cell MC000, the node N1 is 3V and the node N2 is 0V. If "1" is written in the MC000, the node N1 is 0V and the node N2 is 3V. Become. Thereafter, when the column selection signal CSL1 changes from 0V to 3V, the data latched in the CMOS flip-flop is output to I / O and I / O '(time t8).
[0340]
The timing of the read operation is arbitrary. For example, at time t5, the transfer gate connecting the bit line and the sense amplifier may be turned on to transfer the potentials of the bit lines BL1 and BL2 to the nodes N1 and N2, and then the transfer gate may be turned off. Accordingly, since the load capacity of the sense amplifier is reduced by disconnecting the bit line pair from the sense amplifier, the potentials of the nodes N1 and N2 are rapidly determined at the time of sensing and data latching.
[0341]
Also, during the sense operation of the sense amplifier, first, SAN is changed from 0 V to 3 V, the N-channel transistor of the CMOS flip-flop FF is turned on, and then SAP is changed from 3 V to 0 V, and the P-channel transistor of the CMOS flip-flop FF is turned on. However, the SAP may be changed from 3V to 0V at the same time as the SAN is changed from 0V to 3V.
[0342]
In the above embodiment, while the bit line to which the memory cell to be read is connected is discharged, the other dummy bit line (for example, the memory cell MC000 in FIG. 48) of the bit line pair connected to the sense amplifier is read. In the case of reading the bit line BL0 and the memory cell MC100, the bit line BL1) is in a floating state. However, while the bit line BL1 is precharged and the data in the memory cell MC000 is read thereafter, the precharge control signal φpA is kept at 3V to fix the reference dummy bit line BL0 to the reference potential of 1.5V. You can also.
[0343]
By maintaining the dummy bit line at the reference potential in this way, noise due to capacitive coupling between adjacent bit lines during bit line discharge can be reduced. As in the case of the above read, the bit line is charged / discharged according to the data written in the cell at the time of verify read after writing, but if the dummy bit line not to be read is kept at the reference potential, it is caused by capacitive coupling between the bit lines. Noise can be reduced.
[0344]
<Write>
A write procedure in this embodiment, for example, when writing to the memory cell MC000 of FIG. 48 will be described below.
[0345]
The selection gate SGD0 and the control gates WL01 to WL07 are set to the intermediate potential Vm (about 10V), WL00 is set to Vpp (about 20V), and the bit line BL0 is charged from VA to Vm8 (about 8V). When "1" is written to the memory cell MC000, Vm8 is applied from the flip-flop FF, and when "0" is written, 0 V is applied to the bit line BL1. Then, electrons are not injected into the memory cell MC100 that is not written and the floating gate of the memory cell MC000 when "1" is written, and electrons are injected from the channel into the floating gate of the memory cell MC000 that is written "0". Is done.
[0346]
After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged, and the writing operation is finished.
[0347]
When writing to MC000 of the memory cell array as shown in FIG. 45, a voltage (eg, −3 V) at which the D-type selection MOS transistor STS10 is turned off may be applied to the selection gate SGS0.
[0348]
After the writing is completed, a write verify operation is performed to check whether the writing has been sufficiently performed.
[0349]
First, .phi.A and .phi.B become Vcc, the precharge signals .phi.pB and .phi.pA become Vcc, and the bit line BL1 is precharged to 1.7 V, for example, (dummy) bit line BL0 to 1.5 V, for example.
[0350]
When the precharge is finished, φpA and φpB become Vss, and the bit lines BL1 and BL0 are in a floating state. Thereafter, a desired voltage is applied from the row decoder 3 to the selection gate and the control gate. The control gate WL00 is a verify voltage (for example, 0.5V), WL01 to WL07 are Vcc (for example, 3V), SGS0 is 1.5V, and SGD0 is 3V. When "0" is sufficiently written in the memory cell MC000, the memory cell does not flow because the threshold voltage of the memory cell is positive, and the potential of the bit line BL1 remains 1.7V. When "1" write or "0" write is insufficient, the cell current flows and the potential of the bit line BL1 decreases to 1.5 V or less. The dummy bit line BL0 may be left floating during this time, or may be fixed at 1.5V by setting φpA to Vcc. If the dummy bit line is kept at a constant voltage, the capacitive coupling noise between the bit lines during the bit line discharge can be significantly reduced.
[0351]
After the bit line is discharged, when the verify signal φBV becomes 3V and the data written in the memory cell MC000 is “1”, the bit line BL1 is charged close to 3V. Here, the voltage level of the charge performed by the verify signal may be a precharge voltage of 1.5 V or higher for the dummy bit line BL0.
[0352]
Thereafter, SAP becomes 3V, SAN becomes 0V, the CMOS flip-flop FF is inactivated, and φE becomes 3V, so that the CMOS flip-flop FF is equalized and the nodes N1 and N2 become Vcc / 2 (for example, 1.5V). become. Thereafter, φA and φB become 3V, and after the bit line and the sense amplifier are connected, SAN is changed from 0V to 3V, SAP is changed from 3V to 0V, and the potential difference between the bit line BL1 and the dummy bit line BL0 is amplified, The sense data is latched by the write data.
[0353]
As described above, according to this embodiment, by changing the threshold voltage of the selection MOS transistor and the voltage applied to the selection gate, the folded bit line can be increased without increasing the chip area as in the first embodiment. The system can be realized and high-speed random reading is possible. As a method for changing the threshold value, various methods described in the first embodiment can be employed.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a NAND cell type EEPROM according to a first embodiment.
FIG. 2 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 3 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 4 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 5 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 6 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
7 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment; FIG.
FIG. 8 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 9 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 10 is a timing chart for explaining a data read operation in the first embodiment.
FIG. 11 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 12 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to the first embodiment.
FIG. 13 is a diagram showing a configuration of a twisted bit line system.
FIG. 14 is a diagram showing a configuration of a twisted bit line system.
FIG. 15 is a diagram showing a configuration of a memory cell array in which a selection MOS transistor has a selection gate and a floating gate.
FIG. 16 is a diagram showing a configuration of a memory cell array in the first embodiment.
FIG. 17 is a diagram showing an overall configuration of a NAND cell type EEPROM according to a second embodiment;
FIG. 18 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 19 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 20 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 21 is a diagram showing a configuration of a memory cell array in a second embodiment.
FIG. 22 is a diagram showing a configuration of a sense amplifier circuit in a second embodiment.
FIG. 23 is a diagram illustrating a configuration of a sense amplifier circuit according to a second embodiment.
FIG. 24 is a timing chart for explaining a data read operation in the second embodiment;
FIG. 25 is a timing chart for explaining a data read operation in the second embodiment;
FIG. 26 is a timing chart for explaining a data read operation in the second embodiment;
FIG. 27 is a timing chart for explaining a data read operation in the second embodiment;
FIG. 28 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 29 is a diagram showing a configuration of a memory cell array in the second embodiment.
FIG. 30 is a diagram showing a configuration of an inverter type sense amplifier circuit;
FIG. 31 is a diagram showing a configuration of a single-ended memory cell array and a sense amplifier.
FIG. 32 is a diagram showing an entire configuration of a NAND cell type EEPROM according to a third embodiment;
FIG. 33 is a diagram showing a configuration of a sense amplifier circuit according to a third embodiment.
FIG. 34 is a diagram showing a configuration of a sense amplifier circuit according to a third embodiment.
FIG. 35 is a timing chart for explaining a data read operation in the third embodiment;
FIG. 36 is a diagram showing the influence of noise on adjacent bit lines due to capacitive coupling between bit lines when a bit line potential is amplified;
FIG. 37 shows a structure of a shared sense amplifier type memory cell array.
FIG. 38 is a diagram showing a configuration of a shared sense amplifier type memory cell array;
FIG. 39 is a diagram showing a configuration of a shared sense amplifier type sense amplifier circuit;
FIG. 40 is a timing chart for explaining a data read operation in the third embodiment;
FIG. 41 is a timing chart for explaining a data write operation in the fourth embodiment;
FIG. 42 is a diagram showing a configuration of a folded bit line type sense amplifier circuit according to a fourth embodiment;
FIG. 43 is a diagram showing a configuration of a memory cell array in the fifth embodiment.
FIG. 44 is a diagram showing a configuration of a memory cell array in the fifth embodiment.
FIG. 45 is a diagram showing a configuration of a memory cell array in a sixth embodiment.
FIG. 46 is a diagram showing a configuration of a memory cell array in the sixth embodiment.
FIG. 47 is a timing chart for explaining a data read operation in the sixth embodiment;
FIG. 48 is a diagram showing a configuration of a memory cell array and a sense amplifier circuit according to a sixth embodiment;
[Explanation of symbols]
1, 1A, 1B, 1A1, 1A2, 1B1, 1B2... Memory cell array
2, 2A, 2B ... sense amplifier and latch circuit
3, 3A, 3B ... row decoder
4 ... Column decoder
5 ... Address buffer
6 ... I / O sense amplifier
7 ... Data I / O buffer
8 ... Board potential control circuit
BL ... Bit line
WL ... Word line
STD: First selection MOS transistor
STS ... second selection MOS transistor
SGD: First selection gate
SGS ... second selection gate

Claims (4)

A plurality of electrically rewritable nonvolatile memory cells connected in series, one NAND cell unit having one end connected to the bit line and the other end connected to the source line;
A memory cell array comprising a first sub-array and a second sub- array comprising a plurality of NAND cell units and comprising a data write area divided into predetermined units;
Data that is provided corresponding to each of the plurality of subarrays and that is stored in the NAND cell unit depending on whether the bit line is charged in advance and the NAND cell unit passes current from the bit line to the source line. A readout circuit for reading out,
A plurality of latch circuits provided corresponding to each of the plurality of subarrays, connected to each of the plurality of bit lines and temporarily storing data read from the NAND cell unit;
A data output circuit for outputting the data of the latch circuit to the outside,
In the plurality of NAND cells, one end of two NAND cells is connected to one bit line,
The first sub-array includes a first memory unit, and the second sub-array includes a second memory cell unit;
Each of the subarrays includes first and second memory cell units,
The NAND cell unit of the first memory cell unit has a first selection transistor having a first threshold connected to the bit line and a second threshold connected to the source line. Two selection transistors,
The NAND cell unit of the second memory cell unit has a third selection transistor having a third threshold connected to the bit line and a fourth threshold connected to the source line. 4 selection transistors,
A gate of the first selection transistor and a gate of the third selection transistor are commonly connected by a first control line;
A gate of the second selection transistor and a gate of the fourth selection transistor are commonly connected by a second control line;
The first threshold is greater than the third threshold;
The first threshold value and the fourth threshold value are equal;
The second threshold and the third threshold are equal;
Out of the data read from the first memory cell unit or the second memory cell unit, the data latched in the latch circuit is output from the data output circuit to the outside and the data is read from the other memory cell unit. A non-volatile semiconductor memory device.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the latch circuit further has a function of sensing potentials of the plurality of bit lines.   3. The nonvolatile semiconductor device according to claim 1, wherein a plurality of MOS transistors for controlling connection between the plurality of bit lines and the latch circuit are provided between the plurality of bit lines and the latch circuit. Storage device.   4. The nonvolatile semiconductor memory device according to claim 1, wherein the data of the plurality of latch circuits is divided into a plurality of times and output to the outside from the data output circuit. 5.

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