JP4020515B2 - Track hold circuit and buffer circuit for track hold circuit - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to a track hold circuit for capturing a high-frequency signal, and more particularly to a track hold circuit suitable for use in a preceding stage of an AD converter.
[0002]
[Prior art]
In general, it is difficult to convert an analog signal that changes very quickly to digital with an AD converter with high accuracy. However, by providing a track hold circuit that follows the signal and holds the voltage value of the signal at a certain timing before the AD converter, a high-frequency signal can be converted to digital with high accuracy.
[0003]
Generally, the track hold circuit includes an open loop configuration shown in FIG. 5 and a closed loop configuration shown in FIG. In the track hold circuit of FIG. 5, an input signal Vin is applied to the input buffer circuit 1, a capacitor 3 for holding a voltage is connected to the input of the output buffer 2, and the output of the input buffer 1 is A sampling switch 4 controlled by a timing signal is provided between the input of the output buffer 2. On the other hand, in the track hold circuit of FIG. 6, an operational amplifier is used for the input buffer circuit 5 and the output buffer circuit 6, the input signal Vin is applied to one input of the input buffer circuit 5, and the output buffer circuit 6 is applied to the other input. Is returned. A capacitor 7 for holding a voltage is connected to the output of the output buffer circuit 6 and one input thereof, and the other input is connected to a predetermined potential, for example, a ground potential. A sampling switch 8 is provided between the output of the input buffer circuit 5 and one input of the output buffer circuit 6.
[0004]
5 and FIG. 6, when the sampling switches 4 and 8 are OFF, the input buffer circuits 1 and 5 can obtain an output signal that follows the voltage of the input signal Vin. When the sampling switches 4 and 8 are turned on, the output voltages of the input buffer circuits 1 and 5 are held in the capacitors 3 and 7. When the sampling switches 4 and 8 are turned off, the voltage held in the capacitors 3 and 7 is output from the output buffer circuits 4 and 6, and the voltage is continuously held.
[0005]
The track-hold circuit having the open loop configuration shown in FIG. 5 has a simple structure and high speed, but has a drawback that accuracy is poor because there is no feedback loop. Further, the feature of the track-and-hold circuit of the closed loop configuration shown in FIG. 6 is that high accuracy can be obtained because it includes a feedback path, but there is a disadvantage that the operation speed is slowed down due to the influence of this feedback path. .
[0006]
[Problems to be solved by the invention]
An object of the present invention is to obtain a track-hold circuit having both high speed and high accuracy, and an object thereof is to improve the accuracy of the track-hold circuit having the open loop configuration shown in FIG. Thus, as a result of examining the cause of the deterioration of the accuracy of the track-and-hold circuit of the open loop configuration, two major factors were grasped. One is the influence of charge injection due to the stray capacitance of a MOS transistor normally used as the sampling switch 4, and the other is the influence of the nonlinearity of the source follower buffer used for the input buffer and the output buffer.
[0007]
Charge injection is a phenomenon in which, when the MOS transistor is turned off, the charge accumulated in the capacitor 3 is taken to the stray capacitance between the source and the gate, whereby the output voltage of the output buffer 2 changes. This amount of change depends nonlinearly on the output signal voltage of the buffer circuit 1. That is, in the case of an N-channel MOS transistor, the MOS transistor is turned on with the power supply voltage Vdd being applied to the gate. At this time, the output signal voltage of the input buffer circuit 1 is charged to the capacitor 3 via the MOS transistor. In addition, the stray capacitance between the gate and the source is charged. Therefore, the charge charged in the stray capacitance between the gate and the source follows the difference voltage between the voltage value of the output signal and the power supply voltage Vdd, and the amount of charge charged in the stray capacitance changes when the output signal voltage changes. To do. When a ground voltage is applied to the gate of the MOS transistor from this state, the MOS transistor is turned off and the buffer circuit 1 and the buffer circuit 2 are disconnected. At this time, since the gate voltage becomes the ground potential, the charge flows out from the capacitor 3 according to the charge charged in the stray capacitance, the signal input voltage of the output buffer 2 decreases, and the voltage of the output signal voltage Vout Will also decline. The amount of decrease in the output signal voltage depends on the charge amount of the stray capacitance, that is, the magnitude of the output signal voltage of the input buffer circuit 1. Therefore, the entire track hold circuit has non-linear characteristics, which causes a deterioration in accuracy.
[0008]
On the other hand, the input buffer circuit 1 and the output buffer circuit 2 are constituted by a source follower buffer circuit of a P-channel MOS transistor 9 as shown in FIG. The output voltage Vout is higher than the input voltage Vin by a gate-source voltage necessary for causing a constant current to flow through the MOS transistor 9 by the constant current circuit 10, but the source-drain voltage is a function of the input voltage Vin. Therefore, the output voltage becomes non-linear with respect to the input voltage due to the channel length modulation effect.
[0009]
[Means for Solving the Problems]
The present invention has been created in view of the above points. First, the first and second buffer circuits to which an input voltage is applied are connected to the output of the second buffer circuit. A switch circuit; voltage holding means connected to the output of the switch circuit; and voltage addition means for applying a voltage obtained by adding a predetermined voltage to the output voltage of the first buffer circuit to the control electrode of the switch circuit. Thus, a high-speed and high-accuracy track hold circuit is realized.
[0010]
Second, first and second buffer circuits to which an input voltage is applied, a MOS switch connected to the output of the second buffer circuit, and a first capacitor connected to the other end of the MOS switch A second capacitor for holding a predetermined voltage; one end of the second capacitor connected to a predetermined potential; the other end connected to a ground potential; and a control electrode of the MOS switch connected to a ground potential. 1 switch group and a second switch group in which one end of the second capacitor is connected to the control electrode of the MOS switch and the other end is connected to the output of the first buffer circuit. A highly accurate track hold circuit is realized.
[0011]
Third, in the track hold circuit described above, the first switch group and the second switch group operate in a complementary manner.
[0012]
Fourth, a first MOS transistor to which an input signal is applied, a constant current source provided between the source of the first MOS transistor and one power source, and the source of the first MOS transistor In the buffer circuit in which the output is taken out from the first MOS transistor, a second MOS transistor is provided between the drain of the first MOS transistor and the other power source, and the voltage at which the difference from the voltage value of the input signal becomes a constant value is applied By applying the voltage to the gates of the two MOS transistors, a highly accurate buffer circuit for a track hold circuit is realized.
[0013]
Fifth, a first MOS transistor to which an input signal is applied, a first constant current source provided between the source of the first MOS transistor and one power source, and the first MOS transistor A second MOS transistor connected in series between the first power source and the other power source, a third MOS transistor having the input signal applied to the gate, and a second MOS transistor connected to the source of the third MOS transistor. A high-precision buffer circuit for a track hold circuit is realized by connecting a connection point between the third MOS transistor and the second constant current source to the gate of the second MOS transistor. To do.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram of a track and hold circuit showing an embodiment of the present invention. The input signal Vin is applied to the inputs of the first buffer circuit 11 and the second buffer circuit 12. A signal voltage holding capacitor 14 is connected to the input of the third buffer circuit 13, and an N-channel MOS transistor 15 as a sampling switch is connected between the inputs of the buffer circuit 12 and the buffer circuit 13. The The capacitor 16 is a capacitor for holding the power supply voltage Vdd, adding it to the input signal Vin, and applying it to the gate of the MOS transistor 15. A switch SW1 is provided at one end of the capacitor 16 and the power supply voltage Vdd. A switch SW 2 is provided between one end and the gate of the MOS transistor 15. Further, a switch SW3 is provided between the other end of the capacitor 16 and the ground GND, and a switch SW4 is provided between the capacitor 16 and the output of the buffer circuit 1. Further, a switch SW5 is provided between the gate of the MOS transistor 15 and the ground GND. Among these switches, the switches SW1, SW3, and SW5 that are the first switch group are driven on and off in conjunction with each other, and the switches SW2 and SW4 that are the second switch group are on and off in conjunction with each other. However, the first switch group and the second switch group operate complementarily to each other.
[0015]
Next, the operation will be described.
[0016]
First, in the hold mode, the switches SW1, SW3, and SW5 are turned on, the switches SW2 and SW4 are turned off, and the capacitor 16 is connected between the power supply voltage Vdd and the ground GND. Charged. Since the ground potential is applied to the gate of the MOS transistor 15, the MOS transistor 15 is off, and the output voltage Vout of the buffer circuit 13 becomes a voltage according to the voltage held in the capacitor 14.
[0017]
Next, in the track mode, the switches SW1, SW3, SW5 are turned off, SW2, SW4 are turned on, and the capacitor 16 is connected between the buffer circuit 1 and the gate of the MOS transistor 15. Therefore, a voltage obtained by adding the voltage charged in the capacitor 16 to the output voltage V1 of the buffer circuit 11 is applied to the gate of the MOS transistor 15, and the MOS transistor 15 is turned on. Since the buffer circuits 11 and 12 are formed with the same configuration, the output voltages V1 and V2 are the same. Therefore, the gate voltage of the MOS transistor 15 is higher than the voltage V2 charged in the capacitor 14 by the power supply voltage Vdd. That is, the voltage charged in the floating capacitance between the gate and source of the MOS transistor 15 is always charged with the power supply voltage Vdd regardless of the output voltage of the buffer circuit 12. Accordingly, when the switch enters the hold mode, that is, when the switches SW2 and SW4 are turned off and the switches SW1, SW3, and SW5 are turned on, even if the ground potential GND is applied to the gate of the MOS transistor 15, the stray capacitance is supplied from the capacitor 14. Since the electric charge drawn out to becomes an almost constant electric charge according to the power supply voltage Vdd, the change of the signal voltage applied to the input of the buffer circuit 13 becomes constant, and the linearity is maintained. Further, since a voltage equal to or higher than the power supply voltage Vdd is applied to the gate of the MOS transistor 15, the ON resistance of the MOS transistor is also reduced.
[0018]
FIG. 2 is a specific circuit diagram of the embodiment shown in FIG.
The buffer circuits 11 and 12 have the same configuration, in which four P-channel MOS transistors are connected in series between the power supply Vdd and the ground GND. The MOS transistors 17, 18, 19, and 20 to which the bias voltages Vb1 and Vb2 are applied to the gates form constant current sources, respectively, and outputs are respectively taken out from the sources of the MOS transistors 21 and 22 to which the input signal Vin is applied. A source follower is formed. Further, a voltage that is lowered by a fixed voltage E from the voltage of the input signal Vin is applied to the gates of the MOS transistors 23 and 24. By providing the MOS transistors 23 and 24, the source-drain voltages of the MOS transistors 21 and 22 become constant regardless of the voltage value of the input signal Vin.
[0019]
The switches SW1, SW3, SW5 are composed of N-channel MOS transistors, and a control clock CLK1 is applied to their gates. The switch SW2 is composed of a P-channel MOS transistor, and SW4 is composed of a transmission gate, to which a control clock CLK2 and its inverted signal * CLK2 are applied.
[0020]
FIG. 3 is a timing diagram of CLK1 and CLK2. The period when CLK1 is at H level is a hold mode in which the switches SW1, SW3 and SW5 are on, and the period when CLK2 is at H level is a track mode in which the switches SW2 and SW4 are on. The H level timings of CLK1 and CLK2 are set so as not to overlap.
[0021]
FIG. 4 is a circuit diagram for explaining the buffer circuits 11 and 12 shown in FIG. The constant current source 24 is a constant current source formed by the MOS transistors 12 and 19 shown in FIG. 2, and the constant current source 24 and the MOS transistors 21 and 23 are connected in series between the power supply Vdd and the ground GND. . On the other hand, the circuit for generating the fixed voltage E is constituted by an N-channel MOS transistor 25 connected in series between the power supply Vdd and the ground GND, and a constant current source 26. The gate of the MOS transistor 25 is connected to the gate of the MOS transistor 21. The same input signal Vin is applied. The connection point between the source of the MOS transistor 25 and the constant current source 26 is connected to the gate of the MOS transistor 23. That is, since the output of the MOS transistor 25 is a source follower, the voltage applied to the gate of the MOS transistor 23 is a voltage that is reduced by the gate-source voltage E of the MOS transistor 25 from the input signal Vin. Further, the drain voltage of the MOS transistor 21 is higher than the gate-source voltage of the MOS transistor 23. Therefore, the drain-source voltage of the MOS transistor 21 is constant regardless of the voltage value of the input signal Vin, so that the influence on the output Vout can be prevented and a linear buffer circuit can be realized.
[0022]
【The invention's effect】
As described above, according to the present invention, the charge change of the capacitor 14 due to charge injection based on the stray capacitance of the MOS switch 15 depends on the voltage value of the output voltage of the buffer circuit 12, in other words, the voltage value of the input signal Vin. Can be prevented, and the linearity of the track and hold circuit is improved. In addition, since a voltage higher than the power supply voltage is applied to the gate of the MOS switch 15, the on-resistance is reduced and the high-frequency characteristics of the track hold circuit are improved.
[0023]
In addition, since the influence of the input voltage between the source and drain of the MOS transistors constituting the source follower of the buffer circuit on the output can be prevented, the linearity of the buffer circuit is improved.
[0024]
As described above, a high-speed and high-precision CMOS track hold circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a specific circuit diagram of the embodiment shown in FIG. 1;
FIG. 3 is a timing chart for explaining the operation of the circuit shown in FIG. 2;
FIG. 4 is a circuit diagram of a buffer circuit used in a track hold circuit.
FIG. 5 is a block diagram showing a conventional open loop type track hold circuit.
FIG. 6 is a block diagram showing a conventional closed-loop type track hold circuit.
FIG. 7 is a circuit diagram showing a conventional buffer circuit.
[Explanation of symbols]
11 First buffer circuit 12 Second buffer circuit 13 Third buffer circuit 14 Capacitor 15 Sampling MOS transistor 16 Capacitor 24 Constant current source 26 Constant current source

Claims (2)

  A first and a second buffer circuit to which an input voltage is applied; a MOS switch connected to the output of the second buffer circuit; a first capacitor connected to the other end of the MOS switch; A second capacitor for holding a voltage, and a first switch group in which one end of the second capacitor is connected to a predetermined potential, the other end is connected to the ground potential, and the control electrode of the MOS switch is connected to the ground potential. And a track hold circuit including a second switch group in which one end of the second capacitor is connected to the control electrode of the MOS switch and the other end is connected to the output of the first buffer circuit.   2. The track hold circuit according to claim 1, wherein the first switch group and the second switch group operate complementarily.

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