JP4018432B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor film formed on an insulator surface is used as an active layer. Note that in this specification, a semiconductor device refers to a device including a transistor, in particular, a field effect transistor, typically a MOS (Metal Oxide Semiconductor) transistor or a thin film transistor (hereinafter referred to as TFT). Specifically, a liquid crystal display device having a circuit manufactured using the semiconductor device in a driver circuit or a pixel portion, and an electric appliance using the liquid crystal display device in the display portion are also included in the category. To do.
[0002]
[Prior art]
In forming a semiconductor device, a plasma chemical vapor deposition (hereinafter referred to as PCVD) method is widely used to form a thin film such as a semiconductor film or an insulating film. In the PCVD method, SiH which is the first gas containing silicon is used. _Four N, which is a second gas that does not contain silicon ₂ O, NH _Three , N ₂ , H ₂ , Or applying high frequency power to Ar or the like, or TEOS (Si (OC ₂ H _Five ) _Four : Tetraethylorthosilicate) and O, the second gas that does not contain silicon ₂ A high frequency power is applied to the semiconductor layer to form an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The PCVD method is a thin film formation method in which high-frequency power is applied to a sample gas to cause a chemical reaction in a high energy plasma state, and it can be applied to a wide range of fields because it can be formed on glass and plastic. ing.
[0003]
[Problems to be solved by the invention]
It is known that several types of radicals exist when plasma is generated by applying high-frequency power to the first gas containing silicon as described above. Some of them have a short lifetime as radicals, and it is said that they become nuclei and grow in the gas phase to generate particles. Therefore, the film formed by the PCVD method has a problem in that these particles are mixed in the film, resulting in a breakdown voltage failure (leakage) and variations in characteristics.
[0004]
In recent years, development of submicron order miniaturization technology has become extremely important. Among these, the thinning of the gate insulating film is an important issue. However, it is clear that as the film thickness becomes thinner, the above-mentioned breakdown voltage breakdown (leakage) and characteristic variations become more serious problems.
[0005]
The present invention is a technique for solving such a problem relating to a method of forming a thin film by the PCVD method, and in particular, to improve insulation breakdown voltage failure (leakage) and variation in characteristics of the insulating film due to particles generated during film formation. Is an issue.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, in the present invention, a first gas containing silicon and a second gas not containing silicon are supplied into a reaction chamber capable of maintaining a reduced pressure state, and discharged with a first power. The first process of forming a thin film on the substrate by stopping the supply of the first gas containing silicon and stopping the supply of only the second gas not containing silicon while maintaining the discharge And a second process for applying the electric power.
[0007]
Furthermore, in the present invention, a first gas containing silicon and a second gas not containing silicon are supplied into a reaction chamber capable of maintaining a reduced pressure state, and a discharge is generated with the first electric power on the substrate. The first treatment for forming a thin film and the supply of the first gas containing silicon are stopped, the supply of only the second gas not containing silicon is continued, and the second power is applied while maintaining the discharge to react. And a second process for discharging particles existing in the room.
[0008]
Furthermore, in the present invention, the first power containing the first gas containing silicon and the second gas containing no silicon are supplied into the reaction chamber capable of maintaining the reduced pressure state, and the first power is maintained in a state where the constant pressure is maintained. In the first process of generating a thin film on the substrate by generating a discharge, and the supply of the first gas containing silicon is stopped, only the second gas not containing silicon is continuously supplied, and the discharge is maintained, And a second process of applying the second power only to the second gas not containing silicon under a pressure condition different from that of the first process.
[0009]
Furthermore, in the present invention, the first power containing the first gas containing silicon and the second gas containing no silicon are supplied into the reaction chamber capable of maintaining the reduced pressure state, and the first power is maintained in a state where the constant pressure is maintained. In the first process of generating a thin film on the substrate by generating a discharge, and the supply of the first gas containing silicon is stopped, only the second gas not containing silicon is continuously supplied, and the discharge is maintained, And a second process for discharging particles existing in the reaction chamber by applying a second power under a pressure condition different from that of the first process.
[0010]
In the configuration of the present invention, the first gas containing silicon is SiH. _Four , Si ₂ H ₆ Or Si (OC ₂ H _Five ) _Four It includes one kind selected from. The second gas that does not contain silicon is N ₂ O, NH _Three , N ₂ , H ₂ , Ar, or O ₂ It includes one kind selected from.
[0011]
In the present invention, the second power applied to generate the discharge is applied with the same power as the first power or a lower power than the first power.
[0012]
Moreover, when applying high frequency power to the second gas not containing silicon, the pressure may be changed simultaneously. The pressure is changed so that the charged value of the electrode portion is weakened or 0 (zero), or the sign is reversed. As a result, particles are easily discharged.
[0013]
Further, when applying high frequency power to the second gas not containing silicon, the same effect as when the pressure is changed can be expected even if the RF power is reduced.
[0014]
Of course, when high frequency power is applied to the second gas not containing silicon, it is possible to simultaneously change the pressure and reduce the RF power.
[0015]
In this way, after supplying the first gas containing silicon and the second gas not containing silicon and generating discharge with the first power to form the target thin film, the silicon is maintained while maintaining the discharge. By cutting off the supply of only the first gas containing silicon and supplying only the second gas containing no silicon, the growth of particles is stopped and released into the gas phase of the reaction chamber capable of maintaining a reduced pressure state. Particles can be discharged out of the reaction chamber. For this reason, it is possible to prevent particles from being mixed into the thin film, and to prevent generation of a breakdown voltage defect (leakage) or characteristic variation.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG.
[0017]
The procedure for forming an insulating film by the PCVD method is as follows. First, in a reaction chamber having a high-frequency power source 105, a substrate 101 is placed on a susceptor 102 and SiH, which is a first gas containing silicon. _Four N, which is a second gas that does not contain silicon ₂ O, NH _Three , N ₂ , H ₂ Alternatively, Ar or the like is supplied and high frequency power is applied to generate plasma 103. At this time, particles 104 are generated between the electrode and the plasma generation region 106 (hereinafter referred to as a sheath region) (FIG. 1A). After the insulating film 108 is formed, SiH, which is a first gas containing silicon, with high-frequency power applied. _Four Only the supply of etc. is stopped, and the particles 104 existing in the sheath region 106 are discharged (FIG. 1B). Since the supply of the first gas containing silicon is stopped, no new particles are generated, so it is possible to discharge particles existing in the sheath region 106 (particles generated when the insulating film is formed). . Thereafter, by stopping the application of the high-frequency power, the amount of particles falling on the substrate can be reduced (FIG. 1C).
[0018]
[Embodiment 2]
An embodiment of the present invention will be described with reference to FIG.
[0019]
The procedure for forming an insulating film by the PCVD method is as follows. First, a substrate 101 is placed on a susceptor 102 in a reaction chamber having a high-frequency power source 105, and TEOS which is a first gas containing silicon and second containing no silicon. O which is the gas of ₂ And plasma 103 is generated by applying high frequency power. At this time, particles 104 are generated in the sheath region 106 (FIG. 1A). After the insulating film 108 is formed, only the supply of TEOS, which is the first gas containing silicon, is stopped while the high frequency power is applied, and the particles 104 existing in the sheath region 106 are discharged (FIG. 1B). Since the supply of the first gas containing silicon is stopped, no new particles are generated, so it is possible to discharge particles existing in the sheath region 106 (particles generated when the insulating film is formed). . Thereafter, by stopping the application of the high-frequency power, the amount of particles falling on the substrate can be reduced (FIG. 1C).
[0020]
【Example】
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel portion and TFTs (n-channel TFT and p-channel TFT) of a driver circuit provided around the pixel portion on the same substrate will be described in detail.
[0021]
As the substrate 200, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed on the surface thereof may be used. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0022]
Next, as illustrated in FIG. 2A, a base film 201 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 200. Although a two-layer structure is used as the base film 201 in this embodiment, a single-layer film of an insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 201, SiH is used as the first gas containing silicon. _Four NH as the second gas without silicon _Three Or N ₂ Using O, the silicon oxynitride film 201a is formed to a thickness of 50 to 100 nm, and then SiH is applied while the high frequency power is applied. _Four The supply of NH _Three And N ₂ Plasma treatment is performed with O gas. Next, as the second layer of the base film 201, SiH is used as the first gas containing silicon. _Four N as the second gas without silicon ₂ Using O, the silicon oxynitride film 201b is laminated to a thickness of 100 to 150 nm, and then SiH is applied while the high frequency power is applied. _Four The supply of N, N ₂ Plasma treatment is performed with O gas. By this film formation method, dust on the base film can be reduced.
[0023]
Next, an amorphous semiconductor film 202 is formed over the base film 201. The amorphous semiconductor film is formed with a thickness of 30 to 60 nm. The material of the amorphous semiconductor film is not limited, but is preferably silicon or silicon germanium (Si _1-x Ge _x X = 0.001 to 0.05) It may be formed of an alloy or the like. In this embodiment, SiHH is formed by PCVD. _Four An amorphous silicon film is formed using a gas.
[0024]
In this embodiment, SiH is used to form an amorphous silicon film. _Four Only gas is used, but SiH _Four H as the second gas that does not contain silicon in the gas ₂ Or Ar can be used at the same time. In such a case, it is needless to say that the present invention can be applied even when an amorphous silicon film is formed.
[0025]
Further, since the base film and the amorphous semiconductor film can be formed by the same film formation method, the base 201 and the amorphous semiconductor film 202 can also be formed continuously.
[0026]
Next, a crystalline semiconductor film obtained by performing known crystallization treatment (laser crystallization method, thermal crystallization method, thermal crystallization method using a catalyst such as nickel) on the amorphous semiconductor film 202 is obtained. Pattern into a desired shape. In this embodiment, after a nickel-containing solution is held on an amorphous silicon film, dehydrogenation (500 ° C., 1 hour) is continued, and thermal crystallization (550 ° C., 4 hours) is performed. A crystalline silicon film is formed by performing laser annealing for improving the formation. Then, a patterning process using a photolithography method is performed on the crystalline silicon film to form semiconductor layers 206 to 210 (FIG. 2A).
[0027]
Then, an impurity element imparting p-type conductivity is added to control the threshold value (Vth) of the n-channel TFT (FIG. 2B). As an impurity element imparting p-type to a semiconductor, periodic group 13 elements such as boron (B), aluminum (Al), and gallium (Ga) are known. In this embodiment, boron (B) is added.
[0028]
When a crystalline semiconductor film is formed by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO _Four A laser can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. The practitioner may select the crystallization conditions as appropriate.
[0029]
Next, a gate insulating film 211 covering the island-shaped semiconductor layers 206 to 210 is formed to a thickness of 40 to 150 nm. In this embodiment, the gate insulating film 211 is made of SiH as the first gas containing silicon. _Four N as the second gas without silicon ₂ The gate insulating film 211 is formed to a thickness of 100 to 120 nm using O, and then SiH is applied while the high frequency power is applied. _Four Only supply of N, N ₂ Plasma treatment with O gas was performed for 15 seconds. Needless to say, this gate insulating film can be formed using an insulating film containing silicon as a single layer or a stacked structure.
[0030]
Here, a MOS is formed with the gate insulating film formed by the conventional film forming method and the gate insulating film formed by the film forming method using the present invention, and JE measurement (FIG. 15) and CV measurement (FIG. 16) are performed. The results are shown. The results of the J-E measurement showed that the conventional film formation method showed an insulation breakdown voltage defect and variation, but the film formation method using the present invention showed no insulation breakdown voltage defect and almost no variation. It was. Further, when the results of CV measurement are seen, there is no significant difference between the conventional film formation method and the film formation method using the present invention, and the film quality of the gate insulating film is improved by plasma treatment after the gate insulating film is formed. It was confirmed that there was no significant change.
[0031]
When a silicon oxide film is used, TEOS is used as the first gas containing silicon and O2 is used as the second gas not containing silicon by the PCVD method. ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² Then, only the TEOS supply is stopped while the high frequency power is being applied. ₂ Plasma treatment may be performed with gas. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. after formation.
[0032]
Next, a first conductive film (TaN) 212 with a thickness of 20 to 100 nm and a second conductive film (W) 213 with a thickness of 100 to 400 nm are stacked over the gate insulating film 211. The gate conductive film may be formed of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. The first conductive film is formed of a tantalum (Ta) film, the second conductive film is a W film, the first conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed. The first conductive film may be formed of a tantalum nitride (TaN) film, and the second conductive film may be a Cu film.
[0033]
Next, resist masks 214 to 219 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. In this embodiment, an ICP (Inductively Coupled Plasma) etching method is used, and CF is used as an etching gas. _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered.
[0034]
Thereafter, the resist masks 214 to 219 are not removed and the second etching condition is changed, and the etching gas is changed to CF. _Four And Cl ₂ The gas flow ratio is 30/30 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma for about 30 seconds. Etching is performed. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. CF _Four And Cl ₂ Under the second etching condition in which is mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.
[0035]
In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of this taper portion is 15 to 45 °. Thus, the first shape conductive layers 221 to 226 (the first conductive layers 221a to 226a and the second conductive layers 221b to 226b) formed of the first conductive layer and the second conductive layer by the first etching process. Form. Reference numeral 220 denotes a gate insulating film, and regions that are not covered with the first shape conductive layers 221 to 226 are etched and thinned by about 20 to 50 nm.
[0036]
Then, a first doping process is performed without removing the resist mask, and an impurity element imparting n-type conductivity is added to the semiconductor layer (FIG. 3C). The doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 ¹³ ~ 5x10 ¹⁵ atoms / cm ² The acceleration voltage is set to 60 to 100 keV. As the impurity element imparting n-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As) is used. In this case, the conductive layers 221 to 225 serve as a mask for the impurity element imparting n-type, and the first impurity regions 227 to 231 are formed in a self-aligning manner. The first impurity regions 227 to 231 have 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three An impurity element imparting n-type is added in a concentration range of.
[0037]
Next, a second etching process is performed as shown in FIG. 4A without removing the resist mask. CF as etching gas _Four And Cl ₂ And O ₂ Each gas flow rate ratio is 25/25/10 (sccm), and 500 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. . 20 W RF (13.56 MHz) power is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. The W film is etched under this third etching condition. Thus, the W film is anisotropically etched under the third etching conditions to form the second shape conductive layers 233 to 238.
[0038]
Next, a second doping process is performed as shown in FIG. 4A without removing the resist mask. In this case, an impurity element imparting n-type conductivity is doped as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is 70 to 120 keV, and in this embodiment, the acceleration voltage is 90 keV. ¹² atoms / cm ² Then, a new impurity region is formed in the semiconductor layer inside the first impurity region formed in FIG. 3C. Doping is performed using the second shape conductive layers 233 to 237 as masks against the impurity elements so that the impurity elements are also added to the semiconductor layers below the second conductive layers 233a to 237a.
[0039]
Thus, second impurity regions 239 to 243 overlapping with the second conductive layers 233a to 237a and first impurity regions 250 to 254 are formed. The impurity element imparting n-type conductivity is 1 × 10 6 in the second impurity region. ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three So that the concentration becomes.
[0040]
Next, the gate insulating film is etched as shown in FIG. 4B without removing the resist mask. During etching of the gate insulating film, the second conductive layers 233a to 238a are also etched at the same time to form third shape conductive layers 244 to 249. Thus, the second impurity region can be distinguished into a region that does not overlap with a region that overlaps with the second conductive layers 244a to 248a.
[0041]
Then, after removing the resist mask, new resist masks 255 to 257 are formed, and a third doping process is performed as shown in FIG. By this third doping treatment, fourth impurity regions 258 to 263 to which an impurity element imparting a conductivity type opposite to the one conductivity type is added to the semiconductor layer which becomes an active layer of the p-channel TFT are formed. The third shape conductive layers 245 and 248 are used as masks against the impurity element, and a fourth impurity region is formed in a self-aligned manner by adding an impurity element imparting p-type conductivity. In this embodiment, the impurity regions 258 to 263 are diborane (B ₂ H ₆ ) Using an ion doping method. In the third doping process, the semiconductor layer forming the n-channel TFT is covered with masks 255 to 257 made of resist. By the first doping process and the second doping process, phosphorus is added to the impurity regions 258 to 263 at different concentrations, and the concentration of the impurity element imparting p-type in each of the regions is 2 ×. 10 ²⁰ ~ 2x10 ^{twenty one} atoms / cm ^Three By performing the doping treatment so as to become, no problem arises because it functions as the source region and drain region of the p-channel TFT.
[0042]
Through the above steps, impurity regions are formed in the respective semiconductor layers. The third shape conductive layers 244 to 248 overlapping with the semiconductor layer function as gate electrodes. Reference numeral 249 denotes a source wiring, and 248 functions as a second electrode for forming a storage capacitor.
[0043]
Next, the resist masks 255 to 257 are removed, and a first interlayer insulating film 264 covering the entire surface is formed (FIG. 5A). The first interlayer insulating film 264 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a PCVD method or a sputtering method. In this embodiment, SiH is used as the first gas containing silicon by the PCVD method. _Four N as the second gas without silicon ₂ A silicon oxynitride film having a thickness of 150 nm is formed using O, and then SiH is applied while high-frequency power is applied. _Four The supply of N, N ₂ Plasma treatment is performed with O gas. Needless to say, the first interlayer insulating film 264 is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0044]
Next, as shown in FIG. 5A, a step of activating the impurity element added to each semiconductor layer is performed. This activation process is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.
[0045]
In this embodiment, at the same time as the activation treatment, nickel used as a catalyst during crystallization is gettered to impurity regions 250 to 254, 258, and 261 containing high-concentration phosphorus, and mainly channel forming regions. The nickel concentration in the semiconductor layer is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0046]
Further, the activation treatment may be performed before the first interlayer insulating film 264 is formed. However, when the wiring material used for 244 to 248 is weak against heat, an interlayer insulating film (insulating film containing silicon as a main component, for example, a silicon nitride film) is formed to protect the wiring and the like as in this embodiment. After that, it is preferable to perform an activation treatment.
[0047]
Furthermore, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.
[0048]
In the case where a laser annealing method is used as the activation treatment, it is desirable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the hydrogenation.
[0049]
Next, a second interlayer insulating film 265 made of an organic insulating material is formed on the first interlayer insulating film 264. Next, patterning is performed to form contact holes that reach the source wiring 249 and contact holes that reach the impurity regions 250, 252, 253, 258, and 261.
[0050]
In the driver circuit 306, wirings 266 to 271 that are electrically connected to the first impurity region or the fourth impurity region are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm.
[0051]
In the pixel portion 307, a pixel electrode 274, a gate conductive film 273, and a connection electrode 272 are formed (FIG. 5B). With this connection electrode 272, the source wiring 248 is electrically connected to the pixel TFT 304. The gate conductive film 273 is electrically connected to the first electrode (third shape conductive layer 247). Further, the pixel electrode 274 is electrically connected to the drain region of the pixel TFT, and further electrically connected to a semiconductor layer functioning as one electrode forming a storage capacitor. Further, as the pixel electrode 274, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof.
[0052]
As described above, the driver circuit 306 including the n-channel TFT 301, the p-channel TFT 302, and the n-channel TFT 303, and the pixel portion 307 including the pixel TFT 304 and the storage capacitor 305 can be formed over one copper substrate. . In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0053]
The n-channel TFT 301 of the driver circuit 306 includes a channel formation region 275, a third impurity region 239b (GOLD region) that overlaps with the third shape conductive layer 244 that forms the gate electrode, and a second impurity region that is formed outside the gate electrode. Impurity region 239a (LDD region) and a first impurity region 250 functioning as a source region or a drain region. The p-channel TFT 302 includes a channel formation region 276, a fourth impurity region 260 that overlaps with the third shape conductive layer 245 that forms the gate electrode, a fourth impurity region 259 formed outside the gate electrode, and a source region Alternatively, the fourth impurity region 258 functioning as a drain region is provided. The n-channel TFT 303 includes a channel formation region 277, a third impurity region 241b (GOLD region) that overlaps with the third shape conductive layer 246 that forms the gate electrode, and a second impurity region formed outside the gate electrode. 242a (LDD region) and a first impurity region 252 which functions as a source region or a drain region.
[0054]
The pixel TFT 304 in the pixel portion includes a channel formation region 278, a third impurity region 242b (GOLD region) overlapping with the third shape conductive layer 247 forming the gate electrode, and a second impurity formed outside the gate electrode. A region 242a (LDD region) and a first impurity region 253 functioning as a source region or a drain region are provided. In addition, an impurity element imparting p-type conductivity is added to each of the semiconductor layers 261 to 263 functioning as one electrode of the storage capacitor 305 at the same concentration as that of the fourth impurity region. The storage capacitor 305 is formed using the second electrode 248 and the semiconductor layers 261 to 263 using an insulating film (the same film as the gate insulating film) as a dielectric.
[0055]
A top view of a pixel portion of an active matrix substrate manufactured in this embodiment is shown in FIG. In addition, the same code | symbol is used for the part corresponding to FIGS. A chain line AA ′ in FIG. 6 corresponds to a cross-sectional view taken along the chain line AA ′ in FIG. Also, a chain line BB ′ in FIG. 6 corresponds to a cross-sectional view taken along the chain line BB ′ in FIG.
[0056]
As described above, in the active matrix substrate having the pixel structure of this embodiment, the first electrode 247 that partially functions as the gate electrode and the gate conductive film 273 are formed in different layers, and the gate conductive film 273 is used as a semiconductor. It is characterized by shielding the layer.
[0057]
In the pixel structure of this embodiment, the end of the pixel electrode overlaps with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.
[0058]
In addition, it is desirable to increase the whiteness by making the surface of the pixel electrode of this embodiment uneven by a known method such as a sand blasting method or an etching method to prevent specular reflection and scattering the reflected light.
[0059]
FIG. 7 shows a cross-sectional view of an active matrix substrate suitable for a transmissive liquid crystal display device. The processes up to the formation of the second interlayer film are the same as those of the reflection type. A transparent conductive film is formed on the second interlayer film. Then, patterning is performed to form the transparent conductive film layer 282. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0060]
Then, wirings 266 to 277 that are electrically connected to the first impurity region or the fourth impurity region in the driver circuit 306 are formed. Note that these wirings are formed by patterning a laminated film of a Ti film having a thickness of 50 nm and an alloy (alloy film of Al and Ti) having a thickness of 500 nm. In the pixel portion 307, pixel electrodes 283 and 284, a gate conductive film 273, and a connection electrode 272 are formed. In this manner, an active matrix substrate suitable for a transmissive liquid crystal display device can be manufactured by increasing the number of masks by one.
[0061]
[Example 2]
In this embodiment, a process for manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 8 is used for the description.
[0062]
First, after an active matrix substrate in the state of FIG. 5B is obtained according to Embodiment 1, an alignment film 801 is formed on the active matrix substrate of FIG. 5B and a rubbing process is performed. In this embodiment, before forming the alignment film 801, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 806 for maintaining the substrate interval at a desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0063]
Next, colored layers 804 and 805 and a planarization film 807 are formed over the counter substrate 803. The red colored layer 804 and the blue colored layer 805 are partially overlapped to form the second light shielding portion. Although not shown in FIG. 8, the first light-shielding portion is formed by partially overlapping the red colored layer and the green colored layer.
[0064]
Next, a counter electrode 810 was formed in the pixel portion, an alignment film 808 was formed on the entire surface of the counter substrate, and a rubbing process was performed.
[0065]
Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached to each other with a sealant 802. A filler is mixed in the sealant 802, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer 806. Thereafter, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. Thus, the active matrix type liquid crystal display device shown in FIG. 8 is completed.
[0066]
In this embodiment, the substrate shown in Embodiment 1 is used. Therefore, in FIG. 6 showing a top view of the pixel portion of Embodiment 1, at least the gap between the gate wiring 273 and the pixel electrodes 274 and 281, the gap between the gate wiring 273 and the connection electrode 272, and the connection electrode 272 and the pixel electrode 274. It is necessary to shield the gap. In this embodiment, the counter substrate is bonded so that the first light-shielding portion and the second light-shielding portion overlap each other at the position where light should be shielded.
[0067]
[Example 3]
In this embodiment, a method for simultaneously manufacturing a pixel portion on the same substrate and TFTs (n-channel TFT and p-channel TFT) for forming a driver circuit around the pixel portion will be described with reference to FIGS. .
[0068]
First, as shown in FIG. 9A, a substrate 901 made of glass such as barium borosilicate glass represented by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is preferably used. The gate electrodes 902 to 904, the source wirings 906 and 907, and the storage capacitor of the pixel portion are formed from a conductive film containing one or more selected from molybdenum (Mo), tungsten (W), and tantalum (Ta). A capacitor wiring 905 is formed. For example, an alloy of Mo and W is suitable from the viewpoint of resistance reduction and heat resistance. Alternatively, aluminum may be used to oxidize the surface to form the gate electrode.
[0069]
In order to improve the coverage (step coverage) of the film formed on the gate electrode formed using the first photomask with a thickness of 200 to 400 nm, preferably 250 nm. The end is formed to have a tapered shape. The angle of the tapered portion is 5 to 30 degrees, preferably 15 to 25 degrees. The tapered portion is formed by a dry etching method, and its angle is controlled by an etching gas and a bias voltage applied to the substrate side.
[0070]
Next, as illustrated in FIG. 9B, a first insulating layer 908 is formed to cover the gate electrodes 902 to 904, the source wirings 906 and 907, and the capacitor wiring 905 for forming a storage capacitor of the pixel portion. The first insulating layer 908 is formed of an insulating film containing silicon with a thickness of 40 to 200 nm by PCVD or sputtering. For example, the first insulating layer 908 is formed from a silicon nitride film 908a with a thickness of 50 nm and a silicon oxide film 908b with a thickness of 120 nm. When forming by the PCVD method, the first gas, SiH _Four N which is the second gas ₂ O and NH _Three A silicon oxynitride film is formed by using SiH, which is the first gas while applying high-frequency power. _Four The supply of N, N ₂ O and NH _Three Plasma treatment is performed at
[0071]
The first insulating layer 908 is used as a gate insulating film by forming a semiconductor layer thereon, and functions as a blocking layer that prevents impurities such as alkali metals from diffusing from the substrate 901 into the semiconductor layer. Also have.
[0072]
A crystalline semiconductor film 909 is formed over the first insulating layer 908 with a thickness of 30 to 100 nm, preferably 40 to 60 nm. The material of the crystalline semiconductor film is not limited, but is typically silicon or silicon germanium (Si _x Ge _1-x X = 0.01 to 10 atomic%) and an alloy. The method for obtaining the crystalline semiconductor film may be referred to Example 1.
[0073]
The semiconductor layer 909 made of a polycrystalline semiconductor is formed in a predetermined pattern using a second photomask. FIG. 9C illustrates the semiconductor layers 910 to 913 divided into island shapes. The semiconductor layers 910 to 912 are formed so as to partially overlap with the gate electrodes 902 and 904.
[0074]
Thereafter, an insulating film made of silicon oxide or silicon nitride is formed to a thickness of 100 to 200 nm on the divided semiconductor layers 910 to 913. In FIG. 9D, third insulating layers 914 to 918 that serve as channel protective films are formed on the semiconductor layers 910 to 912 in a self-aligning manner by an exposure process from the back surface using the gate electrode as a mask.
[0075]
Then, a first doping process for forming the LDD region of the n-channel TFT is performed. Doping may be performed by ion doping or ion implantation. Phosphorus (P) is added as an n-type impurity (donor), and first impurity regions 919 to 922 formed using the third insulating layers 915 to 918 as masks are formed. The donor concentration in this region is 1 × 10 ¹⁶ ~ 2x10 ¹⁷ / Cm ^Three Concentration.
[0076]
The second doping step is a step of forming a source region and a drain region of the n-channel TFT, and masks 923 to 925 are formed using a third photomask as shown in FIG. . Masks 924 and 925 are formed so as to cover the LDD region of the n-channel TFT, and 1 × 10 6 is formed in the second impurity regions 926 to 928. ²⁰ ~ 1x10 ^{twenty one} / Cm ^Three The donor impurity is added in the concentration range of.
[0077]
Before and after the second doping step, it is preferable to perform etching with hydrofluoric acid in a state where the masks 923 to 925 are formed to remove the third insulating layers 914 and 918.
[0078]
As shown in FIG. 10B, the source region and the drain region of the p-channel TFT are formed by a third doping process, and a p-type impurity (acceptor) is added by an ion doping method or an ion implantation method. The impurity regions 930 and 931 are formed. The p-type impurity concentration in this region is 2 × 10 ²⁰ ~ 2x10 ^{twenty one} / Cm ^Three To be. In this step, a p-type impurity is also added to the semiconductor layer 913.
[0079]
Next, as illustrated in FIG. 10C, a second insulating layer is formed over the semiconductor layer. Preferably, the second insulating layer is formed using a plurality of insulating films. The first layer 932 of the second insulating layer formed over the semiconductor layer is an inorganic insulator made of a silicon nitride film or a silicon nitride oxide film containing hydrogen. When formed by PCVD, the first layer 932 containing silicon is used. SiH as gas _Four NH as the second gas without silicon _Three , H ₂ Or N ₂ O is used to form a thickness of 50 to 200 nm, and then SiH is applied while high frequency power is applied. _Four The supply of NH _Three , H ₂ Or N ₂ Plasma treatment is performed with O gas. Thereafter, a step of activating the impurities added to the respective semiconductor layers is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, heat treatment is performed in a nitrogen atmosphere at 400 to 600 ° C., typically 450 to 500 ° C. for 1 to 4 hours.
[0080]
By this heat treatment, hydrogen of the silicon nitride film or the silicon nitride oxide film of the first layer 932 of the second insulating layer is released simultaneously with the activation of the impurity element, and the semiconductor layer can be hydrogenated. This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen. As a means for performing hydrogenation more efficiently, plasma hydrogenation (using hydrogen excited by plasma) may be performed before forming the first layer 932 of the second insulating layer.
[0081]
A second layer 933 of the second insulating layer illustrated in FIG. 11A is formed using an organic insulating material such as polyimide or acrylic to planarize the surface. Of course, a silicon oxide film formed using TEOS by the PCVD method may be applied, but it is desirable to use an organic material from the viewpoint of improving flatness.
[0082]
Next, a contact hole is formed using a fifth photomask. Then, a connection electrode 934 and source or drain wirings 935 to 937 are formed in the driver circuit 1005 using aluminum (Al), titanium (Ti), tantalum (Ta), or the like with the use of a sixth photomask. In the pixel portion 1006, a pixel electrode 940, a gate wiring 939, and a connection electrode 938 are formed.
[0083]
Thus, a driver circuit 1005 having a p-channel TFT 1001 and an n-channel TFT 1002 and a pixel portion 1006 having a pixel TFT 1003 and a storage capacitor 1004 are formed over the same substrate. In the p-channel TFT 1001 of the driver circuit 1005, a channel formation region 1007 and a source or drain region 1008 including a third impurity region are formed. In the n-channel TFT 1002, a channel formation region 1009, an LDD region 1010 composed of a first impurity region, and a source or drain region 1011 composed of a second impurity region are formed. A pixel TFT 1003 in the pixel portion 1006 has a multi-gate structure, and a channel formation region 1012, an LDD region 1013, and source or drain regions 1014 and 1016 are formed. The second impurity region located between the LDD regions is useful for reducing off current. The storage capacitor 1004 is formed of a capacitor wiring 905, a semiconductor layer 913, and a first insulating layer formed therebetween.
[0084]
In the pixel portion 1006, the source wiring 907 is electrically connected to the source or drain region 1014 of the pixel TFT 1003 by the connection electrode 938. In addition, the gate wiring 939 is electrically connected to the first electrode. Further, the pixel electrode 940 is connected to the source or drain region 1016 of the pixel TFT 1003 and the semiconductor layer 913 of the storage capacitor 1004.
[0085]
FIG. 11B illustrates a contact portion between the gate electrode 904 and the gate wiring 939. The gate electrode 904 also serves as one electrode of a storage capacitor of an adjacent pixel, and forms a capacitor in a portion overlapping with the semiconductor layer 944 connected to the pixel electrode 945. FIG. 11C illustrates the arrangement relationship between the source wiring 907, the pixel electrode 940, and the adjacent pixel electrode 946. By forming an end portion of the pixel electrode over the source wiring 907 and forming an overlapping portion, stray light can be obtained. The shading is improved. In the present specification, such a substrate is referred to as an active matrix substrate for convenience.
[0086]
The pixel structure shown in FIG. 11 is suitable for a reflective liquid crystal display device, but has a pixel structure suitable for a transmissive liquid crystal display device by using a transparent conductive film as in the first embodiment. Things can also be made.
[0087]
[Example 4]
TFTs formed by implementing the present invention can be used in various electro-optical devices (typically active matrix liquid crystal displays). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices and semiconductor circuits are incorporated as parts.
[0088]
Such electronic devices include video cameras, digital cameras, projectors (rear or front type), head mounted displays (goggles type displays), car navigation systems, car stereos, personal computers, and personal digital assistants (mobile computers, mobile phones). Phone or electronic book). Examples of these are shown in FIGS.
[0089]
FIG. 12A shows a personal computer, which includes a main body 1201, an image input portion 1202, a display portion 1203, a keyboard 1204, and the like. The present invention can be applied to the image input unit 1202, the display unit 1203, and other signal control circuits.
[0090]
FIG. 12B illustrates a video camera, which includes a main body 1205, a display portion 1206, an audio input portion 1207, operation switches 1208, a battery 1209, an image receiving portion 1210, and the like. The present invention can be applied to the display portion 1206 and other signal control circuits.
[0091]
FIG. 12C illustrates a mobile computer (mobile computer), which includes a main body 1211, a camera unit 1212, an image receiving unit 1213, an operation switch 1214, a display unit 1215, and the like. The present invention can be applied to the display portion 1215 and other signal control circuits.
[0092]
FIG. 12D illustrates a goggle type display, which includes a main body 1216, a display portion 1217, an arm portion 1218, and the like. The present invention can be applied to the display portion 1217 and other signal control circuits.
[0093]
FIG. 12E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded, and includes a main body 1219, a display portion 1220, a speaker portion 1221, a recording medium 1222, an operation switch 1223, and the like. This player uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can enjoy music, movies, games, and the Internet. The present invention can be applied to the display portion 1220 and other signal control circuits.
[0094]
FIG. 12F illustrates a digital camera, which includes a main body 1224, a display portion 1225, an eyepiece portion 1226, an operation switch 1227, an image receiving portion (not shown), and the like. The present invention can be applied to the display portion 1225 and other signal control circuits.
[0095]
FIG. 13A illustrates a front type projector, which includes a projection device 1301, a screen 1302, and the like. The present invention can be applied to a liquid crystal display device 1314 constituting a part of the projection device 1301 and other signal control circuits.
[0096]
FIG. 13B shows a rear projector, which includes a main body 1303, a projection device 1304, a mirror 1305, a screen 1306, and the like. The present invention can be applied to the liquid crystal display device 1314 constituting a part of the projection device 1304 and other signal control circuits.
[0097]
Note that FIG. 13C illustrates an example of the structure of the projection devices 1301 and 1304 in FIGS. 13A and 13B. The projection devices 1301 and 1304 include a light source optical system 1307, mirrors 1308 and 1310 to 1312, a dichroic mirror 1309, a prism 1313, a liquid crystal display device 1314, a retardation plate 1315, and a projection optical system 1316. The projection optical system 1316 includes an optical system that includes a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. In addition, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.
[0098]
FIG. 13D illustrates an example of the structure of the light source optical system 1307 in FIG. In this embodiment, the light source optical system 1307 includes a reflector 1318, a light source 1319, lens arrays 1320 and 1321, a polarization conversion element 1322, and a condenser lens 1323. Note that the light source optical system illustrated in FIG. 13D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.
[0099]
However, the projector shown in FIG. 13 shows a case where a transmissive electro-optical device is used, and an application example of the reflective electro-optical device is not shown.
[0100]
FIG. 14A shows a mobile phone, which includes a display panel 1401, an operation panel 1402, a connection portion 1403, a sensor built-in display 1404, an audio output portion 1405, an operation key 1406, a power switch 1407, an audio input portion 1408, and an antenna 1409. Etc. The present invention can be applied to the sensor built-in display 1404, the audio output unit 1405, the audio input unit 1408, and other signal control circuits.
[0101]
FIG. 14B illustrates a portable book (electronic book), which includes a main body 1411, a display portion 1412, a storage medium 1413, operation switches 1414, an antenna 1415, and the like. The present invention can be applied to the display portion 1412, the storage medium 1413, and other signal circuits.
[0102]
FIG. 14C illustrates a display which includes a main body 1416, a support base 1417, a display portion 1418, and the like. The present invention can be applied to the display portion 1418. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for displays having a diagonal of 10 inches or more (particularly 30 inches or more).
[0103]
As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields.
[0104]
【The invention's effect】
According to the present invention, particles generated when a thin film is formed by the PCVD method can be removed, so that it is possible to suppress an insulation breakdown voltage defect (leakage) and variation in characteristics of the insulating film due to the particles. That is, according to the present invention, it is possible to create TFTs with better characteristics.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of this embodiment.
FIG. 2 is a cross-sectional view of a TFT according to the first embodiment.
FIG. 3 is a cross-sectional view of a TFT according to the first embodiment.
4 is a cross-sectional view of the TFT of Example 1. FIG.
5 is a cross-sectional view of the TFT of Example 1. FIG.
6 is a cross-sectional view of the TFT of Example 1. FIG.
7 is a cross-sectional view of the TFT of Example 1. FIG.
FIG. 8 is a cross-sectional view of a TFT according to the second embodiment.
FIG. 9 is a cross-sectional view of a TFT according to the third embodiment.
10 is a cross-sectional view of a TFT of Example 3. FIG.
11 is a cross-sectional view of a TFT of Example 3. FIG.
12 is a diagram showing various semiconductor devices of Example 4. FIG.
13 is a diagram showing various semiconductor devices of Example 4. FIG.
14 is a diagram showing various semiconductor devices of Example 4. FIG.
FIG. 15 is a diagram showing an example of the present invention.
FIG. 16 is a diagram showing an example of the present invention.

Claims (5)

Supplying a first gas containing silicon and a second gas not containing silicon into the reaction chamber in which the substrate is installed;
Forming a thin film on the substrate by generating a plasma in the reaction chamber by applying high-frequency power in a state where the first pressure is maintained;
A method for manufacturing a semiconductor device, wherein the supply of only the first gas is stopped while the high-frequency power is applied, and the particles are discharged in a state where the second pressure different from the first pressure is maintained. Supplying a first gas containing silicon and a second gas not containing silicon into the reaction chamber in which the substrate is installed;
A first thin film is formed on the substrate by generating a plasma in the reaction chamber by applying a first high-frequency power while maintaining the first pressure,
In a state where only the first gas is stopped and the second pressure different from the first pressure is maintained, a second high frequency power lower than the first high frequency power is applied to discharge particles. A method for manufacturing a semiconductor device.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the charged value of the electrode portion in the reaction chamber is smaller when discharging the particles than when forming the thin film. In any one of Claims 1 thru | or 3 ,
The method for manufacturing a semiconductor device, wherein the first gas containing silicon includes at least one selected from SiH ₄ , Si ₂ H _6, and Si (OC ₂ H ₅ ). In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the second gas not containing silicon includes at least one selected from N ₂ O, NH ₃ , N ₂ , H ₂ , Ar, and O ₂ .

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