JP4009169B2

JP4009169B2 - Semiconductor element storage package and semiconductor device

Info

Publication number: JP4009169B2
Application number: JP2002278528A
Authority: JP
Inventors: 義明植田; 正和安井
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2002-08-13
Filing date: 2002-09-25
Publication date: 2007-11-14
Anticipated expiration: 2022-09-25
Also published as: JP2004134413A

Description

【０００１】
【発明の属する技術分野】
本発明は、ＦＥＴ等の半導体素子を収納するための半導体素子収納用パッケージおよび半導体装置に関する。
【０００２】
【従来の技術】
従来、マイクロ波帯域やミリ波帯域の高周波信号により作動するＦＥＴ（Field Effect Transistor：電界効果型トランジスタ）等の半導体素子を収納するための半導体素子収納用パッケージ（以下、半導体パッケージともいう）には、大電力を入力したり、半導体素子と外部電気回路との高周波信号の入出力を行うための入出力端子が設けられている。この半導体パッケージの斜視図を図４に示し、半導体パッケージに用いられる入出力端子の斜視図を図５に示す。
【０００３】
入出力端子103は、略長方形の平板部103ａの上面に略直方体の立壁部103ｂが積層されて成り、一般的にセラミックグリーンシート積層法によって多数個取りの手法を用いて作製され、半導体素子109と外部電気回路（図示せず）との高周波信号の入出力を行う機能を有するとともに、半導体パッケージの内外を気密に遮断している。
【０００４】
入出力端子103の平板部103ａは、アルミナ（Ａｌ₂Ｏ₃）質焼結体，窒化アルミニウム（ＡｌＮ）質焼結体，ムライト（３Ａｌ₂Ｏ₃・２ＳｉＯ₂）質焼結体等の焼結体（セラミックス）から成り、その上面に、一辺から立壁部103ｂを挟んで対向する他辺にかけて、タングステン（Ｗ），モリブデン（Ｍｏ）−マンガン（Ｍｎ）等のメタライズ層から成る線路導体103ａ−Ａ、および同一面接地導体103ａ−Ｂが形成される。平板部103ａの下面には、その略全面に線路導体103ａ−Ａと同様のメタライズ層から成る下部接地導体103ａ−Ｃが形成され、また線路導体103ａ−Ａと略平行な両側面には、その中央部に線路導体103ａ−Ａと同様のメタライズ層から成る側部接地導体103ａ−Ｄが形成されている。
【０００５】
メタライズ層から成る線路導体103ａ−Ａ，同一面接地導体103ａ−Ｂ，下部接地導体103ａ−Ｃ，側部接地導体103ａ−Ｄは、Ｗ，Ｍｏ−Ｍｎ等から成る。例えば、Ｗから成る場合、Ｗの粉末を主成分として有機溶剤、溶媒を添加混練して得た金属ペーストを、平板部103ａ用のセラミックグリーンシートに予め従来周知のスクリーン印刷法により所定パターンに印刷塗布しておき、これを焼成することにより形成される。
【０００６】
一方、立壁部103ｂは、平板部103ａと同様のセラミックスから成り、その上面の略全面に線路導体103ａ−Ａと同様のメタライズ層から成る上部接地導体103ｂ−Ａが形成される。また、平板部103ａの線路導体103ａ−Ａに略平行な両側面に略面一な立壁部103ｂの両側面（両端面）には、その略全面に線路導体103ａ−Ａと同様のメタライズ層から成る側部接地導体103ｂ−Ｄが、側部接地導体103ａ−Ｄに連続して形成される。
【０００７】
メタライズ層から成る上部接地導体103ｂ−Ａ，側部接地導体103ｂ−Ｄは、平板部103ａに形成される線路導体103ａ−Ａ等と同様の方法によりセラミックグリーンシートの積層体に所定パターンで印刷塗布しておき、焼成することにより形成される。
【０００８】
この半導体パッケージは、基体101と、その上面に接合された枠体102と、枠体102の側部に嵌着された入出力端子103と、枠体102上面に接合されたシールリング106（図６）とを具備している。基体101は、半導体素子109を載置する載置部101ａを有し、半導体素子109の作動時に発する熱を外部に効率よく放散するための銅（Ｃｕ）等の金属または銅−タングステン（Ｗ）等の複合金属材料から成る。枠体102は、基体101上面の外周部に載置部101ａを囲繞するように銀ロウ等のロウ材で接合され、側部に入出力端子103を嵌着する取付部102ａが形成されたものであり、Ｆｅ−Ｎｉ−Ｃｏ合金やＦｅ−Ｎｉ合金等の金属から成る。
【０００９】
入出力端子103の線路導体103ａ−Ａに略平行な側面のメタライズ層は、立壁部103ｂの両側面の略全面に形成された側部接地導体103ｂ−Ｄと、平板部103ａの両側面の中央部に形成された側部接地導体103ａ−Ｄとから成る。この側面のメタライズ層が入出力端子103の側面の中央部に形成されているとともに、平板部103ａの上面の両端に位置する同一面接地導体103ａ−Ｂと側面のメタライズ層とが電気的に接続されていることにより、同一面接地導体103ａ−Ｂによる接地が充分なものとなり、いわゆるコプレナー構造を形成する。そして、このコプレナー構造により線路導体103ａ−Ａにおける高周波の伝送特性が良好なものとなる。具体的にはノイズの影響が少ない高周波の伝送が可能となる。
【００１０】
また、リード端子104は、線路導体103ａ−Ａの枠体102外側の部位に銀ロウ等のロウ材を介して接合され、外部電気回路と入出力端子103との高周波信号の入出力を行うものであり、Ｆｅ−Ｎｉ−Ｃｏ合金等の金属から成る。シールリング106は、枠体102上面に銀ロウ等のロウ材で接合され、その上面に蓋体（図示せず）をシーム溶接等により接合するための接合媒体として機能する（例えば、下記の特許文献１参照）。
【００１１】
そして、入出力端子103に半導体素子109を電気的に接続して半導体パッケージ内に半導体素子109を収容するに際して、コンデンサやコイルなどの電子部品を半導体パッケージ内に設置することが近年頻繁に行なわれている。このとき、電子部品との位置関係から半導体素子109と入出力端子103との距離が大きくならざるを得ないことが多く、例えば、図５に示すように上面に接続用配線105ｂを有する中継基板Ｂを半導体素子109と入出力端子103との間に配設する構成とする。その際、ボンディングワイヤワイヤ105ｃによって、半導体素子109と接続用配線105ｂとの間、接続用配線105ｂと入出力端子103との間が電気的に接続される。
【００１２】
このような半導体パッケージに、半導体素子109を載置部101ａに錫（Ｓｎ）−鉛（Ｐｂ）半田等の低融点ロウ材で載置固定するとともに、線路導体103ａ−Ａと半導体素子109とを中継基板105を介して、ボンディングワイヤ105ｃで電気的に接続し、次にシールリング106上面に蓋体をシーム溶接等により接合することにより、製品としての半導体装置となる。この半導体装置は、例えば半導体素子109がＦＥＴであれば、外部電気回路から供給される電力により半導体素子109を作動させて外部から入力される大容量の情報を高速で処理し外部に出力するものであり、通信分野に多用されている。
【００１３】
【特許文献１】
特開平10−242716号公報（第７−９頁、図１）
【００１４】
【発明が解決しようとする課題】
しかしながら、上記従来の半導体パッケージにおいては、図６に示すように、半導体素子109から出力される高周波信号等の電気信号を外部電気回路装置に伝送するには、電気信号はボンディングワイヤ105ｃ、中継基板Ｂ上面の接続用配線105ｂ、ボンディングワイヤ105ｃおよび入出力端子103を介して伝送されるため、中継基板Ｂがない従来の半導体パッケージに比して伝送経路において約２倍以上のインダクタンスが生じてしまうという問題点があった。また、その結果、高周波信号の伝送損失が発生したり、ボンディングワイヤ105ｃがコイルとして作用して、ボンディングワイヤ105ｃから高周波信号が電磁波として漏れたり、外部からのノイズがボンディングワイヤ105ｃに入り込んでノイズが増加するといった不具合が発生していた。
【００１５】
そこで、入出力端子103の平板部103ａを枠体102内側に延出させて、その延出部に半導体素子109からの電気信号を伝送するボンディングワイヤ105ｃを直接接続することによって、中継基板105を不要とし、ワイヤボンディング105ｃの長さを略１／２とすることが考えられる。しかしながら、平板部103ａの枠体102内側の部位を延出させない場合の３倍以上に長くすると、平板部103ａの下面に形成している下部接地導体103ａ−Ｃの収縮率や収縮開始のタイミングなどの収縮挙動と平板部103ａを構成する絶縁体の収縮挙動との差により、入出力端子３の平板部３ａに上に凸の反りや下に凸の反りが発生し、そのため入出力端子103の接合不良やそれに起因するボンディングワイヤ105ｃの接続不良が発生していた。すなわち、下部接地導体103ａ−Ｃと略同じ面積で略同じ厚さの導体が、平板部103ａの厚さ方向の中心に対して略対称の位置（平板部103ａの内部や上面）に形成されていれば、問題が生じることがないが、そのように構成することは高周波の伝送特性上非常に困難である。
【００１６】
従って、本発明は上記従来の問題点に鑑み完成されたものであり、その目的は、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良を有効に防止して、入出力端子の平板部を半導体パッケージの内側方向に延出させた構成とするとともに中継基板を不要とすることである。また、その結果、入出力端子に半導体素子からの信号を伝送するワイヤを直接的に接続できるようにして、半導体素子から伝送される高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることである。さらに、半導体パッケージを小型化することにより高周波信号の電磁波の共振点が低下するのを防ぎ、その結果、半導体パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることである。さらに、中継基板を不要とすることにより製造工程を少なくし、効率的に製造できるものとすることである。
【００１７】
【課題を解決するための手段】
本発明は、同一面接地導体に関して、平板部と立壁部との積層領域、および、平板部と延出部との積層領域において、非形成部が設けられているものである。
【００１８】
本発明の半導体素子収納用パッケージは、入出力端子は、平板部の線路導体に平行な方向における枠体内側の部位の長さが枠体外側の部位の長さの３倍以上とされており、立壁部の両端部に枠体内側に延出する延出部が幅方向で線路導体に達しないようにしてそれぞれ形成されていることから、平板部における反りの発生が延出部により抑えられ、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良が有効に防止される。また中継基板が不要となるため、半導体素子からの電気信号を伝送するボンディングワイヤを入出力端子の線路導体に直接的に接続でき、半導体素子から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることができる。さらに、半導体素子収納用パッケージが小型化されることにより、高周波信号の電磁波の共振点が低下するのを防ぐことができ、その結果、半導体素子収納用パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることができる。さらに、中継基板が不要となることにより製造工程が少なくなり、効率的に製造できることとなる。
【００１９】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記延出部は、その幅が前記平板部の上面の前記線路導体に直交する方向の長さの１／６倍乃至１／４倍とされていることを特徴とする。
【００２０】
本発明の半導体素子収納用パッケージは、延出部はその幅が平板部の上面の線路導体に直交する方向の長さの１／６倍乃至１／４倍とされていることから、入出力端子の平板部に反りが発生するのをより有効に防止することができる。その結果、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良がより有効に防止される。
【００２１】
本発明の半導体素子収納用パッケージにおいて、好ましくは、前記平板部の上面で前記線路導体の両側に略等間隔をもって同一面接地導体が形成されており、該同一面接地導体は、前記平板部と前記立壁部との前記線路導体に略平行な側面における境界線に沿って導体非形成部が設けられている。
【００２２】
本発明の半導体素子収納用パッケージは、同一面接地導体は平板部と立壁部との線路導体に略平行な側面における境界線に沿って導体非形成部が形成されていることから、平板部と立壁部との接合面において特に剥離が生じ易い端部で、平板部と立壁部とが同一面接地導体を介することなく密着されるため、接合強度が大きくなって平板部と立壁部との間で剥離が生じ難いものとすることができる。
【００２３】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、前記載置部に載置固定されるとともに前記入出力端子に電気的に接続された半導体素子と、前記枠体の上面に接合された蓋体とを具備したことを特徴とする。
【００２４】
本発明の半導体装置は、上記の構成により、高周波信号の伝送特性が良好であり半導体素子が長期に亘って安定に作動する、高性能で信頼性の高いものとなる。
【００２５】
【発明の実施の形態】
参考例の半導体素子収納用パッケージを以下に詳細に説明する。図１は参考例の半導体パッケージについて実施の形態の例を示す斜視図、図２は図１の入出力端子の斜視図、図３（ａ）は本発明の半導体パッケージについて実施の形態の他の例を示す入出力端子の透視斜視図、図３（ｂ）は図３（ａ）の要部拡大透視斜視図である。
【００２６】
図１〜図３において、１は基体、１ａは載置部、２は枠体、２ａは入出力端子３の取付部、３は入出力端子、３ａは入出力端子３の平板部、３ａ−Ａは線路導体、３ａ−Ｂは同一面接地導体、３ａ−Ｃは下部接地導体、３ａ−Ｄは側部接地導体、３ｂは立壁部、３ｂ−Ａは上部接地導体、３ｂ−Ｄは側部接地導体、Ａは立壁部３ｂの両端部、４はリード端子、５は立壁部３ｂの延出部、５ａは延出部５の端面、６はシールリングである。これら基体１と枠体２と入出力端子３とシールリング６とで、内部にＦＥＴ等の半導体素子９を収納するための半導体パッケージが基本的に構成される。また、半導体パッケージ内に半導体素子９を収容してシールリング６の上面に蓋体（図示せず）を取着することにより半導体装置となる。
【００２７】
本発明の半導体パッケージは、上側主面に半導体素子９が載置される載置部１ａを有する基体１と、基体１の上側主面に載置部１ａを囲繞するように取着された金属製の枠体２と、枠体２の側部に形成された貫通孔または切欠きから成る入出力端子３の取付部２ａと、上面に一辺から対向する他辺にかけて線路導体３ａ−Ａを有する略四角形の誘電体から成る平板部３ａおよび平板部３ａの上面に線路導体３ａ−Ａの一部を間に挟んで接合された誘電体から成る立壁部３ｂを有する、取付部２ａに嵌着された入出力端子３とを具備した基本構成である。
【００２８】
本発明の基体１は、上側主面に半導体素子９を載置する載置部１ａを有し、半導体素子９を支持する支持部材として機能するとともに、半導体素子９の熱を外部に効率良く放散する機能を有する。この基体１は、その形状は略長方形の平板状であり、Ｆｅ−Ｎｉ−Ｃｏ合金やＣｕ−Ｗ等の金属、アルミナ，窒化アルミニウム，ムライト等のセラミックスから成る。金属から成る場合、例えば、Ｆｅ−Ｎｉ−Ｃｏ合金のインゴット（塊）に圧延加工や打ち抜き加工等の従来周知の金属加工法を施すことによって所定形状に製作される。また、セラミックスから成る場合、その原料粉末に適当な有機バインダや溶剤等を添加混合しスラリー状と成し、このスラリーをドクターブレード法やカレンダーロール法などの成形法によってセラミックグリーンシートと成し、しかる後、セラミックグリーンシートに適当な打ち抜き加工を施し、これを複数枚積層し焼成することによって作製される。
【００２９】
なお、基体１が金属からなる場合、その表面に耐蝕性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ0.5〜９μｍのＮｉ層と、厚さ0.5〜５μｍのＡｕ層を順次メッキ法により被着させておくのがよく、基体１が酸化腐蝕するのを有効に防止できるとともに、基体１の載置部１ａに半導体素子９を強固に接着固定させることができる。また、基体１がセラミックスから成る場合、載置部１ａに耐蝕性に優れかつロウ材との濡れ性に優れる金属、具体的には厚さ0.5〜９μｍのＮｉ層と厚さ0.5〜５μｍのＡｕ層を順次メッキ法により被着させておくのがよく、基体１の上側主面の載置部１ａに半導体素子９を強固に接着固定させることができる。
【００３０】
また、基体１の上側主面には、載置部１ａを囲繞するように、側部に入出力端子３を嵌着するための貫通孔または切欠きから成る取付部２ａが形成された枠体２が銀ロウ等のロウ材で接合されており、枠体２の内側に半導体素子９を収納するための空所が形成される。この枠体２は、基体１と同様の金属から成り、箱状体の側壁を成すものであり、その製作は基体１と同様の加工法により、側部に取付部２ａを有する形状に加工される。
【００３１】
なお、枠体２の基体１への接合は、基体１の上側主面と枠体２の下面とを、基体１の上側主面に敷設した適度なボリュームを有するプリフォームとされた銀ロウ等のロウ材を介して接合される。さらに、枠体２の表面には、基体１と同様に厚さ0.5〜９μｍのＮｉ層や厚さ0.5〜５μｍのＡｕ層等の金属層をメッキ法により被着させておくと良い。
【００３２】
また、枠体２の取付部２ａには、半導体素子９と外部電気回路との高周波信号の入出力を行うとともに半導体パッケージの内外を気密に遮断する入出力端子３が、その周囲に設けられているメタライズ層（上部接地導体３ｂ−Ａ、側部接地導体３ａ−Ｄ，３ｂ−Ｄ、下部接地導体３ａ−Ｃ）を介して銀ロウ等のロウ材で接合される。この入出力端子３は、略長方形等の略四角形の平板部３ａの上面に、横倒しにされた四角柱状の立壁部３ｂが積層されて成る。
【００３３】
入出力端子３の平板部３ａおよび立壁部３ｂは、アルミナ，窒化アルミニウム，ムライト等のセラミックスから成る。そして、平板部３ａの上面には、１辺から対向する他辺にかけて、Ｗ，Ｍｏ−Ｍｎ等のメタライズ層から成る線路導体３ａ−Ａが形成され、好ましくは線路導体３ａ−Ａの両側に略等間隔をもって上記メタライズ層から成る同一面接地導体３ａ−Ｂが形成される。これにより、線路導体３ａ−Ａに対する接地が充分なものとなり、いわゆるコプレナー構造を形成するため、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。また、平板部３ａの下面の略全面には、線路導体３ａ−Ａと同様のメタライズ層から成る下部接地導体３ａ−Ｃが形成される。
【００３４】
なお、同一面接地導体３ａ−Ｂは、平板部３ａの上面の端（辺）に接するように形成されているのがよい。これにより、線路導体３ａ−Ａに対する接地が良好となり、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。また、図３（ａ），（ｂ）に示すように、平板部３ａと立壁部３ｂとの線路導体３ａ−Ａに略平行な側面における境界線に沿って導体非形成部３ｃが設けられていてもよい。これにより、平板部３ａと立壁部３ｂとの接合面において特に剥離が生じ易い端部で、平板部３ａと立壁部３ｂとが同一面接地導体３ａ−Ｂを介することなく密着されるため、接合強度が大きくなって平板部３ａと立壁部３ｂとの間で剥離が生じ難いものとすることができる。
【００３５】
導体非形成部３ｃは、同一面接地導体３ａ−Ｂの幅に対して１／３倍乃至２／３倍の幅とされているのがよい。１／３倍未満であれば、導体非形成部３ｃにおいて平板部３ａと立壁部３ｂとが同一面接地導体３ａ−Ｂを介することなく接合される部分の面積が小さくなって平板部３ａと立壁部３ｂとの間で剥離が生じ易くなり、立壁部３ｂが平板部３ａの反りを抑制する効果が低下し易くなる。また、２／３倍を超えると、同一面接地導体３ａ−Ｂの面積が小さくなって線路導体３ａ−Ａに対する接地が不十分となり、線路導体３ａ−Ａにおける高周波信号（５ＧＨｚ以上）の伝送特性が低下し易くなる。
【００３６】
また、導体非形成部３ｃは、図３（ｂ）に示すように、同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続する細い線路状の接続部３ｃ−Ａが導体非形成部３ｃを横切るように形成されていてもよい。これにより、平板部３ａと立壁部３ｂとの接合強度を維持することができるとともに、同一面接地導体３ａ−Ｂの接地性を向上させることができる。
【００３７】
接続部３ｃ−Ａは、幅が0.2〜0.5ｍｍとされているのがよい。0.2ｍｍ未満であると、接続部３ｃ−Ａの抵抗が大きくなり、同一面接地導体３ａ−Ｂの接地性の向上は見込めない。また、0.5ｍｍを超えると、導体を介しての平板部３ａと立壁部３ｂとの接合面積が大きくなるために平板部３ａと立壁部３ｂとの接合強度が低下して平板部３ａと立壁部３ｂとが剥離し易くなる。
【００３８】
また、接続部３ｃ−Ａは、合計の面積が導体非形成部３ｃの面積の0.15〜0.4倍とされているのがよい。0.15倍未満であると、接続部３ｃ−Ａの抵抗が大きくなり、同一面接地導体３ａ−Ｂの接地性の向上は見込めない。また、0.4倍を超えると、平板部３ａと立壁部３ｂとの間においてセラミック同士の接合面積が充分に確保できなくなり、その為に接合強度が低下して平板部３ａと立壁部３ｂとが剥離し易くなる。
【００３９】
平板部３ａの線路導体３ａ−Ａ、同一面接地導体３ａ−Ｂ、下部接地導体３ａ−Ｃ、側部接地導体３ａ−Ｄ、および接続部３ｃ−ＡはＷ，Ｍｏ−Ｍｎ等のメタライズ層から成る。例えばＷからなる場合、Ｗ粉末を主成分とする金属粉末に有機溶剤、溶媒を添加混合して得た金属ペーストを、平板部３ａ形成用のセラミックグリーンシートに、予め従来周知のスクリーン印刷法により所定パターンに印刷塗布しておき、焼成することによって形成される。
【００４０】
また、平板部３ａの上面には立壁部３ｂが積層される。この立壁部３ｂは、平板部３ａと同様のセラミックスから成り、その上面の延出部５を除く略全面に線路導体３ａ−Ａと同様のメタライズ層から成る上部接地導体３ｂ−Ａが形成され、また側面には側部接地導体３ｂ−Ｄが形成される。さらに、立壁部３ｂの上部接地導体３ｂ−Ａ、側部接地導体３ｂ−Ｄは、平板部３ａに形成される下部接地導体３ａ−Ｃの形成と同様の方法により所定パターンに印刷塗布しておき、焼成することにより形成される。
【００４１】
本発明においては、図３（ａ）に示すように、入出力端子３は、平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位の長さが枠体２外側の部位の長さの３倍以上とされており、立壁部３ｂの両端部Ａに枠体２内側に延出する延出部５が幅方向で線路導体３ａ−Ａに達しないようにしてそれぞれ形成されている。延出部５は平板部３ａの上面との間に同一面接地導体３ａ−Ｂを挟持するようにして形成される。このとき、延出部５は、同一面接地導体３ａ−Ｂの幅方向で全面を覆っていてもよく、または幅方向で同一面接地導体３ａ−Ｂの一部が露出していてもよく、いずれの場合でも線路導体３ａ−Ａにおける高周波信号の伝送特性に変わりがないことが確認された。
【００４２】
また、平板部３ａの線路導体３ａ−Ａに略平行な側面からその側面に略面一な立壁部３ｂの側面にかけて、メタライズ層（側部接地導体３ａ−Ｄ，側部接地導体３ｂ−Ｄ）が同一面接地導体３ａ−Ｂや下部接地導体３ａ−Ｃおよび上部接地導体３ｂ−Ａと電気的に接続されて形成される。側部接地導体３ａ−Ｄは、図２に示すように、同一面接地導体３ａ−Ｂが平板部３ａの上面の端（辺）に接するように形成されている場合、側部接地導体３ｂ−Ｄと略同じ幅で側部接地導体３ｂ−Ｄに連続して形成されるのがよい。これにより、入出力端子３を取付部２ａに嵌着させるに際してロウ材の連続したメニスカスの形成を促し、入出力端子３と取付部２ａとの接着性が向上して、気密性の良い構造とすることができる。また、側部接地導体３ａ−Ｄは、図３（ａ），（ｂ）に示すように、導体非形成部３ｃが平板部３ａと立壁部３ｂとの線路導体３ａ−Ａに略平行な側面における境界線に沿って形成されている場合、平板部３ａの線路導体３ａ−Ａに略平行な側面全面に形成されていてもよい。これにより、同一面接地導体３ａ−Ｂに導体非形成部３ｃが形成されていても同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続することができ、線路導体３ａ−Ａに対する接地が良好となり、線路導体３ａ−Ａにおける高周波信号の伝送特性が向上する。
【００４３】
以上の構成により、入出力端子３の平板部３ａの焼成時において発生する反りを抑制することができ、ワイヤボンディングの接続不良が発生するのを有効に防止できる。また、製造工程において同一面接地導体３ａ−Ｂとなる金属ペーストの印刷層にニジミが発生しても、延出部５によりニジミの広がりが抑制され、線路導体３ａ−Ａと同一面接地導体３ａ−Ｂとの間が短絡することが抑えられる。
【００４４】
また、延出部５の側面においては、浮遊容量の増大を極力少なくするため、立壁部３ｂにおける側部接地導体層３ｂ−Ｄは、延出部５の側面側へ0.25〜0.3ｍｍ程度延出して形成されていてもよい。このように側部接地導体３ｂ−Ｄを延出部５の側面側へ延出しておくと、入出力端子３を取付部２ａに嵌着させるに際してロウ材によるメニスカスの形成を促すことを可能として、信頼性の良い構造を実現するとともに、浮遊容量の増大がほとんどないようにできる。
【００４５】
本発明において、平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位の長さが枠体２外側の部位の長さの３倍以上とされており、これにより、平板部３ａの枠体２内側の部位に中継基板が不要となるため、入出力端子３に直接的に半導体素子９を電気的に接続できる。その結果、半導体素子９から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、高周波信号の伝送特性を良好なものとできる。
【００４６】
平板部３ａの線路導体３ａ−Ａに平行な方向における枠体２内側の部位３ａａ（図２）の長さが枠体２外側の部位３ａｂ（図２）の長さの３倍未満の場合、平板部３ａに大きな反りがほとんど発生することがなく、延出部５は不要となるが、入出力端子３に接近させて半導体素子９を搭載することが困難となり、中継基板が必要になる。
【００４７】
３倍を超える場合、立壁部３ｂに延出部５がないと、平板部３ａに少なからず反りが発生し、ときには反りが20μｍを超える場合がある。この場合、入出力端子３を取付部２ａに嵌着するに際してロウ材の厚みにバラツキが発生し、入出力端子３が傾いた状態で取付部２ａに嵌着される。その結果、線路導体３ａ−Ａの枠体２内側の部位にワイヤボンディングした時にその接続不良を誘発させることとなる。しかし、本発明のように、３倍を超える場合に立壁部３ｂに延出部５があると、平板部３ａの反りは大幅に抑制され、その結果、中継基板が不要となる。
【００４８】
本発明において、延出部５は、その幅をｂ（ｍｍ）、平板部３ａの上面の線路導体３ａ−Ａに直交する方向の長さをａ（ｍｍ）としたとき、ａ／６≦ｂ≦ａ／４であることが好ましい。ｂ＜ａ／６であると、平板部３ａの反りを抑制する効果が低下するとともに、同一面接地導体３ａ−Ｂとなる金属ペーストをセラミックグリーンシートに印刷する際に発生するニジミが広がるのを延出部５で抑えることが困難になり、線路導体３ａ−Ａと同一面接地導体３ａ−Ｂとが短絡し易くなる。ｂ＞ａ／４となると、平板部３ａの反りを抑制する効果は十分であるが、線路導体３ａ−Ａの幅を所望の大きさとすることが困難となって抵抗が増大し、高周波信号の伝送遅延や反射が発生し、また大電流の入力用として用いた場合には発熱し易くなる。
【００４９】
また、延出部５の線路導体３ａ−Ａに平行な方向の長さは、平板部３ａの部位３ａａの長さの１／２〜３／４であることが好ましい。１／２未満では、平板部３ａの反りを抑えることが困難になる。３／４を超えると、延出部５が障害になって線路導体３ａ−Ａや同一面接地導体３ａ−Ｂにボンディングワイヤを接続することが困難になる。
【００５０】
また、図２，図３（ａ），（ｂ）に示すように、同一面接地導体３ａ−Ｂは、延出部５に覆われていない露出した部位の長さは延出部５の端面５ａから0.5ｍｍ以上、好ましくは0.75ｍｍ以上あれば良く、この長さがあれば半導体素子９へのボンディングワイヤを介しての電気的接続が容易となる。
【００５１】
このような半導体パッケージは、半導体素子９を載置部１ａにＳｎ−Ｐｂ半田等の低融点ロウ材で載置固定するとともに、線路導体３ａ−Ａ、同一面接地導体３ａ−Ｂと半導体素子９とをボンディングワイヤで電気的に接続し、シールリング６上面にＦｅ−Ｎｉ−Ｃｏ合金等から成る蓋体（図示せず）をシーム溶接等により接合することにより、製品としての半導体装置となる。この半導体装置は、例えば外部電気回路から供給される高周波信号等の駆動信号によって半導体素子９を作動させ、大容量の情報を高速に伝送する、通信基地局などの通信装置等に用いられる。
【００５２】
【実施例】
本発明の半導体素子収納用パッケージの実施例を以下に説明する。
【００５３】
（参考例１）
まず、立壁部３ｂに延出部５がない従来構成の入出力端子３のサンプルとして、外形寸法が縦４〜７ｍｍ×横４ｍｍ×厚さ１ｍｍでありアルミナセラミックスから成る平板部３ａと、外形寸法が縦１ｍｍ×横４ｍｍ×厚さ１ｍｍでありアルミナセラミックスから成る立壁部３ｂとを有し、厚さ15μｍで幅が１ｍｍのＷから成る線路導体３ａ−Ａ、線路導体３ａ−Ａと同じ厚さおよび幅のＷから成る同一面接地導体３ａ−Ｂ、厚さ15μｍのＷから成る下部接地導体３ａ−Ｃ、厚さ15μｍのＭｏ−Ｍｎから成る側部接地導体３ａ−Ｄ、厚さ15μｍのＷから成る上部接地導体３ｂ−Ａ、厚さ15μｍのＭｏ−Ｍｎから成る側部接地導体３ｂ−Ｄを形成して成る入出力端子３を作製した。このとき、平板部３ａの枠体２外側の部位３ａｂの長さを１ｍｍとし、平板部３ａの枠体２内側の部位３ａａの長さを部位３ａｂの２，2.5，３，3.5，４，５（倍）とした６種の入出力端子３を各５個ずつ作製した。
【００５４】
また、参考例の入出力端子３のサンプルとして、上記６種の入出力端子３において、立壁部３ｂに延出部５を設け、延出部５の幅を0.8ｍｍとし、延出部５の
端面５ａが平板部３ａの線路方向の端から0.5ｍｍの位置に位置するようにして
作製した入出力端子３を各５個用意した。
【００５５】
これらのサンプルについて、平板部３ａの反り（平均値）、ボンディングワイヤの接続状態を評価した。平板部３ａの反りは、平板部３ａの下面の対角線に沿って表面粗さ計で測定した。ボンディングワイヤの接続状態は、接続不可のものや接続不良のもの（傾いた状態で接続されたもの等）がないか調べた。その結果を表1に示す。
【００５６】
なお、表１において、Ｌrは、平板部３ａの部位３ａｂに対する部位３ａａの比（倍）を示す。
【００５７】
【表１】

【００５８】
表1より、比較例のサンプルでは、平板部３ａの部位３ａｂの長さに対して部位３ａａの長さが３倍以上になると、平板部３ａの反りが大きくなってボンディングワイヤの接続不良が発生した。これに対し、参考例のサンプルでは、平板部３ａの反りが抑制され、ボンディングワイヤの接続状態が大幅に改善されることが判った。また、参考例のサンプルでは、平板部３ａにボンディングワイヤを介して半導体素子９を直接電気的に接続することができ、中継基板が不要となった。
【００５９】
（参考例２）
次に、平板部３ａの部位３ａａの長さを４ｍｍ、部位３ａｂの長さを１ｍｍとし、延出部５の幅を0.4，0.5，0.6，0.67，0.8，0.9，１，1.1，1.2（ｍｍ）と
した９種のサンプルを各５個合計45個作製して、平板部３ａの反り（平均値）、ボンディングワイヤの接続状態を評価した。平板部３ａの反りの大きさは平均値が15μｍ未満を良好とし、15μｍを超える場合を不良とした。評価結果を表２に示す。
【００６０】
【表２】

【００６１】
表２より、参考例のサンプルは、平板部３ａの部位３ａａの長さを部位３ａｂの長さの４倍と長くしても、立壁部３ｂの延出部５の幅を平板部３ａの上面の横の長さ（線路導体３ａ−Ａに直交する方向の長さ）４ｍｍの１／６倍（0.67ｍｍ）以上とすることにより、平板部３ａの反りを小さくできることが明らかになった。また、延出部５の幅が平板部３ａの上面の横の長さの１／４倍（１ｍｍ）を超えると、キャピラリが延出部５に接触してワイヤボンディングが実施できない場合が発生した。そのため、入出力端子３全体を大きくすることとなり、その場合には半導体パッケージが大型化するという不具合を招来した。
【００６２】
（実施例３）
次に、実施例１で用いた平板部３ａの枠体２内側の部位３ａａの長さが部位３ａｂの２，2.5，３，3.5，４，５（倍）であるとともに、幅が0.8ｍｍで端面５ａが平板部３ａの線路方向の端から0.7ｍｍの位置に位置する延出部５が形成されたサンプルと、新たにこれらの同一面接地導体３ａ−Ｂに導体非形成部３ｃを長さが1.7，2.2，2.7，3.2，3.7，4.7（ｍｍ）であり、幅が0.5ｍｍとなるように作製したサンプルとを各５個用意した。
【００６３】
これらのサンプルについて、−65〜125℃の温度サイクル試験を10サイクル（１サイクル60分）実施した後、金属顕微鏡を用いて40倍に拡大してサンプルを観察することにより延出部５と平板部３ａとの界面における剥離（デラミネーション）の発生率を求め、延出部５と平板部３ａとの接着性の評価をした。これらの評価結果を表３に示す。
【００６４】
【表３】

【００６５】
表３より、導体非形成部３ｃを形成していないサンプルでは、平板部３ａの部位３ａａの長さが部位３ａｂの長さの３倍以上となるとデラミネーションが発生した。これに対し、導体非形成部３ｃを形成したサンプルでは、平板部３ａの部位３ａａの長さが部位３ａｂの長さの５倍でもデラミネーションが発生することなく優れていることが判った。
【００６６】
（実施例４）
次に、実施例２で用いた平板部３ａの部位３ａａの長さが４ｍｍ、部位３ａｂの長さが１ｍｍであるとともに、延出部５の幅が0.4，0.5，0.6，0.67，0.8，0.9，１，1.1，1.2（ｍｍ）であるサンプルと、新たにこれらの同一面接地導体３ａ−Ｂに導体非形成部３ｃを長さが3.3ｍｍであり、幅が0.5ｍｍとなるように作製したサンプルとを各５個用意した。
【００６７】
これらのサンプルについて、−65〜125℃の温度サイクル試験を10サイクル（１サイクル60分）実施した後、金属顕微鏡を用いて40倍に拡大してサンプルを観察することにより延出部５と平板部３ａとの界面における剥離（デラミネーション）の発生率を求め、延出部５と平板部３ａとの接着性の評価をした。これらの評価結果を表４に示す。
【００６８】
【表４】

【００６９】
表４より、導体非形成部３ｃを形成していないサンプルでは、延出部５の幅が平板部３ａの上面の横の長さの１／４倍（１ｍｍ）未満となるとデラミネーションが発生率した。これに対し、導体非形成部３ｃを形成したサンプルでは、延出部５の幅が平板部３ａの上面の横の長さの１／10倍（0.4ｍｍ）でもデラミネーションが発生することなく優れていることが判った。
【００７０】
（実施例５）
次に、実施例３で用いた導体非形成部３ｃの長さが1.7，2.2，2.7，3.2，3.7，4.7（ｍｍ）であり幅が0.5ｍｍのサンプルと、新たにこれらの導体非形成部３ｃに、同一面接地導体３ａ−Ｂと側部接地導体３ａ−Ｄとを電気的に接続する幅が0.3ｍｍの接続導体３ｃ−Ａを150μｍの間隔を開けて導体非形成部３ｃを横切るように３本設けたサンプルとを各５個用意した。
【００７１】
これらのサンプルについて、ＦＥＴ（Field Effect Transistor）を半導体パッケージ内に実装し、５ＧＨｚの高周波信号を伝送させた際の入出力端子３における高周波信号の反射損失をネットワークアナライザーを用いて測定することにより、高周波信号の伝送性を評価した。これらの評価結果を表５に示す。
【００７２】
【表５】

【００７３】
表５より、導体非形成部３ｃに接続部３ｃ−Ａを設けていないサンプルでは、伝送損失が−22ｄＢ以上と大きくなった。これに対し、導体非形成部３ｃに接続部３ｃ−Ａを設けたサンプルでは、−23ｄＢ以下と小さく優れていることが判った。
【００７４】
なお、本発明は上記実施の形態および実施例に限定されるものではなく、本発明の要旨を逸脱しない範囲内であれば種々の変更を施すことは何等差し支えない。例えば、半導体素子９が半導体レーザ（ＬＤ），フォトダイオード（ＰＤ）等の光半導体素子である場合においても本発明の効果は同様であり、その場合は枠体２に光ファイバ取着用の貫通孔を設ければ良い。
【００７５】
【発明の効果】
本発明の半導体素子収納用パッケージは、上側主面に半導体素子が載置される載置部を有する基体と、基体の上側主面に載置部を囲繞するように取着された金属製の枠体と、枠体の側部に形成された貫通孔または切欠きから成る入出力端子の取付部と、上面に一辺から対向する他辺にかけて形成された線路導体を有する略四角形の誘電体から成る平板部および平板部の上面に線路導体の一部を間に挟んで接合された誘電体から成る立壁部を有する、取付部に嵌着された入出力端子とを具備し、入出力端子は、平板部の線路導体に平行な方向における枠体内側の部位の長さが枠体外側の部位の長さの３倍以上とされており、立壁部の両端部に枠体内側に延出する延出部が幅方向で線路導体に達しないようにしてそれぞれ形成されていることにより、平板部における反りの発生が延出部により抑えられ、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良が有効に防止される。また中継基板が不要となるため、入出力端子に直接的に半導体素子を電気的に接続でき、半導体素子から出力された高周波信号の伝送経路において大きなインダクタンスが発生せず、よって高周波信号の伝送特性を良好なものとすることができる。さらに、半導体素子収納用パッケージが小型化されることにより、高周波信号の電磁波の共振点が低下するのを防ぐことができ、その結果、半導体素子収納用パッケージ内部に収容する半導体素子を長期に亘り正常かつ安定に作動させることができる。さらに、中継基板が不要となることにより製造工程が少なくなり、効率的に製造できることとなる。
【００７６】
本発明の半導体素子収納用パッケージは、好ましくは、延出部はその幅が平板部の上面の線路導体に直交する方向の長さの１／６倍〜１／４倍とされていることにより、入出力端子の平板部に反りが発生するのをより有効に防止することができる。その結果、平板部の反りによる入出力端子の枠体に対する接合不良やワイヤボンディングの接続不良がより有効に防止される。
【００７７】
本発明の半導体素子収納用パッケージは、同一面接地導体は平板部と立壁部との線路導体に略平行な側面における境界線に沿って導体非形成部が設けられていることから、平板部と立壁部との接合面において特に剥離が生じ易い端部で、平板部と立壁部とが同一面接地導体を介することなく接着されるため、接合強度が大きくなって平板部と立壁部との間で剥離が生じ難いものとすることができる。
【００７８】
本発明の半導体装置は、上記本発明の半導体素子収納用パッケージと、載置部に載置固定されるとともに入出力端子に電気的に接続された半導体素子と、枠体の上面に接合された蓋体とを具備したことにより、高周波信号の伝送特性が良好であり半導体素子が長期に亘って安定に作動する、高性能で信頼性の高いものとなる。
【図面の簡単な説明】
【図１】参考例の半導体素子収納用パッケージについて実施の形態の例を示す斜視図である。
【図２】図１の半導体素子収納用パッケージにおける入出力端子を示す斜視図である。
【図３】（ａ）は本発明の半導体素子収納用パッケージにおける入出力端子について実施の形態の他の例を示す透視斜視図であり、（ｂ）は図３（ａ）の要部拡大透視斜視図である。
【図４】従来の半導体素子収納用パッケージの斜視図である。
【図５】図４の半導体素子収納用パッケージにおける入出力端子の斜視図である。
【図６】中継基板を設けた従来の半導体素子収納用パッケージの断面図である。
【符号の説明】
１：基体
１ａ：載置部
２：枠体
２ａ：取付部
３：入出力端子
３ａ：平板部
３ａ−Ａ：線路導体
３ａ−Ｂ：同一面接地導体
３ｂ：立壁部
３ｃ：導体非形成部
５：延出部
９：半導体素子
Ａ：立壁部の両端部[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor element housing package and a semiconductor device for housing semiconductor elements such as FETs.
[0002]
[Prior art]
Conventionally, a semiconductor element storage package (hereinafter also referred to as a semiconductor package) for storing a semiconductor element such as an FET (Field Effect Transistor) operated by a high frequency signal in a microwave band or a millimeter wave band is used. An input / output terminal is provided for inputting high power and for inputting / outputting a high-frequency signal between the semiconductor element and the external electric circuit. 4 is a perspective view of the semiconductor package, and FIG. 5 is a perspective view of input / output terminals used in the semiconductor package.
[0003]
The input / output terminal 103 is formed by laminating a substantially rectangular parallelepiped wall 103b on the upper surface of a substantially rectangular flat plate portion 103a. Generally, the input / output terminal 103 is produced by a multi-cavity method using a ceramic green sheet laminating method. And an external electric circuit (not shown) have a function of inputting and outputting a high-frequency signal, and the inside and outside of the semiconductor package are hermetically shut off.
[0004]
The flat plate portion 103a of the input / output terminal 103 is made of alumina (Al ₂ O _Three ) Sintered material, aluminum nitride (AlN) sintered material, mullite (3Al ₂ O _Three ・ 2SiO ₂ ) It is made of a sintered body (ceramics) such as a sintered material, and tungsten (W), molybdenum (Mo) -manganese (Mn), etc. A line conductor 103a-A made of a metallized layer and a coplanar ground conductor 103a-B are formed. A lower ground conductor 103a-C made of a metallization layer similar to the line conductor 103a-A is formed on the substantially entire surface of the lower surface of the flat plate portion 103a, and on both side faces substantially parallel to the line conductor 103a-A, A side ground conductor 103a-D made of a metallized layer similar to the line conductor 103a-A is formed at the center.
[0005]
The line conductor 103a-A, the coplanar ground conductor 103a-B, the lower ground conductor 103a-C, and the side ground conductor 103a-D made of a metallized layer are made of W, Mo-Mn, or the like. For example, in the case of W, a metal paste obtained by adding and kneading an organic solvent with a W powder as a main component and a solvent is printed in a predetermined pattern on a ceramic green sheet for the flat plate portion 103a in advance by a well-known screen printing method. It is formed by applying and baking this.
[0006]
On the other hand, the standing wall portion 103b is made of the same ceramic as the flat plate portion 103a, and an upper ground conductor 103b-A made of a metallized layer similar to the line conductor 103a-A is formed on substantially the entire upper surface thereof. Further, on both side surfaces (both end surfaces) of the standing wall portion 103b that is substantially flush with both side surfaces substantially parallel to the line conductor 103a-A of the flat plate portion 103a, a metallized layer similar to that of the line conductor 103a-A is formed on the entire surface. The side ground conductor 103b-D is formed continuously with the side ground conductor 103a-D.
[0007]
The upper ground conductor 103b-A and the side ground conductor 103b-D made of a metallized layer are printed and applied in a predetermined pattern on a laminate of ceramic green sheets in the same manner as the line conductor 103a-A formed on the flat plate portion 103a. In addition, it is formed by firing.
[0008]
This semiconductor package includes a base body 101, a frame body 102 bonded to the upper surface thereof, an input / output terminal 103 fitted to a side portion of the frame body 102, and a seal ring 106 bonded to the upper surface of the frame body 102 (see FIG. 6). The base 101 has a mounting portion 101a for mounting the semiconductor element 109, and a metal such as copper (Cu) or copper-tungsten (W) for efficiently dissipating heat generated when the semiconductor element 109 is operated to the outside. It consists of composite metal materials such as. The frame body 102 is joined to the outer peripheral portion of the upper surface of the base body 101 with a brazing material such as silver solder so as to surround the mounting portion 101a, and a mounting portion 102a for fitting the input / output terminal 103 is formed on the side portion. And made of a metal such as an Fe—Ni—Co alloy or an Fe—Ni alloy.
[0009]
The metallized layer on the side surface substantially parallel to the line conductor 103a-A of the input / output terminal 103 includes side ground conductors 103b-D formed on substantially the entire side surfaces of the standing wall portion 103b and the center of both side surfaces of the flat plate portion 103a. And side ground conductors 103a-D formed in the section. The side metallization layer is formed at the center of the side surface of the input / output terminal 103, and the same-surface ground conductors 103a-B located at both ends of the upper surface of the flat plate portion 103a are electrically connected to the side metallization layer. As a result, the grounding by the same-surface grounding conductor 103a-B becomes sufficient, and a so-called coplanar structure is formed. This coplanar structure improves the high-frequency transmission characteristics of the line conductor 103a-A. Specifically, high-frequency transmission with less influence of noise becomes possible.
[0010]
The lead terminal 104 is joined to a portion of the line conductor 103a-A outside the frame 102 via a brazing material such as silver brazing, and performs input / output of high-frequency signals between the external electric circuit and the input / output terminal 103. And made of a metal such as Fe-Ni-Co alloy. The seal ring 106 is bonded to the upper surface of the frame 102 with a brazing material such as silver brazing, and functions as a bonding medium for bonding a lid (not shown) to the upper surface by seam welding or the like (for example, the following patents) Reference 1).
[0011]
In recent years, when the semiconductor element 109 is electrically connected to the input / output terminal 103 and the semiconductor element 109 is accommodated in the semiconductor package, electronic components such as capacitors and coils are frequently installed in the semiconductor package. ing. At this time, the distance between the semiconductor element 109 and the input / output terminal 103 is inevitably increased due to the positional relationship with the electronic component. For example, as shown in FIG. 5, the relay board having the connection wiring 105b on the upper surface. B is configured to be disposed between the semiconductor element 109 and the input / output terminal 103. At this time, the bonding wire 105c electrically connects the semiconductor element 109 and the connection wiring 105b, and the connection wiring 105b and the input / output terminal 103.
[0012]
In such a semiconductor package, the semiconductor element 109 is mounted and fixed on the mounting portion 101a with a low melting point solder such as tin (Sn) -lead (Pb) solder, and the line conductor 103a-A and the semiconductor element 109 are mounted. By electrically connecting with the bonding wire 105c through the relay substrate 105, and then bonding the lid to the upper surface of the seal ring 106 by seam welding or the like, a semiconductor device as a product is obtained. For example, if the semiconductor element 109 is an FET, this semiconductor device operates the semiconductor element 109 with power supplied from an external electric circuit, processes a large amount of information input from the outside at high speed, and outputs the information to the outside And is widely used in the communication field.
[0013]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-242716 (page 7-9, FIG. 1)
[0014]
[Problems to be solved by the invention]
However, in the conventional semiconductor package, as shown in FIG. 6, in order to transmit an electric signal such as a high frequency signal output from the semiconductor element 109 to an external electric circuit device, the electric signal is a bonding wire 105c, a relay substrate. Since the signal is transmitted through the connection wiring 105b on the upper surface B, the bonding wire 105c, and the input / output terminal 103, an inductance that is about twice or more in the transmission path is generated in comparison with the conventional semiconductor package without the relay substrate B. There was a problem. As a result, transmission loss of the high frequency signal occurs, the bonding wire 105c acts as a coil, the high frequency signal leaks from the bonding wire 105c as an electromagnetic wave, or external noise enters the bonding wire 105c and noise is generated. There was a problem such as an increase.
[0015]
Therefore, by extending the flat plate portion 103a of the input / output terminal 103 to the inside of the frame body 102 and directly connecting a bonding wire 105c for transmitting an electric signal from the semiconductor element 109 to the extended portion, the relay substrate 105 is formed. It is conceivable that the length of the wire bonding 105c is reduced to approximately ½. However, if the portion inside the frame 102 of the flat plate portion 103a is not extended, the contraction rate of the lower ground conductor 103a-C formed on the lower surface of the flat plate portion 103a, the timing of the start of contraction, etc. Due to the difference between the contraction behavior of the insulator and the contraction behavior of the insulator constituting the flat plate portion 103a, the flat plate portion 3a of the input / output terminal 3 is warped upward and convexly downward. A bonding failure or a connection failure of the bonding wire 105c due to the bonding failure has occurred. That is, a conductor having substantially the same area and thickness as the lower ground conductor 103a-C is formed at a substantially symmetrical position (inside or on the upper surface of the flat plate portion 103a) with respect to the center in the thickness direction of the flat plate portion 103a. If this is the case, there will be no problem, but such a configuration is very difficult in terms of high-frequency transmission characteristics.
[0016]
Therefore, the present invention has been completed in view of the above-mentioned conventional problems, and its purpose is to effectively prevent a bonding failure to a frame of an input / output terminal due to warping of a flat plate portion or a connection failure of wire bonding, The configuration is such that the flat plate portion of the input / output terminal extends inward of the semiconductor package and eliminates the need for a relay substrate. As a result, a wire for transmitting a signal from the semiconductor element can be directly connected to the input / output terminal, so that no large inductance is generated in the transmission path of the high-frequency signal transmitted from the semiconductor element. It is to improve the transmission characteristics of the. Further, by reducing the size of the semiconductor package, it is possible to prevent the resonance point of the electromagnetic wave of the high-frequency signal from being lowered, and as a result, to operate the semiconductor element accommodated in the semiconductor package normally and stably for a long time. Furthermore, it is possible to reduce the number of manufacturing steps and eliminate the need for a relay substrate, thereby enabling efficient manufacturing.
[0017]
[Means for Solving the Problems]
In the present invention, a non-formed portion is provided in the laminated region of the flat plate portion and the standing wall portion and the laminated region of the flat plate portion and the extending portion with respect to the same-surface ground conductor.
[0018]
In the package for housing a semiconductor element of the present invention, the length of the input / output terminal in the frame body in the direction parallel to the line conductor of the flat plate portion is at least three times the length of the frame outer portion. In addition, since the extending portions extending inward of the frame body are formed at both ends of the standing wall portion so as not to reach the line conductor in the width direction, the occurrence of warpage in the flat plate portion is suppressed by the extending portions. In addition, poor connection of the input / output terminals to the frame and poor connection of wire bonding due to warpage of the flat plate portion can be effectively prevented. In addition, since no relay board is required, bonding wires that transmit electrical signals from semiconductor elements can be directly connected to the line conductors of input / output terminals, resulting in large inductance in the transmission path of high-frequency signals output from semiconductor elements. Therefore, the transmission characteristics of the high frequency signal can be improved. Further, by reducing the size of the semiconductor element storage package, it is possible to prevent the resonance point of the electromagnetic wave of the high frequency signal from being lowered. As a result, the semiconductor element stored in the semiconductor element storage package can be used for a long time. It can be operated normally and stably. Further, since the relay substrate is not necessary, the number of manufacturing processes is reduced, and the manufacturing can be efficiently performed.
[0019]
In the package for housing a semiconductor element of the present invention, preferably, the extension portion has a width that is 1/6 times to 1/4 times a length of the upper surface of the flat plate portion in a direction perpendicular to the line conductor. It is characterized by.
[0020]
In the package for housing a semiconductor element of the present invention, the extending portion has a width that is 1/6 times to 1/4 times the length in the direction perpendicular to the line conductor on the upper surface of the flat plate portion. It is possible to more effectively prevent the warpage of the flat plate portion of the terminal. As a result, poor connection of the input / output terminals to the frame body and poor connection of wire bonding due to warpage of the flat plate portion can be more effectively prevented.
[0021]
In the package for housing a semiconductor element of the present invention, preferably, the same plane ground conductor is formed at substantially equal intervals on both sides of the line conductor on the upper surface of the flat plate portion. A conductor non-forming portion is provided along a boundary line on a side surface substantially parallel to the line conductor with the standing wall portion.
[0022]
In the package for housing a semiconductor element of the present invention, the same-surface ground conductor is formed with a conductor non-forming portion along a boundary line on a side surface substantially parallel to the line conductor between the flat plate portion and the standing wall portion. Since the flat plate portion and the standing wall portion are in close contact with each other without going through the same surface ground conductor at the end portion where the separation is particularly likely to occur on the joining surface with the standing wall portion, the bonding strength is increased and the flat plate portion and the standing wall portion are interposed. It is possible to make it difficult for peeling to occur.
[0023]
A semiconductor device according to the present invention includes a semiconductor element storage package according to the present invention, a semiconductor element mounted and fixed on the mounting portion and electrically connected to the input / output terminal, and an upper surface of the frame. And a bonded lid.
[0024]
With the above structure, the semiconductor device of the present invention has high-frequency signal transmission characteristics and high performance and high reliability with semiconductor elements operating stably over a long period of time.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Reference example The semiconductor element storage package will be described in detail below. Figure 1 Reference example FIG. 2 is a perspective view of the input / output terminal of FIG. 1, and FIG. 3 (a) is an input / output showing another example of the embodiment of the semiconductor package of the present invention. FIG. 3B is an enlarged perspective view of a main part of FIG. 3A.
[0026]
1 to 3, reference numeral 1 denotes a base, 1a denotes a mounting portion, 2 denotes a frame, 2a denotes a mounting portion of the input / output terminal 3, 3 denotes an input / output terminal, 3a denotes a flat plate portion of the input / output terminal 3, 3a- A is a line conductor, 3a-B is a coplanar ground conductor, 3a-C is a lower ground conductor, 3a-D is a side ground conductor, 3b is a standing wall portion, 3b-A is an upper ground conductor, and 3b-D is a side portion. A grounding conductor, A is both end portions of the standing

wall portion

3b, 4 is a lead terminal, 5 is an extending portion of the standing

wall portion

3b, 5a is an end surface of the extending portion 5, and 6 is a seal ring. The base body 1, the frame body 2, the input / output terminals 3, and the seal ring 6 basically constitute a semiconductor package for housing a semiconductor element 9 such as an FET. In addition, the semiconductor element 9 is accommodated in the semiconductor package and a lid (not shown) is attached to the upper surface of the seal ring 6 to obtain a semiconductor device.
[0027]
The semiconductor package of the present invention includes a base body 1 having a mounting portion 1a on which the semiconductor element 9 is mounted on the upper main surface, and a metal attached to the upper main surface of the base body 1 so as to surround the mounting portion 1a. A frame body 2; a mounting portion 2a of an input / output terminal 3 formed of a through hole or a notch formed in a side portion of the frame body 2; and a line conductor 3a-A extending from one side to the other side facing the upper surface. A flat plate portion 3a made of a substantially rectangular dielectric material and a standing wall portion 3b made of a dielectric material joined to the upper surface of the flat plate portion 3a with a part of the line conductor 3a-A interposed therebetween, are fitted to the mounting portion 2a. The basic configuration includes the input / output terminal 3.
[0028]
The substrate 1 of the present invention has a mounting portion 1a for mounting the semiconductor element 9 on the upper main surface, functions as a support member for supporting the semiconductor element 9, and efficiently dissipates heat of the semiconductor element 9 to the outside. It has the function to do. The substrate 1 has a substantially rectangular flat plate shape, and is made of a metal such as Fe—Ni—Co alloy or Cu—W, or a ceramic such as alumina, aluminum nitride, or mullite. When made of metal, for example, it is manufactured in a predetermined shape by applying a conventionally known metal processing method such as rolling or punching to an ingot (lumb) of an Fe—Ni—Co alloy. In the case of ceramics, an appropriate organic binder or solvent is added to the raw material powder to form a slurry, and this slurry is formed into a ceramic green sheet by a molding method such as a doctor blade method or a calender roll method, Thereafter, an appropriate punching process is performed on the ceramic green sheet, and a plurality of these are laminated and fired.
[0029]
When the substrate 1 is made of metal, the surface thereof has excellent corrosion resistance and wettability with the brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 μm and an Au layer having a thickness of 0.5 to 5 μm. Are sequentially deposited by a plating method, and it is possible to effectively prevent the base 1 from being oxidatively corroded and to firmly adhere and fix the semiconductor element 9 to the mounting portion 1a of the base 1. Further, when the substrate 1 is made of ceramics, the mounting portion 1a has a metal excellent in corrosion resistance and wettability with the brazing material, specifically, a Ni layer having a thickness of 0.5 to 9 μm and an Au having a thickness of 0.5 to 5 μm. The layers are preferably deposited sequentially by plating, and the semiconductor element 9 can be firmly bonded and fixed to the mounting portion 1a on the upper main surface of the base 1.
[0030]
In addition, a frame body in which an attachment portion 2a made of a through hole or a notch for fitting the input / output terminal 3 to the side portion is formed on the upper main surface of the base body 1 so as to surround the placement portion 1a. 2 are joined by a brazing material such as silver brazing, and a space for accommodating the semiconductor element 9 is formed inside the frame 2. The frame 2 is made of the same metal as the base 1 and forms a side wall of the box-like body. The frame 2 is processed into a shape having a mounting portion 2a on the side by the same processing method as the base 1. The
[0031]
Note that the frame 2 is joined to the base 1 by silver brazing or the like having an appropriate volume in which the upper main surface of the base 1 and the lower surface of the frame 2 are laid on the upper main surface of the base 1. It is joined through the brazing material. Furthermore, a metal layer such as a Ni layer having a thickness of 0.5 to 9 μm or an Au layer having a thickness of 0.5 to 5 μm may be deposited on the surface of the frame body 2 by a plating method in the same manner as the substrate 1.
[0032]
In addition, the mounting portion 2a of the frame body 2 is provided with an input / output terminal 3 for inputting and outputting a high-frequency signal between the semiconductor element 9 and an external electric circuit and hermetically blocking the inside and outside of the semiconductor package. The metallized layers (upper grounding conductor 3b-A, side grounding conductors 3a-D, 3b-D, and lower grounding conductor 3a-C) are joined by a brazing material such as silver solder. The input / output terminal 3 is formed by laminating a rectangular column-like standing wall portion 3b which is laid down on an upper surface of a substantially rectangular flat plate portion 3a such as a substantially rectangular shape.
[0033]
The flat plate portion 3a and the standing wall portion 3b of the input / output terminal 3 are made of ceramics such as alumina, aluminum nitride, and mullite. A line conductor 3a-A made of a metallized layer of W, Mo-Mn, or the like is formed on the upper surface of the flat plate portion 3a from one side to the opposite side, preferably approximately on both sides of the line conductor 3a-A. Coplanar ground conductors 3a-B made of the metallized layer are formed at equal intervals. Thereby, the grounding to the line conductor 3a-A becomes sufficient and a so-called coplanar structure is formed, so that the transmission characteristic of the high-frequency signal in the line conductor 3a-A is improved. A lower ground conductor 3a-C made of a metallized layer similar to the line conductor 3a-A is formed on substantially the entire lower surface of the flat plate portion 3a.
[0034]
In addition, the same plane ground conductor 3a-B is preferably formed so as to be in contact with the end (side) of the upper surface of the flat plate portion 3a. Thereby, the grounding with respect to the line conductor 3a-A becomes favorable, and the transmission characteristic of the high-frequency signal in the line conductor 3a-A is improved. Further, as shown in FIGS. 3A and 3B, a conductor non-forming portion 3c is provided along a boundary line on a side surface substantially parallel to the line conductor 3a-A of the flat plate portion 3a and the standing wall portion 3b. May be. As a result, the flat plate portion 3a and the standing wall portion 3b are in close contact with each other without interposing the same plane ground conductor 3a-B at the end portion where the separation is particularly likely to occur at the joining surface between the flat plate portion 3a and the standing wall portion 3b. It is possible to increase the strength and to prevent separation between the flat plate portion 3a and the standing wall portion 3b.
[0035]
The conductor non-forming portion 3c is preferably 1/3 to 2/3 times as wide as the width of the coplanar ground conductor 3a-B. If it is less than 1/3 times, the area of the portion where the flat plate portion 3a and the standing wall portion 3b are joined without passing through the same-surface ground conductor 3a-B in the conductor non-forming portion 3c becomes small, and the flat plate portion 3a and the standing wall Separation easily occurs between the portion 3b and the effect of the standing wall portion 3b suppressing the warpage of the flat plate portion 3a is likely to be reduced. On the other hand, if it exceeds 2/3 times, the area of the ground conductor 3a-B on the same surface is reduced, and the grounding with respect to the line conductor 3a-A becomes insufficient, and the transmission characteristics of the high-frequency signal (5 GHz or more) in the line conductor 3a-A. Tends to decrease.
[0036]
Further, as shown in FIG. 3B, the conductor non-forming portion 3c is a thin line-like connection portion 3c-A that electrically connects the same-surface ground conductor 3a-B and the side ground conductor 3a-D. May be formed so as to cross the conductor non-forming portion 3c. Thereby, while being able to maintain the joining strength of the flat plate part 3a and the standing wall part 3b, the grounding property of the same surface grounding conductor 3a-B can be improved.
[0037]
The connecting portion 3c-A may have a width of 0.2 to 0.5 mm. If it is less than 0.2 mm, the resistance of the connecting portion 3c-A increases, and improvement in the grounding property of the ground contact conductor 3a-B cannot be expected. On the other hand, if the thickness exceeds 0.5 mm, the bonding area between the flat plate portion 3a and the standing wall portion 3b through the conductor increases, so that the bonding strength between the flat plate portion 3a and the standing wall portion 3b decreases, and the flat plate portion 3a and the standing wall portion. It becomes easy to peel from 3b.
[0038]
Moreover, it is preferable that the total area of the connection part 3c-A is 0.15 to 0.4 times the area of the conductor non-formation part 3c. If it is less than 0.15 times, the resistance of the connecting portion 3c-A is increased, and improvement in the grounding property of the same-surface grounding conductor 3a-B cannot be expected. On the other hand, if it exceeds 0.4 times, a sufficient bonding area between the ceramics cannot be ensured between the flat plate portion 3a and the standing wall portion 3b, so that the bonding strength is reduced and the flat plate portion 3a and the standing wall portion 3b are separated. It becomes easy to do.
[0039]
The line conductor 3a-A, the same-surface ground conductor 3a-B, the lower ground conductor 3a-C, the side ground conductor 3a-D, and the connection portion 3c-A of the flat plate portion 3a are made of a metallized layer such as W or Mo-Mn. Become. For example, in the case of W, a metal paste obtained by adding and mixing an organic solvent and a solvent to a metal powder mainly composed of W powder is applied to a ceramic green sheet for forming the flat plate portion 3a in advance by a well-known screen printing method. It is formed by printing and applying to a predetermined pattern and baking.
[0040]
Further, the standing wall portion 3b is laminated on the upper surface of the flat plate portion 3a. The standing wall portion 3b is made of the same ceramic as the flat plate portion 3a, and an upper ground conductor 3b-A made of a metallized layer similar to the line conductor 3a-A is formed on substantially the entire surface excluding the extending portion 5 on the upper surface thereof. Further, side ground conductors 3b-D are formed on the side surfaces. Further, the upper ground conductor 3b-A and the side ground conductor 3b-D of the standing wall 3b are printed and applied in a predetermined pattern in the same manner as the formation of the lower ground conductor 3a-C formed on the flat plate portion 3a. It is formed by firing.
[0041]
In the present invention The figure As shown in FIG. 3A, the input / output terminal 3 has a length of the portion inside the frame 2 in the direction parallel to the line conductor 3a-A of the flat plate portion 3a is 3 times the length of the portion outside the frame 2. The extending portions 5 extending inward of the frame body 2 are formed at both end portions A of the standing wall portion 3b so as not to reach the line conductors 3a-A in the width direction. The extending portion 5 is formed so as to sandwich the same-surface ground conductor 3a-B between the upper surface of the flat plate portion 3a. At this time, the extending portion 5 may cover the entire surface in the width direction of the same-surface ground conductor 3a-B, or a part of the same-surface ground conductor 3a-B may be exposed in the width direction. In any case, it was confirmed that there was no change in the transmission characteristics of the high-frequency signal in the line conductor 3a-A.
[0042]
Further, metallized layers (side ground conductors 3a-D, side ground conductors 3b-D) are formed from the side surface substantially parallel to the line conductor 3a-A of the flat plate portion 3a to the side surface of the standing wall portion 3b substantially flush with the side surface. Is formed by being electrically connected to the same plane ground conductor 3a-B, the lower ground conductor 3a-C, and the upper ground conductor 3b-A. As shown in FIG. 2, the side ground conductor 3a-D is formed so that the same-surface ground conductor 3a-B is in contact with the end (side) of the upper surface of the flat plate portion 3a. It is preferable to be formed continuously to the side ground conductor 3b-D with substantially the same width as D. This facilitates the formation of a continuous meniscus of brazing material when the input / output terminal 3 is fitted to the mounting portion 2a, improves the adhesion between the input / output terminal 3 and the mounting portion 2a, and has an airtight structure. can do. Further, as shown in FIGS. 3A and 3B, the side ground conductor 3a-D has a side surface in which the conductor non-forming portion 3c is substantially parallel to the line conductor 3a-A of the flat plate portion 3a and the standing wall portion 3b. May be formed on the entire side surface substantially parallel to the line conductor 3a-A of the flat plate portion 3a. Thereby, even if the conductor non-forming portion 3c is formed on the same plane ground conductor 3a-B, the same plane ground conductor 3a-B and the side ground conductor 3a-D can be electrically connected, and the line conductor The grounding with respect to 3a-A becomes good, and the transmission characteristic of the high-frequency signal in the line conductor 3a-A is improved.
[0043]
With the above configuration, it is possible to suppress the warpage that occurs when the flat plate portion 3a of the input / output terminal 3 is fired, and to effectively prevent the occurrence of poor connection in wire bonding. Further, even if a smear occurs in the printed layer of the metal paste that becomes the same-surface ground conductor 3a-B in the manufacturing process, the extension of the extension 5 is suppressed, and the same-surface ground conductor 3a as the line conductor 3a-A is suppressed. A short circuit with -B is suppressed.
[0044]
Further, in order to minimize the increase in stray capacitance on the side surface of the extension portion 5, the side ground conductor layer 3b-D in the standing wall portion 3b extends to the side surface side of the extension portion 5 by about 0.25 to 0.3 mm. It may be formed. If the side ground conductor 3b-D is extended to the side surface side of the extending portion 5 in this way, it is possible to promote the formation of a meniscus by the brazing material when the input / output terminal 3 is fitted to the mounting portion 2a. In addition, a highly reliable structure can be realized and the stray capacitance can be hardly increased.
[0045]
In the present invention, the length of the portion on the inner side of the frame 2 in the direction parallel to the line conductor 3a-A of the flat plate portion 3a is set to be not less than three times the length of the portion on the outer side of the frame 2. Since no relay substrate is required at the portion inside the frame 2 of the portion 3a, the semiconductor element 9 can be electrically connected directly to the input / output terminal 3. As a result, a large inductance is not generated in the transmission path of the high-frequency signal output from the semiconductor element 9, and the transmission characteristic of the high-frequency signal can be improved.
[0046]
When the length of the portion 3aa (FIG. 2) inside the frame 2 in the direction parallel to the line conductor 3a-A of the flat plate portion 3a is less than three times the length of the portion 3ab (FIG. 2) outside the frame 2, The flat part 3a is hardly warped and the extension part 5 is not necessary, but it becomes difficult to mount the semiconductor element 9 close to the input / output terminal 3, and a relay substrate is required.
[0047]
In the case of exceeding 3 times, if there is no extension part 5 in the standing wall part 3b, the flat plate part 3a is warped not a little, and sometimes the warpage exceeds 20 μm. In this case, when the input / output terminal 3 is fitted to the attachment portion 2a, the thickness of the brazing material varies, and the input / output terminal 3 is fitted to the attachment portion 2a in an inclined state. As a result, the connection failure is induced when wire bonding is performed on a portion inside the frame body 2 of the line conductor 3a-A. However, if the extending wall 5 is provided on the standing wall 3b in the case of exceeding 3 times as in the present invention, the warpage of the flat plate 3a is greatly suppressed, and as a result, a relay board is not required.
[0048]
In the present invention, the extension portion 5 has a width of b (mm), and the length in the direction perpendicular to the line conductor 3a-A on the upper surface of the flat plate portion 3a is a (mm). It is preferable that ≦ a / 4. If b <a / 6, the effect of suppressing the warpage of the flat plate portion 3a is reduced, and the blurring that occurs when printing the metal paste that becomes the ground contact conductor 3a-B on the ceramic green sheet is spread. It becomes difficult to suppress with the extension part 5, and it becomes easy to short-circuit the line conductor 3a-A and the same surface ground conductor 3a-B. When b> a / 4, the effect of suppressing the warpage of the flat plate portion 3a is sufficient, but it becomes difficult to set the width of the line conductor 3a-A to a desired size, the resistance increases, and the high frequency signal Transmission delay and reflection occur, and when used for inputting a large current, heat is easily generated.
[0049]
Moreover, it is preferable that the length of the extension part 5 in the direction parallel to the line conductor 3a-A is 1/2 to 3/4 of the length of the portion 3aa of the flat plate part 3a. If it is less than 1/2, it is difficult to suppress the warpage of the flat plate portion 3a. If it exceeds 3/4, the extension portion 5 becomes an obstacle, and it becomes difficult to connect the bonding wire to the line conductor 3a-A or the same plane ground conductor 3a-B.
[0050]
Also, as shown in FIGS. 2, 3 (a) and 3 (b), the same-surface ground conductor 3 a -B has the length of the exposed portion that is not covered by the extension portion 5 as the end face of the extension portion 5. 5a to 0.5 mm or more, preferably 0.75 mm or more is sufficient, and this length facilitates electrical connection to the semiconductor element 9 through a bonding wire.
[0051]
In such a semiconductor package, the semiconductor element 9 is mounted and fixed on the mounting portion 1a with a low melting point brazing material such as Sn-Pb solder, and the line conductor 3a-A, the coplanar ground conductor 3a-B, and the semiconductor element 9 are mounted. And a lid (not shown) made of an Fe—Ni—Co alloy or the like is joined to the upper surface of the seal ring 6 by seam welding or the like, so that a semiconductor device as a product is obtained. This semiconductor device is used for a communication device such as a communication base station that operates the semiconductor element 9 by a drive signal such as a high-frequency signal supplied from an external electric circuit and transmits a large amount of information at high speed.
[0052]
【Example】
Embodiments of the semiconductor element storage package of the present invention will be described below.
[0053]
( reference Example 1)
First, as a sample of the input / output terminal 3 having a conventional configuration in which the extending portion 5 is not provided on the standing wall portion 3b, a flat plate portion 3a made of alumina ceramics having outer dimensions of 4 to 7 mm × width 4 mm × thickness 1 mm, and outer dimensions Has a vertical wall portion 3b of 1 mm in length, 4 mm in width, and 1 mm in thickness, made of alumina ceramics, and has the same thickness as the line conductor 3a-A and the line conductor 3a-A made of W having a thickness of 15 μm and a width of 1 mm. Coplanar grounding conductor 3a-B composed of W and width W, lower grounding conductor 3a-C composed of W having a thickness of 15 μm, side grounding conductor 3a-D composed of Mo—Mn having a thickness of 15 μm, and W having a thickness of 15 μm. An input / output terminal 3 was prepared by forming an upper ground conductor 3b-A made of and a side ground conductor 3b-D made of Mo-Mn having a thickness of 15 μm. At this time, the length of the portion 3ab outside the frame 2 of the flat plate portion 3a is set to 1 mm, and the length of the portion 3aa inside the frame 2 of the flat plate portion 3a is set to 2,2.5, 3, 3.5, 4, 5 of the portion 3ab. Five (6) input / output terminals 3 each (double) were prepared.
[0054]
Also, Reference example As a sample of the input / output terminal 3, in the above six types of input / output terminals 3, the extending portion 5 is provided on the standing wall portion 3 b, the width of the extending portion 5 is 0.8 mm, and
The end surface 5a is positioned at a position 0.5 mm from the end of the flat plate portion 3a in the line direction.
Five manufactured input / output terminals 3 were prepared.
[0055]
About these samples, the curvature (average value) of the flat plate part 3a and the connection state of the bonding wire were evaluated. The warpage of the flat plate portion 3a was measured with a surface roughness meter along the diagonal line on the lower surface of the flat plate portion 3a. The connection state of the bonding wire was examined for any connection failure or connection failure (such as connection in a tilted state). The results are shown in Table 1.
[0056]
In Table 1, Lr indicates the ratio (times) of the portion 3aa to the portion 3ab of the flat plate portion 3a.
[0057]
[Table 1]

[0058]
From Table 1, in the sample of the comparative example, when the length of the portion 3aa is more than three times the length of the portion 3ab of the flat plate portion 3a, the warpage of the flat plate portion 3a is increased and bonding wire connection failure occurs. did. In contrast, Reference example In this sample, it was found that the warpage of the flat plate portion 3a is suppressed and the connection state of the bonding wire is greatly improved. Also, Reference example In this sample, the semiconductor element 9 can be directly electrically connected to the flat plate portion 3a via a bonding wire, and a relay substrate is not necessary.
[0059]
( reference Example 2)
Next, the length of the part 3aa of the flat plate part 3a is 4 mm, the length of the part 3ab is 1 mm, and the width of the extension part 5 is 0.4, 0.5, 0.6, 0.67, 0.8, 0.9, 1, 1.1, 1.2 (mm). )When
A total of 45 of each of the nine types of samples were prepared, and the warpage (average value) of the flat plate portion 3a and the connection state of the bonding wires were evaluated. As for the magnitude of the warpage of the flat plate portion 3a, an average value of less than 15 μm was regarded as good, and a case where it exceeded 15 μm was regarded as defective. The evaluation results are shown in Table 2.
[0060]
[Table 2]

[0061]
From Table 2, Reference example In this sample, even if the length of the portion 3aa of the flat plate portion 3a is four times as long as the length of the portion 3ab, the width of the extending portion 5 of the standing wall portion 3b is set to the lateral length of the upper surface of the flat plate portion 3a ( It has been clarified that the warpage of the flat plate portion 3a can be reduced by setting it to 1/6 (0.67 mm) or more of 4 mm (the length in the direction orthogonal to the line conductor 3a-A). In addition, when the width of the extended portion 5 exceeds 1/4 times (1 mm) the lateral length of the upper surface of the flat plate portion 3a, the capillary may come into contact with the extended portion 5 and wire bonding cannot be performed. . For this reason, the entire input / output terminal 3 is enlarged, and in this case, the semiconductor package becomes large.
[0062]
(Example 3)
Next, the length of the portion 3aa inside the frame 2 of the flat plate portion 3a used in Example 1 is 2, 2.5, 3, 3.5, 4, 5 (times) of the portion 3ab, and the width is 0.8 mm. A sample in which the extended portion 5 in which the end surface 5a is located at a position of 0.7 mm from the end in the line direction of the flat plate portion 3a is formed, and a conductor non-forming portion 3c is newly added to the same grounded conductor 3a-B. 5 were prepared for each sample having a width of 0.5 mm and 1.7, 2.2, 2.7, 3.2, 3.7, and 4.7 (mm).
[0063]
These samples were subjected to a temperature cycle test of −65 to 125 ° C. for 10 cycles (1 cycle 60 minutes), then magnified 40 times using a metal microscope, and the samples were observed by observing the extension 5 and the flat plate. The occurrence rate of peeling (delamination) at the interface with the portion 3a was determined, and the adhesion between the extended portion 5 and the flat plate portion 3a was evaluated. These evaluation results are shown in Table 3.
[0064]
[Table 3]

[0065]
From Table 3, in the sample in which the conductor non-forming portion 3c is not formed, delamination occurs when the length of the portion 3aa of the flat plate portion 3a is three times or more the length of the portion 3ab. On the other hand, it was found that the sample in which the conductor non-forming portion 3c was formed was excellent without causing delamination even when the length of the portion 3aa of the flat plate portion 3a was five times the length of the portion 3ab.
[0066]
(Example 4)
Next, the length of the part 3aa of the flat plate part 3a used in Example 2 is 4 mm, the length of the part 3ab is 1 mm, and the width of the extension part 5 is 0.4, 0.5, 0.6, 0.67, 0.8, 0.9. , 1, 1.1, 1.2 (mm), and a new conductor non-forming portion 3c on these same-surface grounded conductors 3a-B were made to have a length of 3.3 mm and a width of 0.5 mm. Five samples were prepared.
[0067]
These samples were subjected to a temperature cycle test of −65 to 125 ° C. for 10 cycles (1 cycle 60 minutes), then magnified 40 times using a metal microscope, and the samples were observed by observing the extension 5 and the flat plate. The occurrence rate of peeling (delamination) at the interface with the portion 3a was determined, and the adhesion between the extended portion 5 and the flat plate portion 3a was evaluated. These evaluation results are shown in Table 4.
[0068]
[Table 4]

[0069]
From Table 4, in the sample in which the conductor non-formed portion 3c is not formed, the delamination occurs when the width of the extended portion 5 is less than 1/4 times (1 mm) the horizontal length of the upper surface of the flat plate portion 3a. did. On the other hand, in the sample in which the conductor non-forming portion 3c is formed, delamination does not occur even when the width of the extending portion 5 is 1/10 times (0.4 mm) the horizontal length of the upper surface of the flat plate portion 3a. I found out.
[0070]
(Example 5)
Next, a sample in which the length of the conductor non-forming part 3c used in Example 3 is 1.7, 2.2, 2.7, 3.2, 3.7, 4.7 (mm) and the width is 0.5 mm, and these conductor non-forming parts are newly added. 3c, a connection conductor 3c-A having a width of 0.3 mm for electrically connecting the same-surface ground conductor 3a-B and the side ground conductor 3a-D across the conductor non-forming portion 3c with an interval of 150 μm. 5 samples each were prepared.
[0071]
About these samples, FET (Field Effect Transistor) is mounted in a semiconductor package, and the reflection loss of the high frequency signal at the input / output terminal 3 when a high frequency signal of 5 GHz is transmitted is measured using a network analyzer. High frequency signal transmission was evaluated. These evaluation results are shown in Table 5.
[0072]
[Table 5]

[0073]
From Table 5, in the sample in which the connection part 3c-A is not provided in the conductor non-forming part 3c, the transmission loss is as large as −22 dB or more. On the other hand, it was found that the sample in which the connection portion 3c-A is provided in the conductor non-forming portion 3c is excellent as small as −23 dB or less.
[0074]
The present invention is not limited to the above-described embodiments and examples, and various modifications may be made without departing from the scope of the present invention. For example, when the semiconductor element 9 is an optical semiconductor element such as a semiconductor laser (LD) or a photodiode (PD), the effect of the present invention is the same. In that case, the through hole for attaching the optical fiber to the frame 2 is used. Should be provided.
[0075]
【The invention's effect】
The package for housing a semiconductor element according to the present invention is a base having a mounting portion on which the semiconductor element is mounted on the upper main surface, and a metal attached so as to surround the mounting portion on the upper main surface of the base From a substantially rectangular dielectric having a frame, a mounting portion for an input / output terminal consisting of a through-hole or notch formed in a side portion of the frame, and a line conductor formed from one side to the other side facing the upper surface An input / output terminal fitted to the mounting portion, and having an upright wall portion made of a dielectric material joined to the upper surface of the flat plate portion with a part of the line conductor interposed therebetween, The length of the portion inside the frame body in the direction parallel to the line conductor of the flat plate portion is set to be three times or more the length of the portion outside the frame body and extends to the inside of the frame body at both ends of the standing wall portion. Each extension is formed so as not to reach the line conductor in the width direction. , Warping of the flat plate portion is restrained by the extending portion, connection failure of the bonding failure or a wire bonding with respect to the frame of the input and output terminals due to warping of the flat plate portion can be effectively prevented. Also, since no relay board is required, the semiconductor element can be electrically connected directly to the input / output terminals, and no large inductance is generated in the transmission path of the high-frequency signal output from the semiconductor element. Can be made good. Further, by reducing the size of the semiconductor element storage package, it is possible to prevent the resonance point of the electromagnetic wave of the high frequency signal from being lowered. As a result, the semiconductor element stored in the semiconductor element storage package can be used for a long time. It can be operated normally and stably. Further, since the relay substrate is not necessary, the number of manufacturing processes is reduced, and the manufacturing can be efficiently performed.
[0076]
In the package for housing a semiconductor element of the present invention, preferably, the extending portion has a width that is 1/6 times to 1/4 times a length in a direction perpendicular to the line conductor on the upper surface of the flat plate portion. Thus, it is possible to more effectively prevent the warpage of the flat plate portion of the input / output terminal. As a result, poor connection of the input / output terminals to the frame body and poor connection of wire bonding due to warpage of the flat plate portion can be more effectively prevented.
[0077]
In the package for housing a semiconductor element of the present invention, the same-surface ground conductor is provided with a conductor non-forming portion along a boundary line on a side surface substantially parallel to the line conductor between the flat plate portion and the standing wall portion. Since the flat plate portion and the standing wall portion are bonded to each other without interposing the same surface ground conductor at the end portion where the separation is particularly likely to occur on the joining surface with the standing wall portion, the bonding strength is increased and the flat plate portion and the standing wall portion are interposed. It is possible to make it difficult for peeling to occur.
[0078]
The semiconductor device of the present invention is bonded to the upper surface of the frame body, the semiconductor element housing package of the present invention, the semiconductor element mounted and fixed on the mounting portion and electrically connected to the input / output terminals. By including the lid, the high-frequency signal transmission characteristics are good, and the semiconductor element operates stably over a long period of time.
[Brief description of the drawings]
[Figure 1] Reference example It is a perspective view which shows the example of embodiment about the package for semiconductor element accommodation of this.
2 is a perspective view showing input / output terminals in the package for housing a semiconductor element of FIG. 1. FIG.
3A is a perspective view showing another example of an embodiment of an input / output terminal in a package for housing a semiconductor element of the present invention, and FIG. 3B is an enlarged perspective view of a main part of FIG. It is a perspective view.
FIG. 4 is a perspective view of a conventional semiconductor element storage package.
5 is a perspective view of input / output terminals in the package for housing a semiconductor element of FIG. 4. FIG.
FIG. 6 is a cross-sectional view of a conventional semiconductor element housing package provided with a relay substrate.
[Explanation of symbols]
1: Substrate
1a: Placement part
2: Frame
2a: Mounting part
3: Input / output terminal
3a: Flat plate part
3a-A: Line conductor
3a-B: Coplanar ground conductor
3b: Standing wall
3c: Conductor non-formation part
5: Extension part
9: Semiconductor element
A: Both ends of the standing wall

Claims

A base body having an upper principal surface on which a semiconductor element is placed;
A metal frame attached to the upper main surface of the base body so as to surround a region where the semiconductor element is placed;
A rectangular flat plate portion made of a dielectric, a line conductor formed on the upper surface of the flat plate portion, and a coplanar ground conductor formed at equal intervals on both sides of the line conductor on the upper surface of the flat plate portion. The side surface ground conductor formed on the side surface of the flat plate portion and connected to the same plane ground conductor, and the upper surface of the flat plate portion sandwiching a part of the line conductor and a portion of the same plane ground conductor A standing wall portion made of a dielectric layer laminated on the plate member, and an extending portion that extends from the standing wall portion to the inside of the frame body and is laminated on the flat plate portion with a part of the ground conductor interposed therebetween, An input / output terminal attached to the side of the frame,
The input / output terminal is attached to the frame so that the length of the inner part of the frame is three times or more of the length of the outer part of the frame;
The coplanar ground conductor is provided with a non-forming portion in a laminated region of the flat plate portion and the standing wall portion and a laminated region of the flat plate portion and the extending portion. Storage package.

2. The package for housing a semiconductor element according to claim 1, further comprising a connection conductor that is provided in the non-forming portion and electrically connects the same-surface ground conductor and the side-surface ground conductor.

A package for housing a semiconductor element according to claim 1 or 2,
A semiconductor element mounted on the substrate and electrically connected to the input / output terminal;
And a lid bonded to the upper surface of the frame.