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JP4004460B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP4004460B2
JP4004460B2 JP2003418144A JP2003418144A JP4004460B2 JP 4004460 B2 JP4004460 B2 JP 4004460B2 JP 2003418144 A JP2003418144 A JP 2003418144A JP 2003418144 A JP2003418144 A JP 2003418144A JP 4004460 B2 JP4004460 B2 JP 4004460B2
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terminals
terminal
control circuit
low potential
potential
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JP2005183463A (en
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和広 栗秋
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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Description

本発明は半導体装置に関し、特にトランスファモールドによって樹脂封止された半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device sealed with a transfer mold.

トランスファモールドによって樹脂封止された半導体装置では、端子はパッケージの側面に一列に配設される構成を採るので、必要な端子数に対して、端子を配設できる領域は自ずと制限される。従って、インバータモジュールのように、高電位となるスイッチングデバイスが含まれるような場合には、高電位端子と、低電位端子とがパッケージの同じ側面に一列に配設されることになる。   In a semiconductor device sealed with a resin by transfer molding, the terminals are arranged in a line on the side surface of the package. Therefore, the area where the terminals can be arranged is naturally limited with respect to the required number of terminals. Therefore, when a switching device having a high potential is included as in the inverter module, the high potential terminal and the low potential terminal are arranged in a row on the same side surface of the package.

この場合、高電位端子と低電位端子とは地絡を防ぐために所定の絶縁距離を隔てて配設しなければならず、半導体装置の小型化という観点から、端子の配設順序には工夫が必要であった。   In this case, the high-potential terminal and the low-potential terminal must be arranged with a predetermined insulation distance to prevent a ground fault, and the arrangement of the terminals is devised from the viewpoint of miniaturization of the semiconductor device. It was necessary.

例えば、特許文献１には、対をなす高電位端子がパッケージの右端に配設され、その隣に所定の絶縁距離を隔てて、対をなす低電位端子が配設され、以後、高電位、低電位の順で計６組の端子対が配列された構成が示されている。   For example, in Patent Document 1, a pair of high potential terminals is disposed at the right end of the package, and a pair of low potential terminals are disposed adjacent to each other at a predetermined insulation distance. A configuration is shown in which a total of six terminal pairs are arranged in the order of low potential.

このように配列することで、絶縁距離確保のためのスペースは５カ所で済むが、対をなす低電位端子をパッケージの右端に配設した場合には、端子対の配列の終わりが高電位端子となるので、以後に続く低電位端子との間にも絶縁距離確保のためのスペースを設ける必要が生じ、絶縁距離確保のためのスペースは６カ所となってしまい、パッケージを大きくする必要が生じる。   By arranging in this way, only five spaces for securing the insulation distance are required. However, when a pair of low potential terminals is arranged at the right end of the package, the end of the arrangement of the terminal pair is the high potential terminal. Therefore, it is necessary to provide a space for securing the insulation distance between the subsequent low-potential terminals, and there are six spaces for securing the insulation distance, which necessitates a larger package. .

特開２０００−１３８３４２号公報（図１）JP 2000-138342 A (FIG. 1)

上述した特許文献１に開示される端子の配設順序を採用すれば、高電位端子と低電位端子との間に設けるべき絶縁距離確保のためのスペースを削減することはできるが、以下の問題が発生する可能性があった。   If the arrangement order of the terminals disclosed in Patent Document 1 described above is adopted, the space for securing the insulation distance to be provided between the high potential terminal and the low potential terminal can be reduced, but the following problems Could occur.

特許文献１の半導体装置では、対をなす高電位端子と対をなす低電位端子とが交互に配設されるため、対をなす高電位端子のうち出力端子に接続される端子、例えばＶＶＦＳ端子と、対をなす低電位端子のうち制御信号入力端子、例えばＵＰ端子とが接近して配設されるため、制御信号入力端子にノイズが与える影響が大きくなる可能性があった。   In the semiconductor device of Patent Document 1, since a pair of high potential terminals and a pair of low potential terminals are alternately arranged, a terminal connected to an output terminal among the pair of high potential terminals, for example, a VVFS terminal Further, since the control signal input terminal, for example, the UP terminal, of the paired low potential terminals is disposed close to the control signal input terminal, the influence of noise on the control signal input terminal may be increased.

すなわち、各端子間には寄生容量が存在し、この寄生容量と、スイッチングデバイスのオン・オフ動作時の電圧変化率（ｄＶ／ｄｔ）との積で与えられる電流がノイズとして制御信号入力端子に流れ込むことで、誤動作の原因となる。そして、寄生容量は端子間距離に反比例するので、端子間距離が狭いと寄生容量が大きくなり、ノイズも大きくなってノイズが制御信号に与える影響が大きくなる。   That is, there is a parasitic capacitance between the terminals, and the current given by the product of this parasitic capacitance and the voltage change rate (dV / dt) during the ON / OFF operation of the switching device is input to the control signal input terminal as noise. Flowing in may cause malfunction. Since the parasitic capacitance is inversely proportional to the distance between the terminals, if the distance between the terminals is small, the parasitic capacitance increases, noise increases, and the influence of noise on the control signal increases.

本発明は上記のような問題点を解消するためになされたもので、半導体装置を小型化できるとともに、制御信号にノイズが与える影響を低減した半導体装置を提供することを目的とする。   The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the size of the semiconductor device can be reduced and the influence of noise on the control signal is reduced.

本発明に係る請求項１記載の半導体装置は、高電位の第１の主電源端子と低電位の第２の主電源端子との間に直列に介挿され、相補的に動作する少なくとも１組の第１および第２のスイッチング素子と、高電位側の前記第１のスイッチング素子の駆動制御を行う第１の制御回路と、低電位側の前記第２のスイッチング素子の駆動制御を行う第２の制御回路と、を備え、前記少なくとも１組の第１および第２のスイッチング素子、前記第１および第２の制御回路が平面視矩形のパッケージ部に樹脂封止される半導体装置であって、前記第１の制御回路に接続される複数の端子および、前記第２の制御回路に接続される複数の端子が前記パッケージ部の一側面から突出するように配設され、前記第１の制御回路に接続される前記複数の端子のうち、高電位側に属する複数の高電位端子が前記パッケージ部の前記一側面の長辺に沿った方向の一方端寄りの位置に高電位端子列として配列され、前記第１の制御回路に接続される前記複数の端子のうち、低電位側に属する複数の低電位端子が、前記高電位端子列に続いて第１の低電位端子列として配列され、前記第２の制御回路に接続される前記複数の端子が、前記第１の低電位端子列に続いて第２の低電位端子列として配列される。   According to a first aspect of the present invention, there is provided at least one set of semiconductor devices that are inserted in series between a high-potential first main power supply terminal and a low-potential second main power supply terminal and operate in a complementary manner. First and second switching elements, a first control circuit for controlling the driving of the first switching element on the high potential side, and a second for controlling the driving of the second switching element on the low potential side. And at least one set of the first and second switching elements, and the first and second control circuits are resin-sealed in a rectangular package portion in plan view, A plurality of terminals connected to the first control circuit and a plurality of terminals connected to the second control circuit are disposed so as to protrude from one side surface of the package part, and the first control circuit Of the plurality of terminals connected to A plurality of high potential terminals belonging to the high potential side are arranged as a high potential terminal row at a position near one end in the direction along the long side of the one side surface of the package part, and are connected to the first control circuit. Among the plurality of terminals, a plurality of low potential terminals belonging to a low potential side are arranged as a first low potential terminal row following the high potential terminal row, and are connected to the second control circuit. Are arranged as a second low potential terminal row following the first low potential terminal row.

本発明に係る請求項１記載の半導体装置によれば、高電位側に属する複数の高電位端子がパッケージ部の一側面の長辺に沿った方向の一方端寄りの位置に高電位端子列として配列され、低電位側に属する複数の低電位端子が、高電位端子列に続いて第１の低電位端子列として配列され、第２の制御回路に接続される複数の端子が、第１の低電位端子列に続いて第２の低電位端子列として配列されるので、高電位端子の配設領域と低電位端子の配設領域とが完全に分離されることになる。このため、高電位端子と低電位端子とが隣り合うのは、１箇所だけとなり、高電位端子と低電位端子との間に存在する寄生容量が小さくなる。従って、例えば低電位の制御信号入力端子と高電位の基準電位端子との間の寄生容量に起因して発生するノイズが小さくなって、ノイズが制御信号に与える影響を小さくできる。また、高電位端子だけを並べて配設することで、高電位端子と低電位端子とを交互に配設する場合に比べて、絶縁距離確保のためのスペースを大幅に削減することができる。   According to the semiconductor device of the first aspect of the present invention, the plurality of high potential terminals belonging to the high potential side are arranged as a high potential terminal row at a position near one end in the direction along the long side of one side surface of the package portion. A plurality of low potential terminals arranged on the low potential side are arranged as a first low potential terminal row following the high potential terminal row, and a plurality of terminals connected to the second control circuit are connected to the first control circuit. Since the second low potential terminal row is arranged following the low potential terminal row, the high potential terminal placement region and the low potential terminal placement region are completely separated. For this reason, the high potential terminal and the low potential terminal are adjacent to each other only in one place, and the parasitic capacitance existing between the high potential terminal and the low potential terminal is reduced. Therefore, for example, noise generated due to parasitic capacitance between the low-potential control signal input terminal and the high-potential reference potential terminal is reduced, and the influence of the noise on the control signal can be reduced. Further, by arranging only the high potential terminals side by side, the space for securing the insulation distance can be greatly reduced as compared with the case where the high potential terminals and the low potential terminals are alternately arranged.

＜実施の形態＞
＜Ａ．装置構成＞
図１に本発明に係る実施の形態の半導体装置として、３相ブリッジ回路を有するインバータモジュール１００の外観平面図を示す。 <Embodiment>
<A. Device configuration>
FIG. 1 shows an external plan view of an inverter module 100 having a three-phase bridge circuit as a semiconductor device according to an embodiment of the present invention.

図１に示すように、インバータモジュール１００は、トランスファモールドによって形成されたパッケージ部ＰＧの２つの長手側面に、それぞれ１列に端子列が設けられたＤＩＰ（Dual-In-line Package）構造となっている。   As shown in FIG. 1, the inverter module 100 has a DIP (Dual-In-line Package) structure in which terminal rows are provided in one row on each of two longitudinal side surfaces of a package portion PG formed by transfer molding. ing.

それぞれの端子列は、一方が制御回路側端子列１０であり、他方が出力側端子列２０である。ここで、制御回路側端子列１０はスイッチングデバイスを駆動制御するための制御回路、すなわち、低電圧集積回路（ＬＶＩＣ：Low Voltage Integrated Circuit）や、高電圧集積回路（ＨＶＩＣ：High Voltage Integrated Circuit）に関連する端子の配列であり、出力側端子列２０は、スイッチングデバイスの出力端子および、インバータモジュール１００の主電源端子の配列である。   One of the terminal rows is the control circuit side terminal row 10 and the other is the output side terminal row 20. Here, the control circuit side terminal array 10 is a control circuit for driving and controlling the switching device, that is, a low voltage integrated circuit (LVIC) or a high voltage integrated circuit (HVIC). The output side terminal row 20 is an arrangement of the output terminals of the switching device and the main power supply terminals of the inverter module 100.

なお、インバータモジュール１００は、スイッチングデバイスだけでなくスイッチングデバイスを駆動制御するための制御回路を含んでおり、いわゆるＩＰＭ（Intelligent Power Module）と呼ばれる装置である。   The inverter module 100 includes a control circuit for driving and controlling the switching device as well as the switching device, and is a so-called IPM (Intelligent Power Module) device.

制御回路側端子列１０は、高電位端子の配設領域と低電位端子の配設領域とが完全に分離された構成を採っている。すなわち、パッケージ部ＰＧの図１に向かって左端から６本目までの端子が高電位側に属する高電位端子であり、それ以外の端子が低電位側に属する低電位端子となっている。なお、各端子の機能については図２を用いて説明する。   The control circuit side terminal row 10 has a configuration in which a high potential terminal arrangement region and a low potential terminal arrangement region are completely separated. In other words, the sixth terminal from the left end of the package part PG in FIG. 1 is a high potential terminal belonging to the high potential side, and the other terminals are low potential terminals belonging to the low potential side. The function of each terminal will be described with reference to FIG.

一方、出力側端子列２０は、パッケージ部ＰＧの図１に向かって左端側および右端側に、それぞれ主電源端子Ｐおよび主電源端子Ｎが配設され、両者の間に出力端子Ｕ、ＶおよびＷが配列されている。   On the other hand, the output side terminal row 20 is provided with a main power terminal P and a main power terminal N on the left end side and the right end side of the package part PG in FIG. 1, respectively, and the output terminals U, V and W is arranged.

以下、図２に示すブロック図を用いて、インバータモジュール１００の内部構成の一例を説明する。   Hereinafter, an example of the internal configuration of the inverter module 100 will be described with reference to the block diagram shown in FIG.

図２に示すように、主電源端子となるＰ−Ｎ端子間（高電位の主電源端子Ｐと低電位の主電源端子Ｎとの間）に、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）などのパワーデバイスであるトランジスタ１１および１２、２１および２２、３１および３２の組がトーテムポール接続され、それぞれの接続ノードがモジュールのＵ相、Ｖ相、Ｗ相の出力端子Ｕ、Ｖ、Ｗに接続されている。なお、これらのモジュールの端子の配列が出力側端子列２０である。   As shown in FIG. 2, power such as an IGBT (insulated gate bipolar transistor) is provided between the PN terminals (between the high potential main power supply terminal P and the low potential main power supply terminal N) as the main power supply terminals. A set of transistors 11 and 12, 21 and 22, 31 and 32, which are devices, are totem-pole connected, and their connection nodes are connected to output terminals U, V, and W of the U phase, V phase, and W phase of the module. Yes. The arrangement of the terminals of these modules is the output side terminal row 20.

また、トランジスタ１１、１２、２１、２２、３１および３２には、それぞれフリーホイールダイオード１１１、１２１、２１１、２２１、３１１および３２１が逆並列接続されている。   Further, free wheel diodes 111, 121, 211, 221, 311 and 321 are connected in reverse parallel to the transistors 11, 12, 21, 22, 31 and 32, respectively.

そして、高電位側デバイスであるトランジスタ１１、２１および３１をそれぞれ制御するため、制御回路ＨＩＣ１、ＨＩＣ２およびＨＩＣ３が配設されている。なお、制御回路ＨＩＣ１〜ＨＩＣ３は、いわゆるＨＶＩＣであり、機能的に同じものであるので、端子符号は同じものとする。   Control circuits HIC1, HIC2, and HIC3 are provided to control the transistors 11, 21, and 31, which are high potential side devices, respectively. Since the control circuits HIC1 to HIC3 are so-called HVICs and are functionally the same, the terminal symbols are the same.

トランジスタ１１、１２および１３の各々のゲート電極には、制御回路ＨＩＣ１、ＨＩＣ２およびＨＩＣ３のそれぞれの制御信号出力端子ＯＵＴから制御信号が与えられる構成となっている。   A control signal is applied to each gate electrode of the transistors 11, 12, and 13 from each control signal output terminal OUT of the control circuits HIC 1, HIC 2, and HIC 3.

また、制御回路ＨＩＣ１〜ＨＩＣ３の各基準電位端子ＶＳは、それぞれ出力端子Ｕ、Ｖ、Ｗに接続されるとともに、モジュールの基準電位端子ＶUS、ＶVS、ＶWSに接続されている。また、制御回路ＨＩＣ１〜ＨＩＣ３の各駆動電圧端子ＶＢは、それぞれモジュールの駆動電圧端子ＶUB、ＶVB、ＶWBに接続されている。なお、基準電位端子ＶＳは、高電位側の基準電位を各ＩＣ内に供給する端子である。 The reference potential terminals VS of the control circuits HIC1 to HIC3 are connected to the output terminals U, V, and W, respectively, and are connected to the reference potential terminals V US , V VS , and V WS of the module. The drive voltage terminals VB of the control circuits HIC1 to HIC3 are connected to the drive voltage terminals V UB , V VB , and V WB of the modules, respectively. The reference potential terminal VS is a terminal that supplies a reference potential on the high potential side into each IC.

また、制御回路ＨＩＣ１〜ＨＩＣ３は、何れも駆動電圧端子ＶCC、接地端子ＧＮＤ、制御信号入力端子ＩＮを有している。 Each of the control circuits HIC1 to HIC3 has a drive voltage terminal V CC , a ground terminal GND, and a control signal input terminal IN.

そして、制御回路ＨＩＣ１〜ＨＩＣ３の各駆動電圧端子ＶCCは、それぞれモジュールの駆動電圧端子ＶＰ１、ＶＰ２およびＶＰ３に接続され、各接地端子ＧＮＤはモジュールの接地端子ＶＰＣに共通に接続されている。 The drive voltage terminals V CC of the control circuits HIC1 to HIC3 are connected to the drive voltage terminals VP1, VP2, and VP3 of the module, respectively, and the ground terminals GND are commonly connected to the module ground terminal VPC.

また、制御回路ＨＩＣ１〜ＨＩＣ３の各制御信号入力端子ＩＮは、それぞれモジュールの制御信号入力端子ＩＮ１、ＩＮ２およびＩＮ３に接続されている。   The control signal input terminals IN of the control circuits HIC1 to HIC3 are connected to the control signal input terminals IN1, IN2, and IN3 of the module, respectively.

また、インバータモジュール１００内には、低電位側デバイスであるトランジスタ１２、２２および３２を制御するため、制御回路ＬＩＣが配設されている。なお、制御回路ＬＩＣは、いわゆるＬＶＩＣである。   Further, in the inverter module 100, a control circuit LIC is disposed to control the transistors 12, 22, and 32 that are low potential side devices. The control circuit LIC is a so-called LVIC.

トランジスタ１２、２２および３２の各ゲート電極には、それぞれ制御回路ＬＩＣの制御信号出力端子ＵＯＵＴ、ＶＯＵＴおよびＷＯＵＴから制御信号が与えられる構成となっている。   The gate electrodes of the transistors 12, 22 and 32 are configured to receive control signals from the control signal output terminals UOUT, VOUT and WOUT of the control circuit LIC.

また、制御回路ＬＩＣの基準電位端子ＶＮＯは、モジュールの低電位側の主電源端子Ｎに接続されている。なお、基準電位端子ＶＮＯは低電位側の基準電位（接地電位）を制御回路ＬＩＣ内に供給する端子である。   The reference potential terminal VNO of the control circuit LIC is connected to the main power supply terminal N on the low potential side of the module. The reference potential terminal VNO is a terminal for supplying a reference potential (ground potential) on the low potential side into the control circuit LIC.

また、制御回路ＬＩＣは、トランジスタ１２、２２および３２のそれぞれを制御するための制御信号が与えられる制御信号入力端子ＵＩＮ、ＶＩＮおよびＷＩＮを有するとともに、駆動電圧端子ＶCC、フォールト端子ＦO、エラー時間設定端子ＣＦO、電流検出端子ＣＩＮＬ、接地端子ＧＮＤを有している。 The control circuit LIC has control signal input terminals UIN, VIN, and WIN to which control signals for controlling the transistors 12, 22, and 32 are respectively supplied, and includes a drive voltage terminal V CC , a fault terminal F O , an error It has a time setting terminal CF O , a current detection terminal CINL, and a ground terminal GND.

そして、制御回路ＬＩＣの駆動電圧端子ＶCC、フォールト端子ＦO、エラー時間設定端子ＣＦO、電流検出端子ＣＩＮＬおよび接地端子ＧＮＤは、それぞれモジュールの駆動電圧端子ＶＮ１、フォールト端子ＦＯ、エラー時間設定端子ＣＦＯ、電流検出端子ＣＩＮおよび接地端子ＶＮＣに接続されている。 The drive voltage terminal V CC , fault terminal F O , error time setting terminal CF O , current detection terminal CINL and ground terminal GND of the control circuit LIC are the module drive voltage terminal VN1, fault terminal FO and error time setting terminal, respectively. The CFO, the current detection terminal CIN, and the ground terminal VNC are connected.

また、制御回路ＬＩＣの制御信号入力端子ＵＩＮ、ＶＩＮおよびＷＩＮは、それぞれモジュールの制御信号入力端子ＵＮ、ＶＮおよびＷＮに接続されている。   The control signal input terminals UIN, VIN and WIN of the control circuit LIC are connected to the control signal input terminals UN, VN and WN of the module, respectively.

図２に示すように、モジュールの駆動電圧端子ＶUB、ＶVBおよびＶWBのそれぞれは、対応する各相の基準電位端子ＶUS、ＶVSおよびＶWSと対をなすように配設されている。これらの端子は何れも高電位端子であり、高電位端子列ＨＶをなしている。残りの端子は何れも低電位端子であり、制御回路ＨＩＣ１〜ＨＩＣ３に接続される複数の端子のうち、低電位となる複数の端子が、低電位端子列ＬＶ１（第１の低電位端子列）として、高電位端子列ＨＶに続いて配列され、制御回路ＬＩＣに接続される複数の端子が、低電位端子列ＬＶ２（第２の低電位端子列）として、低電位端子列ＬＶ１に続いて配列される。 As shown in FIG. 2, each of the drive voltage terminals V UB , V VB, and V WB of the module is arranged to make a pair with the corresponding reference potential terminals V US , V VS, and V WS . Yes. These terminals are all high-potential terminals and form a high-potential terminal array HV. The remaining terminals are all low-potential terminals, and among the plurality of terminals connected to the control circuits HIC1 to HIC3, a plurality of terminals having a low potential are the low-potential terminal row LV1 (first low-potential terminal row). A plurality of terminals arranged following the high potential terminal row HV and connected to the control circuit LIC are arranged as the low potential terminal row LV2 (second low potential terminal row) following the low potential terminal row LV1. Is done.

なお、高電位端子の配列順序はパッケージ部ＰＧの端からＶUB、ＶUS、ＶVB、ＶVS、ＶWB、ＶWSとした例を示したが、この順序に限定されるものではない。また、低電位端子の配列順序も図２の順序に限定されるものではない。 In addition, although the example in which the arrangement order of the high potential terminals is V UB , V US , V VB , V VS , V WB , V WS from the end of the package part PG is shown, it is not limited to this order. Further, the arrangement order of the low potential terminals is not limited to the order shown in FIG.

＜Ｂ．効果＞
以上説明したように、制御回路側端子列１０においては、高電位端子の配設領域と低電位端子の配設領域とを完全に分離しているので、高電位端子と低電位端子とが隣り合うのは、基準電位端子ＶWSと駆動電圧端子ＶＰ１だけとなり、低電位端子である制御信号入力端子ＩＮ１、ＩＮ２およびＩＮ３は、高電位の基準電位端子のいずれとも隣り合うこともまた、制御信号入力端子ＩＮ１以外は高電位の基準電位端子のいずれとも近接することもない。 <B. Effect>
As described above, in the control circuit side terminal row 10, the high-potential terminal arrangement area and the low-potential terminal arrangement area are completely separated, so that the high-potential terminal and the low-potential terminal are adjacent to each other. Only the reference potential terminal V WS and the drive voltage terminal VP1 are matched, and the control signal input terminals IN1, IN2, and IN3, which are low potential terminals, are adjacent to any of the high potential reference potential terminals. Other than the input terminal IN1, there is no proximity to any of the high potential reference potential terminals.

このため、制御信号入力端子と基準電位端子との間に存在する寄生容量が小さくなり、寄生容量に起因して発生するノイズが小さくなって、ノイズが制御信号に与える影響を小さくできる。   For this reason, the parasitic capacitance existing between the control signal input terminal and the reference potential terminal is reduced, noise generated due to the parasitic capacitance is reduced, and the influence of the noise on the control signal can be reduced.

また、高電位端子だけを並べて配設することで、高電位端子と低電位端子とを交互に配設する場合に比べて、絶縁距離確保のためのスペースを大幅に削減することができる。   Further, by arranging only the high potential terminals side by side, the space for securing the insulation distance can be greatly reduced as compared with the case where the high potential terminals and the low potential terminals are alternately arranged.

すなわち、図１に示すように、Ｕ相、Ｖ相およびＷ相ごとに配設される駆動電圧端子と基準電位端子との各端子対は、相間短絡を防ぐためにスペースＬ１を隔てて配設されるが、スペースＬ１は２カ所に設けるだけで良く、高電位端子である基準電位端子ＶWSと低電位端子である駆動電圧端子ＶＰ１との間には、地絡を防ぐためのスペースＬ２を設けるので、絶縁距離として比較的大きな距離が必要となるスペースは３カ所だけで済むことになる。従って、当該スペースが５〜６カ所は必要であった従来装置に比べて端子の配設領域を小さくすることができ、モジュールの小型化が可能となる。 That is, as shown in FIG. 1, each terminal pair of the drive voltage terminal and the reference potential terminal arranged for each of the U phase, the V phase, and the W phase is arranged with a space L1 therebetween to prevent a short circuit between the phases. However, the space L1 only needs to be provided in two places, and a space L2 for preventing a ground fault is provided between the reference potential terminal V WS which is a high potential terminal and the drive voltage terminal VP1 which is a low potential terminal. Therefore, only three spaces need a relatively large distance as an insulation distance. Accordingly, the area where the terminals are arranged can be reduced as compared with the conventional device which requires 5 to 6 spaces, and the module can be miniaturized.

なお、スペースＬ１は、スペースＬ２と同じ距離に設定しても良いし、スペースＬ２よりも小さく設定しても良い。この場合はモジュールのさらなる小型化が可能となる。   The space L1 may be set to the same distance as the space L2, or may be set smaller than the space L2. In this case, the module can be further miniaturized.

また、制御回路ＨＩＣ１〜ＨＩＣ３の各接地端子はモジュールの接地端子ＶＰＣに接続され、制御回路ＬＩＣの接地端子はモジュールの接地端子ＶＮＣに接続される構成としたので、高電位側の制御回路および低電位側の制御回路に、それぞれ独立して接地電位を与えることができる。   Further, since the ground terminals of the control circuits HIC1 to HIC3 are connected to the ground terminal VPC of the module and the ground terminal of the control circuit LIC is connected to the ground terminal VNC of the module, A ground potential can be independently applied to the control circuit on the potential side.

また、以上の説明では、３相ブリッジ回路を有するインバータを例として説明したが、本発明の適用は３相インバータに限定されるものではなく、高電位端子と低電位端子とがパッケージの一側面から突出する半導体モジュールであれば適用可能である。   In the above description, an inverter having a three-phase bridge circuit has been described as an example. However, the application of the present invention is not limited to a three-phase inverter, and a high-potential terminal and a low-potential terminal are provided on one side of the package. Any semiconductor module protruding from the above can be applied.

＜Ｃ．変形例１＞
以上説明したインバータモジュール１００においては、図１および図２に示したように、モジュールの低電位側の主電源端子Ｎは１つであり、そこに、制御回路ＬＩＣの基準電位端子ＶＮＯおよびトランジスタ１２、２２および３２のエミッタが共通に接続される構成となっていたが、図３および図４に示すインバータモジュール１００Ａのように、低電位側の主電源端子を各相のトランジスタごとに設けるようにしても良い。 <C. Modification 1>
In the inverter module 100 described above, as shown in FIGS. 1 and 2, there is one main power supply terminal N on the low potential side of the module, which includes the reference potential terminal VNO of the control circuit LIC and the transistor 12. , 22 and 32 are connected in common. However, as in the inverter module 100A shown in FIGS. 3 and 4, a low-potential main power supply terminal is provided for each phase transistor. May be.

すなわち、図３に示すように、出力側端子列２０Ａにおいて、パッケージ部ＰＧの図３に向かって右端側に、主電源端子ＮＷ、ＮＶおよびＮＵが配設するようにしても良い。   That is, as shown in FIG. 3, in the output side terminal row 20A, the main power supply terminals NW, NV and NU may be arranged on the right end side of the package part PG in FIG.

インバータモジュール１００Ａの内部構成は、図４に示すように、Ｕ相のトランジスタ１２のエミッタが主電源端子ＮＵに接続され、Ｖ相のトランジスタ２２のエミッタが主電源端子ＮＶに接続され、Ｗ相のトランジスタ３２のエミッタが主電源端子ＮＷに接続される構成となっている。ここで、主電源端子ＮＷには、制御回路ＬＩＣの基準電位端子ＶＮＯも接続されている。   As shown in FIG. 4, the internal configuration of the inverter module 100A is such that the emitter of the U-phase transistor 12 is connected to the main power supply terminal NU, the emitter of the V-phase transistor 22 is connected to the main power supply terminal NV, The emitter of the transistor 32 is connected to the main power supply terminal NW. Here, the reference potential terminal VNO of the control circuit LIC is also connected to the main power supply terminal NW.

なお、図１および図２を用いて説明したインバータモジュール１００と同一の構成については同一の符号を付し、重複する説明は省略する。   In addition, the same code | symbol is attached | subjected about the structure same as the inverter module 100 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

このような構成を採ることで、各トランジスタの近くに主電源端子を配設することが可能となり、トランジスタのエミッタと主電源端子との間の配線長さを短くできる。このため、例えばワイヤボンディングにより配線を行う場合には、ワイヤどうしの接触や、樹脂封止工程でのワイヤ流を防止することができる。   By adopting such a configuration, it is possible to dispose the main power supply terminal near each transistor, and the wiring length between the emitter of the transistor and the main power supply terminal can be shortened. For this reason, for example, when wiring is performed by wire bonding, it is possible to prevent contact between wires and wire flow in a resin sealing process.

＜Ｄ．変形例２＞
また、インバータモジュール１００においては、図１および図２に示したように、制御回路ＨＩＣ１〜ＨＩＣ３の各接地端子ＧＮＤはモジュールの接地端子ＶＰＣに共通に接続され、制御回路ＬＩＣの接地端子ＧＮＤはモジュールの接地端子ＶＮＣに接続される構成となっていたが、図５および図６に示すインバータモジュール１００Ｂのように、接地端子は接地端子ＶＮＣの１本だけとしても良い。 <D. Modification 2>
In the inverter module 100, as shown in FIGS. 1 and 2, the ground terminals GND of the control circuits HIC1 to HIC3 are commonly connected to the module ground terminal VPC, and the ground terminal GND of the control circuit LIC is connected to the module. However, as in the inverter module 100B shown in FIGS. 5 and 6, only one ground terminal VNC may be provided.

すなわち、図５に示すように、制御回路側端子列１０Ａにおいては、図１において示されていた接地端子ＶＰＣを有さない構成となっている。   That is, as shown in FIG. 5, the control circuit side terminal row 10A is configured not to have the ground terminal VPC shown in FIG.

インバータモジュール１００Ｂの内部構成は、図４に示すように、制御回路ＨＩＣ１〜ＨＩＣ３の各接地端子ＧＮＤおよび制御回路ＬＩＣの接地端子ＧＮＤはモジュールの接地端子ＶＰＣに共通に接続される構成となっている。   As shown in FIG. 4, the internal configuration of the inverter module 100B is such that the ground terminals GND of the control circuits HIC1 to HIC3 and the ground terminal GND of the control circuit LIC are commonly connected to the module ground terminal VPC. .

なお、図１および図２を用いて説明したインバータモジュール１００と同一の構成については同一の符号を付し、重複する説明は省略する。   In addition, the same code | symbol is attached | subjected about the structure same as the inverter module 100 demonstrated using FIG. 1 and FIG. 2, and the overlapping description is abbreviate | omitted.

このような構成を採ることで、制御回路側端子の個数を減らすことができ、モジュールのさらなる小型化が可能となる。   By adopting such a configuration, the number of control circuit side terminals can be reduced, and the module can be further miniaturized.

本発明に係る半導体装置の実施の形態のモジュールの構成を説明する外観平面図である。It is an external appearance top view explaining the structure of the module of embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態のモジュールの構成を説明するブロック図である。It is a block diagram explaining the structure of the module of embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態のモジュールの変形例１の構成を説明する外観平面図である。It is an external appearance top view explaining the structure of the modification 1 of the module of embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態のモジュールの変形例１の構成を説明するブロック図である。It is a block diagram explaining the structure of the modification 1 of the module of embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態のモジュールの変形例２の構成を説明する外観平面図である。It is an external appearance top view explaining the structure of the modification 2 of the module of embodiment of the semiconductor device which concerns on this invention. 本発明に係る半導体装置の実施の形態のモジュールの変形例２の構成を説明するブロック図である。It is a block diagram explaining the structure of the modification 2 of the module of embodiment of the semiconductor device which concerns on this invention.

符号の説明Explanation of symbols

ＨＩＣ１〜ＨＩＣ３，ＬＩＣ 制御回路、ＨＶ 高電位端子列、ＬＶ１，ＬＶ２ 低電位端子列。
HIC1 to HIC3, LIC control circuit, HV high potential terminal row, LV1, LV2 low potential terminal row.

Claims (4)

高電位の第１の主電源端子と低電位の第２の主電源端子との間に直列に介挿され、相補的に動作する少なくとも１組の第１および第２のスイッチング素子と、
高電位側の前記第１のスイッチング素子の駆動制御を行う第１の制御回路と、
低電位側の前記第２のスイッチング素子の駆動制御を行う第２の制御回路と、を備え、
前記少なくとも１組の第１および第２のスイッチング素子、前記第１および第２の制御回路が平面視矩形のパッケージ部に樹脂封止される半導体装置であって、
前記第１の制御回路に接続される複数の端子および、前記第２の制御回路に接続される複数の端子が前記パッケージ部の一側面から突出するように配設され、
前記第１の制御回路に接続される前記複数の端子のうち、高電位側に属する複数の高電位端子が前記パッケージ部の前記一側面の長辺に沿った方向の一方端寄りの位置に高電位端子列として配列され、
前記第１の制御回路に接続される前記複数の端子のうち、低電位側に属する複数の低電位端子が、前記高電位端子列に続いて第１の低電位端子列として配列され、
前記第２の制御回路に接続される前記複数の端子が、前記第１の低電位端子列に続いて第２の低電位端子列として配列される、半導体装置。 At least one set of first and second switching elements which are inserted in series between a first main power supply terminal having a high potential and a second main power supply terminal having a low potential, and operate in a complementary manner;
A first control circuit for controlling the driving of the first switching element on the high potential side;
A second control circuit for controlling the driving of the second switching element on the low potential side,
A semiconductor device in which the at least one set of first and second switching elements and the first and second control circuits are resin-sealed in a rectangular package portion in plan view,
A plurality of terminals connected to the first control circuit and a plurality of terminals connected to the second control circuit are arranged so as to protrude from one side surface of the package part,
Among the plurality of terminals connected to the first control circuit, a plurality of high potential terminals belonging to a high potential side are high at a position near one end in a direction along the long side of the one side surface of the package portion. Arranged as a potential terminal array,
Among the plurality of terminals connected to the first control circuit, a plurality of low potential terminals belonging to a low potential side are arranged as a first low potential terminal row following the high potential terminal row,
The semiconductor device, wherein the plurality of terminals connected to the second control circuit are arranged as a second low potential terminal row following the first low potential terminal row. 前記少なくとも１組の第１および第２のスイッチング素子は、複数組の第１および第２のスイッチング素子を含み、
前記第２の主電源端子は、
前記複数組の第１および第２のスイッチング素子のそれぞれに対応して複数設けられ、
前記複数組の第１および第２のスイッチング素子のそれぞれの出力端子、前記第１の主電源端子および前記複数の第２の主電源端子は前記パッケージ部の前記一側面と平行な側面から突出するように配設される、請求項１記載の半導体装置。 The at least one set of first and second switching elements includes a plurality of sets of first and second switching elements;
The second main power supply terminal is
A plurality of first and second switching elements corresponding to each of the plurality of sets;
The respective output terminals of the plurality of sets of first and second switching elements, the first main power supply terminals, and the plurality of second main power supply terminals protrude from side surfaces parallel to the one side surface of the package portion. The semiconductor device according to claim 1, arranged as described above. 前記第１および第２の制御回路は、それぞれ第１および第２の接地端子を備え、
前記第１および第２の接地端子は、それぞれ前記第１および第２の低電位端子列に含まれる第１および第２のモジュール接地端子に接続される、請求項１記載の半導体装置。 The first and second control circuits include first and second ground terminals, respectively.
2. The semiconductor device according to claim 1, wherein the first and second ground terminals are respectively connected to first and second module ground terminals included in the first and second low potential terminal rows. 前記第１および第２の制御回路は、それぞれ第１および第２の接地端子を備え、
前記第１および第２の接地端子は、前記第２の低電位端子列に含まれるモジュール接地端子に共通に接続される、請求項１記載の半導体装置。
The first and second control circuits include first and second ground terminals, respectively.
2. The semiconductor device according to claim 1, wherein the first and second ground terminals are commonly connected to a module ground terminal included in the second low potential terminal row.
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