JP4096506B2 - ASK modulation circuit - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The present invention relates to an ASK (Amplitude Shift Keying) modulation circuit, and more particularly to an ASK modulation circuit suitable for application to a wireless communication system.
[0002]
[Background]
At present, an ETC (Electric Toll Collection) system that can collect tolls at toll roads such as toll roads unattended and without stopping the vehicle is attracting attention. In the ETC system, a toll is automatically deducted from a bank account of a vehicle owner by radio communication between a radio beacon installed beside a road and an in-vehicle terminal device. At this time, as a modulation method in the wireless communication, for example, an ASK modulation method using a 5.8 [GHz] band is used.
[0003]
In the ASK modulation method, when data to be wirelessly transmitted is at a logical level “H”, radio waves are transmitted only during that period, and when the data is at a logical level “L”, transmission of radio waves is stopped during that period. Thus, data communication is established.
FIG. 1 is a diagram showing a configuration of a conventional ASK modulation circuit.
In FIG. 1, the local oscillation circuit 1 generates a 5.8 [GHz] band radio carrier signal (hereinafter simply referred to as a carrier signal) and supplies it to the buffer amplifier 2. The buffer amplifier 2 supplies an amplified carrier signal obtained by amplifying the carrier signal to a gate terminal G of a gallium arsenide (GaAs) -field effect transistor 5 (hereinafter referred to as FET 5) as a modulator. A digital input data signal to be transmitted is supplied to the drain terminal D of the FET 5 through the input terminal 3 and the high frequency choke coil 4. The source terminal S of the FET 5 is grounded.
[0004]
According to the above configuration, power is supplied to the FET 5 while the input data signal input via the input terminal 3 is at the logic level “H”. Therefore, the FET 5 sends the amplified carrier signal supplied to the gate terminal G to the power amplifier circuit 6 via the drain terminal D. On the other hand, during a period in which the data signal input through the input terminal 3 is at the logic level “L”, the power is not supplied to the FET 5. Therefore, at this time, the FET 5 greatly attenuates the amplified carrier signal supplied to the gate terminal G and sends it to the power amplifier circuit 6.
[0005]
That is, the FET 5 sends the amplified carrier signal supplied from the buffer amplifier 2 to the power amplifier circuit 6 while the input data signal is at the logic level “H”, while the input data signal is at the logic level “L”. During this period, the transmission of the amplified carrier signal to the power amplifier circuit 6 is stopped. By such an operation, a carrier wave signal that is intermittently synchronized with a change in the logic level of the input data signal, that is, an ASK modulation signal of 5.8 [GHz] band is obtained on the output side (drain terminal D) of the FET. become.
[0006]
The 5.8 [GHz] band ASK modulation signal sent from the FET 5 as the modulator is amplified to a predetermined power level by the power amplifier circuit 6 and then supplied to the band pass filter 7. The band pass filter 7 supplies the amplified ASK modulated signal, from which spurious radiation components unnecessary for communication are removed, to an antenna element (not shown) via the antenna terminal 9. The antenna element radiates the ASK modulated signal from the spurious radiation component supplied from the band pass filter 7 as a radio wave.
[0007]
Here, the input data signal is a Manchester-encoded short wave having a transmission rate of 2.048 [MHz] having characteristics as shown in the following equation.
10 · log ₁₀ [sin ⁴ (πf / 2 · 10 ⁶ ) / (πf / 2 · 10 ⁶ ) ² ]
Therefore, if the FET 5 is turned ON / OFF by the input data signal as described above and the 5.8 [GHz] band carrier signal is ASK modulated as it is, the spectrum has an infinitely wide spectrum at the frequency of the modulation wave. Become. Therefore, in order to effectively use the frequency resource, it is necessary to limit the band of the modulated wave to such an extent that the recoverability to the digital data signal can be ensured during demodulation. At this time, the band limitation of the modulated wave is
(1) The band pass filter 7 passes only the low frequency band among the frequency components constituting the short wave of the input data signal.
[0008]
(2) The modulated wave in which the envelope of the carrier wave signal is changed by the FET 5 is output so as to have a linear relationship with the amplitude voltage of the band-limited input signal.
It can be realized by such means.
FIG. 2 is a diagram showing a configuration of a conventional ASK modulation circuit in which band limiting is performed by employing the above-described means.
[0009]
The configuration shown in FIG. 2 is the same as the configuration shown in FIG. 1 except that the driver 10 performs current amplification for securing the current necessary for impedance conversion and the operation of the FET 5, and the frequency constituting the short wave of the input data signal. A band limiting filter 11 that passes only a low frequency band among the components is added. The input data signal input to the input terminal 3 is supplied to the drain terminal D of the FET 5 through the driver 10, the band limiting filter 11 and the high frequency choke coil 4.
[0010]
With this configuration, the FET 5 as the modulator shown in FIG. 2 has a carrier signal from the local oscillating unit 1 so as to maintain a linear relationship with the amplitude voltage of the input data signal band-limited by the band-limiting filter 11. Change the envelope.
However, the above-described conventional ASK modulation circuit has the following problems.
[0011]
Since the FET 5 as a modulator used in the ASK modulation circuit is a non-linear element, it has a drain-source voltage versus output voltage characteristic as shown in FIG. Therefore, when the FET 5 is operated outside the linear operation region as shown in FIG. 3, a linear relationship can be maintained between the amplitude voltage waveform of the band-limited input data signal and the envelope of the voltage waveform of the ASK modulation signal. Disappear.
[0012]
FIG. 4 is a diagram showing an eye pattern in the case where the envelope of the voltage waveform of the ASK modulation signal is represented by being temporally overlapped for each transition of the logic level of the input data signal.
FIG. 4A is a diagram showing an eye pattern when the FET 5 is operated in the non-linear operation region, and the voltage waveform of the ASK modulation signal is distorted by the non-linear characteristics. On the other hand, FIG. 4B is a diagram showing an eye pattern when the FET 5 is operated in the linear operation region.
[0013]
As shown in FIG. 4B, if the waveform of the ASK modulation signal is not distorted, the ASK when the input data signal changes from the logic level “H” to “L” and from “L” to “H”. The voltage value at the cross point B or C of the modulation signal is an intermediate value between the maximum amplitude and the minimum amplitude of the ASK modulation signal. On the other hand, when the voltage waveform of the ASK modulation signal is distorted, the voltage value at the cross point does not match the maximum amplitude and the minimum intermediate value of the ASK modulation signal, as shown in FIG.
[0014]
A demodulator that receives and demodulates such an ASK modulated signal performs binarization after removing the high frequency signal component by performing envelope detection on the ASK modulated signal. The binarization circuit provided in the demodulating unit has a logic level “H” during a period when the detected analog signal is larger than a predetermined threshold voltage, and a logic level “L” during a period when the analog signal is small. Is output as a demodulated data signal.
[0015]
Therefore, when the duty ratio of the input data signal is “1”, that is, the ratio between the period in which the input data signal is at the logic level “H” and the period in which the input data signal is “L” is “1”, binary The digitizing circuit must output a demodulated data signal with a duty ratio of “1”.
At this time, when the waveform of the ASK modulation signal is shown in FIG. 4B, the voltage value at the cross point B or C is equal to the intermediate voltage Vs between the maximum amplitude value and the minimum amplitude value of the ASK modulation signal. Therefore, the binarization circuit performs the binarization as described above by using the intermediate voltage Vs as the threshold voltage. According to such binarization, a data signal having the same duty ratio as that of the input data signal can be demodulated.
[0016]
However, for example, as shown in FIG. 4A, the cross point is higher than the intermediate voltage Vs between the maximum amplitude value and the minimum amplitude value. As shown in FIG. When binarization is performed, the duty ratio becomes smaller than “1”.
Therefore, when ASK modulation is performed using the nonlinear region of the transistor (FET 5), the level at the cross point is shifted from the intermediate value between the maximum amplitude value and the minimum amplitude value of the modulation signal. There was a problem that binarization could not be performed. The above problem can be solved by operating the transistor only in the linear operation region. However, in order to realize the modulation operation as described above only in the linear operation region, a relatively large transistor with high power consumption is used. It is necessary to use it.
[0017]
[Problems to be solved by the invention]
The present invention has been made to solve such a problem, and provides an ASK modulation circuit that is small in size, low in power consumption, and capable of highly accurately demodulating a binary data signal. With the goal.
[0018]
[Means for Solving the Problems]
An ASK modulation circuit according to the present invention is an ASK modulation circuit that generates an ASK modulation signal by intermittently outputting a carrier signal having a predetermined frequency in accordance with a logic level of an input data signal, and generates the carrier signal. An oscillation circuit; an adjustment circuit that adjusts a duty ratio of the input data signal to obtain a duty adjustment data signal; and the ASK modulation by intermittently outputting the carrier wave signal according to a logic level of the duty adjustment data signal Switching means for generating a signal.
[0019]
[Action]
By performing ASK modulation after changing the duty ratio of the input data signal, the deviation of the cross point of the modulation signal due to the influence of the nonlinear characteristic of the transistor as the ASK modulator is corrected.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of an ASK modulation circuit according to the present invention will be described below with reference to the drawings.
FIG. 5 is a diagram showing a configuration of an ASK modulation circuit according to the present invention.
In FIG. 5, the local oscillation circuit 1 generates a 5.8 [GHz] band carrier signal and supplies it to the buffer amplifier 2. The buffer amplifier 2 supplies an amplified carrier signal obtained by amplifying the carrier signal to a gate terminal G of a gallium arsenide-field effect transistor 5 (hereinafter referred to as FET 5) as a modulator.
[0021]
A digital input data signal as shown in FIG. 6 input to be transmitted is supplied to a crosspoint adjustment circuit 100 including a low-pass filter 103, a comparator 104, and a duty ratio adjustment voltage generation circuit 105 via an input terminal. The
The low-pass filter 103 includes coils L1 and L2 connected in series with each other, one end of which is grounded, and the other end of which is one end of the coil L1, the other end of the coil L1 (one end of L2), and the coil L2. This is a low-pass filter including capacitors C1 to C3 connected to the other end. With such a configuration, the low-pass filter 103 removes the harmonic component constituting the short wave of the input data signal, and the level change at the rising and falling edges of the rectangular wave is made gentle in FIG. A low-frequency data signal LD as shown is generated and supplied to the comparator 104. In the low frequency data signal LD shown in FIG. 6, for convenience of explanation, the waveform of the band limited data signal that would be obtained when the input data signal is logically inverted is also superimposed on the same position in time. Show.
[0022]
The duty ratio adjustment voltage generation circuit 105 generates a voltage obtained by dividing the DC voltage Vc by the resistors R 1 and R 2 as the duty ratio adjustment voltage Vr, and supplies this to the comparator 104.
The comparator 104 has a voltage corresponding to the logic level “H” during the period when the low-frequency data signal LD is higher than the duty ratio adjustment voltage Vr, and to the logic level “L” during the period when it is low. A duty adjustment data signal DD is generated and supplied to the driver 10. As the comparator 104, a comparator having no hysteresis characteristic is used.
[0023]
Next, the operation of the cross point adjustment circuit 100 including the low-pass filter 103, the comparator 104, and the duty ratio adjustment voltage generation circuit 105 as described above will be described with reference to FIG.
First, in the duty ratio adjustment voltage generation circuit 105, when the resistance values of the resistors R1 and R2 are set so that the duty ratio adjustment voltage Vr becomes the voltage V ₁ shown in FIG. The duty adjustment data signal DD as shown in FIG. That is, at this time, the comparator 104 adjusts the duty so that the low level data signal LD shown in FIG. 6 is at the logic level “H” when the level is higher than the voltage V _{1 and} at the logic level “L” during the low period. The data signal DD is generated.
[0024]
Further, the duty ratio adjusting voltage generation circuit 105, when the duty ratio adjusting voltage Vr set the resistance values of the resistors R1 and R2 so that the voltage V ₂ shown in FIG. 6, the comparator 104, FIG. 6 (b The duty adjustment data signal DD as shown in FIG. That is, at this time, the comparator 104 adjusts the duty so that the low level data signal LD shown in FIG. 6 is at the logic level “H” when the level is higher than the voltage V _{2 and} at the logic level “L” during the low period. The data signal DD is generated.
[0025]
Further, the duty ratio adjusting voltage generation circuit 105, when the duty ratio adjusting voltage Vr set the resistance values of the resistors R1 and R2 so that the voltage V ₃ shown in FIG. 6, the comparator 104, FIG. 6 (c The duty adjustment data signal DD as shown in FIG. That is, at this time, the comparator 104 adjusts the duty level so that the low level data signal LD shown in FIG. 6 is at the logic level “H” when the level is higher than the voltage V _{3 and} at the logic level “L” during the low period. The data signal DD is generated.
[0026]
As described above, the cross point adjustment circuit 100 changes the duty ratio of the input data signal by, for example, FIGS. 6A to 6C according to the duty ratio adjustment voltage Vr generated by the duty ratio adjustment voltage generation circuit 105. ). Then, the cross point adjustment circuit 100 supplies the driver 10 with a duty adjustment data signal DD in which the duty ratio of the input data signal is adjusted.
[0027]
The driver 10 performs current amplification for ensuring the current necessary for the operation of the FET 5 with respect to the duty adjustment data signal DD, and supplies this to the band limiting filter 11. The band limiting filter 11 limits the band of the current-amplified duty adjustment data signal DD and supplies it to the drain terminal D of the FET 5 through the high frequency choke coil 4. FIG. 6 (g) is a diagram showing a data signal waveform output from the band limiting filter 11 when the waveform of the duty adjustment data signal DD has the form as shown in FIG. 6 (c).
[0028]
The FET 5 sends the amplified carrier signal supplied from the buffer amplifier 2 to the power amplifier circuit 6 as it is as an ASK modulation signal during the period when the data signal supplied from the band limiting filter 11 is at the logic level “H”. On the other hand, during the period when the data signal supplied from the band limiting filter 11 is at the logic level “L”, the FET 5 stops sending the amplified carrier signal to the power amplifier circuit 6. By this operation, the carrier wave signal output intermittently in synchronization with the change in the logic level of the duty adjustment data signal DD, that is, the ASK in the 5.8 [GHz] band, from the output side (drain terminal D) of the FET 5. A modulated signal is obtained.
[0029]
At this time, the waveform of the data signal supplied to the drain terminal D of the FET 5 via the high frequency choke coil 4 is distorted with respect to the low frequency data signal LD as shown in FIG. However, when this is ASK modulated, the voltage value at the cross point B or C of the ASK modulation signal is the maximum amplitude value V _MAX and the minimum amplitude value as shown in the eye pattern of FIG. It becomes substantially equal to the intermediate value between _{V MIN (V MAX + V MIN} ) / 2.
[0030]
That is, by adjusting the duty ratio in the cross point adjustment circuit 100, the voltage value at the cross point of the ASK modulation signal is adjusted to be equal to the intermediate value between the maximum amplitude value and the minimum amplitude value.
The ASK modulation signal is supplied to an antenna element (not shown) via the power amplifier circuit 6, the band pass filter 7 and the antenna terminal 9, and is radiated as a radio wave by the antenna element. Therefore, in the demodulation circuit that receives and demodulates the ASK modulated signal, if the ASK modulated signal is binarized using an intermediate voltage between the maximum amplitude value and the minimum amplitude value as a threshold voltage, It becomes possible to demodulate a data signal having the same duty ratio as that of the original data signal.
[0031]
In short, the ASK modulation circuit according to the present invention adjusts the duty ratio of the input data signal to be transmitted in anticipation of a shift in the duty ratio of the modulation signal due to the influence of the nonlinear characteristic of the transistor (FET 5) used as the modulator. As a result, the cross point in the eye pattern of the modulation signal can be adjusted to the vicinity of the intermediate value between the maximum amplitude value and the minimum amplitude value of the modulation signal as shown in FIG. Therefore, according to such an ASK modulation circuit, even if ASK modulation is performed using a non-linear operation region of a transistor, binarization accuracy at the time of demodulation can be increased.
[0032]
FIG. 8 is a diagram showing a configuration of an ASK modulation circuit according to another embodiment of the present invention.
The ASK modulation circuit shown in FIG. 8 employs a crosspoint adjustment circuit 100 ′ instead of the crosspoint adjustment circuit 100 shown in FIG. 5, and other configurations are the same as those shown in FIG. . Therefore, only the operation of the cross point adjustment circuit 100 ′ will be described below.
[0033]
The low-pass filter 103 of the cross-point adjustment circuit 100 ′ is a diagram in which the harmonic component of the input data signal supplied via the input terminal 102 is removed, and the level change at the rising and falling edge portions is moderated. 6 generates a low-frequency data signal LD. The voltage dividing unit including the resistors R3 and R4 supplies an adjustment data signal obtained by adjusting the signal level of the low-frequency data signal LD in accordance with the adjustment amount of the duty ratio to the base terminal of the transistor Q1. A DC voltage Vc is applied to the collector terminal of the transistor Q1 via a resistor R5, and its emitter terminal is grounded. The transistor Q1 is turned on when the signal level of the adjustment data signal is higher than a saturation voltage (for example, 0.6 volts), and is turned off when the signal level of the adjustment data signal is lower than the saturation voltage. It becomes. Therefore, when the transistor Q1 is in the ON state, a signal having a ground voltage (0 volt) corresponding to the logic level “L” is supplied to the inverter IV via the collector terminal. On the other hand, when the transistor Q1 is in the OFF state, a signal having a DC voltage Vc corresponding to the logic level “H” is supplied to the inverter IV via the collector terminal. The inverter IV supplies a signal obtained by inverting the logic level of the signal supplied from the transistor Q1 as described above to the driver 10 as the duty adjustment data signal DD.
[0034]
In the cross point adjustment circuit 100 ′, the saturation voltage of the transistor Q1 becomes a threshold value when the low-frequency data signal LD is binarized. At this time, the period ratio of the logic levels “H” and “L”, that is, the duty ratio is changed by adjusting the signal level of the low-frequency data signal LD by the voltage divider (resistors R3 and R4). The duty adjustment data signal DD as shown in FIGS. 6A to 6C is obtained.
[0035]
As described above, in the cross point adjustment circuit 100 ′, a cross-point adjustment similar to that of the cross point adjustment circuit 100 is realized by using an inexpensive and high-speed transistor instead of the comparator 104 shown in FIG. is doing. Therefore, according to the crosspoint adjustment circuit 100 ′ shown in FIG. 8, it is possible to provide an ASK modulation circuit that is less expensive than the crosspoint adjustment circuit 100 shown in FIG. .
[0036]
In the above embodiment, the duty ratio of the duty adjustment data signal DD depends on the duty ratio adjustment voltage Vr as a threshold voltage as shown in FIG. 6, but the duty ratio varies depending on the magnitude of the threshold voltage. The size is not constant.
For example, as shown in FIG. 6, when changing the duty ratio adjusting voltage Vr as clique value voltage from voltages V ₁ to the voltage V _2, the period in which the voltage of the low-frequency data signal LD is larger than the duty ratio adjusting voltage Vr Is a period T1 shown in FIG. Similarly, when the threshold voltage is changed from the voltage V ₁ to the voltage V ₃ , the period during which the voltage of the low-frequency data signal LD is larger than the threshold voltage is a period T2 shown in FIG. In this case, the period T1 or T2 is not constant, and the range in which the duty ratio can be practically varied by adjusting the threshold value is limited to a case where the duty ratio is close to “1” only when the duty ratio is smaller than “1”. Is difficult. This indicates that adjustment is difficult in the above-described embodiment when a modulator that requires only a small amount of cross-point adjustment is targeted for adjustment because its linearity is relatively good and distortion is small. ing.
[0037]
Such a case can be dealt with by changing the cutoff frequency of the band limiting filter 11 and changing the band limitation of the input data signal. When the cutoff frequency of the filter is high, the frequency component passing through the filter increases, so that the voltage waveform of the signal passing through the filter becomes close to the voltage waveform of the input signal. Therefore, the change in the duty ratio due to the change in the threshold voltage is reduced, and fine adjustment is possible.
[0038]
【The invention's effect】
As described above, in the ASK modulation circuit according to the present invention, the oscillation circuit for generating the carrier wave signal, the adjustment circuit for adjusting the duty ratio of the input data signal to obtain the duty adjustment data signal, and the logic of the duty adjustment data signal Switching means for generating an ASK modulation signal by intermittently outputting the carrier signal according to the level. By adjusting the duty ratio, it is possible to correct the deviation of the cross point of the modulation signal due to the influence of the nonlinear characteristic of the switching means.
[0039]
Therefore, according to the present invention, even if the ASK modulation is performed using the nonlinear operation region of the switching means, the binary data signal is accurately demodulated. Therefore, the ASK modulation is performed using only the linear operation region. As compared with the case of performing ASK, it is possible to realize an ASK modulation circuit that is inexpensive and has low power consumption.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a conventional ASK modulation circuit.
FIG. 2 is a diagram showing a configuration of a conventional ASK modulation circuit.
FIG. 3 is a diagram showing drain-source voltage versus output voltage characteristics of FET5.
FIG. 4 is a diagram showing an eye pattern of an ASK modulation signal indicating a relationship between an intermediate voltage Vs between an amplitude maximum value and an amplitude minimum value of the ASK modulation signal and cross points B and C;
FIG. 5 is a diagram showing a configuration of an ASK modulation signal according to the present invention.
6 is a waveform diagram showing the operation of the cross point adjustment circuit 100. FIG.
FIG. 7 is a diagram showing an eye pattern of an ASK modulated signal obtained by an ASK modulated signal according to the present invention.
FIG. 8 is a diagram showing another configuration of an ASK modulated signal according to the present invention.
[Explanation of symbols]
5 FET
100,100 'cross point adjustment circuit 103 low pass filter 104 comparator 105 duty ratio adjustment voltage generation circuit

Claims (4)

An ASK modulation circuit that generates an ASK modulation signal by intermittently outputting a carrier wave signal having a predetermined frequency according to a logic level of an input data signal,
An oscillation circuit for generating the carrier wave signal;
An adjustment circuit for adjusting the duty ratio of the input data signal to obtain a duty adjustment data signal;
Switching means for generating the ASK modulation signal by intermittently outputting the carrier wave signal according to the logic level of the duty adjustment data signal. 2. The ASK modulation circuit according to claim 1, wherein the switching means is a gallium arsenide field effect transistor. The adjustment circuit includes a duty ratio adjustment voltage generation circuit that generates a duty ratio adjustment voltage for setting an adjustment amount of the duty ratio;
A low-pass filter that generates a low-frequency data signal in which the level change at the rising and falling edges of the input data signal is moderated;
A signal corresponding to the first logic level during a period when the signal level of the low frequency data signal is higher than the duty ratio adjustment voltage, and a signal corresponding to a second logic level different from the first logic level during a low period. The ASK modulation circuit according to claim 1, further comprising a comparator that generates the duty adjustment data signal. The adjustment circuit includes a low-pass filter that generates a low-frequency data signal in which a level change at the rising and falling edges of the input data signal is moderated;
Level adjustment means for obtaining a level adjustment data signal in which the amplitude level of the low frequency data signal is adjusted by an amount corresponding to the adjustment amount of the duty ratio;
The duty adjustment data is a signal corresponding to a first logic level when the signal level of the level adjustment data signal is higher than a saturation voltage, and a signal corresponding to a second logic level different from the first logic level when the signal level is lower than a saturation voltage. 2. The ASK modulation circuit according to claim 1, further comprising: a transistor that generates a signal.

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