JP4093259B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily implement a system LSI using a semiconductor device in which a plurality of LSI chips are sealed with resin. <P>SOLUTION: To implement functionality as a desired system LSI using two LSI chips by mounting a part of a required circuit as a system LSI on an LSI chip 113 which an LSI chip 103 does not have by providing a pad electrode 105 for connection with a lead 9 and a pad electrode 125 for internal interface on the main front surface of an LSI chip 103 and electrically connecting a pad electrode 115 and the pad electrode 125 of an LSI chip 113 arranged on this main front surface with wires 117. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device formed by sealing a plurality of semiconductor elements with a resin.

  Conventionally, a semiconductor device is generally formed by sealing a semiconductor element (hereinafter referred to as an LSI chip) containing a large-scale integrated circuit (hereinafter referred to as LSI) in which a plurality of circuits are integrated with a resin. is there.

  FIG. 16 is a cross-sectional view showing the internal structure of a conventional semiconductor device 1. As shown in FIG. 16, the LSI chip 3 is fixedly disposed on the die 8 with an adhesive. The plurality of pad electrodes 5 arranged on the main surface of the LSI chip 3 are electrically connected to leads 9 made of a conductive material serving as terminals for connection to the outside by wires 7 which are thin metal wires. The LSI chip 3, the pad electrode 5, the die 8, the wire 7, and a part of the lead 9 including the connecting portion with the wire 7 (portion called an inner lead) are sealed with an insulating resin 10. A part of the lead 9 derived from the resin 10 (portion called the outer lead) is electrically connected to another device through, for example, a printed circuit board, and exchanges signals and the like.

  The LSI chip 3 realizes a composite function such as a core for a central processing unit (hereinafter referred to as a CPU) such as a microcomputer (hereinafter referred to as a microcomputer), a memory, and a circuit for other peripheral functions. In the case of a system LSI, the functions are mixedly mounted on the same semiconductor substrate. For this reason, when a DRAM (dynamic random access memory) or a batch erasable EEPROM (electrically erasable read only memory) is mounted as a memory in the system LSI, a circuit for a CPU core and peripheral functions is provided. A unique manufacturing process that is not included in the manufacturing process (hereinafter referred to as the Logic process) to be realized is required. As a result, in order to realize such a system LSI, a product is developed by applying a unique manufacturing process (a process for mixing Logic and memory).

  In recent years, a semiconductor device has emerged in which a plurality of LSI chips are sealed with resin and are commercialized (that is, a plurality of semiconductor elements are housed in one package). Such a semiconductor device is said to be an MCP (Multiple Chip Package) type. The MCP type semiconductor device is applied to an LSI of a memory system. For example, by storing the same type of memory in one package, the memory capacity can be expanded, or one type of memory having a different function can be used. It is applied to realize space saving by storing in one package.

  17 is a cross-sectional view showing the internal structure of the MCP type semiconductor device 11, and FIG. 18 is a plan view showing the internal structure of the MCP type semiconductor device 11. 17 and 18, the same reference numerals are given to the same components as those in FIG.

  As shown in FIGS. 17 and 18, the LSI chip 3 fixedly arranged by an adhesive is mounted on the die 8. On the main surface of the LSI chip 3, a plurality of pad electrodes 5 electrically connected to the leads 9 by wires 7 are arranged. Further, the LSI chip 13 is fixedly disposed on the main surface of the LSI chip 3 via an insulating adhesive. A plurality of pad electrodes 15 are arranged on the main surface of the LSI chip 13, and each of these pad electrodes 15 is electrically connected to a corresponding one of the leads 9 by wires 17. These two LSI chips 3 and 13, a part of the lead 9 including a connection portion with the wire 7 and the wire 17, the die 8 are sealed with a resin 10.

  As described above, the MCP type semiconductor device 11 has a configuration in which the plurality of LSI chips 3 and 13 are accommodated in one package and the leads 9 for connection to the outside of the LSI chips 3 and 13 are provided.

  An example of such an MCP-compatible semiconductor device 11 is a BGA (Ball Grid Array). This is because different types of memory such as SRAM (Static Random Access Memory) and batch erasable EEPROM are housed in one package, and the input / output terminals of each memory are individually set so that each memory operates independently. It is structured to be connected to the lead 9. With such a configuration, it is possible to realize functions for two LSI chips in a space of one LSI chip.

  As described above, in LSI integrated in a semiconductor device, in particular, system LSI, product development is performed by applying a mixed process. In a memory LSI, an MCP type semiconductor device is used to increase the memory capacity. Product development is being carried out by increasing or compounding different types of memory.

  However, a semiconductor device mounted with a system LSI has the following problems because it is manufactured on the same semiconductor substrate by a specific process in which a memory-specific manufacturing process and a logic process are incorporated.

  First, since the number of masks is larger than that of a Logic alone manufacturing process or a memory alone manufacturing process, the yield is reduced. Second, since it is a unique process, it cannot easily cope with the improvement in the performance of the logic part and the improvement in the performance of the memory part. Third, since the manufacturing process becomes complicated, TAT becomes long. Fourth, the manufacturing process becomes complicated and the number of masks increases, resulting in an increase in process cost. Fifth, LSI consisting of SOI (Silicon On Insulator) that pursues low voltage / low current operation and LSI consisting of a special process for creating high voltage element elements (high voltage MOS transistors, etc.) The development of the process for the LSI is technically very difficult.

  In particular, in the future, in LSIs to which a finer sub-micron manufacturing process is applied, the voltage reduction (about 0.8 to 1.5 V) will be accelerated even in the Logic process. In this case, a plurality of voltages including a high voltage (for example, 8 to 12 V) higher than a power supply voltage (for example, 3.3 V or 5 V) are required at the time of data rewriting or reading, such as a batch erasable EEPROM. Therefore, it becomes difficult to realize a system LSI (such as a memory erasable microcomputer equipped with a batch erasure) configured by incorporating a high breakdown voltage process and a logic process for creating a high breakdown voltage element.

  In addition, as described above, the MCP type semiconductor device is intended to increase the memory capacity and save space, so that the same type of memory LSIs can be housed in one package, or different types of memory LSIs can be installed in one package. It has been limited to providing leads for each LSI so as to be housed in one package and to operate different types of memory LSIs independently. Therefore, no MCP type semiconductor device realizes a system LSI.

  An object of the present invention is to solve the above problems and to easily realize a system LSI with a semiconductor device in which a plurality of LSI chips are sealed with resin.

  In addition, the present invention further solves the problems that arise when a system LSI is realized by a semiconductor device in which a plurality of LSI chips are sealed with resin, without compromising the function of the system LSI as compared with the prior art. It aims to be realized.

  In order to solve the above-described problems, the present invention provides a semiconductor device in which a second semiconductor element is disposed on a first semiconductor element and the first and second semiconductor elements are sealed with a resin. The first semiconductor element has a main surface, and is electrically connected to any of a plurality of circuits built in the main surface and electrically connected to any of the plurality of leads. A plurality of first pad electrodes connected to each other and a plurality of second pad electrodes electrically connected to any of a plurality of built-in circuits, and the second semiconductor element has a main surface The main surface is provided with a plurality of third pad electrodes that are electrically connected to any of the plurality of built-in circuits and electrically connected to any of the second pad electrodes. The plurality of circuits of one semiconductor element include a second package. A selection circuit for selecting and controlling signal exchange between the electrode and the built-in circuit, and a voltage level at which signal exchange is possible between the circuit incorporating the selection circuit when the first voltage is input. And a control circuit for generating a control signal at a voltage level that enables the selection circuit to exchange signals between the second pad electrode and the built-in circuit. The pad electrode includes a selection pad electrode that is electrically connected to the input of the control circuit, and the plurality of external terminals include a selection external terminal that is electrically connected to the selection pad electrode. Yes.

  With this configuration, the semiconductor device of the present invention includes a circuit provided in the first semiconductor element and a circuit provided in the second semiconductor element, the second pad electrode and the third pad electrode. Are electrically connected to each other, so that signals can be exchanged, and one function as a system LSI can be realized by these two semiconductor elements. For this reason, a 1st semiconductor element and a 2nd semiconductor element can be manufactured separately, and the said subject can be solved.

  Further, in the present invention, the selection means for selecting the arrangement of the second pad electrode, the supply of the power supply voltage or the ground voltage in the second semiconductor element, and the use of the circuit provided in the second semiconductor element By devising the arrangement of the above, etc., the problems that arise when the system LSI is realized by the MCP type semiconductor device are also solved.

  According to the semiconductor device of the present invention, the system LSI can be easily realized by a semiconductor device in which a plurality of LSI chips are sealed with resin.

  In addition, according to the semiconductor device of the present invention, it is possible to solve the problems that occur when the system LSI is realized by a semiconductor device in which a plurality of LSI chips are sealed with resin. It can be realized without impairing the function.

  The semiconductor device of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a cross-sectional view showing the internal structure of the MCP type semiconductor device 100 according to the first embodiment of the present invention, and FIG. 2 is a plan view showing the internal structure of the semiconductor device 100. In FIG. 1, the same components as those in FIGS. 16 to 18 are denoted by the same reference numerals.

  1 and 2, the semiconductor device 100 includes an LSI chip 103 that is a first semiconductor element and an LSI chip 113 that is a second semiconductor element. Both the LSI chip 103 and the LSI chip 113 have the same shape (in the present invention, a rectangular shape).

  The LSI chip 103 is fixedly disposed on a substantially central region of the die 8 with an adhesive provided between the back surface of the LSI 103 and the die 8. A plurality of first pad electrodes 105 are disposed on the main surface of the LSI chip 103. In the first embodiment, each pad electrode 105 is aligned and arranged on two parallel sides of the LSI chip 103.

  A plurality of second pad electrodes 125 are further arranged on the main surface of the LSI chip 103. Each pad electrode 125 is arranged at an arbitrary position around the area where the LSI chip 113 is arranged.

  The LSI chip 113 having a smaller size than the LSI chip 103 is fixedly disposed on a substantially central region of the LSI chip 103 with an adhesive provided between the back surface of the LSI 113 and the main surface of the LSI chip 103. In order to avoid unnecessary electrical connection with the LSI chip 113, it is desirable that the main surface of the LSI chip 103 is formed of an insulating protective film. A plurality of third pad electrodes 115 are arranged on the main surface of the LSI chip 113. In the first embodiment, each pad electrode 115 is aligned and arranged on two sides of the LSI chip 113 (side on which the second pad electrode 125 is arranged).

  Each of the plurality of first pad electrodes 105 is electrically connected to the corresponding lead 9 by a wire 107. Each of the plurality of second pad electrodes 125 is electrically connected to one of the corresponding plurality of third pad electrodes 115 by a wire 117.

  The LSI chips 103 and 113, the die 8, the wires 107 and 117, and the leads 9 that are connected in this way are partially sealed with the resin 10 including the connection portion with the wire 107.

  FIG. 3 is a perspective view for explaining assembly of the semiconductor device in FIG. In FIG. 3, the lead 9 and the wire 107 are partially deleted because they are used for explanation of assembly. As shown in FIG. 3, first, the LSI chip 103 having the first pad electrode 105 and the second pad electrode 125 is prepared. At this time, at the time of manufacturing the LSI chip 103, the pad electrode 125 is arranged around the region 103a on the main surface where the LSI chip 113 is to be mounted later. Further, the LSI chip 113 is separately manufactured and prepared independently of the manufacture of the LSI chip 103. At this time, the arrangement of the pad electrode 115 is set according to the position where the pad electrode 125 is arranged in order to easily perform the wire bonding performed later and prevent a short circuit between the wires. It is good to be done. The arrangement of the pad electrode 125 and the arrangement of the pad electrode 115 in each LSI chip is determined in advance at the time of designing the circuit layout in the LSI chip in which either one of the pad electrodes is arranged. If this is done, the LSI chip on which the other pad electrode is arranged can be easily handled.

  After the first pad electrode 105 of the LSI chip 103 and the lead 9 are electrically connected by the wire 107, the LSI chip 113 is mounted in a predetermined region 103 a on the main surface of the LSI chip 103. Thereafter, electrical connection between the pad electrode 115 and the pad electrode 125 is performed by wire bonding. The manufacturing method is not limited to this, and before the first pad electrode 105 of the LSI chip 103 and the lead 9 are electrically connected by the wire 107, the LSI chip 113 is attached to the main surface of the LSI chip 103. Are mounted in a predetermined region 103a to be arranged, and thereafter, electrical connection between the first pad electrode 105 and the lead 9 by the wire 107 and electrical connection by the wire 117 between the pad electrode 115 and the pad electrode 125 are performed. May be performed. Since the latter can perform the wire bonding process collectively, it can be expected to be more efficient.

  As described above, in the semiconductor device according to the first embodiment, after the LSI chip 103 and the LSI chip 113 are independently developed and manufactured, signal transmission / reception between these two LSI chips is transmitted to the LSI chip 103. By using the provided pad electrode 125, one function (function as a system LSI) is realized.

  As a typical example of a system LSI applied to the semiconductor device of the present invention, a description will be given using a microcomputer on which a batch erasable EEPROM is mounted. FIG. 4 is a block diagram showing the configuration of the microcomputer 50 having a batch erasable EEPROM.

  As shown in FIG. 4, such a microcomputer 50 includes a CPU 51, peripheral functions such as a timer 58 and a serial-parallel conversion circuit 59, an SRAM 55 used for holding and sending data, and a program memory storing various instructions. These are composed of various components such as a batch erasable EEPROM 53 and an input / output interface unit 57.

  These components are connected so that signals can be transmitted and received by a large number of signal lines and buses. The common bus 56 is used for transferring the output signal of the timer 58 via the signal line 66 and for transferring the output signal from the serial-parallel conversion circuit via the signal line 67. The common bus 56 exchanges data with the CPU 51 via the signal line 61 and is used for exchange of addresses and data with the SRAM via the signal line 62. The signal line 63 transmits a control signal such as a write instruction signal output from the CPU 51 to the SRAM 55. The input / output interface unit 57 transmits data received from the outside through the signal line 69 to the CPU through the signal line 64 and transmits a control signal from the CPU 51 to the interface unit 57. It is used to transmit data read from the SRAM 55 to the interface unit 57 and receive signals sent from the interface unit 57. The interface unit 57 exchanges signals such as data with the outside through a signal line 69.

  The EEPROM 53 sends a stored program such as a command to the CPU 51 using the signal line 68. Further, a desired program is selected according to the address sent from the CPU 51 via the signal line 68. That is, the signal line 68 includes a plurality of signal lines such as an address bus, a data bus, a memory control signal, and a power supply voltage supply line for the EEPROM 53.

  In the semiconductor device 100 according to the first embodiment of the present invention, the LSI chip 113 is a memory LSI on which the EEPROM 53 of FIG. 4 is mounted, and the LSI chip 103 is other than that shown in FIG. This is a Logic LSI on which the components are mounted.

  Therefore, the plurality of pad electrodes 115 of the LSI 113 and the plurality of pad electrodes 125 of the LSI 103 are used for transmitting and receiving signals similar to those of the signal line 68 in FIG. In other words, by using the wires 117 to electrically connect the plurality of pad electrodes 115 of the LSI 113 and the plurality of pad electrodes 125 of the LSI 103, it is possible to exchange signals similar to the signal lines 68.

  As described above, the second pad electrode 125 provided on the LSI chip 103 serves as an electrode pad used for interfacing with the LSI chip 113, and signals are exchanged with the LSI chip 113 using the pad electrode 125. By enabling the above, it becomes possible to operate as a microcomputer equipped with a batch erasable EEPROM. In addition, the lead 9 does not cause any new restrictions on the number and arrangement of the conventional leads, and may remain the same as the conventional one.

  In the first embodiment of the present invention, the operation as one microcomputer can be realized by using two LSI chips of the LSI chip 103 and the LSI chip 113 housed in one package. Therefore, the following effects can be obtained in the semiconductor device according to the first embodiment of the present invention.

  Since the LSI chip 103, which is the first semiconductor element, and the LSI chip 113, which is the second semiconductor element, can be individually manufactured, the respective LSI chips can be manufactured in parallel. Therefore, the TAT for development and manufacturing can be shortened.

  Further, since the LSI chip 103 can be manufactured by a logic process and the LSI chip 113 can be manufactured by a process peculiar to a memory, it is not necessary to develop a mixed mounting process in which a logic process and a memory process are combined. In particular, it is possible to combine LSIs composed of high-withstand-voltage processes peculiar to LSIs that require high-breakdown element elements such as batch erasable EEPROM and LSIs composed of SOI processes. Development becomes feasible.

  Further, it is realized by stacking LSI chips, and the arrangement and the number of leads 9 may be the same as those of the LSI chip 103 which is one semiconductor element. For this reason, the size of the semiconductor device does not increase, and there is no need to newly develop a lead frame, and a semiconductor device manufactured by a conventional mixed mounting process can be applied as it is.

  Here, in the commercialization of microcomputers, the same function is realized when a circuit function that is hardware such as a CPU or DSP (Digital Signal Processor) and a program memory that is software are mixed to realize one function. As a program memory, a product using a mask ROM in which software (program) is fixed (hereinafter referred to as a mask ROM version microcomputer) and an EEPROM whose software can be changed even after the program memory is incorporated in an LSI are used as the program memory. A form having a product (hereinafter referred to as an EEPROM version microcomputer) is common. In addition to this, an EPROM is installed for software, and the package is provided with a window for ultraviolet irradiation, or OTP (One Time Programming) that can write a program only once without providing this window. There is also a version microcomputer.

  Generally, an EEPROM version microcomputer is applied to obtain the following effects because it can be written into the EEPROM, that is, the software can be rewritten even after the EEPROM as a program memory is incorporated in the LSI. Yes.

  First, software development and debugging can be supported until immediately before shipment of microcomputer products. Second, since the software can be rewritten after the shipment of the microcomputer product, it is possible to cope with the occurrence of the software bug and to cope with the improvement (version upgrade, etc.) of the product.

  In other words, the EEPROM version microcomputer is used for product development for a new field on the premise that the program is rewritten for the purpose of shortening the TAT and improving the function of the product development.

  However, since the EEPROM version microcomputer uses a voltage higher than the power supply voltage for data writing or the like, a special manufacturing process is required and the product cost tends to increase.

  On the other hand, the mask ROM version microcomputer uses a mask used in a general logic process such as a metal layer, a contact layer, and an implant layer, although there are some differences depending on the type of mask ROM to be mounted. It can be manufactured by manufacturing a fixed program code mask. For this reason, since the mask ROM version microcomputer does not require a special manufacturing process, the product cost can be reduced (about 1/2 to 1/3 of the product cost of the EEPROM version microcomputer).

  Due to such a difference in product cost, the EEPROM version microcomputer and the mask ROM version microcomputer are generally applied as follows.

  First, when developing a microcomputer product, an EEPROM version microcomputer is used to enable rewriting of the program. Hardware and software are debugged by making the program rewritable.

  Immediately after the start of mass production of microcomputer products, the EEPROM version microcomputer is applied for mass production. This is to make it possible to deal with program bugs that may occur.

  After shipping the product as an EEPROM version microcomputer, the market performance (program bug occurrence status, etc.) is confirmed, and in a stable situation, the EEPROM version microcomputer is switched to a mask ROM version microcomputer capable of realizing the same function.

  Thus, the EEPROM version microcomputer is applied at the time of development and at the initial stage of mass production shipment. For this reason, considering the lifetime shipment quantity of this type of microcomputer, the mask ROM version microcomputer is overwhelmingly more than the EEPROM version microcomputer.

  Therefore, when considering the development of a microcomputer having a new function, it is necessary to develop not only a mask ROM version microcomputer but also an EEPROM version microcomputer with a small mass production quantity. For this reason, when releasing a microcomputer having a new function, TAT, development man-hours, and development costs are increased. In particular, an EEPROM version microcomputer with a small mass production quantity has a poor investment efficiency.

  In addition, since the EEPROM version microcomputer and the mask ROM version microcomputer must be able to realize the same function, the EEPROM version microcomputer must realize various characteristics equivalent to the final mask ROM version microcomputer. Don't be. These characteristics include not only electrical characteristics and functions but also current consumption, latch-up characteristics, noise characteristics, and the like. If the EEPROM version microcomputer and the mask ROM version microcomputer do not have substantially the same characteristics, there will be a problem that a difference occurs in the EMC standard. For example, when the EEPROM version microcomputer is replaced with the mask ROM version microcomputer, the operation margin increases, noise increases, the accuracy of the analog circuit built in the microcomputer changes, and readjustment is required. The problem arises that the duration of the battery changes.

  In the second embodiment, the semiconductor device according to the first embodiment of the present invention is applied to solve the above-described problems that occur between the EEPROM version microcomputer and the mask ROM version microcomputer. An improved version is provided. The semiconductor device according to the second embodiment of the present invention will be described below with reference to the drawings. 5 and 6 are plan views of the semiconductor device according to the second embodiment of the present invention, respectively. FIG. 5 is a diagram of a semiconductor device as an EEPROM version microcomputer, and FIG. 6 is a diagram of a semiconductor device as a mask ROM version microcomputer. 5 and 6 correspond to FIG. 2, and the same reference numerals are given to the same components as those in FIG.

  In FIG. 5, an EEPROM as a program memory is mounted on the LSI chip 213. The LSI chip 203 on which the LSI chip 213 is disposed on the main surface is equipped with a mask ROM as a program memory and all circuits necessary as a microcomputer other than the program memory.

  Each of the plurality of pad electrodes 225 arranged on the main surface of the LSI chip 203 is electrically connected to the corresponding one of the plurality of pad electrodes 215 arranged on the main surface of the LSI chip 213 by wires 217. I have to. Each of the plurality of leads 9 is electrically connected to a corresponding one of the plurality of pad electrodes 205 by a wire 207.

  Here, the LSI chip 203 is provided with a selection pad electrode 205 a as one of the first pad electrodes 205. In the EEPROM version microcomputer in FIG. 5, the pad electrode 205a is electrically connected to the power supply voltage lead 9a by a wire 207a. The power supply voltage lead 9 a is also connected to the power supply voltage pad electrode 205 in the LSI chip 207.

  The mask ROM version microcomputer of FIG. 6 does not have the LSI chip 213. For this reason, none of the pad electrodes 225 is wire-bonded. The LSI chip 203 has a mask ROM 222 mounted thereon. The pad electrode 205a is not wire-bonded to the power supply voltage lead 9a.

  Here, the relationship between the pad electrode 205a of the LSI chip 203 and the circuit mounted inside the LSI chip 203 will be described. FIG. 7 is a diagram illustrating a circuit of the LSI chip 203 connected to the pad electrode 205a.

  In FIG. 7, the pad electrode 205 a is connected to the grounded pull-down resistor 251 and is connected to one input terminal of the AND gate 253. A reset signal RES for initialization of the microcomputer is input to the other input terminal of the AND gate 253 via the delay buffer 257. An output terminal of the AND gate 253 is connected to an input terminal D of a latch circuit (hereinafter referred to as LAT) 255. A reset signal RES is input to the clock terminal of the LAT 255. An output signal of the LAT 255 is input to an internal circuit described later as a selection signal SEL. In FIG. 7, a flip-flop may be used as the LAT 255. Although the AND gate 253 is not necessarily provided, the AND gate 253 is preferably provided in order to keep the potential level of the signal input to the input terminal D of the LAT 255 stable. For example, in the LAT 255, if the signal input from the input terminal D is received by an analog switch whose conduction is controlled by the reset signal RES, the AND gate 253 may be omitted. If the signal received from the input terminal D is received by the inverter inside the LAT 255, it is preferable to provide the AND gate 253 because the operation state of the inverter can be reliably stabilized. .

  The operation of the circuit shown in FIG. 7 will be described. First, as shown in FIG. 5, it is assumed that the pad electrode 205a is electrically connected to the power supply voltage lead 9a by wire bonding. Therefore, a power supply potential level (hereinafter, H level) signal is input to one input terminal of the AND gate 253. At the initialization of the microcomputer, the reset signal RES changes from the ground potential level (hereinafter referred to as L level) to the H level. At this time, the potential level of the output signal of the AND gate 253 becomes the H level. Thereafter, with the cancellation of initialization of the microcomputer, the potential level of the reset signal RES changes from H level to L level. The LAT 255 takes in the signal received at the input terminal D in response to the fall of the reset signal RES (H through L latch type). Since the buffer 257 is provided, the potential level of the signal captured by the LAT 255 is in accordance with the potential level of the pad electrode 205a. As a result, the potential level of the selection signal SEL that is the output signal of the LAT 255 becomes the H level.

  Further, as shown in FIG. 6, it is assumed that the pad electrode 205a is not electrically connected to the power supply voltage lead 9a by wire bonding. For this reason, the potential level of one input terminal of the AND gate 253 becomes L level by the pull-down resistor 251. Thereafter, as described above, the LAT 255 takes in the signal received at the input terminal D as the potential level of the reset signal RES changes from the L level to the H level and then changes to the L level again. As a result, the potential level of the selection signal SEL that is the output signal of the LAT 255 becomes the L level.

  Thus, the potential level of the selection signal SEL can be switched depending on whether or not the pad electrode 205a is connected to the lead 9a by wire bonding.

  Next, a circuit to which the selection signal SEL in the LSI chip 203 is input will be described. FIG. 8 is a conceptual diagram of the selection circuit 260 to which the selection signal SEL is input, and FIG. 9 is a specific circuit diagram of the selection circuit 260. 8 and 9 show examples in which the EEPROM mounted on the LSI chip 213 and the mask ROM mounted on the LSI chip 203 handle 8-bit data.

  In FIG. 8, the selection circuit 260 receives data D0 to D7 from the EEPROM mounted on the LSI chip 213 at one input terminal (0 side input). In addition, data D′ 0 to D′ 7 from the mask ROM mounted on the LSI chip 203 is input to one input terminal (one side input) to the selection circuit 260. In FIG. 8, one signal line for transmitting data D0 to D7 and data D'0 to D'7 is shown, but 8-bit data is transferred in parallel by eight signal lines. It is. A selection signal SEL is input to the selection circuit 260. When the potential level of the selection signal SEL is L level, the output signals ID0 to ID7 of the selection circuit 260 are signals corresponding to the data D0 to D7, respectively. When the potential level of the selection signal SEL is H level, the output data ID0 to ID7 of the selection circuit 260 are signals corresponding to the data D′ 0 to D′ 7, respectively.

  The above operation will be described with reference to a specific circuit diagram of the selection circuit 260 shown in FIG. The selection circuit 260 includes 14 2-input 1-output AND gates 261-0 to 261-7, 263-0 to 263-7, 7 2-input 1-output OR gates 265-0 to 265-7, The inverter 267 is configured. Data D′ n is input to one input terminal of the AND gate 261-n (where n is an integer of 0 to 7). The selection signal SEL is input to the other input terminal of the AND gate 261-n. Data Dn is input to one input terminal of the AND gate 263-n. The output signal of the inverter 267 to which the selection signal SEL is input is input to the other input terminal of the AND gate 263-n. The output signal of the AND gate 261-n and the output signal of the AND gate 263-n are input to the two input terminals of the OR gate 265-n, respectively.

  As can be understood from the configuration of the selection circuit 260 illustrated in FIG. 9, when the potential level of the selection signal SEL is L level, the AND gate 263 -n side to which the signal whose potential level is H level is input from the inverter 267 is effective. Thus, data D0 to D7 are output as output data ID0 to ID7 via AND gates 263-n and OR gates 265-n, respectively. When the potential level of the selection signal SEL is H level, the AND gate 261-n side to which the signal having the potential level of H level is input from the selection signal SEL is valid, and the data D′ 0 to D′ 7 are respectively AND gates. It is output as output data ID0 to ID7 via 261-n and OR gate 265-n. The output data ID0 to ID7 are transmitted to the internal bus in the LSI chip 203 so that they can be transferred to other circuits mounted on the LSI chip 203.

  Thus, if the potential level of the selection signal SEL is L level, the mask ROM mounted on the LSI chip 203 is used, and if the potential level of the selection signal SEL is H level, it is mounted on the LSI chip 213. It is possible to switch to using the existing EEPROM. In FIGS. 8 and 9, only the selection of the data bus portion for transferring data is shown as an example, but actually, other control required for accessing each memory (mask ROM, EEPROM) is shown. The signal must be selectable as well. In addition, the batch erasable EEPROM requires a special bus for data writing as a difference from the mask ROM. On the other hand, when the LSI chip 213 is selected, a bus that is used only when the LSI chip is written to the EEPROM is provided in the LSI chip 203, or the data shown in FIGS. The signal line for transmitting D'0 to D'7, the signal line for transmitting ID0 to ID7, and the like are bidirectional buses, and the configuration of the selection circuit 260 is an analog switch instead of an AND gate or an OR gate. Can be realized.

  As described above, the MCP mode using the LSI chip 213 and the Single Chip mode using only the LSI chip 203 can be switched in accordance with the presence or absence of bonding to the electrode pad 205a. In other words, in the semiconductor device according to the second embodiment of the present invention, an LSI chip 203 on which a mask ROM is mounted as a program memory and an LSI chip on which a batch erasable EEPROM for program memory developed for MCP is mounted. In combination with 213, in the case of an EEPROM version microcomputer, the LSI chip 203 and the LSI chip 213 are combined as an MCP to realize operation as a microcomputer. In the case of a mask ROM version microcomputer, the MCP using the LSI chip 213 is not used. In addition, the operation as a microcomputer can be realized only by the LSI chip 203.

  By adopting such a configuration, in the semiconductor device according to the second embodiment of the present invention, the following effects can be obtained in addition to the effects of the semiconductor device according to the first embodiment.

  First, since the LSI chip 213 of the MCP type EEPROM can be designed separately from the LSI chip 203, the EEPROM version microcomputer can be realized only by a new design of the LSI chip 203 which is a mask ROM version microcomputer. Can also be realized at the same time. That is, since it is not necessary to individually develop the EEPROM version microcomputer and the mask ROM version microcomputer, the development TAT can be shortened and the development cost can be reduced. Further, since the LSI chip 213 of the MCP type EEPROM can be applied not only to a specific microcomputer but also to various microcomputers, a reduction in development cost can be expected.

  Second, since the LSI chip 203, which is a mask ROM version microcomputer, is also used as a base in the EEPROM version microcomputer, by applying a common circuit to the configuration other than the program memory, the electrical characteristics, noise characteristics, etc. Differences in characteristics can be made extremely small. As a result, it is possible to easily provide an EEPROM version microcomputer and a mask ROM version microcomputer that do not differ in EMC standards.

  Third, compared to the conventional EEPROM version microcomputers, which were realized by applying a special manufacturing process, the conventional high voltage process was applied to the EEPROM part, and the circuit parts of other microcomputers were conventionally This can be realized by applying the MOS process. For this reason, the EEPROM version microcomputer can be realized at a lower cost.

  Fourthly, by changing the LSI chip 213, a microcomputer adapted to various specifications can be developed in a short period of time. For example, it is possible to realize a microcomputer having a different memory size, batch-erasable EEPROM rewrite guarantee number, operating voltage, and the like only by newly developing the LSI chip 213.

  In the second embodiment, the LSI chip 203 as a mask ROM version microcomputer is applied. However, the LSI chip 203 is developed as a microcomputer that does not have a program memory, that is, does not have a mask ROM. As LSI chip 213, a mask ROM version and a batch erasable EEPROM are developed, and one of them is applied as a program memory to realize a mask ROM version microcomputer and an EEPROM version microcomputer. May be. In this case, in any case, since the pad electrode 225 is electrically connected to the pad electrode 215 of the LSI chip 213, circuits as shown in FIGS. 7 to 9 are unnecessary. Further, the LSI chip 213 combined with the LSI chip 203 as the mask ROM version microcomputer is not limited to the batch erasable EEPROM, but may be a mask ROM, EPROM, or the like. For example, when the memory capacity of the mask ROM mounted on the developed LSI chip 203 is insufficient, a mask ROM having a large memory capacity is developed with the LSI chip 213 without newly developing the LSI chip 203. Since the LSI chip 203 uses the mask ROM of the LSI chip 213, it is possible to easily cope with it.

  Heretofore, the first and second embodiments of the present invention have been described in detail. In particular, in the second embodiment, the LSI chip 203 is described as a mask ROM version microcomputer, and the LSI chip 213 is described as a batch erasable EEPROM for a program memory, but the LSI chip 213 is as follows. It is also possible to apply.

  (1) Equipped with batch erasable EEPROM and analog circuit such as analog-digital converter (2) Analog circuit such as analog-digital converter (3) Equipped with batch erasable EEPROM and SRAM (4 ) Mask ROM (5) DRAM (6) SRAM (7) EEPROM

  For example, a logic process employed in a microcomputer or the like has become a low voltage (for example, a power supply voltage Vdd = 1.6 to 2.0 V in a 0.18 μm process). On the other hand, in a circuit portion that handles an analog signal such as an analog-digital converter, it is necessary to maintain a conventional interface level (5 V or 3 V) in a sensor, an actuator, or the like. The above (1) and (2) can sufficiently cope with this. Specifically, a mask ROM version microcomputer not including an analog circuit is developed as the LSI chip 203, and the circuit of (2) is applied as the LSI chip 213, and these LSI chips are used in the first or second implementation. A system LSI is realized by combining as an MCP type as shown in FIG. In the case of an EEPROM version microcomputer, the LSI chip 213 (1) may be applied. In this case, it is possible to commercialize the mask ROM version microcomputer as a microcomputer without an analog circuit without developing (2).

  In the second embodiment, (3) can be used to simultaneously increase the memory for storing data. In this case, the SRAM of the LSI chip 213 is used for adding a memory for storing data, and the batch erasable EEPROM is used for a program memory.

  Also, (4) to (7) are applied when realizing the purpose of increasing the data storage memory mounted on the LSI chip 203 or the mixed mounting of a memory having a different manufacturing process from the LSI chip 203. is there. For example, the address control signal and the chip select signal are controlled so that when the memory space of the data storage memory in the LSI chip 203 is exceeded, access is transferred to the data storage expansion memory mounted on the LSI chip 213. do it. In this way, a desired system LSI can be realized in a short period of time without increasing the product cost.

  In the first and second embodiments, two LSI chips are used and connected to each other to realize an MCP type semiconductor device as a system LSI. It goes without saying that a semiconductor device that realizes a function as a system LSI by connecting three or more LSI chips to each other may be used. For example, four LSI chips, an LSI chip as a mask ROM version microcomputer, an LSI chip as a erasable EEPROM, an LSI chip as a power supply control circuit, and an LSI chip as an analog LSI for communication, are connected to each other. The functions as a system LSI may be realized by being housed in one package.

  In the first and second embodiments, a system LSI represented by a microcomputer has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to the following cases. .

  For example, an LSI may be realized by interconnecting a plurality of LSI chips having different manufacturing processes that are difficult to manufacture on the same semiconductor substrate, which is one of the gist of the present invention. For example, a power LSI to which a bipolar process is applied and an LSI to which a logic process used for control thereof are connected may be connected to each other and housed in one package.

  Further, the present invention can be applied to a plurality of LSI chips that can be manufactured on the same semiconductor substrate and have the same manufacturing process (for example, all of which a Logic process is applied). For example, a communication LSI that has already been developed and equipped with many analog circuits that can operate as a single LSI and a microcomputer for controlling the communication LSI are connected to each other and housed in one package. Also good. This makes it possible to develop different LSIs with high added value in a short period of time.

  As described above, in any case, a plurality of LSI chips housed in one package are connected to each other so as to be able to exchange data, and the desired functions as a semiconductor device can be achieved with these LSI chips. It is important to be configured to achieve

  In the second embodiment, whether or not the LSI chip 213 is used is selected in the circuit mounted in the LSI chip 203 depending on whether or not the wire bonding to the pad electrode 205a is performed. Instead, the same selection can be realized by other methods as follows.

  First, the selection is performed by using a mask layer for the mask ROM in the LSI chip 203. That is, there are various mask layers for determining a code (program) in the mask ROM, such as a metal layer, a contact layer, and an implantation layer depending on the memory type, and the mask ROM is manufactured using a desired mask corresponding to the program code. For this reason, in addition to the mask ROM code, a mask for the mask layer can be used for selection as described above. In this case, if the selection process is performed to use the LSI chip 213, the LSI chip 203 cannot be used alone. In this case, a special pad electrode for selection such as the pad electrode 205a is provided. There is no need. In addition, since the code mask of the mask ROM can also be used for selection, it is possible to prevent an increase in cost such as an increase in the mask and an increase in the manufacturing process.

  Next, a selection method is performed using a fuse ROM. That is, the LSI chip 203 is provided with a fuse (hereinafter referred to as a fuse ROM) made of metal wiring that allows a predetermined current to flow or can be disconnected by a laser, and is selected according to the disconnection state. You should do so. In the example of FIG. 7, the power supply voltage is applied via the fuse ROM instead of the pad electrode 205a, and the power supply voltage is applied to the AND gate according to the disconnection state of the fuse ROM. Alternatively, it may be possible to selectively control whether the ground voltage is applied via the pull-down resistor 251. With such a configuration, selection processing can be performed at the time of wafer probing of the LSI chip 203, so that it is possible to cope flexibly in consideration of adjustments to the inventory and the like.

  Next, there is a method in which a predetermined pad electrode 205 of the LSI chip 203 is used as a pad electrode exclusively for selection. This is selected by removing the pull-down resistor 251 in FIG. 7, electrically connecting the pad electrode 205a to a lead dedicated to selection, and applying an m power supply voltage or a ground voltage to this lead. It is what I did. In this way, the mask ROM version microcomputer and the EEPROM version microcomputer can be easily selected even after the semiconductor device housed in the package is incorporated into the electronic device. As a result, device debugging and difference evaluation in each case of the mask ROM version microcomputer and the EEPROM version microcomputer can be realized with high accuracy and at low cost.

  As a method of providing the lead and pad electrode dedicated for selection as described above, separate programs may be incorporated in the LSI chip 203 and the LSI chip 213, respectively. That is, it is possible to selectively realize a microcomputer that can realize different operations according to different programs depending on the potential level of a signal supplied to a lead dedicated to selection. That is, as a package, one microcomputer can be used in two ways. In this case, the electronic device to which such a semiconductor device is applied can be switched without turning off the power. For example, the continuation of the program stored in the mask ROM of the LSI chip 203 is stored in the EEPROM of the LSI chip 213. The program can be executed continuously. In addition, after developing an LSI chip 203 for one microcomputer (mask ROM version microcomputer), an LSI chip 213 can be developed as an application product of the microcomputer.

  Next, there is a method of selecting by a program stored in the mask ROM of the LSI chip 203 or a program stored in the EEPROM of the LSI chip 213. That is, in a microcomputer in which the LSI chip 203 and the LSI chip 213 are housed in one package, the program activation at the initial operation (default) is stored in the program stored in the mask ROM of the LSI chip 203 or in the EEPROM of the LSI chip 213. And decide which LSI chip to use (which LSI chip program to use) by the first program routine in the program of the selected LSI chip. do it. For example, in the startup program as this program routine, the potential level of the signal input from the selection lead described above is confirmed, and the confirmation result is confirmed by a mode designation register built in the microcomputer according to the confirmation result. May be held and used as a selection signal for which LSI chip program to use.

  In addition, as a method of selecting by another program of the activation program, a method of confirming the above-described register state is also possible. For example, if the LSI chip 213 is a register that is set or reset depending on whether or not the LSI chip 213 is connected to the LSI chip 203 so as to be able to exchange data, it can be realized. Is possible.

  Next, there is a method of selecting the LSI chip 203 by hardware such as a determination circuit for determining whether or not the LSI chip 213 is connected to the LSI chip 203 side so as to be able to exchange data. That is, at the time of initialization of the microcomputer, the presence / absence of the LSI chip 213 is determined by such a determination circuit. When it is determined that there is no LSI chip 213, the program on the LSI chip 203 side is activated, and when it is determined that the LSI chip 213 is present, the program on the LSI chip 213 side is activated. . As such a determination circuit, a configuration similar to that shown in FIG. 7 can be applied, and this may be connected to a signal line capable of being determined instead of the pad electrode 205a. In addition, such a determination circuit is determined by an access operation to a predetermined register via a bus line, or between a desired pad electrode of each of two LSI chips using a determination detection wire or the like. The connection may be made, and the determination may be made in this connection state (for example, a power supply voltage is applied when the connection is established, and an open state is established when the connection is not established).

  Up to this point, the modification examples and application examples related to the combination and selection processing of the two LSI chips in the first and second embodiments have been described in detail. Next, modifications and application examples related to the layout such as the arrangement of pad electrodes will be described below.

  In the first and second embodiments, as shown in FIG. 2 and FIG. 5, the pad electrode 125 and the pad electrode 225 are regions that are relatively close to the outer periphery of the LSI chip 113 and the LSI chip 213, respectively. (In the figure, the two LSI chips are arranged at substantially the center position of the distance between the parallel outer peripheries). Further, as shown in the plan view of FIG. 10, a pad electrode 325 is further disposed in the region where the LSI chip 113 is disposed, at a position closer to the outer periphery of the LSI chip 113 than the outer periphery of the LSI chip 103. In such an arrangement of the pad electrode, the wire 107 for connecting the lead 9 and the pad electrode 105 does not intersect the wire 117 for connecting the pad electrode 115 and the pad electrode 325. However, the following problems are considered.

  First, when the chip size of the LSI chip 113 mounted on the main surface of the LSI chip 103 is changed, it is difficult to cope with the size change or a margin for that is reduced. The possibility that such a size change may be caused by a specification change such as an increase in memory size or a change in a manufacturing process to be applied is sufficiently conceivable.

  Second, since the pad electrodes 125, 325 and the like are arranged in a region near the center of the LSI chip 103, the protection circuits such as the pad electrodes 125 and 325 are arranged when designing the layout of the LSI chip 103. It is difficult to increase the number of useless areas, and the circuit module in the LSI chip 103 is divided in the arrangement area of the pad electrodes 125 and 325. If there are such restrictions, it becomes impossible to efficiently design an LSI layout by applying a normal CAD system.

  In order to solve such a problem, it can be solved by applying a pad electrode layout as shown in the plan view of FIG. In FIG. 11, the same reference numerals are given to the same configurations as those in FIG.

  In FIG. 11, pad electrodes 425 corresponding to the pad electrodes 125 and 325 are arranged in a staggered manner with the pad electrodes 105 at positions closer to the outer periphery of the LSI chip 103 than to the outer periphery of the LSI chip 113. Other configurations are the same as those in FIG. As described above, the pad electrodes 105 for connecting to the leads and the pad electrodes 425 for connecting to the pad electrodes 115 are alternately arranged in a staggered manner, thereby solving the above-mentioned problems and saving space. Efficient layout.

  Next, in the above-described embodiments, modifications, and the like, the example in which the pad electrodes are disposed only on the two sides of the LSI chip 103 and the LSI chip 113 is not limited to this. For example, as shown in the plan view of FIG. 12, a pad electrode 505 corresponding to the pad electrode 105 is arranged along each of four sides of the LSI chip 503 corresponding to the LSI chip 103, and an LSI corresponding to the LSI chip 113. A pad electrode 515 corresponding to the pad electrode 115 may be disposed along each of the four sides of the chip 513. Further, the pad electrodes 525 corresponding to the pad electrodes 125 are arranged in a staggered manner with the pad electrodes 505 in accordance with the arrangement of the pad electrodes 115. The pad electrode 505 is electrically connected to the corresponding lead 9 via a wire 507, and the pad electrode 515 is electrically connected to the corresponding pad electrode 525 via a wire 517.

  The layout of pad electrodes as shown in FIG. 12 depends on the relationship between the size of the LSI chip 503 and the size of the LSI chip 513, the number of pad electrodes 525, and the design restrictions on the mounting for wire bonding to these pad electrodes 525. It is arranged along the four sides of the chip. However, if possible, as shown in the plan view of FIG. 13, the pad electrode 615 corresponding to the pad electrode 515 is arranged on the opposite two sides of the LSI chip 613 corresponding to the LSI chip 513, and this is arranged on this. In addition, the pad electrode 625 corresponding to the pad electrode 525 of the LSI chip 603 corresponding to the LSI chip 503 is preferably arranged on the two opposite sides of the LSI chip 603.

  By arranging the pad electrode as shown in FIG. 12, the following effects can be expected. For example, the distance between the pad electrode 615 and the pad electrode 625 used for the internal interface needs to be a certain distance on the mounting due to restrictions during wire bonding. However, since there is no restriction as described above with respect to the side where the pad electrode 615 is not disposed, the outer peripheral portion of the LSI chip 613 is brought close to the vicinity of the pad electrode 605 for connection with the lead. You can do this. For example, it can be configured as shown in the plan view of FIG.

  In FIG. 14, it will be understood that the size of the LSI chip 613 in the horizontal direction in the drawing is increased. In other words, the distance (L1) between the side of the LSI chip 613 on the side where the pad electrode 615 is disposed and the side of the LSI chip 603 on the side where the pad electrode 625 is disposed is on the side where the pad electrode 615 is not disposed. The distance (L2) between the side of the LSI chip 613 and the side of the LSI chip 603 on the side where the pad electrode 625 is not disposed is shorter.

  For this reason, the one shown in FIG. 13 or FIG. 14 has fewer restrictions on the chip size and shape of the LSI chip 613 than the one shown in FIG. 12, and the degree of freedom in design and shape increases. . Further, if the size of the LSI chip 613 can be made as close as possible to the size of the LSI chip 603, the thicker portion increases accordingly, so that it can be made stronger against external stress. Become.

  13 and 14 exemplify the case where the interface pad electrode 615 and the pad electrode 625 are arranged on two sides, the interface pad electrode 615 and the pad electrode 625 are arranged on three sides or one side. It may be arranged.

  Thus, by narrowing down the sides where the pad electrode 615 for interface and the pad electrode 625 are arranged, signals for these pad electrodes 625 can be collectively laid out in the LSI chip 603, so that efficient wiring In addition, it becomes possible to test a plurality of LSI chips 613 at the same time during wafer probing of the LSI chips 613.

  Next, modified examples relating to the test in the semiconductor device of the present invention will be described below. In the present invention, in an MCP type semiconductor device, a desired function is realized by using a plurality of LSI chips housed in one package. For this reason, at the time of a test as a semiconductor device after assembly, the lead 9 is used to test whether a desired function is correctly executed and to select a non-defective product or a defective product. Here, in the semiconductor device of the present invention, for example, a test circuit capable of individually testing the LSI chip 103 and the LSI chip 113 is preferably incorporated in the LSI chip 103, for example. For example, a test that allows a signal of a predetermined potential level to be input or an individual test to one of the leads 9 for instructing the test and one of the pad electrodes 105 for instructing the test. It becomes possible by providing a function. In such a case, by this test signal, the input / output lead in the lead 9 is selectively connected to the input / output signal of the LSI chip 103 or the input / output signal of the LSI chip 113 by the selection circuit as shown in FIG. It is only necessary to be controlled so as to be performed. In this way, for example, it is possible to test the LSI chip 113 made of a batch erasable EEPROM using the lead 9 by the memory tester and the LSI chip 103 using the logic tester. Therefore, the coverage for the test can be improved.

  Next, modified examples related to wire bonding in the semiconductor device of the present invention will be described below. In the first and second embodiments described above, the pad electrode for power supply and the pad electrode for grounding in the pad electrode 115 of the LSI chip 113 are also electrically connected to the pad electrode 125. However, among the pad electrodes 113, the power supply pad electrode, the grounding pad electrode, and the analog signal pad electrode are considered to be affected by noise, and sometimes the amount of current is different from that of the power supply pad electrode. For many cases, the layout of portions connected to these pad electrodes in the LSI chip 103 becomes large, and the desired performance cannot be realized.

  To solve such a problem, it is only necessary to directly connect the lead 9x and the lead 9y with the wire 517x and the wire 517y like the pad electrode 515x and the pad electrode 515y of FIG. In FIG. 12, for example, the pad electrode 515x is a pad electrode for power supply, the pad electrode 515y is a pad electrode for grounding, the lead 9x is a lead for power supply, and the lead 9y is a lead for grounding. . Also in FIG. 13, a pad electrode 615x corresponding to the pad electrode 515x and a pad electrode 615y corresponding to the pad electrode 515y are shown.

  As shown in FIGS. 12 and 13, the power supply lead 9x and the grounding lead 9y are directly connected to the power supply pad electrode and the grounding pad electrode of the LSI chip 515 and 615 by wire bonding. Therefore, the above problems can be solved. Therefore, the noise of the power supply system can be prevented, and it is not necessary to supply power via the internal wiring of the LSI chip 503 or 603. Therefore, it is possible to secure the metal width of the wiring for handling a large current in the LSI chip 503 or 603. It becomes unnecessary.

  As for the analog electrode pad electrode among the pad electrodes 113 in the LSI chip 113, the analog signal lead 9w and the analog signal pad electrode 715w are directly connected to the wire 717 as shown in the plan view of FIG. Thus, the above problems can be solved. Further, it is possible to correspond to the pad electrode for grounding in the LSI chip 113 like the pad electrode 715w and the lead 9w in FIG.

  Next, the mounting of the oscillation circuit in the semiconductor device of the present invention will be described below. When the LSI chip 103 and the LSI chip 113 require different source oscillation clocks on the mounted circuits, it is necessary to incorporate an oscillation circuit in each LSI chip and connect a crystal resonator to each. In this case, in the oscillation circuit on the LSI chip 113 side, the wire length to the lead becomes long and the coil component becomes large, so that the influence of induction becomes large.

  In such a case, an LSI circuit for the LSI chip 113 may be provided on the LSI chip 103 side. Even if the LSI chip 113 has an oscillation circuit mounted thereon, the oscillation circuit mounted on the LSI chip 113 is not used, and the LSI chip 113 uses an oscillation circuit for the LSI chip 113 as an alternative to the LSI chip 103 to obtain a desired one. A clock signal may be input.

  Next, the structure of the semiconductor device of the present invention will be described below. In any of the above-described embodiments, for example, the LSI chip 103 having a large chip size is disposed below, and the LSI chip 113 having a small chip size is disposed on the LSI chip 103. Here, there are some EEPROMs that can be erased at once, such that stress is applied to the upper portion of the memory cell, which affects various circuit characteristics such as endurance characteristics. For an LSI chip that is easily affected by such stress, the LSI chip 113 should always be placed on the upper side of the two LSI chips, for example, as an arrangement that can further reduce the influence on the stress. Good.

  As mentioned above, although this invention was demonstrated in detail, in this invention, a various improvement and change are not prevented in the range which does not change the summary.

  For example, in FIG. 12, the pad electrodes 505 and the pad electrodes 525 are arranged in a staggered manner, but the present invention is not limited to this. In FIG. 12, due to layout restrictions, this is applied when the spacing between the pad electrodes of the pad electrode 505 in the LSI chip 503 is narrow or when the arrangement of the protective circuit with respect to the pad electrode 525 is restricted. . The restriction on the arrangement of the protective circuit with respect to the pad electrode 525 is eliminated, and the spacing between the pad electrodes of the pad electrode 505 in the LSI chip 503 is relatively wide (for example, another pad electrode can be arranged between adjacent pad electrodes 505). In such a case, the pad electrode 525 may be disposed between adjacent pad electrodes 505. That is, the pad electrode 505 and the pad electrode 525 may be arranged in a line on each side of the outer periphery of the LSI chip 503. In this case, the power supply wiring and the ground wiring laid out in the vicinity of the pad electrode 505 can be shared by the protection circuit in the pad electrode 505 and the protection circuit in the pad electrode 525, which is more effective.

  In the second embodiment, an example in which a circuit as shown in FIG. 7 is used has been described. However, the circuit configuration is not limited to that shown in FIG. For example, if the potential level of the selection signal SEL is to be reversed from that described above, the pull-down resistor 251 is a pull-up resistor disposed between the power supply potential and the pad electrode 205a, and the pad electrode 205a is used for grounding. The selection may be made depending on whether or not the lead and the wire are connected, or can be realized as follows.

  FIG. 19 shows a modification of the circuit of FIG. In FIG. 19, the same components as those in FIG.

  In FIG. 19, an N-channel MOS transistor 851 is provided instead of the pull-down resistor 251 shown in FIG. Other configurations in FIG. 19 are the same as those in FIG. One electrode (for example, drain side) of the MOS transistor 851 is connected to the pad electrode 205a, and the other electrode (for example, source side) is grounded. A reset signal RES is input to the gate electrode of the MOS transistor 851 through the buffer 257.

  With the configuration as shown in FIG. 19, when the potential level of the reset signal RES becomes H level, the MOS transistor 851 becomes conductive. At this time, if the pad electrode 205 a is electrically connected to the power supply lead 9 a by a wire, a signal whose potential level is H level is input to the LAT 255 from the AND gate 253. In order to ensure this, it is desirable that the on-resistance when the MOS transistor 851 is in a conductive state is a high resistance like the pull-down resistor 251. If the pad electrode 205 a is not electrically connected to the power supply lead 9 a by a wire, a signal having an L level potential is input to the LAT 255 from the AND gate 253. Thereafter, a selection signal SEL having a potential level corresponding to the potential level of the signal input to the LAT 255 is output, and the LAT 255 maintains the potential level of the selection signal SEL even when the potential level of the reset signal RES returns to the L level. be able to. Therefore, the same selection as in the second embodiment can be performed.

  Compared with the circuit of FIG. 7, the circuit of FIG. 19 is not in the reset process (that is, the potential level of the reset signal RES is higher) even if the pad electrode 205 a is electrically connected to the power supply lead 9 a by a wire. The current that flows between the pad electrode 205a and the ground can be reduced by the MOS transistor 851 except when it is at the H level. For this reason, the circuit of FIG. 19 can reduce power consumption compared with the circuit of FIG. If it is considered that the resistor 251 is a MOS resistor, there is no difference in layout between FIG. 19 and FIG. 7, and the number of elements does not change.

  There is also a method that does not use a circuit as shown in FIG. FIG. 20 is a plan view showing an internal structure of an MCP type semiconductor device according to a modification of the second embodiment of the present invention when the circuit of FIG. 7 is not used. FIG. 20 corresponds to FIG. 5, and in FIG. 20, the same components as those in FIG.

  In FIG. 20, in addition to the configuration shown in FIG. 5, a pad electrode 205b is added. The pad electrode 205b is arranged at a position connectable to the grounding lead 9b by a wire.

  FIG. 21 is a diagram showing a circuit of the LSI chip 203 connected to the pad electrode 205a and the pad electrode 205b used in the modification of FIG.

  As shown in FIG. 21, the LSI chip 203 is provided with a buffer 853 instead of the circuit as shown in FIG. The pad electrode 205a and the pad electrode 205b are connected to the input end of the buffer 853 through a common wiring. That is, the pad electrode 205 a and the pad electrode 205 b are wired-ORed by the wiring in the LSI chip 103 and input to the buffer 853. A signal output from the buffer 853 is used as the selection signal SEL.

  With this configuration, the pad electrode 205a is electrically connected to the lead 9a for power supply through a wire, and the pad electrode 205b is not electrically connected to the lead 9b for grounding through a wire in an open state. If there is, the potential level of the selection signal SEL that is the output of the buffer 853 is maintained at the H level. If the pad electrode 205a is in an open state without being electrically connected to the power supply lead 9a by a wire, and the pad electrode 205b is electrically connected to the grounding lead 9b by a wire, the buffer The potential level of the selection signal SEL, which is the output of 853, is L level. Therefore, the same selection as in the second embodiment can be performed.

  This increases the number of pad electrodes 205b. However, since the circuit as shown in FIG. 7 is not necessary, it can contribute to cost reduction and size reduction of the LSI chip 203.

  Note that in the case where the pad electrode 205b cannot be provided, the input terminal of the buffer 853 may be connected only to the pad electrode 205a, and a signal output from the buffer 853 may be used as the selection signal SEL. In this case, in order to facilitate wire bonding and prevent a short circuit between the wires, as shown in FIG. 22, the power supply lead 9a and the grounding lead 9b are arranged adjacent to each other, It is desirable that the pad electrode 205a is disposed between the pad electrode 205d and the ground pad electrode 205g. In this manner, the potential level of the selection signal SEL can be selectively controlled by wire bonding the pad electrode 205a to either the power supply lead 9a or the ground lead 9b.

  Here, in order to reduce wire bonding errors to the pad electrode 205a during manufacturing, it is more preferable to dispose the power supply lead 9a and the ground lead 9b in FIG. 22 apart from each other. To cope with this case, it is necessary to provide the pad electrode 205a and the pad electrode 205b as shown in FIG.

  As a method using the pad electrode 205a and the pad electrode 205b, the following method is also considered.

  In this method, the input end of the buffer 853 in FIG. 21 can be selectively connected between the input end and the ground using a mask layer for the mask ROM in the LSI chip 203. That is, as described above, the mask layer for determining the code (program) in the mask ROM includes various types such as a metal layer, a contact layer, and an implantation layer depending on the memory type, and the mask ROM using a desired mask corresponding to the program code. Is produced. For this reason, in addition to the mask ROM code, a mask for the mask layer can be used for selection as described above. For example, if the buffer layer is connected between the input terminal of the buffer and the ground, the potential level of the selection signal SEL can be fixed to the L level. In this case, both the pad electrode 205a and the pad electrode 205b can be opened without being electrically connected to a desired lead by wire bonding. For this reason, when the use as a mask ROM version microcomputer is decided, the above problem can be solved by fixing the potential level of the selection signal SEL in the mask layer in this way. In this case, since the mask for the program code is used, there is no increase in manufacturing process or manufacturing cost.

  Here, when the use as the mask ROM version microcomputer is decided, the pad electrode 205a, the pad electrode 205b, the pad electrode 205a and the buffer in which the pad electrode 205b is connected to the input end are used, and the buffer is used in the mask layer. It is effective to ground the input end of each other. Here, a method for responding to such a microcomputer in response to a request to be applied to the EEPROM version microcomputer will be described below.

  For such a requirement, it is effective to use a circuit as shown in FIG. Since FIG. 23 can be seen corresponding to FIG. 19, in FIG. 23, the same reference numerals as those in FIG.

  In the circuit of FIG. 23, the AND gate 253 shown in FIG. 19 is deleted. This is for the reason described above in FIG. Further, in place of the buffer 853, a LAT 255, a buffer 257, and a MOS transistor 851 similar to those in FIG. The pad electrode 205 a and the pad electrode 205 b are wired-ORed by wiring in the LSI chip 103 and connected to the input terminal D of the LAT 255. The reset signal RES is input to the gate terminal of the LAT 255 and also input to the gate electrode of the N-channel MOS transistor 851 through the buffer 257. One electrode (for example, the source side) of the N-channel MOS transistor 851 is grounded, and the other electrode (for example, the drain side) is selectively connected in the mask layer of the mask ROM described above. It can be connected to the input terminal D of the LAT 255 via the switch means 861 in FIG. A signal output from the output terminal O of the LAT 255 is the selection signal SEL. The operation is basically the same as in FIG.

  Next, the operation of the circuit of FIG. 23 will be described. In the semiconductor device using the LSI chip 103 and the LSI chip 113 mounted with the circuit of FIG. 23, when the potential level of the selection signal SEL is L level, the semiconductor device is set to be a mask ROM version microcomputer, In the following description, it is assumed that when the potential level of the selection signal SEL is H level, control is performed so that the microcomputer is an EEPROM version. In FIG. 23, the switch means 861 is not connected (that is, the MOS transistor is not electrically connected to the input terminal D of the LAT 255 in the mask layer), and the pad electrode 205a is connected to the power supply lead 9a and the wire. The potential level of the selection signal SEL can be selectively set based on the reset signal RES depending on whether the bonding is performed or the pad electrode 205b is wire-bonded to the ground lead electrode 9b. In this case, either an EEPROM version microcomputer or a mask ROM version microcomputer can be selected by wire bonding. Further, the switch means 861 is connected (that is, the MOS transistor and the input terminal D of the LAT 255 are electrically connected in the mask layer), and the pad electrode 205a and the pad electrode 205b are both opened without wire bonding. In this case, even if the potential level of the selection signal SEL is set based on the reset signal RES, the potential level of the selection signal SEL can be fixed to the L level. In this case, it is fixed as a mask ROM version microcomputer.

  Further, in a state where the switch means 861 is connected (that is, in a state where the MOS transistor and the input terminal D of the LAT 255 are electrically connected in the mask layer), the pad electrode 205a is electrically connected with the power supply lead 9a and the wire. If connected to each other, the potential level of the signal input to the input terminal of the LAT 255 can be set to the H level. Therefore, even when the switch unit 861 is in the connected state, the potential level of the selection signal SEL can be set to the H level based on the reset signal RES. In this case, what is fixed as the mask ROM version microcomputer can be forcibly reused as the EEPROM version microcomputer.

  The above problems can be solved by using the circuit of FIG. Further, in the circuit of FIG. 23, it is possible to contribute to reduction of power consumption as in FIG.

  Note that each of the circuits shown in FIGS. 7, 19, and 23 sets the potential level of the selection signal SEL based on the reset signal RES. For this reason, there may occur a case where the potential level of the reset signal RES whose potential level is the L level temporarily becomes the H level and returns to the L level again due to an unexpected situation such as a momentary power interruption. In order to obtain more reliable stabilization of the potential level of the selection signal SEL in such a case, for example, the circuit shown in FIG. 21 is used rather than the circuits as shown in FIGS. In addition, it is better to set the potential level of the selection signal SEL regardless of the reset signal RES as described above.

  As a method of using only the pad electrode 205a without providing the pad electrode 205b without using the reset signal RES, the following method is also possible.

  For example, the input end is connected to the pad electrode 205a, and the output signal is used as the selection signal SEL in the same manner as described above. Here, instead of providing the pad electrode 205b, the pad electrode 205a and the ground can be selectively connected by using a mask layer for the mask ROM in the LSI chip 203. For example, the potential level of the selection signal SEL can be fixed to the L level by opening the pad electrode 205a without performing wire bonding and connecting the pad electrode 205a and the ground in the mask layer. If the pad electrode 205a and the ground are not connected in the mask layer, the potential level of the selection signal SEL is set to the H level if the pad electrode 205a is electrically connected to the power supply lead 9a by a wire. Can be. If the ground lead 9b is disposed adjacent to the lead 9a, the potential level of the selection signal SEL is set to the L level if the pad electrode 205a and the ground lead 9b are electrically connected by a wire. can do. Further, even if the pad electrode 205a is connected to the ground in the mask layer, if the pad electrode 205a is electrically connected to the power supply lead 9a with a wire, the power consumption increases, but the selection signal The potential level of SEL can be set to H level.

  As described above, there are various selection methods in the second embodiment. For this reason, it can be said that the object can be satisfied by applying any of the various selection methods described above according to the configuration and object of the product to which the semiconductor device of the present invention is applied.

  In the above description, the MCP type connecting a plurality of LSI chips using wires is described as an example. However, the present invention is not limited to this and can be applied to the following.

  For example, a plurality of LSI chips may be stacked on the same plane side without being stacked, and connected to each other by printed wiring on the substrate. Specifically, the wire bonding is performed so that the pad electrode 105 and the pad electrode 125 of the LSI chip 103 are electrically connected to predetermined wiring portions provided on the substrate on which the LSI chip 103 itself is mounted. Similarly, the pad electrode 115 of the LSI chip 113 is wire-bonded so as to be electrically connected to a predetermined wiring portion provided on the substrate on which the LSI chip 113 itself is mounted. Here, wire bonding is performed so that the pad electrode 115 and the pad electrode 125 are electrically connected via a wiring provided on the substrate. In addition, the wiring to which the pad electrode 105 is connected by wire bonding on the substrate is further provided by an external terminal such as a lead by wire bonding or a bump electrode provided on a plane on the side where the LSI chip is not mounted by a through hole or the like. And electrically connected.

  Further, the LSI chips may be arranged on the front and back surfaces of the die and the substrate in the lead frame and connected to each other. Specifically, the LSI chip 103 is arranged on the surface of the substrate, and the pad electrode 105 and the pad electrode 125 of the LSI chip 103 are respectively connected to predetermined wiring portions provided on the surface side on which the LSI chip 103 itself is mounted. Wire bonding is performed so as to be electrically connected. Further, the LSI chip 113 is disposed on the back surface of the substrate, and the pad electrode 115 of the LSI chip 113 is electrically connected to a predetermined wiring portion provided on the back surface side where the LSI chip 113 itself is mounted. Wire bonding. Here, the pad electrode 115 and the pad electrode 125 are electrically connected to each other through the wiring provided on the substrate and the through hole. Further, the wiring on the substrate to which the pad electrode 105 is connected by wire bonding is further electrically connected to an external terminal such as a lead by wire bonding.

  Further, the pad electrodes may be connected to each other in a bump structure. This is a configuration in which the pad electrode 105 and the pad electrode 125 are directly connected without using wire bonding.

  In any case, an LSI chip having a pad electrode as in the present invention can be applied, and a desired function can be realized by interconnecting these LSI chips.

  However, the increase in cost and size due to the use of the substrate, the difficulty of mutual connection between LSI chips when using the front and back surfaces of the die, and the bump structure of the pad electrode of the upper LSI chip From the viewpoint of the necessity of dealing with the change in the arrangement of the pad electrodes to be connected to the upper LSI chip in the lower LSI chip with respect to the change in arrangement, as shown in FIGS. Those that interconnect with each other are more optimal.

  However, if it is desired to avoid as much as possible the influence of stress on each LSI chip in the laminated structure due to various factors such as wire bonding, two LSI chips are mounted on the substrate as described above. It is better to use the mutual connection between the two LSI chips. For this reason, the method using a substrate is suitable for products that place importance on reducing stress and products that have other factors that can sufficiently compensate for cost.

  Further, although related to the influence of stress on the above-described LSI chip, in the second embodiment, the large-sized LSI chip 203 is described as a microcomputer, and the small-sized LSI chip 213 is described as an EEPROM capable of batch erasing. However, it is not limited to this. For example, the LSI chip 203 having a large size may be an EEPROM that can be erased collectively, and the LSI chip 213 having a small size may be a microcomputer.

  For example, depending on the manufacturing process applied to the two LSI chips to be stacked, the case where the LSI chip of the microcomputer is smaller in size than the EEPROM LSI chip capable of batch erasure is considered. However, when the LSI chip 203 having a large size is an erasable EEPROM and the LSI chip 213 having a small size is a microcomputer, the following points should be considered.

  FIG. 24 is a diagram showing a layout of an internal circuit when a batch-erasable EEPROM is used as the LSI chip 913 corresponding to the LSI chip 203.

  The LSI chip 913 includes a memory cell region 913-1 in which a memory cell unit is disposed, a first peripheral circuit region 913-2 in which peripheral circuits such as a charge pump circuit are disposed, and a second in which other peripheral circuits are disposed. Peripheral circuit region 913-3. At this time, characteristics of the memory cell portion arranged in the memory cell region 913-1 are likely to change due to the influence of stress. FIG. 25 is a plan view in which an LSI chip 903 as a microcomputer is stacked on the main surface of the LSI chip 913. FIG. 26 is a plan view showing the relationship between the arrangement of internal circuits in the LSI chip 903 and the LSI chip 913 in FIG. Note that FIG. 25 shows a state in which the leads, the sealing resin, and the wires are deleted.

  As shown in FIG. 25, a pad electrode 915 for interfacing with the internal circuit of the LSI chip 903 is disposed on the main surface of the LSI chip 913. In FIG. 25, the LSI chips 913 are arranged in alignment on the two outer sides. An LSI chip 903 is disposed on the main surface of the LSI chip 913. On the main surface of the LSI chip 903, a pad electrode 925 for interfacing with an internal circuit of the LSI chip 913, which should be electrically connected to the pad electrode 915, is arranged. The pad electrode 925 is arranged along each side of the adjacent LSI chip 903 in parallel with the side of the LSI chip 913 on which the pad electrode 915 is arranged in consideration of the ease of wire bonding processing. On the main surface of the LSI chip 903, pad electrodes 905 to be electrically connected to external connection leads (not shown) are arranged. The pad electrodes 905 may be arranged in a staggered manner with the pad electrodes 925 along the same side as the side where the pad electrodes 925 are arranged on the outer periphery of the LSI chip 903, or the pad electrodes 925 are not arranged. You may arrange | position along a side. Further, when the pad electrode 905 is disposed along the same side as the side where the pad electrode 925 is disposed, the pad electrode 925 is disposed between the pad electrodes 905 if the interval between the adjacent pad electrodes 905 is wide. The pad electrode 905 and the pad electrode 925 may be arranged in a line. In this case, it is difficult to distinguish between the pad electrode 905 and the pad electrode 925 to be connected to the lead at the time of wire bonding, but a wire for electrically connecting the pad electrode 905 and the lead by wire bonding, It is easy to prevent a short circuit between the wire that electrically connects the pad electrode 915 and the pad electrode 925, and in order to prevent such a short circuit, the pad electrode 905 and the lead are electrically connected by wire bonding. Since it is not necessary to increase the height of the apex of the wire to be connected, the thickness of the sealing resin can be reduced. Note that the pad electrode 925 may be disposed in consideration of wire bonding with a lead to be connected.

  As shown in FIG. 26, the LSI chip 903 (the area where the area is arranged by a dotted line in FIG. 26) is located above the memory cell area 913-1 where the memory cell portion of the LSI chip 913 is arranged. It is arranged to completely cover.

  Such an arrangement has the following effects. That is, for example, the region 913-2 in FIG. 26 is a memory cell region due to a difference in thermal expansion coefficients of the LSI chips 903 and 913, a difference in thermal expansion coefficient of a sealing resin for sealing the LSI chips, and the like. Then, it can be seen that there are a portion of the memory cell that is covered by the LSI chip 903 and a portion that is not covered above the memory cell. When LSI chips stacked in such a state are sealed with resin, the stress on the memory cells is not uniform due to the difference in thermal expansion coefficient as described above (especially in the LSI chip 903 in the memory cell region). Memory cell at the boundary between the covered portion and the uncovered portion), and as a result, the characteristics of the memory cell are affected. Therefore, when another LSI chip 903 is stacked on the LSI chip 913 having such a memory cell area, the LSI chip 903 is completely above the memory cell area 913-1 as shown in FIG. The above-mentioned problem can be solved by arranging so as to cover.

  27 is a cross-sectional view of a semiconductor device in which the two stacked LSI chips of FIG. 25 are sealed with resin. FIG. 27 corresponds to the A-A ′ sectional view of FIG. 25. In addition, the same code | symbol is attached | subjected to the component similar to FIG. As shown in FIG. 27, the pad electrode 915 for interface and the pad electrode 925 are electrically connected by a wire 917. Further, the pad electrode 905 is electrically connected to the lead 9 by a wire 907. Note that the height of the apex of the wire 907 needs to be sufficiently high so that the wire 907 and the wire 917 are not short-circuited. Further, the resin 9 is sealed with a sealing resin 10 with a sufficient thickness so that the wire 917 is not exposed to the outside.

  FIG. 28 is a diagram showing a modified example of the layout of the internal circuit in the LSI chip 913. Similarly to FIG. 26, the area where the LSI chip 903 is arranged is indicated by a dotted line. In FIG. 28, the memory cell region 913-1 is set to a substantially central region of the LSI chip 913. The periphery of the memory cell region 913-1 is a first peripheral circuit region 913-2 and a second peripheral circuit region 913-3. With this arrangement, if the LSI chip 903 is arranged so as to cover the substantially central region of the main surface of the LSI chip 913, the LSI chip 903 can sufficiently cover the memory cell region 913-1.

  FIG. 29 is a plan view in which an LSI chip 903 as a microcomputer is stacked on the main surface of the LSI chip 913 in FIG. By arranging the memory cell region 913-1 as shown in FIG. 28, the arrangement of the pad electrodes as shown in FIG. 29 can be realized. That is, the pad electrode 925 for interface can be arranged on two parallel sides of the outer periphery of the LSI chip 903, and the pad electrode 905 for connecting to the lead can be arranged on the other two parallel sides. The pad electrode 915 is provided in the vicinity of the outer periphery of the LSI chip where the pad electrode 925 is disposed.

  30 and 31 are cross-sectional views of a semiconductor device in which the two stacked LSI chips of FIG. 31 are sealed with resin. 30 corresponds to the A-A ′ sectional view of FIG. 29, and FIG. 31 corresponds to the B-B ′ sectional view of FIG. 29.

  As shown in FIG. 30, the pad electrode 905 is electrically connected to the lead 9 by a wire 907. As shown in FIG. 31, the pad electrode 915 is electrically connected to the pad electrode 925 through a wire 917.

  As described above, as can be seen from FIGS. 28 to 31, the pad electrode 905 and the pad electrode 925 can be arranged along different sides on the outer periphery of the LSI chip 903, so that the wire 907 and the wire 917 are There is no problem of short circuit. Further, since it is not necessary to increase the height of the apex of the wire 907 in order to prevent such a short circuit, the thickness of the sealing resin can be made thinner in FIG. 30 than in the case of FIG. . Further, since the pad electrode 905 and the pad electrode 925 are arranged along different sides, it is possible to reduce erroneous wire bonding.

  In the above description, the LSI chip 913 is described as a batch erasable EEPROM. However, the LSI chip 913 is a batch as long as it has memory cells and circuits that cause the same stress problem as the batch erasable EEPROM. Not only the erasable EEPROM but also a method as shown in FIGS. 24 to 31 can be applied. The LSI chip 903 is not limited to a microcomputer. In an MCP using LSI chips of different sizes, the arrangement of LSI chips in the MCP in consideration of such stress is sufficiently effective even when applied to the conventional MCP shown in FIG.

  Thus, in the present invention, for example, any one of the two LSI chips can be used as a microcomputer and any of them can be used as a memory. That is, if one is provided with the pad electrode 125 for interface and the pad electrode 105 for connecting the lead as in the LSI chip 103, the upper side of this LSI chip can be obtained when the size of the other LSI chip is large. The LSI chip having the pad electrode 105 and the pad electrode 205 may be disposed on the LSI chip. When the size of the other LSI chip is small, the size of the LSI chip is provided on the LSI chip having the pad electrode 105 and the pad electrode 205. A small LSI chip may be arranged. In this way, by developing one LSI chip, it is possible to apply various sizes and functions as the other LSI chip, thereby providing various system LSIs in a short time. In this case, since it is not necessary to redevelop one LSI chip again, the cost can be reduced.

  Note that various modifications and application examples described in this specification can be applied to the configuration described with reference to FIGS.

  The pull-down resistor and the N-channel MOS transistor in the circuits shown in the above embodiments, modifications, and application examples may be a pull-up resistor or a P-channel MOS transistor depending on how to use the potential level of the selection signal SEL. Also good. In addition to the reset signal RES, other signals may be used, but the reset signal RES is suitable as one that is automatically set at the initial stage of the operation of the LSI chip.

1 is a cross-sectional view showing an internal structure of an MCP type semiconductor device 100 according to a first embodiment of the present invention. 1 is a plan view showing an internal structure of an MCP type semiconductor device 100 according to a first embodiment of the present invention. It is a perspective view explaining the assembly of the semiconductor device 100 in FIG. It is a block diagram which shows the structure of the microcomputer 50 which mounts EEPROM which can be erased collectively. It is a top view which shows the internal structure of the MCP type semiconductor device in the 2nd Embodiment of this invention, and is a figure of the semiconductor device as EEPROM version microcomputer. It is a top view which shows the internal structure of the MCP type semiconductor device in the 2nd Embodiment of this invention, and is a figure of the semiconductor device as a mask ROM version microcomputer. It is a figure which shows the circuit of LSI chip 203 connected to the pad electrode 205a. It is a conceptual diagram of the selection circuit 260 to which the selection signal SEL is input. 3 is a specific circuit diagram of a selection circuit 260. FIG. FIG. 6 is a plan view of a semiconductor device showing a modification example of FIG. 2. FIG. 6 is a plan view of a semiconductor device showing a modification example of FIG. 2. It is a top view of the semiconductor device which shows the application example of FIG. It is a top view of the semiconductor device which shows the modification of FIG. It is a top view of the semiconductor device which shows the application example of FIG. It is a top view of the semiconductor device which shows the modification in wire bonding. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows another conventional semiconductor device. FIG. 18 is a plan view of the semiconductor device of FIG. 17. It is a figure which shows the modification of the circuit of LSI chip 203 connected to the pad electrode 205a. It is a top view which shows the internal structure of the MCP type semiconductor device in the modification of the 2nd Embodiment of this invention. It is a figure which shows the circuit of LSI chip 203 connected to the pad electrode 205a and the pad electrode 205b. It is a figure which shows arrangement | positioning of a pad electrode and arrangement | positioning of a lead in the modification of this invention. It is a figure which shows the other example of the circuit of the LSI chip 203 connected to the pad electrode 205a and the pad electrode 205b. FIG. 3 is a diagram showing a layout of an internal circuit when a batch-erasable EEPROM is used as an LSI chip 913 corresponding to the LSI chip 203; 3 is a plan view in which an LSI chip 903 is stacked on the main surface of an LSI chip 913. FIG. FIG. 26 is a plan view showing the relationship between the arrangement of internal circuits in an LSI chip 903 and an LSI chip 913 in FIG. 25. FIG. 26 is a cross-sectional view of a semiconductor device in which two stacked LSI chips of FIG. 25 are sealed with resin. FIG. 20 is a diagram showing a modification of the layout of the internal circuit in the LSI chip 913. FIG. 29 is a plan view in which an LSI chip 903 is stacked on the main surface of an LSI chip 913 in the modification of FIG. FIG. 30 is a cross-sectional view (A-A ′ cross-sectional view) of a semiconductor device in which two stacked LSI chips of FIG. 29 are sealed with resin. FIG. 30 is a cross-sectional view (B-B ′ cross-sectional view) of a semiconductor device in which two stacked LSI chips of FIG. 29 are sealed with resin.

Explanation of symbols

9 Lead 103, 203, 503, 603, 703 LSI chip (lower side)
113, 213, 513, 613, 713 LSI chip (upper side)
105, 205, 505, 605, 705 Pad electrode (for lead connection)
115, 215, 515, 615, 715 Pad electrode (for internal interface)
125, 225, 325, 425, 525, 625, 725 Pad electrode (for internal interface)
107, 207, 507 wire 117, 217, 517, 717 wire

Claims (2)

In a semiconductor device in which a second semiconductor element is disposed on a first semiconductor element and the first and second semiconductor elements are sealed with a resin,
Having a plurality of external terminals,
The first semiconductor element has a main surface, and the main surface is electrically connected to any of a plurality of built-in circuits and electrically connected to any of the plurality of external terminals. A first pad electrode and a plurality of second pad electrodes electrically connected to any of the plurality of built-in circuits,
The second semiconductor element has a main surface, and the main surface is electrically connected to one of a plurality of built-in circuits and electrically connected to one of the second pad electrodes. A plurality of third pad electrodes are provided;
The plurality of circuits of the first semiconductor element are supplied with a selection circuit for selecting and controlling signal transmission / reception between the second pad electrode and a built-in circuit, and the selection circuit by inputting a first voltage. The voltage level is such that signals can be exchanged between the circuits in which the signal is incorporated, and when the second voltage is input, the selection circuit can exchange signals between the second pad electrode and the circuit incorporated therein. A control circuit for generating a control signal having a voltage level of
The plurality of first pad electrodes include a selection pad electrode electrically connected to the input of the control circuit, and the plurality of external terminals are electrically connected to the selection pad electrode, An external terminal for selection to which either the first voltage or the second voltage is input ;
The first semiconductor element has a first memory for storing a first program; the second semiconductor element has a second memory having a second program different from the first program; One of the first program and the second program is selectively executed in accordance with a selection state by the selection circuit.   2. The semiconductor device according to claim 1, wherein the first memory is a mask ROM, and the second memory is an EEPROM.

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