JP4087971B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, and more particularly to a variable electronic shutter control circuit and a pixel signal readout control circuit of the solid-state imaging device, and is used for a video camera, an electronic steel camera, and the like.
[0002]
[Prior art]
FIG. 12 shows an equivalent circuit of the CMOS solid-state imaging device (amplified CMOS image sensor) of Conventional Example 1 provided with a readout circuit capable of reading out pixel signals for each pixel.
[0003]
In FIG. 12, unit cells of 1 pixel (1 pixel) / 1 unit are formed in a cell region (imaging region) arranged in a two-dimensional matrix.
[0004]
Each unit cell includes, for example, four transistors Ta, Tb, Tc, Td, and one photodiode PD.
[0005]
That is, a photodiode PD to which a ground potential is applied to the anode side, a read transistor (shutter gate transistor) Td having one end connected to the cathode side of the photodiode PD, and a gate connected to the other end of the read transistor Td. An amplifying transistor Tb, a vertical selection transistor (row selection transistor) Ta having one end connected to one end of the amplifying transistor Tb, and a reset transistor Tc having one end connected to the gate of the amplifying transistor Tb. .
[0006]
In the cell region, corresponding to each pixel row, the read line 4 commonly connected to the gates of the read transistors Td of the unit cells in the same row, and the vertical selection transistors Ta of the unit cells in the same row. A vertical selection line 6 connected in common to the gates of the first row and a reset line 7 connected in common to the gates of the reset transistors Tc of the unit cells in the same row are formed.
[0007]
In the cell region, corresponding to each pixel column, a vertical signal line VLIN commonly connected to the other end side of each amplification transistor Tb of the unit cell in the same column, and each reset of the unit cell in the same column A power supply line 9 connected in common to the other end side of the transistor Tc and the other end side of each vertical selection transistor Ta is formed.
[0008]
Further, outside the one end side of the cell region, a plurality of load transistors TL respectively connected between one end side of the vertical signal line VLIN and the ground node are arranged in the horizontal direction.
[0009]
A plurality of noise canceller circuits including, for example, two transistors TSH and TCLP and two capacitors Cc and Ct are arranged in the horizontal direction outside the other end of the cell region.
[0010]
A plurality of horizontal selection transistors TH connected to the other end sides of the vertical signal lines VLIN via the noise canceller circuits are arranged in the horizontal direction.
[0011]
A horizontal signal line HLIN is commonly connected to the other ends of the horizontal selection transistor TH, and a horizontal reset transistor (not shown) and an output amplifier circuit AMP are connected to the horizontal signal line HLIN.
[0012]
Each noise canceller circuit includes a sample-hold transistor TSH having one end connected to the other end of the vertical signal line VLIN, and a coupling capacitor Cc having one end connected to the other end of the sample-hold transistor TSH. And a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and the ground node, and a potential clamping transistor TCLP connected to the connection node of the capacitors Cc and Ct. One end of the horizontal selection transistor TH is connected to a connection node of the capacitors Cc and Ct.
[0013]
Further, outside the cell region, a vertical shift register 2 for scanning and controlling a plurality of vertical selection lines 6 in the cell region, a horizontal shift register 3 for scanning the horizontal selection transistor TH, A timing generation circuit 10 for generating various timing signals to be supplied to the noise canceller circuit and the like; a bias generation circuit 11 for generating a predetermined bias potential at one end of a potential clamp transistor TCLP of the noise canceller circuit; A pulse selector 2a for selectively controlling the output pulse of the vertical shift register 2 to drive the vertical selection line 6 in each row of the cell region in a scanning manner is provided.
[0014]
FIG. 13 is a timing waveform diagram showing an example of the operation of the solid-state image sensor shown in FIG.
[0015]
Next, the operation of the solid-state image sensor of FIG. 12 will be described with reference to FIG.
[0016]
Signal charges generated by photoelectric conversion of incident light of each photodiode PD are accumulated in the photodiode PD.
[0017]
When the signal charge of the photodiode PD is read from a unit cell for one row in the horizontal blanking period, first, in order to select each vertical signal line VLIN, a signal (φADRES pulse) of the vertical selection line 6 of the selection target row By turning on, the row selection transistors Ta for one row are turned on.
[0018]
As a result, in the unit cell for one row, the source follower circuit including the amplification transistor Tb and the load transistor TL to which the power supply potential VDD (for example, 3.3 V) is supplied via the row selection transistor Ta is operated.
[0019]
Next, in the unit cell for one row, the reference voltage is output to the vertical signal line VLIN by turning on the signal (φRESET pulse) of the reset line 7 and resetting the gate voltage of the amplification transistor Tb to the reference voltage for a certain period. To do.
[0020]
However, there is a variation in the gate potential of the amplification transistor Tb reset as described above, and there is also a variation in the reset potential of the vertical signal line VLIN on the other end side.
[0021]
Therefore, in order to reset the variation in the reset potential of each vertical signal line VLIN, the drive signal (φSH pulse) of the sample hold transistor TSH in the noise canceller circuit is turned on in advance (for example, simultaneously with the turning on of the φADRES pulse), After the reference voltage is output to the vertical signal line VLIN, the reference signal is set at the connection node of the capacitors Cc and Ct of the noise canceller circuit by turning on the drive signal (φCLP pulse) of the potential clamping transistor TCLP for a predetermined time. To do.
[0022]
Next, after the φRESET pulse is turned off, the read line 4 in a predetermined row is selected and the signal (φREAD pulse) is turned on to turn on the read transistor Td, and the charge accumulated in the photodiode PD is amplified by the amplification transistor Tb. The gate potential is changed by reading to the gate. The amplification transistor Tb outputs a voltage signal corresponding to the change amount of the gate potential to the corresponding vertical signal line VLIN and the noise canceller circuit.
[0023]
Thereafter, by turning off the φSH pulse in the noise canceller circuit, a signal component (signal voltage from which noise is removed) corresponding to the difference between the reference voltage read out as described above and the signal voltage is converted into a capacitor Ct for charge accumulation. In addition, it can be accumulated during the horizontal effective scanning period.
[0024]
That is, noise mixed in the previous stage from the noise canceler circuit such as variations in reset potential of each vertical signal line VLIN caused by the cell region is removed.
[0025]
Then, by turning off the φADRES pulse, the vertical selection transistor Ta is controlled to be in an off state and the unit cell is in a non-selected state, whereby the cell region and each noise canceller circuit are electrically separated.
[0026]
In the subsequent horizontal effective scanning period, the horizontal selection transistor TH is sequentially turned on by sequentially turning on the drive signal (φH pulse) of the horizontal selection transistor TH, and the connection node (signal storage node) of the capacitors Cc and Ct. Are sequentially read out to the horizontal signal line HLIN, amplified by the output amplifier circuit AMP, and output.
[0027]
In the above operation, the voltage VVLIN of the vertical signal line VLIN becomes the operating voltage Vm (about 1.5 V) of the source follower circuit during the horizontal blanking period.
The noise removal operation described above is performed for each readout operation for each horizontal line.
[0028]
FIG. 14 is a timing waveform diagram showing an operation example of the timing generation circuit 10, the vertical shift register 2, and the pulse selector 2a in FIG.
[0029]
Here, a case where the solid-state imaging device of FIG. 12 is used in a system of 1 field = 1/30 Hz (30 frames / second image where one field is one frame) is shown.
[0030]
The timing generation circuit 10 shapes the external input pulse signals φVR and φHP with a buffer circuit, and inputs the pulse signal φVRR having a field cycle and the pulse signal φHPV having a horizontal cycle to the vertical shift register 2.
[0031]
The vertical shift register 2 clears all the register outputs during the period when the pulse signal φVRR input is “L” level and sets it to “L” level, and then performs a shift operation with the pulse signal φHPV to output the pulse signal ROi (i =... , n, n + 1,... are sequentially set to the “H” level and input to the pulse selector 2a.
[0032]
As shown in FIG. 13, the pulse selector 2a outputs the signal on the vertical selection line 6 (φADRES pulse), the signal on the reset line 7 (φRESET pulse), and the signal on the read line 4 (φREAD pulse) for each selection target row. Activate and scan selected rows.
[0033]
As described above, the solid-state imaging device of FIG. 12 outputs each output pulse signal ROi of the vertical shift register 2 for selecting and controlling a specific selection target row only once within one field period. That is, since the photodiode PD performs signal readout only once per field, an electronic shutter operation that equivalently controls the light reception time by controlling the signal accumulation time of the photodiode PD is impossible.
[0034]
On the other hand, FIG. 15 schematically shows a configuration of a CMOS solid-state imaging device of Conventional Example 2 capable of electronic shutter operation.
[0035]
This solid-state imaging device includes, for example, an imaging region (photoelectric conversion unit) 14 in which pixel cells 13 configured as shown in FIG. 12 are two-dimensionally arranged in a matrix, and a pixel column direction of the imaging region 14. In order to control to read out the photoelectric conversion signal of each pixel cell 13 formed in the pixel row direction of the imaging region 14 and in each pixel row unit to the plurality of vertical signal lines VLIN. A plurality of read control vertical selection lines 6, and a first vertical selection circuit (read vertical shift register) 2 for scanning and controlling the plurality of read control vertical selection lines 6 at a read timing. A horizontal selection transistor TH for selecting the vertical signal line VLIN, a horizontal selection circuit (horizontal selection shift register) 3 for selecting and controlling the horizontal selection transistor, and the horizontal selection circuit. A horizontal signal line HLIN for reading a signal of said selected vertical signal line VLIN by Torejisuta 3, and a power amplifier circuit AMP for outputting a signal read out to the horizontal signal line HLIN.
[0036]
Although not particularly illustrated, the load transistor and the noise canceller circuit as shown in FIG. 12 are provided in the periphery of the imaging region 14 in the same manner as the CMOS solid-state imaging device of the first embodiment.
[0037]
Further, a second vertical selection circuit (electronic shutter vertical shift register) 15 for scanning and controlling the plurality of readout control vertical selection lines 6 at a signal accumulation timing, and the first vertical selection circuit And a vertical drive circuit (not shown) for generating a drive signal for selectively driving the plurality of read control vertical selection lines 6 based on the output of the second vertical selection circuit.
[0038]
In other words, a vertical shift register 15 for electronic shutter is provided in addition to the vertical shift register 2 for reading, and the vertical shift register 15 for electronic shutter is also a selection target in the same manner as the vertical shift register 2 for reading at a predetermined timing. It is configured to scan a row.
[0039]
Thus, it becomes possible to select and control a specific selection target row at a timing twice in one field period by the vertical shift register 2 for reading and the vertical shift register 15 for electronic shutter.
[0040]
Therefore, before the read vertical shift register 2 selects and controls the selection target row and reads the pixel signal to the vertical signal line VLIN, the electronic shutter vertical shift register 15 selects and controls the selection target row and accumulates the pixel signal. Thus, an electronic shutter operation that equivalently controls the light receiving time can be performed.
[0041]
By the way, the CMOS solid-state imaging device of FIG. 15 having one readout vertical shift register 2 and one electronic shutter vertical shift register 15 as described above automatically generates a signal automatically in accordance with the output level of the light receiving sensor, for example. When a variable electronic shutter operation is performed in which the light receiving time is equivalently changed by changing the accumulation time, a difference in signal accumulation time occurs between pixel rows according to the length of the signal accumulation time, or two vertical shift registers. There is a problem that the load of 2 and 15 fluctuates.
[0042]
This problem will be described below.
[0043]
FIG. 16 shows an example in which the row selection timings of the two vertical shift registers 2 and 15 in FIG. 15 are fixed.
[0044]
As shown in FIG. 16, the timing at which the electronic shutter vertical shift register 15 performs row selection prior to the readout vertical shift register 2 is fixed, that is, the two vertical shift registers 2 and 15 select the row. The time difference for performing is always constant.
[0045]
When the row selection timings of the two vertical shift registers 2 and 15 are fixed as described above, the readout vertical shift register 2 and the electronic shutter vertical shift register 15 start selecting a certain frame from the first stage to the last stage. When the shift operation up to (that is, the number of pixels in the vertical direction of the solid-state imaging device) is completed, the process returns to the first stage and selection of the next frame is started.
[0046]
Therefore, the solid-state imaging device of FIG. 15 performs signal accumulation when performing a variable electronic shutter operation that changes the light reception time equivalently, for example, by automatically changing the signal storage time according to the output level of the light reception sensor. Depending on the length of time, there is a problem that a difference in signal accumulation time occurs between pixel rows and the load on the two vertical shift registers 2 and 15 fluctuates.
[0047]
Here, as a specific method for changing the signal accumulation time, the timing at which the electronic shutter vertical shift register 15 performs row selection prior to the reading vertical shift register 2 (the timing of the electronic shutter) is changed. The above problem will be described in detail with reference to FIG. 17 in the case where the length of time for storing pixel signals is changed.
[0048]
In FIG. 17, a read control pulse is a signal for starting the shift operation of the read vertical shift register 2, and a variable electronic shutter control pulse is a signal for starting the shift operation of the electronic shutter vertical shift register 15.
[0049]
(1) After the shift operation of the electronic shutter vertical shift register 15 is started by the electronic shutter control pulse generated at the timing t1 in FIG. 17 when the first frame is selected, before the shift operation up to the final stage ends ( Assume that an electronic shutter pulse is generated to select the second frame at timing t3 in FIG. 17 before all pixel rows are selected. In this case, the electronic shutter vertical shift register 15 is reset at the timing t3, and the shift operation (row selection) starts again from the first stage.
[0050]
Accordingly, when the shift operation of the read vertical shift register 2 is started by the read control pulse generated at the timing t2 in FIG. 17 and the first frame is read, the electron whose shift operation has been started at the timing t1. There is a difference in signal accumulation time between the pixel row selected and designated by the shutter vertical shift register 15 and the pixel row not designated and designated.
[0051]
When the difference in signal accumulation time occurs in this way, the readout output level fluctuates depending on the position of the pixel row, and image noise such as horizontal stripes occurs when the output signal of the solid-state imaging device is displayed on the screen of the image display device. Cause it to occur.
[0052]
(2) At the timing t4 in FIG. 17, the selected row of the electronic shutter vertical shift register 15 that started the shift operation at the timing t3 and the selected row of the read vertical shift register 2 that started the shift operation at the timing t2. Since a total of two pixel rows are selected, these two pixel rows serve as loads for the two vertical shift registers 2 and 15.
[0053]
On the other hand, at the timing t6 in FIG. 17, the selected row by the electronic shutter vertical shift register 15 that has started the shift operation at the timing t3 no longer exists, and the shift operation started at the timing t5 in FIG. Since one pixel row is selected by the readout vertical shift register 2, this one pixel row serves as a load for the two vertical shift registers 2 and 15.
[0054]
When the loads of the two vertical shift registers 2 and 15 fluctuate depending on the electronic shutter timing in this way, the voltage of the power supply line of the solid-state imaging device is changed and the output signal of the solid-state imaging device is displayed on the screen of the image display device. In such a case, horizontal stripes are generated, which causes the image quality to deteriorate remarkably.
[0055]
Note that problems such as a difference in signal accumulation time between pixel rows depending on the length of the signal accumulation time as described above and fluctuations in the load on the two vertical shift registers 2 and 15 are associated with CMOS type solid-state imaging devices. This is not limited to the case where a variable electronic shutter operation is performed in a CCD type solid-state imaging device.
[0056]
[Problems to be solved by the invention]
As described above, in the conventional solid-state imaging device, when the variable electronic shutter operation is performed by changing the signal accumulation time, a difference in the signal accumulation time occurs between the pixel rows depending on the length of the signal accumulation time, or the readout vertical There is a problem that the load of the shift register and the vertical shift register for electronic shutter fluctuates, causing image noise such as horizontal stripes on the display screen of the output signal.
[0058]
The present invention was made to solve the above problems, When a variable electronic shutter operation (continuous electronic shutter operation) is performed to change the pixel signal accumulation time on a field-by-field basis, fluctuations in the load of the readout vertical shift register and the electronic shutter vertical shift register can be prevented, and output signals can be displayed. An object of the present invention is to provide a solid-state imaging device capable of preventing the occurrence of image noise such as horizontal stripes on a screen.
[0059]
It is another object of the present invention to provide a solid-state imaging device capable of preventing a difference in signal accumulation time between pixel rows in accordance with the length of signal accumulation time when a continuous electronic shutter operation is performed.
[0060]
It is another object of the present invention to provide a solid-state imaging device capable of preventing the occurrence of image noise such as horizontal stripes on a display screen of an output signal when a continuous electronic shutter operation is performed.
[0063]
[Means for Solving the Problems]
First of the present invention 1 The solid-state imaging device includes a photoelectric conversion unit that photoelectrically converts incident light to a pixel to accumulate charges, a reading unit that reads the accumulated charges to a detection unit, an amplification unit that amplifies the read charges, and a charge of the detection unit Reset hand for resetting Step The unit cell having two-dimensionally arranged on the semiconductor substrate is provided in a horizontal direction corresponding to each pixel row in the imaging region, and an imaging region having a plurality of pixel rows, A plurality of read lines for transmitting a read drive signal for driving each read means of the unit cell And before A read drive signal is selectively supplied to a plurality of read lines to drive the read means. Hanging Direct drive means, row selection means for controlling the vertical drive means so as to sequentially drive the readout means of each pixel row in the imaging area twice at a desired signal accumulation timing and signal readout timing, and in the imaging area A plurality of vertical signal lines for transmitting in a vertical direction signals respectively output from the unit cells of the pixel rows provided corresponding to the pixel columns and sequentially driven by the vertical driving means, The row selection means includes a first means for driving the readout means for each pixel row at the signal readout timing by the vertical drive means, and the signal at the signal accumulation timing by the vertical drive means. Different among multiple pixel rows Read out pixel rows at the same time And at least two second means to be driven.
[0064]
First of the present invention 2 The solid-state imaging device of the first 1 In the solid-state imaging device, the imaging region further includes at least three dummy pixel rows in addition to the plurality of pixel rows for signal readout, and the row selecting unit is configured to perform the dummy pixel by the first unit. One dummy pixel row of the rows is driven, and the other two dummy pixel rows of the dummy pixel rows are driven by the two second means.
[0065]
First of the present invention 3 The solid-state imaging device of the first 1 Or second 2 In the solid-state imaging device, the row selection unit changes the signal accumulation timing within a period of one field period in units of one field corresponding to the period of signal readout timing of each pixel row.
[0066]
First of the present invention 4 The solid-state imaging device of the first 3 In the solid-state imaging device, the at least two second means drive the reading means by relatively different signal accumulation timings with respect to the signal reading timing, and the second means drives the reading means. The control operation of the vertical driving means is alternately switched every field.
[0067]
First of the present invention 5 The solid-state imaging device of the first to the first 4 In any one of the solid-state imaging devices, when the row selection unit drives the readout unit of each pixel row in the imaging region twice, other row adjacent to the readout line around the photoelectric conversion unit The vertical driving means is controlled so that the voltage is substantially the same during the two driving operations.
[0070]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0071]
<First Embodiment>
FIG. 1 shows an equivalent circuit of the amplification type CMOS solid-state imaging device according to the first embodiment.
[0072]
The CMOS solid-state image pickup device of FIG. 1 is largely the same as the CMOS solid-state image pickup device of Conventional Example 2 described above with reference to FIG. 15, but a vertical shift register 2a for reading and a vertical for an electronic shutter. Since the shift register 15a and the like are different and the others are the same, the same reference numerals as in FIG. 15 are given.
[0073]
That is, the CMOS solid-state imaging device of FIG. 1 includes, for example, an imaging region (photoelectric conversion unit) 14 in which pixel cells 13 configured as shown in Conventional Example 1 of FIG. A plurality of vertical signal lines VLIN formed in the pixel column direction of the imaging region 14 and a plurality of vertical signal lines formed in the pixel row direction of the imaging region 14 and the photoelectric conversion signal of each pixel cell 13 in units of pixel rows. A plurality of read control vertical selection lines 6 for controlling to read to the line VLIN, and a first vertical selection circuit for scanning and controlling the plurality of read control vertical selection lines 6 at a read timing (Read vertical shift register) 2a and a second vertical selection circuit (electronic shutter vertical shift register) for scanning and controlling the plurality of read control vertical selection lines 6 at the timing of signal accumulation. 15a and a drive signal for selectively driving the plurality of read control vertical selection lines 6 based on the output of the first vertical selection circuit 2a and the output of the second vertical selection circuit 15a. A vertical drive circuit (pulse selector) 16, a horizontal selection transistor TH for selecting the vertical signal line VLIN, a horizontal selection circuit (horizontal selection shift register) 3 for selecting and controlling the horizontal selection transistor TH, A horizontal signal line HLIN for reading a signal of the vertical signal line VLIN selected by the horizontal selection shift register 3; and an output amplifier circuit AMP for outputting a signal read to the horizontal signal line HLIN. is doing.
[0074]
As in the CMOS solid-state imaging device of Conventional Example 2 in FIG. 15, a load transistor and a noise canceller circuit as shown in FIG.
[0075]
And furthermore,
(1) Two dummy pixel rows (a first dummy pixel row 141 and a second dummy pixel row 142) are added to the imaging region 14 in addition to the original pixel row. (2) The readout vertical shift register (first vertical shift register) 2a has the number of shift stages of the original number of pixel rows in the imaging region 14 + 1, and the electronic shutter vertical shift register (second shift register) The vertical shift register) 15a also has the number of shift stages of the original number of pixel rows in the imaging region 14 + 1. (3) The vertical drive circuit 16 selects the final stage output signal of the vertical shift register 2a for reading and supplies it to the first dummy pixel row 141, and outputs the final stage output signal of the vertical shift register 15a for electronic shutter. Is selected and supplied to the second dummy pixel row 142.
[0076]
The two dummy pixel rows 141 and 142 have the same configuration as the original pixel row, but are added to act as a load when selected by the vertical drive circuit 16.
[0077]
In the solid-state imaging device of FIG. 1, the vertical shift register 15a for electronic shutter and the vertical shift register 2a for readout can select and control the same vertical selection line twice within one field period. A shutter operation for controlling the signal accumulation time of the photodiode) can be performed.
[0078]
In this case, the electronic shutter vertical shift register 15a performs a shift operation based on a shift clock signal for controlling the signal accumulation start timing, and selects and controls each corresponding pixel row during the shutter operation period. Control is performed so that accumulation is performed (reading is not performed), and the second dummy pixel row 142 is selected and controlled during a period other than the shutter operation period (a period from the end of the selection of the pixel row to the start of the next selection).
[0079]
The vertical shift register 2a for reading performs a shift operation based on a shift clock signal that controls the start timing of signal reading, and each corresponding pixel row is set in each horizontal period in the vertical effective scanning period in the vertical period. Selection control is performed, and the first dummy pixel row 141 is selected and controlled during the vertical blanking period.
[0080]
In other words, according to the solid-state imaging device of the first embodiment, one vertical driving circuit 16 corresponds to each output of the vertical shift register 2a for reading and the vertical shift register 15a for electronic shutter. Since (total 2) pixel rows are always selected and driven and the selection loads are always equal, it is possible to prevent the occurrence of horizontal stripes on the display screen due to variations in the read level due to the size of the selection loads.
[0081]
<Second Embodiment>
FIG. 2 shows an equivalent circuit of the amplification type CMOS solid-state imaging device according to the second embodiment.
[0082]
The CMOS solid-state imaging device of FIG. 2 is different from the CMOS solid-state imaging device of the first embodiment described above with reference to FIG. 1 in that (1) one dummy pixel row (third in the imaging region 14). (2) Further, one electronic shutter vertical shift register 15b having the same number of shift stages as the electronic shutter vertical shift register 15a is added, and each stage thereof is added. The output is switched and selected in units of fields and the output of each stage of the electronic shutter vertical shift register 15a and used in the vertical drive circuit (pulse selector) 16a. (3) The vertical drive circuit 16a has three vertical outputs. (4) A point of generating a drive signal for selectively driving the plurality of read control vertical selection lines 6 based on the outputs of the shift registers 2a, 15a and 15b. The drive circuit 16a is slightly different in that the final stage output signal of the added vertical shift register 15b for electronic shutter is supplied to the third dummy pixel row 143, and the others are the same. Are given the same reference numerals.
[0083]
FIG. 3 is a timing chart showing how the two electronic shutter vertical shift registers 15a and 15b alternately control the electronic shutter operation in field units in the solid-state imaging device of FIG.
[0084]
As can be seen from the timing chart shown in FIG. 3, in the solid-state imaging device shown in FIG. By alternately selecting in units, the electronic shutter operation is alternately distributed to the two vertical shift registers 15a and 15b dedicated to the electronic shutter in units of fields.
[0085]
In this case, the selected vertical shift registers 15a and 15b dedicated to the electronic shutter perform row selection prior to the readout vertical shift register 2a, and time for storing pixel signals by changing the timing thereof. It becomes possible to change the length of.
[0086]
Therefore, the same vertical line is selected twice in one field period by the electronic shutter vertical shift registers 15a and 15b and the readout vertical shift register 2, and the variable electronic shutter operation for controlling the signal accumulation time of the selected pixel is performed. Can do.
[0087]
Even if the electronic shutter control signal is input at a time interval shorter than the field period, the shift operation of one of the electronic shutter dedicated vertical shift registers 15a or 15b that has already started the shift operation has reached the final stage ( The signal storage time of the selected pixel is controlled by sequentially selecting up to the last pixel row without being reset halfway before the selection of all the pixel rows for reading is completed.
[0088]
Then, the second dummy pixel row 142 or the third dummy pixel row 143 is set in the period from the end of selection of the last row of readout pixel rows to the start of selection of the first readout pixel row in the next field period. Select and control.
[0089]
The vertical shift register 2a for reading selects and controls each corresponding pixel row during each horizontal period within the vertical effective scanning period, and selects and controls the first dummy pixel row 141 during the vertical blanking period.
[0090]
That is, the vertical shift registers 2a, 15a, and 15b continue to select dummy pixel rows after selecting all the readout pixel rows, and wait for selection start in the subsequent field period.
[0091]
That is, according to the solid-state imaging device of the second embodiment, the signal accumulation time is changed between fields by allocating the electronic shutter operation to two vertical shift registers dedicated to the electronic shutter alternately for each field. It becomes possible.
[0092]
In this case, it is possible to realize an electronic shutter function that continuously changes the signal accumulation time for each field while the scanning time for reading remains constant. In the same field, the signal accumulation time is the same for all selected pixel rows.
[0093]
When the variable electronic shutter operation is performed by changing the signal accumulation time in this way, it is possible to prevent the difference in the signal accumulation time between the pixel rows according to the length of the signal accumulation time. Generation of image noise such as can be prevented.
[0094]
Further, the vertical drive circuit 16a always sets one pixel row (three in total) corresponding to each output of the vertical shift register 2a for reading and the two vertical shift registers 15a and 15b for electronic shutter. Since selection driving is performed and the selection loads are always equal, it is possible to prevent horizontal stripes on the display screen from being generated due to fluctuations in the read level due to the size of the selection loads.
[0095]
The solid-state imaging device shown in FIGS. 1 and 2 is not limited to a CMOS type solid-state imaging device having a readout circuit capable of reading out a pixel signal for each pixel, but a CCD that performs readout in units of horizontal signal lines. The present invention can also be applied to a (charge coupled device) type solid-state imaging device.
[0096]
<Third Embodiment>
FIG. 4 shows an equivalent circuit of the amplification type CMOS solid-state imaging device of the third embodiment.
[0097]
The CMOS solid-state imaging device of FIG. 4 is equivalent to the CMOS solid-state imaging device of Conventional Example 1 described above with reference to FIG. 12 by automatically changing the signal accumulation time according to the output level of the light receiving sensor, for example. The variable electronic shutter operation for changing the light reception time can be continuously changed in units of fields.
[0098]
That is, the CMOS solid-state image pickup device of FIG. 4 is largely the same as the CMOS solid-state image pickup device of Conventional Example 1 described above with reference to FIG. 12, but (1) the vertical shift register 2 for reading and In addition, two electronic shutter vertical shift registers 21 and 22 are added. (3) Operation of two electronic shutter vertical shift registers 21 and 22 (output operation of control pulse of signal accumulation time) ) Is alternately added for each field, and a register switching control circuit (SEL) 23 is added. (4) The configurations of the timing generation circuit 10a and the pulse selector circuit 24 are different, and the others are the same. The same reference numerals as in FIG.
[0099]
That is, in FIG. 4, the cell region (imaging region) includes, for example, four pixels Ta, Tb, Tc, Td and one pixel / unit unit composed of one photodiode PD. The cells are arranged in a two-dimensional matrix. In this case, each unit cell includes a photodiode PD to which a ground potential is applied to the anode side, a read transistor (shutter gate transistor) Td having one end connected to the cathode side of the photodiode PD, and the other end of the read transistor Td. Amplifying transistor Tb having a gate connected to the side, a vertical selection transistor (row selection transistor) Ta having one end connected to one end of the amplifying transistor Tb, and a reset having one end connected to the gate of the amplifying transistor Tb And a transistor Tc.
[0100]
In the cell region, a plurality of read lines 4 commonly connected to the gates of the read transistors Td of the unit cells in the same row and the vertical selections of the unit cells in the same row corresponding to the pixel rows. A vertical selection line 6 commonly connected to the gate of the transistor Ta and a reset line 7 commonly connected to the gates of the reset transistors Tc of the unit cells in the same row are formed.
[0101]
In the cell region, corresponding to each pixel column, a vertical signal line VLIN commonly connected to the other end side of each amplification transistor Tb of the unit cell in the same column, and each reset of the unit cell in the same column A power supply line 9 connected in common to the other end side of the transistor Tc and the other end side of each vertical selection transistor Ta is formed.
[0102]
Further, outside the one end side of the cell region, a plurality of load transistors TL respectively connected between one end side of the vertical signal line VLIN and the ground node are arranged in the horizontal direction.
[0103]
A plurality of noise canceller circuits including, for example, two transistors TSH and TCLP and two capacitors Cc and Ct are arranged in the horizontal direction outside the other end of the cell region.
[0104]
A plurality of horizontal selection transistors TH connected to the other end sides of the vertical signal lines VLIN via the noise canceller circuits are arranged in the horizontal direction.
[0105]
A horizontal signal line HLIN is commonly connected to the other ends of the horizontal selection transistor TH, and a horizontal reset transistor (not shown) and an output amplifier circuit AMP are connected to the horizontal signal line HLIN.
[0106]
Each noise canceller circuit includes a sample-hold transistor TSH having one end connected to the other end of the vertical signal line VLIN, and a coupling capacitor Cc having one end connected to the other end of the sample-hold transistor TSH. And a charge storage capacitor Ct connected between the other end of the coupling capacitor Cc and the ground node, and a potential clamping transistor TCLP connected to the connection node of the capacitors Cc and Ct. One end of the horizontal selection transistor TH is connected to a connection node of the capacitors Cc and Ct.
[0107]
Further, outside the cell region, a vertical shift register 2 for reading and two vertical shift registers (ES1) 21 for electronic shutter for scanning and controlling a plurality of vertical selection lines 6 in the cell region, and (ES2) 22, a pulse selector 24 for selectively controlling the output pulses of the three vertical shift registers 2, 21, 22 to drive the vertical selection lines 6 in the respective rows of the cell region in a scanning manner, the plurality of horizontal The operation of the horizontal shift register 3 for driving the selection transistor TH in a scanning manner and the vertical shift registers 21 and 22 for the two electronic shutters (the output operation of the control pulse of the signal accumulation time) are alternately switched on a field basis. A register switching control circuit 23 for controlling, a timing generation circuit 10a for generating various timing signals, and a noise canceller circuit Position bias generating circuit 11 for generating a predetermined bias potential, such as to one end of the transistor TCLP for clamping are arranged, respectively.
[0108]
The timing generation circuit 10a receives a field cycle timing signal φVR, an accumulation time control timing signal φES variably set in the field cycle, a pulse signal φHP corresponding to a horizontal blanking period, and a clock pulse signal φCK.
[0109]
Then, the timing signal φVR input is buffer-shaped to generate a timing signal φVRR to be supplied to the read vertical shift register, and the pulse signal φHP input is buffer-shaped to read the vertical shift register and two read signals. A timing signal φHPV to be supplied to the vertical shift registers 21 and 22 for the electronic shutter is generated.
[0110]
Further, timing signals φROREAD, φESREAD, φRESET, and φADRES to be supplied to the pulse selector 24 are generated, and pulse signals φCLP and φSH to be supplied to the noise canceller circuit are generated.
Further, a pulse signal φH to be supplied to the horizontal shift register 3 is generated.
[0111]
Also, a field switching control pulse signal φFI is generated based on the field cycle timing signal φVR, and is supplied to the register switching control circuit 23 together with a signal accumulation time control timing signal φESR.
[0112]
The register switching control circuit 23 alternately switches the supply destination of the timing signal φESR for accumulation time control for each field unit based on the input of the pulse signal φFI for field switching control. In this case, the signal accumulation time control timing signal supplied to the electronic shutter vertical shift register 21 is represented by φESR1, and the signal accumulation time control timing signal supplied to the electronic shutter vertical shift register 22 is represented by φESR2. ing.
[0113]
FIG. 5 is a circuit diagram showing an example of the pulse selector 24 in FIG.
[0114]
The pulse selector shown in FIG. 5 receives the output signal ROn of the vertical shift register for reading, the output signals ES1n and ES2n of the two vertical shift registers 21 and 22 for electronic shutter, and from the timing generation circuit 10a. Provided with timing signals φROREAD, φESREAD, φRESET, and φADRES to be supplied, and performs logical processing of these input signals to output various drive signals φREADn, φRESET, and φADRESn, and is configured by a logic gate to be supplied to the cell region Has been.
[0115]
That is, when the output signal ROn of the vertical shift register for reading is in an active state, the timing signal φROREAD is selected and output as the read line drive signal φREADn, and the output signals of the two vertical shift registers 21 and 22 for the electronic shutter are output. When either ES1n or ES2n is active, the timing signal φESREAD is selected and output as the read line drive signal φREADn.
[0116]
When one of the output signal ROn of the vertical shift register for reading Ron and the output signals ES1n and ES2n of the two vertical shift registers 21 and 22 for electronic shutter is active, the timing signal φRESET is selected. The reset line drive signal φRESETn is output.
[0117]
When the output signal ROn of the vertical shift register for reading is in an active state, the timing signal φADRES is selected and output as the vertical selection line drive signal φADRESn.
[0118]
FIG. 6 illustrates a timing generator circuit 10a, three vertical shift registers 2 in FIG. 4 in order to explain the variable electronic shutter operation that can be continuously changed in the field unit in the solid-state imaging device of FIG. FIG. 6 is a timing waveform diagram showing an operation example of the pulse selectors 21 and 22 and the pulse selector 24;
[0119]
Here, a case where the solid-state imaging device of FIG. 4 is used in an imaging system of 1 field = 1/30 Hz (30 frames / second image where one field is one frame) is shown.
[0120]
In FIG. 6, φVR is a field cycle timing signal input, φES is a timing signal input for accumulation time control that is variably set in the field cycle, φVRR is a field cycle timing signal supplied to the read vertical shift register, φFI Is a pulse signal for field switching control, φESR1 is a timing signal for accumulation time control supplied to the vertical shift register 21 for one electronic shutter every other field, and φESR2 is a vertical shift register 22 for the other electronic shutter. An accumulation time control timing signal supplied at one field interval, R0 (i) is the output of the vertical shift register R0 for reading, ES1 (i) is the output of the vertical shift register 21 for one electronic shutter, ES2 ( i) is the output of the vertical shift register 22 for the other electronic shutter. That.
[0121]
FIG. 7 is a timing waveform diagram showing an example of the electronic shutter operation within one field period in FIG.
[0122]
In FIG. 7, ESn is an output signal of the nth stage of the vertical shift register 21 or 22 for electronic shutter, and ROn is an output signal of the nth stage of the vertical shift register 2 for reading.
[0123]
tHES indicates one horizontal period in which the n-th stage output signal ESn of the electronic shutter vertical shift register 21 or 22 is in an active state (“H” level).
[0124]
tHRO represents one horizontal period in which the n-th stage output signal ROn of the vertical shift register 2 for reading is in an active state (“H” level).
[0125]
HBLK is a control pulse signal for dividing one horizontal period into a horizontal blanking period and a horizontal effective scanning period.
[0126]
φCLP and φSH are pulse signals supplied to the noise canceller circuit, and are generated for each horizontal blanking period.
[0127]
φH is a pulse signal supplied to the horizontal selection transistor TH, and is generated so that the horizontal selection transistors TH arranged in the horizontal direction in the horizontal effective scanning line period are sequentially turned on.
[0128]
φADRES, φRESET, and φREAD are pulse signals supplied from the pulse selector 24 to the selected pixel row. Of these, φRESET and φREAD are activated within the horizontal blanking period during the signal accumulation operation and the signal read operation, respectively. However, φADRES is not generated during the signal accumulation operation and is activated during the horizontal blanking period during the signal read operation.
[0129]
In this case, the pulse signal φADRES is activated twice intermittently so that the vertical selection line 6 of the same row is selected and controlled twice in the horizontal blanking period during the signal reading operation for the reason described later. Generated to be in a state.
[0130]
Next, the operation of the solid-state imaging device of FIG. 4 will be described with reference to FIGS. 6 and 7.
[0131]
The operation of the solid-state imaging device of FIG. 4 is basically the same as that of the solid-state imaging device of the conventional example 1 (FIG. 12) (FIG. 13) described above. First, different operations will be described.
[0132]
That is, when performing the electronic shutter operation, the solid-state imaging device of FIG. 4 causes the register switching control circuit 23 to alternately start the shift operations of the two electronic shutter vertical shift registers 21 and 22 in units of fields. By alternately selecting the output in the field unit, the electronic shutter operation is alternately distributed to the two vertical shift registers 21 and 22 dedicated to the electronic shutter in the field unit.
[0133]
Thus, as shown in the field periods tFa and tFb in FIG. 6, even when the signal accumulation time control timing signal φES is input at a time interval shorter than the field period, the vertical shift registers 21 and 22 dedicated to the electronic shutter are used. Can operate simultaneously.
[0134]
In this case, the shift operation of the vertical shift register 21 or 22 dedicated for the electronic shutter which has already started the shift operation by the timing signal φESR1 or φESR2 generated first does not end the selection control of all the pixel rows for reading. It is possible to control the signal accumulation time of the selected pixel by sequentially selecting to the end of the readout pixel row without being reset in the middle.
[0135]
In other words, it is possible to realize an electronic shutter function (continuous electronic shutter operation) that continuously changes the signal accumulation time in field units while the scanning time for reading remains constant. In the same field, the signal accumulation time is the same for all selected pixel rows.
[0136]
In addition, as shown in FIG. 7, pulse signals φRESET and φREAD are supplied to the nth pixel row selected and controlled by the output signal ESn of the nth shift stage of the electronic shutter vertical shift register in the horizontal period tHES. Then, the signal charge previously accumulated in the photodiode PD in the nth pixel row is read out to the gate of the amplifying transistor, thereby making the signal charge of the photodiode zero.
[0137]
In this case, since the pulse signal φADRES remains “L” and the vertical selection transistor remains off, the signal charge read to the gate of the amplification transistor is not output to the vertical signal line VLIN.
[0138]
Thereafter, during the signal read operation from the pixel row, after φRESET is temporarily activated during the horizontal blanking period in the horizontal period tHRO, φADRES is activated, and φREAD is temporarily activated.
[0139]
In this case, when the φREAD is in an active state (“H” level), a noise jump due to the influence of capacitive coupling between the photodiode and its peripheral wiring (φADRES wiring described later in this example) is prevented. The φADRES pulse is temporarily inactivated (“L” level) so as to be in the same state as in the signal accumulation operation, and the φREAD is temporarily activated during the period in which this φADRES is inactive.
[0140]
The operation during signal readout in the horizontal blanking period in the horizontal period tHRO will be described in detail. First, after resetting the gate electrode of the amplification transistor Tb to the reference potential by φRESET, φADRES is activated (first time). Then, the vertical selection transistor Ta of the nth pixel row is turned on, and the pulse signal φCLP supplied to the noise canceller circuit is activated during this active period to clamp the black level.
[0141]
Then, by activating φREAD within the period in which φADRES is inactive, the signal charge previously accumulated in the photodiode PD is read out to the gate of the amplification transistor Tb.
[0142]
Then, φADRES is activated again (second time), the vertical selection transistor Ta of the nth pixel row is turned on again, and the signal charge read to the gate of the amplification transistor Tb is transferred to the vertical signal line VLIN. Output to.
[0143]
With the above operation, the signal accumulation time is from the end point of the active state (“H” level) of the read line drive signal φREAD in the horizontal period tHES to the activation point of the read line drive signal φREAD in the horizontal period tHRO.
[0144]
FIG. 8A is a plan view showing a part of the unit cell in the imaging region in order to explain the noise jump.
[0145]
FIG. 8B is a cross-sectional view taken along the line aa ′ in FIG.
[0146]
8 (c) and 8 (d) respectively correspond to the inside of the substrate in the case where φREAD is activated when φADRES is “L” level / “H” level in FIG. The potential potential of Here, a case where the power supply potential is 3.3 V, for example, is shown.
[0147]
8A and 8B, reference numeral 81 denotes a P-type well region formed in the surface layer portion of the silicon substrate, and reference numeral 82 denotes an element isolation region (for example, a LOCOS region) selectively formed in the substrate surface layer portion. An n-type region serving as a cathode region of the photodiode and a source region of the read transistor Td and an n-type region (detection node DN) serving as the drain region of the read transistor Td are selectively formed in the element region of the substrate surface layer portion. ing.
[0148]
A gate electrode (part of the read line 4) made of polysilicon wiring is formed on the channel region of the read transistor Td via an insulating gate film, and an element isolation region in the vicinity of the n-type region of the photodiode PD. A vertical selection line 5 and a reset line 7 made of polysilicon wiring are formed substantially in parallel on 82.
[0149]
In the reading operation of the present embodiment, as shown in FIG. 8C, when the φADRES wiring adjacent to the photodiode PD is at “L” level, φREAD is activated and the signal charge is read out. The potential of the substrate under the photodiode PD is lowered by −VCa by the coupling capacitance Ca existing between the φADRES wiring, and the stored charge QCa of the photodiode PD is read out.
[0150]
On the other hand, as shown in FIG. 8D, when φREAD is activated and the signal charge is read when the φADRES wiring adjacent to the photodiode PD is at “H” level, the signal charge is read between the photodiode PD and the φADRES wiring. Since the potential potential in the substrate under the photodiode PD is raised by + VCa due to the coupling capacitance Ca existing in the capacitor PD (noise jumps in), the accumulated charge QCa of the photodiode PD is not read out, and the output of the solid-state imaging device When the signal is displayed on the screen of the image display device, the black signal is crushed and the image becomes unsightly.
[0151]
In the solid-state imaging device of the third embodiment, as in the solid-state imaging device of the second embodiment, (1) first to third dummy pixel rows are added to the imaging region. (2) The number of shift stages of the three vertical selection circuits 2, 21, 22 is set to the number of original imaging pixel rows + 1, and (3) a plurality of vertical selection circuits 2, 21, 22 are output based on the outputs of the vertical selection circuits 2, 21, 22 When the pulse selector 24 generates a drive signal for selectively driving the horizontal control line group (4, 6, 7), the activation period of the final stage output signal of the vertical selection circuit 2 is the first dummy. The pixel row is selected and driven. During the activation period of the final stage output signal of the second vertical selection circuit 21, the second dummy pixel row is selected and driven, and the final stage output of the third vertical selection circuit 22 is output. The signal activation period may be configured to select and drive the third dummy pixel row. .
[0152]
With such a configuration, the pulse selector 24 has one pixel (three in total) corresponding to each output of the vertical shift register 2 for reading and the two vertical shift registers 21 and 22 for electronic shutter. Since the rows are always selected and driven, and the selection loads are always equal, it is possible to prevent the occurrence of horizontal stripes on the display screen due to fluctuations in the read level due to the size of the selection loads.
[0153]
In the third embodiment, the case where the φADRES wiring exists as a peripheral wiring that causes a blackout problem due to capacitive coupling with the photodiode PD has been described. However, the φRESET wiring or other wiring is used as the peripheral wiring. Even if it exists, there is a possibility that a black signal collapse (black collapse) may occur due to capacitive coupling between these wirings and the photodiode PD. Therefore, these wirings are also the same as the φADRES wiring in the third embodiment. Similarly, the level may be controlled.
[0154]
That is, as described above, the applied period of the peripheral wiring of the photodiode PD other than the readout gate wiring adjacent to the photodiode PD is the activation period of the signal readout pulse φREAD during the signal readout operation and the readout pulse φREAD during the electronic shutter operation. By applying the same voltage during the activation period, it is possible to control so that excess charges are not read out from the photodiode PD by capacitive coupling between the photodiode PD and the peripheral wiring. An image is obtained.
[0155]
Note that the present invention can also be applied to a solid-state imaging device having an array of unit cells of 2 pixels / 1 unit as described in the following fourth embodiment according to each of the above embodiments.
[0156]
<Fourth embodiment>
FIG. 9 shows an equivalent circuit of a unit cell of 2 pixels / 1 unit in the amplification type CMOS solid-state imaging device of the fourth embodiment. Since this CMOS solid-state imaging device can be configured in the same manner as the above-described embodiments except for the configuration of the unit cell, the configuration of the unit cell of 2 pixels / 1 unit will be mainly described below.
[0157]
The unit cell 30 shown in FIG. 9 has two photodiodes 31a and 31b. The two photodiodes 31a and 31b are given a ground potential to each anode side, and each cathode side corresponds to each. Commonly connected to the gate of one amplification transistor 33 through read transistors (shutter gate transistors) 32a and 32b. Read lines 4a and 4b are connected to the gates of the two read transistors 32a and 32b, respectively.
[0158]
The amplification transistor 33 has one end connected to the vertical signal line VLIN and the other end connected to the power supply line 9 via the vertical selection transistor 34 (that is, the amplification transistor 33 is connected to the source follower). A vertical selection line (address line) 6 is connected to the gate of the transistor 34.
[0159]
Further, one reset transistor 35 is connected between the gate of the amplification transistor 33 and the power supply line 9, and the reset line 7 is connected to the gate of the reset transistor 35.
[0160]
The unit cell of 2 pixels / 1 unit having the above configuration is arranged in a two-dimensional matrix in the imaging region. The two read lines (first read line 4a and second read line 4b), vertical selection line (address line) 6 and reset line 7 are formed in the horizontal direction on the imaging region, The vertical signal line VLIN and the power supply line 9 are formed in the vertical direction on the imaging region.
[0161]
FIG. 10A shows an example of a plane pattern of the unit cell of 2 pixels / 1 unit in FIG. 9, and FIG. 10B schematically shows a cross-sectional structure along the line BB.
[0162]
10A and 10B, reference numeral 90 denotes an N-type silicon substrate, and a P-well 91 is formed on the surface layer portion thereof. In the surface layer portion of the P-well 91, there are an element isolation region (for example, a LOCOS region) 92, a cathode region of one photodiode 31a, an N-type impurity region 931 serving as a source region of one read transistor 32a, and the other photodiode 31b. The N-type impurity region 932 serving as the source region of the other read transistor 32b and the SDG region of the NMOS transistor (only the N-type impurity region 94 serving as the common drain of the read transistors 32a and 32b is selectively shown). Is formed.
[0163]
A silicon oxide film (gate insulating film) 95 is formed on the substrate surface, and a field ion implantation region 96 is formed below the bottom surface of the LOCOS region 92.
[0164]
97 is a polysilicon gate wiring partially including the gate electrode of the amplification transistor 33, 98 is an N-type impurity region serving as a drain region of the amplification transistor 33 and a source region of the vertical selection transistor 34, and 99 is a source region of the reset transistor 35. This is an N-type impurity region.
[0165]
Reference numeral 100 denotes a wiring connecting the source region 99 of the reset transistor 35, the gate wiring 97 of the amplification transistor 33, and the common drain region of the two read transistors 32a and 32b.
[0166]
The read line 4a is composed of a polysilicon gate wiring partly including the gate electrode of the read transistor 32a, and the read line 4b is composed of a polysilicon gate wiring partly including the gate electrode of the read transistor 32b.
[0167]
The vertical selection line (address line) 6 is a polysilicon gate wiring partly including the gate electrode of the vertical selection transistor 34, and the reset line 7 is a polysilicon gate wiring partly including the gate electrode of the reset transistor 35.
[0168]
33 a is a contact portion between the source region of the amplification transistor 33 and the vertical signal line VLIN, and 34 a is a contact portion between the drain region of the vertical selection transistor 34 and the power supply line 9. 97a is a contact portion between the gate wiring 97 and the wiring 100 of the amplification transistor 33, 99a is a contact portion between the source region 99 and the wiring 100 of the reset transistor 35, and 99b is a contact portion between the drain region of the reset transistor 35 and the power supply line 9. , 100a is a contact portion between the wiring 100 and the common drain region of the two read transistors 32a, 32b.
[0169]
The operation of the unit cell of 2 pixels / 1 unit configured as described above is basically the same as the operation of the unit cell of 1 pixel / 1 unit, in which five transistors are operated in a predetermined order to read signal charges from the photodiode. The operation is the same, except that signal charges are read from the two photodiodes 31a and 31b at different timings. That is, when reading the signal charge from one photodiode 31a, the "H" level read signal is applied to the first read line 4a and the "L" level read signal is applied to the second read line 4b. When reading the signal charge from the other photodiode 31b, the "H" level read signal is applied to the second read line 4b, and the "L" level read signal is applied to the first read line 4a. .
[0170]
<Fifth embodiment>
By the way, in the CMOS solid-state imaging device having the array of unit cells of 2 pixels / 1 unit as described above, different timings are obtained from the two photodiodes 31a and 31b even when the electronic shutter function is not provided. As described above, the address line drive signal is intermittently driven twice as described above when reading the signal charge, thereby preventing the occurrence of horizontal stripes on the display screen when the output signal is displayed on the screen of the image display device. It becomes possible to do.
[0171]
FIG. 11 is a timing waveform diagram illustrating an example of a signal read operation in a part of one field period in the CMOS solid-state imaging device according to the fifth embodiment.
[0172]
In FIG. 11, φRESET, φADRES, φREAD1 or φREAD2 is a pulse signal supplied from the pulse selector to the selected pixel row, and is activated during the horizontal blanking period during the signal read operation, but φREAD1, φREAD2 Are supplied within different horizontal blanking periods.
[0173]
Here, the distance between the second read line 4b supplied with φREAD2 and the address line 6 is shorter than the distance between the first read line 4a supplied with φREAD1 and the address line 6, and the first read line This is because the coupling capacity between the second read line 4b and the address line 6 is larger than the coupling capacity between the address line 6a and the address line 6, and the influence on the signal charges read from the two photodiodes 31a and 31b is different. As a result, horizontal stripes on the display screen may be generated when the output signal is displayed on the screen of the image display device.
[0174]
However, φADRES is generated so as to be activated twice intermittently so that the address line 6 in the same row is selected and controlled twice in the horizontal blanking period in the signal read operation. Since φADRES is at “L” level when the signal charges are read from the diodes 31a and 31b, respectively, the influence at the time of reading the signal charges is almost equal, and the problem of occurrence of horizontal stripes on the display screen as described above is caused. Can be prevented.
[0175]
In addition, the present invention is not limited to the solid-state imaging devices of the above-described embodiments, but can be applied to a stacked solid-state imaging device in which photoelectric conversion units are stacked.
[0177]
【The invention's effect】
Claims of the invention 1 According to the solid-state imaging device according to each of the claims dependent thereon, the variable electronic shutter that changes the signal accumulation time in the field unit by allocating the electronic shutter operation alternately in the field unit to the shift registers dedicated to the two electronic shutters Operation (continuous electronic shutter operation) can be realized. In this case, it is possible to prevent the difference in the signal accumulation time between the pixel rows according to the length of the signal accumulation time, and it is possible to prevent the occurrence of image noise such as horizontal stripes on the display screen of the output signal.
[0178]
Especially claims 2 According to the solid-state imaging device of claim 1 As with the solid-state imaging device, a continuous electronic shutter operation can be realized, and two dummy pixel rows are provided corresponding to two vertical shift registers dedicated to the electronic shutter, and a read shift register and two electronic shutters are provided. By always selectively driving the three pixel rows that are selected and controlled by the dedicated shift register, it is possible to eliminate load fluctuations associated with the pixel row selection and to prevent horizontal stripes on the display screen.
[Brief description of the drawings]
FIG. 1 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device according to a second embodiment of the present invention.
3 is a timing chart showing how two electronic shutter vertical shift registers alternately control the electronic shutter operation on a field basis in the solid-state imaging device of FIG. 2;
FIG. 4 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device according to a third embodiment of the present invention.
5 is a circuit diagram showing an example of a pulse selector in FIG. 4. FIG.
6 is a timing waveform diagram showing an operation example of the timing generation circuit, the first vertical shift register to the third vertical shift register, and the pulse selector in FIG. 4;
7 is a timing waveform diagram showing an example of an electronic shutter operation within one field period in FIG. 6. FIG.
8A and 8B are a plan view, a cross-sectional view, and a diagram showing a potential potential in a substrate for illustrating a part of a unit cell in an imaging region in order to explain an operation of suppressing noise jumping in the electronic shutter operation shown in FIG.
FIG. 9 is a diagram showing an equivalent circuit of a unit cell of 2 pixels / 1 unit in an amplification type CMOS solid-state imaging device according to a fourth embodiment of the present invention.
10 is a diagram schematically illustrating an example of a planar pattern of a unit cell of 2 pixels / 1 unit in FIG. 9 and an example of a cross-sectional structure thereof.
FIG. 11 is a timing waveform diagram showing an example of a signal reading operation within one field period in the CMOS solid-state imaging device according to the fifth embodiment of the present invention.
12 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device of Conventional Example 1. FIG.
13 is a timing waveform diagram showing an operation example of the CMOS solid-state imaging device of FIG.
14 is a timing waveform diagram showing an operation example of the timing generation circuit, vertical shift register, and pulse selector in FIG. 13;
15 is a diagram showing an equivalent circuit of a CMOS solid-state imaging device of Conventional Example 2. FIG.
FIG. 16 is a diagram showing an example of row selection timing of two vertical shift registers in FIG. 15;
17 changes the timing at which the electronic shutter vertical shift register performs row selection before the readout vertical shift register in order to change the signal storage time in the solid-state imaging device of FIG. The timing diagram shown in order to demonstrate the problem in the case of changing the length of time to perform.
[Explanation of symbols]
2 ... vertical shift register for reading,
3 ... Horizontal shift register,
4 ... Reading line,
6 ... vertical selection line,
7 ... Reset line,
9 ... Power line,
10a: timing generation circuit,
21, 22 ... Vertical shift register for electronic shutter,
23. Switching control circuit,
24. Vertical drive circuit (pulse selector),
PD ... photodiode,
Ta: vertical selection transistor (row selection transistor),
Tb: amplification transistor,
Tc: reset transistor,
Td: readout transistor,
TH: Horizontal selection transistor,
VLIN: Vertical signal line,
HLIN: Horizontal signal line.

Claims (8)

Photoelectric conversion means for photoelectrically converting incident light to the pixel and accumulating charges, reading means for reading the accumulated charges to the detection section, amplification means for amplifying the read charges, reset for resetting the charges of the detection section unit cell having a hand stage is being two-dimensionally arranged on a semiconductor substrate, an imaging region having a plurality of pixel rows,
A plurality of read lines provided in the horizontal direction corresponding to the respective pixel rows in the imaging region, and for transmitting a read drive signal for driving each read means of the unit cell of the corresponding pixel row ;
A vertical drive means that drive the said reading means selectively supplies the read drive signal before Symbol plurality of read lines,
Row selection means for controlling the vertical drive means so as to sequentially drive the readout means for each pixel row in the imaging region twice at a desired signal accumulation timing and signal readout timing;
A plurality of vertical signal lines that are provided corresponding to the respective pixel columns in the imaging region and that transmit signals output from the unit cells of the pixel rows sequentially driven by the vertical driving unit in the vertical direction; Equipped,
The row selection means includes:
First means for driving the readout means for each pixel row at the signal readout timing by the vertical drive means, and readout means for different pixel rows among the plurality of pixel rows at the signal accumulation timing by the vertical drive means. A solid-state imaging device comprising: at least two second means that are simultaneously driven. The solid-state imaging device according to claim 1 ,
The imaging region further includes at least three dummy pixel rows in addition to the plurality of pixel rows for signal readout,
The row selection unit drives one dummy pixel row of the dummy pixel rows by the first unit, and the other two dummy units of the dummy pixel row by the at least two second units. A solid-state imaging device that drives a pixel row. The solid-state imaging device according to claim 1 or 2 ,
The solid state imaging device, wherein the row selection unit changes signal accumulation timing within a period of one field period in units of one field corresponding to a period of signal readout timing of each pixel row. The solid-state imaging device according to claim 3 ,
The at least two second means drive the reading means by making the signal accumulation timing relative to the signal reading timing relatively different from each other, and control operation of the vertical driving means by the second means Is alternately switched for each field. The solid-state imaging device according to claim 3 ,
The first means of the row selection means includes a read shift register for controlling a start period of signal read from the unit cell,
The second means of the row selecting means alternates with a first electronic shutter shift register for controlling a signal accumulation start period in the unit cell in the first field period and the first field period. A solid-state imaging device comprising: a second electronic shutter shift register for controlling a signal accumulation start period in the unit cell in a second field period repeated in a second step. The solid-state imaging device according to any one of claims 1 to 5 ,
When the row selection unit drives the readout unit of each pixel row in the imaging region twice, the voltage of the other wiring adjacent to the readout line around the photoelectric conversion unit is substantially the same even during the two times of driving. The solid-state imaging device is characterized in that the vertical driving means is controlled so as to be the same. The solid-state imaging device according to any one of claims 1 to 6 ,
The unit cell is
One photodiode having a ground potential applied to the anode side;
One readout transistor having one end connected to the cathode side of the one photodiode and a read line connected to the gate;
One amplifying transistor having a gate connected to the other end of the read transistor and a vertical signal line connected to one end ;
Is connected between the gate and the power supply line of the previous SL amplifying transistor, comprising a single reset transistor reset line is connected to the gate, the one photodiode corresponds to one pixel that A solid-state imaging device. The solid-state imaging device according to any one of claims 1 to 6 ,
The unit cell is
Two photodiodes to which a ground potential is applied to each anode side;
Two read transistors having one end connected to each cathode side of the two photodiodes and two read lines connected to the gates;
A single amplifying transistor having a gate connected in common to each of the other ends of the two read transistors and a vertical signal line connected to one end ;
Is connected between the gate and the power supply line of the previous SL amplifying transistor, provided with one reset transistor reset line is connected to the gate,
2. The solid-state imaging device according to claim 2, wherein the two photodiodes correspond to two pixels.

Images