JP4082568B2 - Integrated circuit design support apparatus and method, and program thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technology for supporting the design of an integrated circuit such as an LSI using a computer, and more particularly to a technology for verifying items other than the operation verification of an integrated circuit based on circuit description data corresponding to the integrated circuit.
[0002]
[Prior art]
Currently, the mainstream of circuit design for LSI and other semiconductor devices is to describe the operation of the circuit in RTL (Register Transfer Level) using HDL (Hardware Description Language) and logically describe it. A method of converting to a net list at the gate level by a synthesis technique is adopted. FIG. 6 shows an RTL description example. This is an RTL description example corresponding to the logic circuit of FIG. After performing the logic synthesis, it is verified whether various design rules are satisfied for the gate level netlist.
[0003]
An example of a design rule is a testability design rule. This rule is, for example, “It is necessary to be able to control the clock terminal of each flip-flop using an external input clock signal”. The rules regarding the clock control will be described with reference to FIG. In FIG. 5, a, b, and ck are external signals, and of these, ck is a clock. In the case of the circuit of FIG. 5, the clock signal of the flip-flop (FF) is cknet, but this cknet cannot be controlled by the external input clock ck. Control here means that cknet is always 1 when the logical value of ck is 1, and cknet is always 0 when the logical value of ck is 0. However, in FIG. 5, when the external input b is 0, cknet is 0 regardless of the logical value of ck. Therefore, the circuit of FIG. 5 does not satisfy the above clock control rule. On the other hand, this rule is satisfied when the external input b is fixed to 1.
[0004]
When checking various design rules at the gate level, if a rule violation is found, the RTL data is corrected and logic synthesis is performed again. Since this increases the period of LSI design, it is desirable to check various design rules directly against RTL data if possible. However, developing a device for performing design rule check on RTL data from scratch is very laborious and difficult to implement.
[0005]
[Problems to be solved by the invention]
The present invention has been made in view of the above circumstances, and its purpose is to use an existing logic simulator and an API (Application Procedure Interface) prepared in advance in the logic simulator, and to operate an integrated circuit based on RTL data. An object is to realize an apparatus and a method for verifying items other than verification. More specifically, an existing logic simulator and an API prepared in advance for the logic simulator are used to realize an apparatus and method for performing a condition leak check on RTL data.
[0006]
[Means for Solving the Problems]
The present invention supports an integrated circuit by using a logic simulator including a logic simulation function and an API that enables setting and referencing of a logic value for the logic simulation function and referencing of parse tree information of circuit description data. Items other than the operation verification of the integrated circuit are verified based on the circuit description data.
[0007]
Against Specifically, each condition signal means and the extracted condition description section for extracting with a condition description section the API from the circuit description data, all the combinations of logic values set by the API, for the combination of the logic values, means allowed to implement the logic simulation by a simulation function, the logic value of the signal that is the assignment target in the condition description section reads, from the read logical values by the API, condition A condition leak check is performed by means for determining whether there is a condition leak in the description part.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram showing a first embodiment of an integrated circuit design support apparatus according to the present invention, which makes it easy to test RTL data in HDL description using a logic simulator and an API prepared beforehand. The example of a structure in the case of implementing a design rule check is shown. In FIG. 1, 110 is a circuit description data file, 120 is a signal constraint file, 130 is a signal constraint file reading unit, 140 is a logic simulator, 150 is a flip-flop information file, and 160 is a testability design rule determination unit. Yes.
[0009]
The circuit description data file 110 holds HDL description RTL data that is circuit description data corresponding to the integrated circuit to be designed. Examples of the HDL format include Verilog-HDL, which is an IEEE standard 1304-1995. In the signal constraint file 120, a signal to be fixed when performing a design rule check, its logic, and the like are described together with a rule to be checked. The external input clock signal name is also described.
[0010]
The logic simulator 140 includes a logic simulation unit 141 and an API unit 142. Here, the API unit 142 is normally incorporated in the logic simulator 140 as a function described in a programming language such as C language. Using this built-in function, you can:
(1) A logic value is set for an arbitrary signal in the logic simulation section.
(2) Refer to the logic value of an arbitrary signal from the logic simulation unit.
(3) Refer to the parse tree information of the HDL description data.
[0011]
Examples of APIs include VPI (Verilog Procedure Interface) which is an API of Verilog-HDL.
[0012]
Originally, the logic simulator 140 has been used to verify whether a circuit operates correctly. In this embodiment, a testability design rule check is performed on RTL data in an HDL description using the logic simulator 140 and an API unit 142 incorporated in advance. FIG. 2 shows a processing procedure of the clock rule check. The operation of the embodiment shown in FIG. 1 will be specifically described below with reference to FIG.
[0013]
First, the logic simulation unit 141 reads RTL data in HDL description as circuit description data from the circuit description data file 110 (S201). Next, the signal constraint file reading unit 130 reads the signal constraint information of the signal constraint file 120 and passes it to the API unit 142 of the logic simulator 140 (S202). As described above, the signal constraint file 120 describes a signal to be fixed when performing a design rule check, its logical value, and the like. The external input clock signal name is also described. Here, in the circuit of FIG. 5, it is assumed that the external signal b is a fixed signal, the fixed value is 1, and the external clock signal is ck.
[0014]
The API unit 142 of the logic simulator 140 sets a logical value for the signal in the signal constraint information of the signal constraint file 120 for the RTL data read by the logic simulation unit 141 (S203). Further, first, a logical value 0 is set in the external clock signal (S204). Through the steps S203 and S204, in the circuit of FIG. 5, the logical value of the external signal b is fixed to 0, and the external clock signal ck is set to the logical value 1 .
[0015]
The logic simulation unit 141 executes logic simulation based on the RTL data read from the circuit description data file 110 under the conditions set by the API unit 142 (S205). After executing the logic simulation, the API unit 142 reads the flip-flop information and outputs it to the flip-flop information file 150 (S206). The flip-flop name can be extracted from the RTL data. The flip-flop information includes the name of each flip-flop, the logical value of the clock terminal, and the like. Here, the logical value of the external clock signal is also added thereto. As a result, in the circuit of FIG. 5, information in which the logic values of the clock signal cknet of the flip-flop FF and the human-powered clock signal are both 0 is output to the flip-flop information file 150.
[0016]
The testability design rule determination unit 160 refers to the flip-flop information file 150 and checks what kind of logic the clock terminal of the flip-flop detected by the API unit 142 is after logic simulation (S207). Here, if the logical value of the external input clock signal is the same as the logical value of the clock terminal of the flip-flop, it is determined that the design rule is satisfied. In the circuit of FIG. 5, ck = 0 and cknet = 0 are determined.
[0017]
Next, the API unit 142 sets the external clock to a logical value 1 (S208). Thereby, in the circuit of FIG. 5, the logical value of the external clock signal ck is changed from 0 to 1. The external input signal b remains fixed at 1.
[0018]
The logic simulation unit 141 executes the logic simulation again under the conditions set by the API unit 142 (S209). After executing the logic simulation, the SPI unit 142 again converts the flip-flop information into the flip-flop information. Read to file 150 (S210). Then, the testability design rule determination unit 160 refers to the flip-flop information file 150 again and checks the logical value of the clock terminal of the flip-flop (S211). As a result, in the circuit of FIG. 5, ck = 1 and cknet = 1 are determined.
[0019]
In the processing procedure of FIG. 2, after step 206, steps S208 to S210 are executed, and after each logical simulation is executed when the logical value of the external clock is 0 and 1, in the testability design rule setting unit 160 The rule determination checks in steps S207 and S211 may be performed together.
[0020]
FIG. 3 is a block diagram showing a second embodiment of the integrated circuit design support apparatus according to the present invention. Using a logic simulator and an API prepared in advance, a condition leak check is performed on RTL data in HDL description. The example of a structure in the case of implementing is shown. 3, 310 is a circuit description data file, 320 is a logic simulator, 330 is a condition description information file, 340 is a logic value setting unit, and 350 is an assignment destination signal check unit.
[0021]
Similar to the circuit description data file 110 of FIG. 1, the circuit description data file 310 holds RTL data of HDL description that is circuit description data corresponding to the integrated circuit to be designed. As described above, as an HDL format, for example, Verilog-HDL, which is an IEEE standard 1364-1995, can be cited.
[0022]
The logic circuit simulator 320 includes a logic simulation unit 321 and an API unit 322. As described above, the API unit 322 is normally incorporated in the logic simulator 320 as a function described in a programming language such as C language, and is used in the logic simulation unit. It is possible to set and refer to a logical value for an arbitrary signal, and to reference parse tree information of HDL description data.
In this embodiment, a condition omission check is performed on circuit description data by using the logic simulator 320 and an API unit 322 incorporated in advance. FIG. 4 shows a procedure for condition leak check. The operation of the embodiment of FIG. 3 will be specifically described below with reference to FIG.
[0023]
First, the logic simulation unit 321 reads RTL data in HDL description as circuit description data from the circuit description data file 310 (S401). The API unit 322 extracts condition description information from a condition description portion such as an if statement in the RTL data of the HDL description, and outputs it to the condition description information file 330 (S402).
[0024]
FIG. 7 shows an example of an if statement. Hereinafter, description will be made by taking the if sentence of FIG. 7 as an example. Here, the condition description information is the following information.
(1) The condition description signals are a and b.
(2) The substitution destination signal is q1.
[0025]
In the logical value setting unit 340, referring to the condition description information file 330, first, signals c, d, e are selected, and the API unit 322 is used to select the signals c, d, e in the logic simulation unit 321. It is initialized with a logical value 0 or 1 (S403). Next, the logical value setting unit 340 similarly uses the API unit 322 to initialize the substitution destination signal q1 of the logical simulation unit 321 with the logical value X (S404), A combination of all logical values is selected one by one, and the logical value is set to the corresponding signals a and b in the logical simulation unit 321 by the API unit 322 (S405), and the logical simulation is performed by the simulation unit 321 ( S406).
[0026]
Here, there are four possible combinations of logical values of the condition description signals a and b: (a, b) = (0, 0), (0, 1), (1, 0), (1, 1). It is. The logic value setting unit 340 selects one of the four combinations, for example, (0, 0), and sets a logic value for the corresponding signal of the logic simulation unit 321 using the API unit 322. Then, the simulation unit 321 performs logic simulation. However, before assigning a logical value to the corresponding signal, the logical value setting unit 340 always initializes the assignment destination signal q1 with the logical value X and the other signals c, d, and e with 0 or 1.
[0027]
After the logic simulation, the substitution destination signal check unit 350 uses the API unit 320 to capture the logic value of the signal q1, and refers to the signal q1 of the condition description information file 330, so that the logic value of the signal q1 is changed from X to other values. It is determined whether or not the value has changed (S407). If X remains as it is (initial value), it is determined that there is a condition omission (S410).
[0028]
The processes in steps S404 to S405 are repeated for all four patterns (a, b) = (0, 0), (0, 1), (1, 0), (1, 1) (S408), In any case, if the logical value of the signal q1 has changed from X, the assignment destination signal check unit 350 determines that there is no condition omission (S409).
[0029]
In the example of the if statement in FIG. 7, when (a, b) = (0, 0), 700 statements are executed, and the logical value of q1 becomes 1 or 0. When (a, b) = (1, 0), no statement in FIG. 7 is executed and the value of q1 remains X. When the substitution destination signal check unit 350 confirms that the logical value of q1 is X, it means that a condition omission has been detected.
[0030]
The processing functions of some or all of the units in the apparatus shown in FIGS. 1 and 3 can be configured by a computer program, and the program can be executed using the computer to realize the present invention, or It goes without saying that the processing procedure shown in FIGS. 2 and 4 can be configured by a computer program and the program can be executed by the computer. In addition, a computer-readable recording medium such as an FD, an MO, a ROM, a memory card, a program for realizing the processing function by the computer or a program for causing the computer to execute the processing procedure, It can be recorded on a CD, DVD, removable disk, etc., stored, provided, and the program can be distributed through a network such as the Internet.
[0031]
【The invention's effect】
According to the present invention, syntax analysis of RTL data in HDL description and propagation of logic values are performed by a logic simulator, and acquisition of syntax analysis information of RTL data and setting and observation of logic values are incorporated in the logic simulator. Since it is performed by API and a condition omission in an if statement is detected, a condition omission check system can be constructed more easily than in the case of developing from scratch.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a first embodiment of the present invention.
FIG. 2 is a processing flowchart for explaining the operation of the first exemplary embodiment of FIG. 1;
FIG. 3 is a configuration diagram of a second embodiment of the present invention.
4 is a process flow diagram for explaining the operation of the second embodiment of FIG. 3; FIG.
FIG. 5 is a diagram illustrating an example of a logic circuit.
6 is a diagram illustrating an RTL description example for FIG. 5; FIG.
FIG. 7 is a diagram illustrating an example of an if sentence of RTL data;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 110 Circuit description data file 120 Signal constraint file 130 Signal constraint file reading part 140 Logic simulator 150 Flip flop information file 160 Testability design rule determination part 310 Circuit description data file 320 Logic simulator 330 Condition description information file 340 Logic value setting part 350 Substitution destination signal check part

Claims (3)

A logic simulator including a logic simulation function and an API that enables setting and referencing of logic values of the logic simulation function and referencing of parse tree information of circuit description data;
Means for inputting circuit description data corresponding to the integrated circuit;
Means for extracting a condition description part from the circuit description data using the API;
Means for setting all combinations of logic values for each condition signal in the extracted condition description section by the API, and performing a logic simulation for the combinations of the logic values by the logic simulation function; ,
Means for reading a logical value of a signal which is a substitution destination in the condition description part by the API, and determining from the read logical value whether there is a condition omission in the condition description part;
An integrated circuit design support apparatus characterized by comprising: A computer having a logic simulation function and a logic simulator including an API that enables setting and referencing of a logic value for an arbitrary signal of the logic simulation function and referencing of parse tree information of circuit description data,
Inputting circuit description data corresponding to the integrated circuit;
Extracting a condition description part from the circuit description data using the API;
Setting all combinations of logic values for each condition signal in the extracted condition description section by the API, and executing a logic simulation for the combinations of the logic values;
A step of reading a logical value of a signal which is a substitution destination in the condition description part by the API, and determining from the read logical value whether there is a condition omission in the condition description part;
An integrated circuit design support method comprising: A program for executing each step of the integrated circuit design support method according to claim 2 by a computer.

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