JP4079974B2 - Delay circuit - Google Patents

Description

  The present invention relates to a timing control circuit and a delay circuit, and more particularly to a delay circuit that controls timing by changing the phase of a signal in an electronic circuit.

  In recent years, for example, as the CPU clock speed in a computer system increases or the processing speed of various other electronic circuits increases, for example, the interface portion also needs to be increased in speed. There is a demand for providing a timing control circuit that appropriately controls the timing of the control signal in accordance with the period of the control signal to be used.

  Conventionally, for example, the clock access time in the synchronous memory (example of the fastest part in the memory) is mainly defined by the delay time such as the delay of the input buffer, the wiring delay due to the long wiring, and the delay of the output buffer. ing. These delay times cannot be shortened unless the chip size is reduced or the transistor characteristics are greatly improved. For example, it is difficult to increase the speed of the synchronous memory.

  By the way, the chip size of LSIs in recent years is increasing, and it is often 1 nsec. Or more only by the wiring delay due to the long wiring. As a result, the clock access time is limited to 5 nsec. The fact is that the number of LSIs that cannot be used is increasing. This means that the operating frequency of about 100 MHz becomes a limit when considering the case where clock access is continued.

  On the other hand, by performing pipeline configuration and parallel-serial conversion, the switching frequency of signals inside the chip can be greatly increased, and the output circuit cannot keep up with the internal characteristics of the chip. .

  FIG. 22 is a diagram for explaining an example of a conventional timing control circuit. FIG. 22A shows, for example, an input buffer (delay by an input buffer) that defines a clock access time, a wiring delay, and , Output buffer (delay due to output buffer). Specifically, for example, in the synchronous memory, when the clock signal CLK supplied to the clock input IN rises (see FIGS. 22C and 22D), data is output from the output OUT after a predetermined clock access time. Is output (see FIG. 22B).

  In recent years, when the external clock CLK used changes from an external clock as shown in FIG. 22 (c) to a high-speed external clock as shown in FIG. 22 (d), it is not after one clock cycle time has elapsed. In some cases, the output is not fixed.

  FIG. 23 is a block diagram schematically showing an example of a circuit configuration to which the timing control circuit is applied. In the figure, reference numeral 221 indicates a clock buffer, 222, 223, and 224 indicate LSIs (functional blocks), and 225, 226, and 227 indicate registers.

  In the circuit shown in FIG. 23, the clock CLK is supplied via the clock buffer 221 to the registers 225, 226, and 227 provided at the outputs of the LSIs 222, 223, and 224, and the data processed by each LSI is output every cycle time. It has come to be. In other words, after three cycle times from the clock supplied to the input IN of the LSI 222, data that has undergone predetermined processing is sent out from the output OUT. Here, the LSIs 222, 223, and 224 may be functional blocks (internal circuits) in one chip. The timing control circuit is provided in the clock buffer 221 or in each of the LSIs 222, 223, and 224.

  As described above, the tint control circuit can be applied to various electronic circuits configured by a plurality of LSIs or various chips configured by a plurality of functional blocks (internal circuits).

  FIG. 24 is a diagram for explaining another example of a conventional timing control circuit, and shows a timing control circuit for a circuit to which a pipeline system is applied.

  In the timing control circuit to which the pipeline system shown in FIG. 24 is applied, in each pipeline process, clock access is started by the clock three cycles before and the delay due to the input buffer, the wiring delay, and the delay due to the output buffer are absorbed. However, the clock access time and the clock cycle time of 3 cycles are used in synchronization. In other words, by starting clock access with a clock one cycle or more before, the internal transmission time is allowed to operate.

  However, in the case where the clock access is started by a clock that is one cycle or more before (for example, three cycles before), if the frequency of the external clock CLK is changed, the specifications regarding the output confirmation time cannot be satisfied. In other words, it is usually necessary to determine the output for a certain period of time before and after the rising edge of the external clock, but if the frequency of the external clock CLK is changed, the clock cycle and the output determination timing will be out of synchronization, resulting in accurate operation Will not be able to do.

  In order to solve the above-described problem, a delay circuit (delay circuit: timing control circuit) whose delay time is variable according to the clock cycle time, or {(clock cycle time) × 2− (clock access time) ) -1/2 output determination time} A circuit (timing control circuit) that shifts the phase of the clock by the amount is required. However, a delay circuit using a simple gate row cannot generate the delay time as described above. Also, as such a circuit, a PLL (Phase-Locked Loop) circuit is known. However, since it is an analog circuit, it is vulnerable to power supply noise, and further, the circuit scale increases and the current consumption increases. Is not practical.

  It is an object of the present invention to provide a delay circuit capable of obtaining an output signal having a delay time and a frequency as required with low power consumption without being affected by noise such as power supply voltage and temperature fluctuation. .

  According to the present invention, a plurality of first gate circuits connected in series each receiving a first control signal and receiving a second control signal are provided, and the first up to the switching point of the second control signal. A first gate row for propagating the first control signal in the first direction for a period of time, and a plurality of second gate circuits connected in series, wherein the second direction is opposite to the first direction. And a second gate line that propagates a signal in a direction, receives an output signal from the first gate line, and generates a second time corresponding to the first time. A delay circuit is provided.

  According to the present invention, there is provided a delay circuit capable of obtaining an output signal having a delay time and a frequency as required with low power consumption without being affected by noise such as fluctuations in power supply voltage and temperature. be able to.

FIG. 1 is a diagram showing a principle configuration of a timing control circuit according to the present invention.
As described in the above prior art, setting the delay time to {(clock cycle time) × 2− (clock access time) −1/2 output determination time} is a delay circuit using a simple gate train. It is difficult.

  Therefore, in the present invention, as shown in FIG. 1, the switching time difference τ1 between the first signal and the second signal is reproduced at the location τ2. In order to simplify the description, it is assumed that the output timing is made simultaneously with the rise of the clock.

  In order to obtain the output confirmation time, it is necessary to switch the output earlier than two clock cycles. However, if the delay time of the second input buffer is omitted in the above time allocation, the output switching is accelerated by that amount. be able to. Furthermore, even when the delay time of the first output buffer is increased, the output can be switched faster by that amount.

  In this way, by realizing a circuit that reproduces the time difference between the switching of the two signals, the control can be performed according to the period of the control signal to be used without using a PLL that is problematic in noise resistance and power consumption. A timing control circuit configured to appropriately control signal timing can be configured.

  For example, by using the timing control circuit of the present invention that can appropriately control the timing of the control signal according to the period of the control signal to be used, the previous clock is used for an arbitrary clock frequency. Thus, clock access can be output, and the operating frequency of the circuit can be increased.

  According to the delay circuit of the present invention, the first switching time difference at which the first input signal and the second input signal are switched by the first conversion circuit is converted into the corresponding first gate stage number information, The conversion circuit converts the second gate stage number information determined according to the first gate stage number information into the second switching time difference, and the third input signal input to the second conversion circuit is the second input signal. Output is delayed by the switching time difference. The first conversion circuit has an array structure in which at least two first unit circuits are regularly repeated, and the first input signal is propagated in the first direction in the array of the first unit circuits. It is supposed to let you. The second conversion circuit has an array structure in which at least two second unit circuits that reproduce the delay time per stage of the first unit circuit are regularly repeated, and a third input signal is received. In the second conversion circuit, the light is propagated in a second direction opposite to the first direction.

  According to the delay circuit of the present invention having the above configuration, an output signal having a delay time and a frequency as required can be obtained with low power consumption without being affected by noise such as power supply voltage and temperature fluctuation. it can.

  Embodiments of a delay circuit according to the present invention will be described below together with a timing control circuit with reference to the accompanying drawings.

  FIG. 2 is a diagram for explaining a first embodiment of the timing control circuit of the present invention. In the figure, reference numeral 1 is an input buffer circuit (delay time: IB-1), 2 is a delay circuit (delay time: IB-2), and 3 is a switching time difference (τ) between two signals described later. A time difference expansion circuit (delay time: Q) to be doubled is shown.

  A clock signal (control signal) CLK is input to the input buffer circuit 1, and the delay circuit 2 has substantially the same delay time as the input buffer circuit 1. As shown in FIG. 2, the clock signal having the delay time (IB-1) + (IB-2) output via the input buffer circuit 1 and the delay circuit 2 becomes the first signal A, and the input A clock signal having a delay time (IB-1) by the buffer circuit 1 becomes an internal clock signal C (second signal), and a signal obtained by doubling the cycle of the internal clock signal is a signal B (second signal). It becomes.

  As apparent from FIG. 2, the time difference expansion circuit 3 operates from the rising timing of the first signal A to the falling timing of the signal B, or the internal clock one cycle after the rising timing of the first signal A. It has a delay time (Q) that doubles the switching time difference τ of the two signals until the rise timing of C. As a result, it is possible to obtain an output (phase-controlled clock signal: OUT) that switches at the same phase as the external clock CLK supplied to the input IN.

  Here, the time difference expansion circuit 3 is not limited to the one that doubles the time difference τ of two signals, and may be configured to expand the time difference τ to N times (N is an integer of 2 or more). . That is, in the timing control circuit of the present invention, the time difference expansion circuit 3 is configured such that the delay time of the time difference expansion circuit is N times the time difference τ, and has the same phase as the external clock CLK supplied to the input IN. You may comprise so that the output which switches may be obtained.

  In the first embodiment of the present invention described above and each of the following embodiments, the delay time of the circuit that changes according to the cycle time of the clock is digitally set according to the clock. This is a circuit (delay circuit: timing control circuit) that digitally accurately multiplies the time difference between two signals that change according to the clock by N (N is an integer of 2 or more, specifically, for example, double). It can be realized by configuring. Further, in the first embodiment of the present invention and each of the following embodiments, the output timing is described on the assumption that the timing of the output coincides with the rise of the clock in order to simplify the explanation. When a signal is used, a signal having a required timing can be obtained by simply adding a predetermined delay to the timing at which the output timing coincides with the rise of the clock.

  FIG. 3 is a diagram for explaining a second embodiment of the timing control circuit according to the present invention. In the second embodiment, the second circuit 2 is composed of two delay circuits 21 and 22. The first delay circuit (long wiring delay part) 21 has a delay time R that the signal transmission unit 4 has until the output signal (phase-controlled clock signal) is supplied from the time difference expansion circuit 3 to the next-stage circuit. The second delay circuit 22 corresponds to the delay circuit 2 having substantially the same delay time (IB-2) as the input buffer circuit 1 in the first embodiment. . Here, the second delay circuit 22 is configured by, for example, a dummy wiring pattern similar to that of the signal transmission unit 4, so that the second delay circuit 22 corresponds to the delay time R included in the signal transmission unit 4. It has a delay time P.

  Therefore, the time difference expansion circuit 3 has the switching timing of the first signal A that has passed through the input buffer circuit 1, the first delay circuit 21 and the second delay circuit 22, and the second timing that has passed through only the input buffer circuit 1. The time difference τ with respect to the switching timing of the signal B (C) is expanded twice (N times) to obtain an output that switches at the same phase as the clock signal CLK.

  FIG. 4 is a diagram for explaining a third embodiment of the timing control circuit according to the present invention. In this third embodiment, the internal circuit (first circuit 1 and second circuit) is the input buffer circuit 1. , A long wiring delay portion 21, an output buffer circuit 23, and a delay circuit 22.

  In the third embodiment, the clock signal (control signal) CLK input in the Mth cycle passes through the internal circuits (input buffer circuit 1, long wiring delay portion 21, output buffer circuit 23, and delay circuit 22). The signal A (first signal) after the signal and the signal B (second signal) after the clock signal CLK input in the [M + 1] cycle passes only a part of the internal circuit (input buffer circuit 1). ) Is input to the time difference expansion circuit 3. This time difference expansion circuit 3 is for doubling (N times) the switching time difference (τ) between two signals, as in the first embodiment.

  In the third embodiment, the output of the time difference expansion circuit is delayed by the signal transmission unit 4 (delay time R) and output. The delay time P of the long wiring delay portion 21 corresponds to the delay time R in the signal transmission unit 4. As a result, a clock signal (internal clock signal) having a timing earlier by the delay time of the output buffer circuit 23 can be output.

  FIG. 5 is a diagram for explaining a fourth embodiment of the timing control circuit of the present invention. In the fourth embodiment, the internal circuits are an input buffer circuit 1, a long wiring delay portion 21, an output buffer circuit 23, In addition, delay circuits 24 and 22 are provided. A signal from the time difference expansion circuit 3 is output via a long wiring delay part (signal transmission part) 4 and an output buffer circuit 5. Here, the delay time P of the long wiring delay portion (first delay circuit) 21 corresponds to the delay time R of the long wiring delay portion (signal transmission unit) 4, and the delay time S of the output buffer circuit 23. Corresponds to the delay time U of the output buffer circuit 5.

  Thus, in the fourth embodiment, the clock signal CLK input in the Mth cycle is the first internal circuit (input buffer circuit 1, long wiring delay portion 21, output buffer circuit 23, delay circuit 24, 22) after the first signal A after passing through 22) and the clock signal CLK input in the [M + 1] cycle pass through only a part of the first internal circuit (input buffer circuit 1). The signal B is input to the time difference expansion circuit 3. Further, the output of the time difference expansion circuit 3 has a delay time (R, U) that is substantially the same as the delay time (P, S) of a predetermined portion (long wiring delay portion 21, output buffer circuit 23) of the first internal circuit. 2 is passed through the internal circuit (long wiring delay portion 4, output buffer circuit 5), and the output of the second internal circuit is used as a phase-controlled signal.

  As a result, a clock signal (internal clock signal) that is earlier than the delay time T of the delay circuit 24 can be output.

  FIG. 6 is a diagram for explaining a fifth embodiment of the timing control circuit of the present invention, and shows a specific application example of the fourth embodiment.

  The fifth embodiment shown in FIG. 6 uses the delay circuit 24 having the delay time T in the fourth embodiment described above in order to determine the output at a predetermined timing. That is, in this embodiment, the timing at which the output changes is advanced by the delay time T of the delay circuit (output decision time setting circuit) 24, so that the timing before the rising (falling) timing of the clock signal (control signal) CLK is reached. And the output is determined in a certain period before and after the rising (falling) timing of the clock signal CLK. As a result, it is possible to prevent erroneous data capture and to ensure the correct operation of the circuit.

  FIG. 7 is a diagram for explaining a sixth embodiment of the timing control circuit according to the present invention, and shows the relationship of signals in the above respective drawings.

  That is, the time difference expansion circuit 3 doubles the switching time difference τ of two signals (N times). Specifically, the delay time output via the input buffer circuit 1 and the delay circuit 2 is used. Double the switching time difference τ between the first signal A having (IB-1) + (IB-2) and the signal B (second signal) having only the delay time (IB-1) by the input buffer circuit 1 It is to make. Here, the signal B has a cycle twice that of the clock signal CLK. In place of the signal B, the internal clock signal C (second signal) can be used to define the switching time difference τ.

  Specifically, the switching time difference τ is 2 from the rising timing of the first signal A to the falling timing of the signal B, or from the rising timing of the first signal A to the rising timing of the internal clock C after one cycle. It corresponds to the switching time of two signals. This switching time difference τ is doubled (N times: delay time Q) by the time difference expansion circuit 3, and as a result, an output (phase-controlled clock signal that switches in the same phase as the external clock CLK supplied to the input IN). : OUT) can be obtained.

  8 to 16 are diagrams for explaining the seventh to fifteenth embodiments of the timing control circuit according to the present invention. In particular, the time difference extending circuit 3 for extending the time difference τ twice, that is, a predetermined time It is a figure which shows the specific structure of the delay circuit (3) which makes a delay time 2 times (N times).

  In the seventh embodiment shown in FIG. 8, reference numeral AA is the first gate row, BB is the second gate row, A1 to An are the gate circuits constituting the first gate row, and B1 to Bn are the first gate row. A gate circuit constituting the gate row, X is a first control signal, and Y is a second control signal.

  The first gate row AA includes a plurality of serially connected gate circuits A1, A2, A3,... That propagate signals in a first direction (a direction from the gate circuit A1 toward An), and a first control signal The activation of at least a part of the first gate row AA is controlled by X. The second gate row BB includes a plurality of gate circuits B1, B2, which are connected in series to propagate a signal in a second direction (direction from the gate circuit Bm to B1) opposite to the first direction. .., And the activation of at least a part of the second gate row BB is controlled by the second control signal Y.

  The first control signal X is supplied to the gate circuits A1 to An of the first gate row AA via the control signal line SLA, and the second control signal Y is supplied to the second gate row AA. The gate circuits B1 to Bm of BB are supplied via the control signal line SLB.

  The outputs of the gate circuits A1, A2,..., An-1 in the first gate row AA are connected to the inputs of the gate circuits B1, B2,..., Bm-1 in the second gate row BB. Yes. Here, the short circuit of the input / output of each gate circuit in the first and second gate rows may not be performed for all the gate circuits. In the embodiment shown in FIG. 8, the gate circuit (A1, A2, A3,..., An) of the first gate row AA and the gate circuit (B1, B2, B3,..., Bm of the second gate row BB are used. ) Are configured to have the same number of stages (ie, n = m). The number of stages of the gate circuit is configured to be three or more.

  The first control signal X and the second control signal Y are generated from the same basic control signal (clock signal CLK), the first control signal X corresponds to the clock signal CLK, and the second control signal Y Corresponds to the inverted clock signal CLK. When the clock signal CLK is at the high level “H”, the first gate row AA is activated to inactivate the second gate row BB, and when the clock signal CLK is at the low level “L”. One gate line AA is deactivated and the second gate line BB is activated.

  Then, for example, at the time τ when the clock signal CLK is at the high level “H” and the first gate array AA is activated (the second gate BB is deactivated), the first gate array AA When the data to be input to “11010” is, when the clock signal CLK becomes the low level “L”, the second gate row BB is activated (the first gate AA is inactivated) and the input data is inverted. Data “01011” is reproduced at time τ, and is output from the second gate row BB.

  In the eighth embodiment shown in FIG. 9, the control signal lines SLA and SLB are connected via inverters (buffer circuits) IA and IB provided for each predetermined number of gate circuits (for example, A1 to A3; B1 to B3). Connected to each gate circuit. Here, in this embodiment, the buffer circuit is configured by inverters IA and IB, and the control signal lines SLA and SLB via the inverters IA and IB are configured to be control signal lines of the opposite gate row. Has been. Here, if a buffer circuit that outputs a positive logic signal is used instead of the inverters IA and IB, it is not necessary to replace the control signal line between the gate arrays AA and BB.

  In the ninth embodiment shown in FIG. 10, the final output terminal OUT (AA) of the first gate line AA is set to a high impedance state, and the input terminal IN (BB) of the second gate line BB is set to a low level potential (the first level). 1 potential) fixed at “L”. The last input signal of the high level potential (second potential) “H” supplied when the first gate row AA is activated (when the clock signal CLK is at the high level “H”). When the second gate row BB is activated, the second gate row BB advances in the reverse direction, and low level “L” data appears from the output terminal OUT (BB) of the second gate row BB. The switching time difference τ between the input signal to the column AA and the first control signal X (CLK) is reproduced by the switching time difference τ between the second control signal Y (/ CLK) and the output signal of the second gate column BB. It is supposed to be. Thereby, for example, the time difference expansion circuit 3 that doubles the switching time difference τ of the two signals in FIGS. 2 to 6 described above can be configured.

  In the tenth embodiment shown in FIG. 11, the gate circuits A1 to An in the first gate row AA and the gate circuits B1 to Bm in the second gate row BB are configured as inverters, and in the gate rows AA and BB. Each gate circuit is configured to have the same number of stages (2N stages: even stages). Here, the sizes of the transistors constituting the gate circuits (inverters) A1 to An constituting the first gate row AA and the gate circuits (inverters) B1 to Bm (Bn) constituting the second gate row BB are constituted. The input signal to the first gate array AA can be inverted by being multiplied by a predetermined time in accordance with the size ratio of the transistors. That is, by changing the sizes of the transistors constituting the gate circuits in the gate arrays AA and BB, the switching time difference τ between the two signals described above is multiplied by a factor corresponding to the size ratio of the transistors (for example, 1.5 times). Can be. Thereby, for example, it is possible to perform control so that the output is determined in a certain period before and after the rising timing regardless of the cycle of the control signal (clock signal).

  In FIG. 11, the first control signal X is generated from the clock signal CLK via the two-stage inverters I1 and I2, and the second control signal Y is generated from the clock signal CLK via the one-stage inverter I1. To be generated. Further, an inverter composed of an N-channel MOS transistor TR0 and a P-channel MOS transistor TR00 is provided at the input terminal IN (AA) of the first gate row AA. That is, the input terminal IN (AA) of the first gate row AA is input to the gates of the N-channel MOS transistor TR0 and the P-channel MOS transistor TR00, and the output of the inverter by the transistors TR0 and TR00 is the gate circuit (inverter ) Is supplied to A1.

  Further, in the tenth embodiment shown in FIG. 11, the final output terminal OUT (AA) of the first gate array AA is in a high impedance state (Open), and the input terminal IN (BB) of the second gate array BB is Fixed to high level “H”. The output terminal OUT (BB) of the second gate row BB is connected to the output (output of the delay circuit) OUT via the inverter I0 so that an output signal having a stable level is taken out.

  In the eleventh embodiment shown in FIG. 12, the gate circuits A1 to An and B1 to Bm in the gate arrays AA and BB in the tenth embodiment are configured as inverters having power supply control transistors. Specifically, for example, the first-stage inverter A1 of the gate array AA includes a P-channel MOS transistor TR11 controlled by the control signal X (/ CLK) and an N-channel MOS transistor controlled by the control signal Y (CLK). TR12 is provided, and activation / deactivation is controlled according to the level of the clock signal CLK.

  Here, the transistor TR1 controlled by the control signal Y is also provided for the source of the transistor TR0 provided at the input terminal IN (AA) of the gate row AA. The control signal X is generated from the clock signal CLK through three stages of inverters I1, I2, and I3, and the control signal Y is generated from the clock signal CLK through two stages of inverters I1 and I4. It is like that. As described above, by providing the power control transistors (TR11, TR12) for the gate circuits A1 to An and B1 to Bm, the load of the transistors that supply the power supply voltage to the gate circuits is distributed. ing.

  In the twelfth embodiment shown in FIG. 13, an output buffer circuit OB is basically provided in place of the inverter I0 provided at the output terminal OUT (BB) of the gate line BB in the eleventh embodiment. Is.

  The output buffer circuit OB includes delay units D1 and D2, each composed of an odd number of inverters, a latch unit LA for eliminating an output indefinite state, a NAND gate ND, and transistors TR101, TR102, and TR103. Yes. Here, the signal is supplied to the first-stage gate circuit A1 only when the signal supplied to the input terminal IN (AA) is at the high level “H”. In this output buffer circuit OB, the final output terminal (OUT (BB)) of the second gate row BB has a low level “L” to a high level “H” (or a high level “H” to a low level “L”). Only the edge of switching to is captured and output.

  Further, in FIG. 13, the input terminal IN (AA) of the first gate row AA has a low level potential (first potential) “L” or a high level potential (second potential) “H”. One-way driving means TR0 for driving only one side is provided. That is, the input terminal IN (AA) of the first gate row AA is input to the gate of the N-channel MOS transistor TR0. Thereby, an output signal excluding unnecessary switching can be obtained.

  In the thirteenth embodiment shown in FIG. 14, for example, the control means for controlling the activation of the gate array by the control signal divides the input clock signal by 1 / N (N is an integer of 2 or more) and the clock signal When the signal is configured to generate a signal having a period N times that of the first gate line AA and the second gate line (in the circuit examples of FIGS. Although it is necessary to provide N sets of circuits corresponding to BB, an overlap output buffer circuit OB ′ for superimposing the outputs (outputs OUT (BB1) to OUT (BBN) of each second gate row) of these N sets of circuits. This shows a circuit example (corresponding to the output buffer circuit OB in FIG. 13).

  As is clear from comparison between FIGS. 13 and 14, in the thirteenth embodiment, the outputs OUT (BB1) to OUT (BBN) of the N sets of circuits include transistors TR112 corresponding to the transistors TR102 and TR103 in FIG. , TR113 to TR1N2, TR1N3 (switch means) are provided, and the drains of the transistors TR112 to TR1N2 are connected in common to take out the superimposed output OUT. Here, the superimposed output OUT is a signal having the same frequency as the clock signal CLK but having a different phase. Note that the N sets of outputs can be configured to be reset to a predetermined level by a common output signal level control circuit after a predetermined time.

  FIG. 15 is a diagram for explaining a fourteenth embodiment of the timing control circuit according to the present invention. In the thirteenth embodiment described above, the input signal is divided by 1/3 to have a period three times that of the input signal. This shows a case where three control signals are generated.

  As shown in FIG. 15, each of the control signals 1 to 3 has a period three times that of the input signal (clock signal CLK). Then, the outputs (output signals 1 to 3) of the three sets of the first gate row and the second gate row corresponding to each of the three control signals are superimposed as shown in FIG. An output signal is obtained by superposition by the output buffer circuit OB ′. The superposition output signal (OUT) is a signal having the same frequency as that of the input signal but having a different phase without depending on the frequency of the input signal (CLK).

  FIG. 16 is a diagram for explaining an application example of the timing control circuit (delay circuit, phase shift circuit) of the present invention. In the figure, reference numeral 61 is a timing control circuit, 62 is an arbitrary circuit (another circuit), and 63 is an output buffer circuit.

  As shown in FIG. 16, the timing control circuit 61 changes the phase of a clock signal (first clock signal) CLK supplied from the outside to generate an internal clock signal (second clock signal). Further, the internal clock signal is supplied to an output buffer circuit 63 to which an output of an arbitrary circuit 62 is input, and an output synchronized with the internal clock signal is obtained from the output buffer circuit 63. Needless to say, the above-described timing control circuit (delay circuit) according to the present invention is not limited to the circuit configuration of FIG. 16 and can be applied to various circuits.

  17 to 19 are circuit diagrams showing examples of a clock generation circuit to which the timing control circuit of the present invention is applied. 17 to 19, reference numeral 71 is a delay circuit (programmable delay circuit), 72 is a dummy wiring portion (long wiring delay portion), and 73 is a frequency dividing circuit (1/2 frequency dividing circuit). .

  20 and 21 are timing charts showing respective signals of the clock generation circuit shown in FIGS. 20 and 21, reference symbol CLK is a clock signal to be input to the clock signal generating circuit, X and Y (signal Y is a signal / X of the inverted level of signal X) is a control signal, and A, B, and C are clock signals. The signal in each part of the generation circuit is shown. Further, reference numerals E1 to E31 indicate output signals of gate circuits (inverters) in each gate row of the clock generation circuit.

  In the clock signal generation circuit shown in FIGS. 17 to 19, the clock signal CLK input by the frequency divider circuit 73 is divided by 1/2 and has a signal having a cycle twice that of the clock signal CLK (corresponding to the control signals X and Y). ). As described above, when the signal obtained by dividing the input signal by ½ is used as the control signals X and Y, as described above, two sets of circuits having the first gate row and the second gate row. (AA1, BB1; AA2, BB2) 74 and 75 are provided. Then, the combined output OUT (G) is taken out via the output buffer circuit (OB ′) that superimposes the outputs OUT (BB1) and OUT (BB2) of the two sets of circuits described with reference to FIGS. It is. Here, in the clock signal generation circuit shown in FIGS. 17 to 19, the combination output OUT (G) is supplied to the read control circuit 70 as an output control clock, and takes the logic with the read control signal (/ RE). Read data D (1) to D (8) are read out.

As shown in FIGS. 17 to 19, each common node in the first gate row AA1, AA2 and the second gate row BB1, BB2 in each set is provided with a capacitance means CL, and the signal propagation time Is supposed to be longer. The value of the capacitance means CL is set to increase as it goes from the input side IN (AA1) (IN (AA2)) to the output side OUT (AA1) (OUT (AA2)) of the first gate row AA1 (AA2). The delay time in each gate circuit (inverter) is increased as it goes to the output side. Specifically, for example, the first part in each group (the part of the input side IN (AA1) (IN (AA2)) of the first gate row AA1 (AA2)) is not provided with a capacitive means, and each gate circuit The delay time is configured to be small. For example, around the 41st stage, the value of the capacitance means CL is set to be four times the capacitance _CIN of the input section, and around the 51st stage, the value of the capacitance means CL is set to the capacity of the input section. It is set to be 12 times _CIN .

  Further, for example, in the clock signal generation circuit shown in FIGS. 17 to 19, the control signal lines for supplying the control signals X and Y are provided with inverters (buffer circuits) IA and IB for every 10 stages of gate circuits, The control signal line via the inverters IA and IB is configured to be the control signal line of the opposite gate row. The configuration of the superimposed output buffer circuit OB ′, the levels of the output terminals OUT (AA1) and OUT (AA2) of the first gate lines AA1 and AA2, and the input terminal IN (BB1) of the second gate lines BB1 and BB2 , IN (BB2) levels and the like are the same as those in the above-described embodiments, and thus the description thereof is omitted.

  As shown in FIGS. 20 and 21, according to the clock signal generation circuit shown in FIGS. 17 to 19, two sets of circuits (AA1, BB1) having a first gate row and a second gate row are provided. AA2, BB2) A superposition output OUT (G) obtained by superimposing the outputs of 74 and 75 can be obtained as a signal having the same frequency as the clock signal CLK and having a different phase. As a result, for example, it is possible to perform control so that the output is determined in a certain period before and after the rising timing regardless of the cycle of the clock signal CLK.

Hereinafter, embodiments of the delay circuit according to the present invention will be described in detail in comparison with the prior art.
FIG. 25 is a block diagram showing an example of a conventional delay circuit. In FIG. 25, reference numeral 300 indicates a unit delay circuit (UD), 301 indicates a multiplexer (MUX), 302 indicates a phase detection circuit, and 303 and 304 indicate RC delay circuits.

  The delay circuit shown in FIG. 25 has a predetermined delay from the input clock signal CLK by selecting each output of the multi-stage delay line (unit delay circuit 300 connected in series) by the multiplexer 301. An output signal CLK ′ is output. That is, the multiplexer 301 detects a signal fed back via the RC delay circuit 304 by the phase detection circuit 302, compares the phase with the clock signal CLK, and sets a predetermined delay time according to the output of the phase detection circuit 302. The output of the delay line which has is selected. Note that a delay circuit including RC delay circuits 303 and 304 resistance (R) and a capacitor (C) is shown, and an output signal CLK ′ is output via the RC delay circuit 303.

  Therefore, the delay circuit shown in FIG. 25 has a problem in terms of power consumption because it is necessary to drive a large number of unit delay circuits 300.

  FIG. 26 is a block diagram showing another example of a conventional delay circuit. In FIG. 26, reference numeral 305 denotes a driver circuit, 306 denotes a multiplexer (MUX), and 307 denotes a capacitor array.

  The delay circuit shown in FIG. 26 selects the output load of the driver circuit 305 (capacitance by the capacitor array 307) by the multiplexer 306, so that the rise time (Rise-Time) and fall time (Fall-Time) of that node are selected. In other words, the output signal CLK ′ having a predetermined delay is output from the input clock signal CLK by utilizing the rounding of the signal waveform. The multiplexer 306 detects the signal fed back via the RC delay circuit 304 by the phase detection circuit 302, compares the phase with the clock signal CLK, and determines a predetermined value of the capacitor array 307 according to the output of the phase detection circuit 302. The output load (capacity) is selected. The output signal CLK ′ is also output via the RC delay circuit 303.

  Therefore, the delay circuit shown in FIG. 26 has a problem in terms of accuracy because it is vulnerable to noise because the delay time is defined using the rounding of the signal waveform.

  FIG. 27 is a block diagram showing an example of a conventional PLL circuit. In FIG. 27, reference numeral 310 is an oscillator, 320 is a phase comparator, and 330 is a control circuit.

  In general, an oscillator whose phase can be controlled by a control signal (CTRL) is called a PLL (Phase-Locked-Loop). This PLL circuit has many methods for controlling the voltage of the delay value of the gate constituting the oscillator (ring oscillator), and is usually configured as an analog circuit. When the delay value is controlled by the gate load, the transistor size, or the number of gate stages, it is also referred to as digital / PLL.

  As shown in FIG. 27, the PLL circuit obtains clocks having various phases (30 degrees, 90 degrees, 120 degrees, etc.) depending on which gate stage of the ring oscillator (oscillator) 310 takes the output. Therefore, a clock having a double period, a triple period, or the like can be created.

  However, this PLL circuit basically includes an oscillator 310, a phase comparator 320, and a control circuit 330, but phase comparison and delay value control depend on power supply voltage and temperature fluctuations (noise, etc.). There is a problem that changes. Furthermore, since a ring oscillator is normally used as the oscillator 310, there is a problem in terms of power consumption.

  Further, in contrast to a conventional PLL that uses a ring oscillator, a case where an open type gate array is used is generally called a DLL (Delay-Line-Lock). The delay circuit of the present invention described below can be applied to a digital DLL circuit capable of greatly reducing power consumption, is resistant to noise, has low power consumption (low standby current), and is stable at high speed. This circuit is suitable for a circuit that generates a clock signal or the like of a high-speed general-purpose memory (DRAM or the like) that requires such a signal.

  FIG. 28 is a block diagram showing a basic configuration of a DLL circuit to which the present invention is applied. In FIG. 28, reference numeral 411 denotes a first conversion circuit (CA), 412 denotes a gate stage number information conversion circuit (CD), 413 denotes a second conversion circuit (CB), and 410 denotes a phase comparator 420 and a control circuit. The fine adjustment circuit comprised by 430 is shown.

  FIG. 29 is a block diagram showing a principle configuration of a delay circuit to which the present invention is applied. As shown in FIGS. 29 (a) and 29 (b), the first conversion circuit CA includes a plurality of unit circuits (first unit circuits) UA connected in cascade (array form), and The second conversion circuit CB includes a plurality of unit circuits (second unit circuits) UB connected in cascade (arranged in an array).

  The first conversion circuit CA converts the first switching time difference τ at which the first input signal CLK-A and the second input signal CLK-B are switched into corresponding first gate stage number information (N bits). . Further, the second conversion circuit CB converts the second gate stage number information (N ′ bits) determined according to the first gate stage number information (N bits) into the second switching time difference τ ′. The delay circuit shown in FIGS. 29A and 29B delays and outputs the third input signal IN input to the second conversion circuit CB by the second switching time difference τ ′ (see FIG. 29A). OUT).

  The first conversion circuit CA has an array structure in which at least two or more first unit circuits UA are regularly repeated, and the first input signal CLK-A is supplied to the first unit circuit UA in the array of the first unit circuit UA. It propagates in the direction D1. Further, the second conversion circuit CB has an array structure in which at least two second unit circuits UB that reproduce the delay time per stage of the first unit circuit UA are regularly repeated. In the second conversion circuit (CB), the input signal IN is propagated in a second direction (D2) opposite to the first direction D1.

  In FIG. 29 (b), the reference symbol CE indicates a reset unit composed of a plurality of reset circuits RST. The reset unit CE resets the input / output signals of each stage of the array of the second unit circuit UB in the second conversion circuit CB immediately before the third input signal IN is input.

  FIG. 30 is a waveform diagram showing a circuit example for generating a clock signal and its operation in the delay circuit of FIG. 29. FIG. 30 (a) is a circuit for generating the first input signal CLK-A, and FIG. The circuit for generating the second input signal CLK-B, and FIG. 8C is a waveform diagram showing the operation of these circuits.

  As shown in FIGS. 30A and 30B, the clock signals (first input signal CLK-A and second input signal CLK-B) use predetermined signals as clock signals as they are. In addition, for example, the clock signal generation circuit includes two control signals CLK-A1 (CLK-B1) and CLK-A2 (CLK-B2) at the gates of P-channel and N-channel MOS transistors and two inverters. The latch circuit may be configured, and the output of the clock signal generation circuit may be used as the first input signal CLK-A and the second input signal CLK-B. As a result, as shown in FIG. 30 (c), the first input signal CLK-A and the second input signal CLK-B having the switching time difference (first switching time difference) τ are generated.

  Here, in the clock signal generation circuit shown in FIGS. 30 (a) and 30 (b), as is apparent from FIG. 30 (c), the first input signal CLK-A and the second input signal CLK-B. Switching time difference (first switching time difference τ) is the time from when the first input signal CLK-A rises to when the second input signal CLK-B falls, and the first input signal CLK-A. Is defined by both the time from when the signal falls to the time when the second input signal CLK-B rises.

  FIG. 31 is a circuit diagram showing a first embodiment of the delay circuit of the present invention, and FIG. 32 is a waveform diagram showing the operation of the delay circuit shown in FIG. In FIG. 31, reference numeral CA is a first conversion circuit, CB1 and CB2 are second conversion circuits, CD1 and CD2 are gate stage number information conversion circuits, and RA is a latch circuit.

  As shown in FIG. 31, the first embodiment of the delay circuit of the present invention includes one first conversion circuit (τ to N conversion circuit) CA, two gate stage number information conversion circuits (N to N ′ conversion circuit). ) CD1, CD2, and two second conversion circuits (N ′ to τ ′ conversion circuit) CB1 and CB2 and a latch circuit RA.

  In the first conversion circuit CA, each unit circuit (first unit circuit) UA is configured by a NOR gate or a NAND gate. Specifically, in the first unit circuit UA, the even-numbered stages are configured by NOR gates, and the odd-numbered stages are configured by NAND gates. That is, the first unit circuit UA includes an inverting gate circuit having an inverting function, and performs conversion using the delay time per gate stage of the inverting gate circuit as a unit time. Here, the first unit circuit UA can be configured with the even-numbered stages by NAND gates and the odd-numbered stages by NOR gates.

  In the second conversion circuit CB (CB1, CB2), each unit circuit (second unit circuit) UB is composed of two NOR gates or two NAND gates. Specifically, in one second conversion circuit CB1, the even-numbered stages are configured by NOR gates, and the odd-numbered stages are configured by NAND gates. In the other second conversion circuit CB2, The even-numbered stages are composed of NAND gates, and the odd-numbered stages are composed of NOR gates. That is, the second unit circuit UB also includes an inverting gate circuit having an inverting function, and performs conversion using the delay time per gate stage of the inverting gate circuit as a unit time. Here, in each of the second unit circuits UB, only one of the two gate circuits is used and the other is not used because the delay time for each unit circuit is accurately defined while maintaining the symmetry of the circuit. It is to do.

  In the latch circuit RA, each unit circuit is composed of two NOR gates or two NAND gates. In the gate stage number information conversion circuit CD (CD1, CD2), each unit circuit UD is composed of a NOR gate or a NAND gate. It is composed of gates. Furthermore, the latch circuit RA is provided corresponding to each first unit circuit UA of the first conversion circuit CA, and the latch circuit (each latch unit of the latch circuit RA) is provided for each first unit circuit UA. The data to be output to is stored.

  The first switching time difference τ at which the first input signal CLK-A and the second input signal CLK-B are switched is converted into corresponding first gate stage number information (N bits) in the first conversion circuit CA. The That is, the signal change is transmitted to the N-bit unit circuit UA (a predetermined number of gates) corresponding to the first switching time difference τ, and the data is held in the latch circuit RA. Then, the data of the latch circuit RA (the output of the gate next to the gate to which the signal is propagated in the first conversion circuit CA) is supplied to the second conversion circuit CB1 through the gate stage number information conversion circuits CD1 and CD2, respectively. And CB2, and in the second conversion circuits CB1 and CB2, the signal is propagated toward the output (OUT) side.

  Here, in the first embodiment, the gate stage number information conversion circuits CD1 and CD2 supply the first gate stage number information (N bits) as it is to the second conversion circuits CB1 and CB2, that is, N to N conversion is performed, and the second switching time difference τ ′ becomes the same as the first switching time difference τ by the conversion by the second conversion circuits CB1 and CB2.

  Therefore, as shown in FIG. 32, the delay at the node (1) and the node (2) is τ, and as a result, the input signal (third input signal) IN is delayed from the output (OUT) by the time τ. The processed signal OUT is taken out. The pulse width TW0 in the signals at the nodes (1) and (2) is generated by the latch circuit LA0 and the delay line DL0 provided at the output (OUT). That is, the signals at the nodes (1) and (2) are reset so as to keep the output (OUT) in the high impedance state after the level change of the pulse width TW0.

  Here, the first gate stage number information (N bits) corresponds to a collection of all or part of data output for each first unit circuit UA, and the second gate stage number information (N The “bit” corresponds to a collection of all or part of the data input for each second unit circuit UB. In the first embodiment, the second gate stage number information corresponds to a collection of all data input for each second unit circuit UB. That is, as the second gate stage number information (N ′ bit), a signal synchronized with the signal of each bit of the first gate stage number information (N bit) is directly input to the second conversion circuit (CB1, CB2). It has become. Further, the gate stage number information (second gate stage number information) directly input to the second conversion circuit may be a signal in phase with the signal of each bit of the first gate stage information (N bits). Of course, it may be a signal.

  33 and 34 are circuit diagrams showing a second embodiment of the delay circuit of the present invention, and FIG. 35 is a waveform diagram showing the operation of the delay circuit shown in FIGS.

  As shown in FIGS. 33 and 34, in the second embodiment, a latch circuit RB is provided in addition to the latch circuit RA described above. The latch circuit RB is provided corresponding to each second unit circuit (UB) of the second conversion circuits CB1, CB2 (CB), and is input to the latch circuit RB for each second unit circuit. Data is stored. The latch circuit RB supplies stable data to the second conversion circuits CB1 and CB2 with no signal fluctuation.

  Here, in the second embodiment shown in FIGS. 33 and 34, reference numeral WR is a write control circuit, and the data of the first latch circuit RA is transferred to the second latch circuit RB in accordance with the operation of the write control circuit WR. To be written.

  FIG. 36 is a diagram showing an example of a unit circuit applied to the delay circuit of the present invention. FIGS. 36 (a) and (b) show configuration examples of the unit circuit, and FIG. 36 (c) explains the operation. It is a waveform diagram.

  As shown in FIGS. 36 (a) and (B), each unit circuit (UA, UB) has an inverter circuit (an inverting gate circuit having an inverting function), and a delay time per stage of each gate of the inverter circuit. Is converted into the corresponding first gate stage number information (N bits) τ (the first switching time difference at which the first input signal CLK-A and the second input signal CLK-B are switched) τ. It is like that.

  Here, in the unit circuit shown in FIGS. 36A and 36B, as shown in FIG. 36C, when the second input signal CLK-B is at the high level “H”, the first circuit When the switching of the input signal CLK-A is started, the output of the gate when the second input signal CLK-B is set to the low level “L” is the first gate corresponding to the first switching time difference τ. It remains as stage number information (N bits).

  FIG. 37 is a diagram showing another example of a unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 37 (a) and (B), each unit circuit (UA, UB) includes a reset signal input terminal (RESET), and a signal depending on the first input signal CLK-A passes therethrough. The previous output is set to the opposite of the expected value. Further, each unit circuit (UA, UB) includes a data capture circuit (CI), and captures data when the second input signal CLK-B is switched in the unit circuit.

  FIG. 38 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 38A and 38B, in each unit circuit (UA, UB), the delay time on the side of propagating the signal depending on the first input signal CLK-1 is made fast. The input threshold values of the first conversion circuit CA and the second conversion circuit CB are biased. That is, in the unit circuit (NAND type) shown in FIG. 38 (a), the transistor size of the P-channel MOS transistor is reduced, the transistor size of the N-channel MOS transistor is increased, and FIG. In the unit circuit (NOR type) shown in (2), the transistor size of the P-channel MOS transistor is increased and the transistor size of the N-channel MOS transistor is decreased. Thereby, the delay time (quantized speed) for each unit circuit can be shortened, and the delay time can be controlled with high accuracy.

  FIG. 39 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 39A and 39B, each unit circuit (UA, UB) is provided with a delay time adjustment capacitor CC, and the above-described data capture is performed by the delay time adjustment capacitor CC. A capacitance corresponding to the input capacitance of the circuit CI is added. Note that the capacitor CC shown in FIGS. 39A and 39B is composed of two transistors (CMOS transistors).

  Further, the unit circuit shown in FIGS. 39A and 39B includes a reset signal input terminal (RESET), and sets the output immediately before the signal depending on the third input signal IN passes to the opposite of the expected value. It is supposed to be.

  FIG. 40 is a circuit diagram showing a third embodiment of the delay circuit of the present invention, and FIG. 41 is a waveform diagram showing the operation of the delay circuit shown in FIG.

  As shown in FIG. 40, the delay circuit of the third embodiment is configured to include two first conversion circuits CA1 and CA2 and two second conversion circuits CB1 and CB2. The gate stage number information output of each unit circuit UA of the conversion circuit CA1 (CA2) is directly supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2), and the second conversion circuit CB1. The delay time of (CB2) is aligned with the delay time of the first conversion circuit CA1 (CA2).

  Here, one second conversion circuit CB1 starts an array from a unit circuit UB having a NAND type delay circuit, and the other second conversion circuit CB2 starts an array from a unit circuit UB having a NOR type delay circuit. The unit circuit of the first stage starts and the input level is fixed so as to be an inverter type delay circuit.

  As shown in FIG. 41, in the third embodiment of FIG. 40, an output signal OUT having a delay time 2τ that is twice the time difference τ is obtained from the input signal IN.

  42 and 43 are circuit diagrams showing a fourth embodiment of the delay circuit of the present invention. FIG. 44 is a waveform diagram showing the operation of the delay circuit shown in FIGS.

  As shown in FIGS. 42 and 43, in the delay circuit of the fourth embodiment, the gate stage number information conversion circuit CD1 (CD2) is replaced with the first conversion circuit CA1 (CA2) and the second conversion circuit CB1 (CB2). Between. That is, the gate stage number information conversion circuit CD1 (CD2) has a gate for every M stages (in this embodiment, every third stage, that is, every two stages) of each unit circuit UA of the first conversion circuit CA1 (CA2). The stage number information output is supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2), and the delay time (τ) of the second conversion circuit CB1 (CB2) is converted into the first conversion circuit. The delay time of the circuit CA1 (CA2) is set to 1 / M (in this embodiment, 1/3).

  Specifically, in the fourth embodiment, one unit circuit UD in the gate stage number information conversion circuit CD2 is provided for the three unit circuits UA1 to UA3 in the first conversion circuit CA2 in FIG. 44, an output signal OUT having a delay time τ / 3 that is 1/3 of the time difference τ is obtained from the input signal IN. Thus, according to the delay circuit of the present embodiment, an output signal having a required delay time can be obtained.

  45 and 46 are circuit diagrams showing a fifth embodiment of the delay circuit of the present invention, and FIG. 47 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 45 and 46.

  As is apparent from a comparison between the fifth embodiment shown in FIGS. 45 and 46 and the fourth embodiment shown in FIGS. 42 and 43, in the fifth embodiment, the first conversion circuit CA1 (CA2) A gate stage number information output for every M stages (in this embodiment, every second stage, ie, every other stage) of each unit circuit UA is sent via an inverter circuit II of a predetermined number of stages (in this embodiment, one stage). It is adapted to the required phase and is supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2). Specifically, the inverter II is inserted at every other stage of the gate output (every other stage gate output) taken out from the first conversion circuit CA1.

  As shown in FIGS. 45 and 46, in the fifth embodiment, two first conversion circuits (CA) (CA1 and CA2) are provided, and the first input in the first conversion circuit (CA1). The delay time when the signal CLK-A rises and the delay time when the first input signal CLK-A falls in the first conversion circuit (CA2) are also set separately.

Thus, as shown in FIG. 47, the time difference τ ₁ when the first input signal CLK-A falls to the high level “H” and the second input signal CLK-B falls to the low level “L”, The time difference τ ₂ when the first input signal CLK-A rises to a low level “L” and the second input signal CLK-B rises to a high level “H” is 1 / M (in this embodiment) Then, a signal having a delay time of 1/2) can be obtained. In the present embodiment, the level of the output signal OUT is inverted with respect to the input signal IN, but it goes without saying that the necessary one can be generated depending on the configuration of the gate circuit. .

  Further, the gate stage number information conversion circuit CD, the gate stage number information output for one stage of each unit circuit UA of the first conversion circuit CA, and the gate stage number information input of the M stage unit circuit UB of the second conversion circuit CB are input. The delay time of the second conversion circuit CB can be set to M times the delay time of the first conversion circuit CA.

  48 and 49 are circuit diagrams showing a sixth embodiment of the delay circuit of the present invention, and FIG. 50 is a waveform diagram showing the operation of the delay circuit shown in FIGS.

As shown in FIGS. 48 and 49, in the sixth embodiment, NAND type unit circuits and NOR type units are alternately arranged in the even and odd stages of the two first conversion circuits CA1 and CA2. The circuits are arranged repeatedly in an array, and the rising time delay time generating unit circuit and the falling time delay time generating unit circuit in the two second conversion circuits CB1 and CB2 are also provided. Similarly, NAND-type unit circuits and NOR-type unit circuits are alternately and repeatedly arranged in an array at even-numbered stages and odd-numbered stages. Then, the delay time generating unit circuit at the time of rising (the time difference τ ₂ when the second input signal CLK-B rises to the high level “H”) and the unit circuit at the time of falling (the second input signal CLK-B is In the delay time generating unit circuit having the time difference τ ₁ ) when falling to the low level “L”, the above NAND type and NOR type arrangements are reversed. Further, the outputs of the first conversion circuits CA1 and CA2 are temporarily latched and output by the latch circuits RA1 and RA2.

50, a signal having a delay time (rise time difference) τ ₂ when the output OUT rises and a delay time (fall time difference) τ ₁ when falling (as shown in FIG. 50). An output signal OUT) is obtained.

  51 and 52 are circuit diagrams showing a seventh embodiment of the delay circuit of the present invention, and FIG. 53 is a waveform diagram showing the operation of the delay circuit shown in FIGS.

  In the seventh embodiment shown in FIG. 51 and FIG. 52, a plurality of second conversion circuits (CB) (four: CB1 to CB4) are provided, and the second input in the second conversion circuits CB1 to CB4. A plurality of types of delay time when the signal CLK-B rises and delay time when the second input signal CLK-B falls in the second conversion circuits CB1 to CB4 are set separately. It has become.

  As shown in FIG. 53, the logic of the outputs (node (1) to node (4)) of each of the second conversion circuits CB1 to CB4 is taken to oscillate the input signal (third input signal) IN. The frequency is changed (in this embodiment, the frequency is changed four times (a constant multiple)). In the seventh embodiment, the output signal OUT is taken out by giving a delay time that is half the time difference τ (τ / 2) to the input signal IN.

  54 is a circuit diagram showing an example of an array structure applied to the delay circuit of the present invention, and FIG. 55 is a circuit diagram showing another example of the array structure applied to the delay circuit of the present invention. The array structures shown in FIGS. 54 and 55 show a configuration example of the first conversion circuit CA.

  As shown in FIG. 54, the first input signal CLK-A is supplied to the first stage of the array of the unit circuits UA in the first conversion circuit CA, and signal propagation is started.

  Further, as is apparent from the comparison between the unit circuits described with reference to FIGS. 55 and 38, the first input signal CLK-A is supplied to the unit circuit UA in the first conversion circuit CA as the reset signal. The delay generation gate in each unit circuit UA may be controlled to be in a reset state or an inversion state. In the array structure shown in FIG. 55, the input of the first stage unit circuit UA in the first conversion circuit CA is set to a fixed level (high level “H”), and the first input signal CLK-A is in an inverted state. When instructed, signal transmission of the array in the first conversion circuit CA is started.

  56 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention. FIG. 57 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention. It is. The array structures shown in FIGS. 56 and 57 show a configuration example of the second conversion circuit CB.

  As shown in FIGS. 56 and 57, the second conversion circuit CB receives the second gate stage number information (N ′ bits), gives the corresponding delay time (τ ′) to the input signal, and outputs the output signal. OUT is sent out, and includes N ′ unit circuits UB corresponding to the second gate stage number information.

  As shown in FIGS. 31 to 35 and FIGS. 40 to 53, the first stage unit circuit (UB) in the second conversion circuit CB is configured as a unit circuit including an inverter type delay circuit. Further, when a long switching time difference (τ) exceeding the delay time in the first conversion circuit CA is input to the input of the first stage of the array of the unit circuits UB in the second conversion circuit CB, the gate stage number information ( N ′) may be clamped to the side to be reversed. Furthermore, an input may be clamped at the first stage of the array of unit circuits UB in the second conversion circuit CB on the side where the delay circuit in the first stage unit circuit UB operates as an inverter.

  Further, the first and second input signals (CLK-A, CLK-B) to the first conversion circuit CA are periodically sent only once every M times (for example, 8 times or 16 times) of clock switching. The second gate stage number information (N ′ bits) may be regenerated. Thereby, even when the master clock fluctuates, it can follow. Further, if the second gate stage number information N ′ that has been regenerated is configured to be reset when the second conversion circuit CB is not propagating the third input signal IN, the other operations are not hindered. Second gate stage number information (N ′ bits) can be regenerated.

  58 and 59 are circuit diagrams showing an eighth embodiment of the delay circuit of the present invention, and FIG. 60 is a waveform diagram showing the operation of the delay circuit shown in FIGS.

  58 and FIG. 59, the second gate stage number information N ′ is regenerated by the delay time variation control circuit CD ′ provided between the latch circuit RA and the latch circuit RB. The old and new fluctuations in the value of the second gate stage number information (N ′) at the time are reduced. That is, the delay time variation control circuit CD ′ takes the output logic of the first and second unit circuits (UA) before and after and gradually changes the value of the regenerated second gate stage number information (N ′). It is like that. FIG. 60 shows a state in which the second gate stage number information N ′ is regenerated and an output signal (OUT) delayed by time (τ) from the input signal (IN) is output.

  61 and 62 are circuit diagrams showing a ninth embodiment of the delay circuit of the present invention, and FIG. 63 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 61 and 62. The ninth embodiment shown in FIGS. 61 and 62 is a modification of the seventh embodiment shown in FIGS. 51 and 52 described above.

  As shown in FIGS. 61 and 62, the ninth embodiment is provided with a plurality of pairs (two pairs) of second conversion circuits CB1, CB2; CB3, CB4, and one second of each pair. The rise timing of the output OUT is delayed by the conversion circuits CB1 and CB3, and the fall timing of the output OUT is delayed by the other second conversion circuits CB2 and CB4. Then, the output switching timing of the reverse output OUT is determined by other output switching timing creation means, and the output in each of the second conversion circuits CB1, CB2; CB3, CB4 and other output switching timing creation The output of the means is bus-connected to the composite output node. Here, the second conversion circuits CB1 and CB3 receive one gate stage number information output in two stages of each unit circuit UA of the first conversion circuit CA.

  As a result, as shown in FIG. 63, the logic of the outputs (node (1) to node (4)) of each of the second conversion circuits CB1 to CB4 is taken to determine the input signal (third input signal) IN. A signal obtained by changing the vibration frequency by a factor of two is obtained. In the ninth embodiment, a delay time that is half the time difference τ (τ / 2) is given to the input signal IN, and the input signal IN is inverted to take out the output signal OUT. Yes.

  64 and 65 are circuit diagrams showing a tenth embodiment of the delay circuit of the present invention, and FIG. 66 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 64 and 65.

  As shown in FIGS. 64 and 65, in the tenth embodiment, 2M (four) second conversion circuits (CB) are provided, and as shown in FIG. IN) is configured to output an output signal having a frequency M times (twice).

  As shown in each of the above-described embodiments, when two second conversion circuits (CB) are provided and the delay at the rising time of the input and the delay at the falling time of the input are separately made, The output in each of the second conversion circuits (CB1, CB2) is bus-connected to the composite output node, and predetermined data is output to the output unit in each of the second conversion circuits for a certain time after output switching. The output impedance can be sufficiently increased during other periods. Specifically, for example, a latch circuit LA0 and a delay line DL0 in FIG. 31 are provided for the output (OUT), and predetermined data is output only for a fixed time after the output is switched, and output is output in other periods. You may make it hold | maintain in a high impedance state.

  Further, a delay circuit capable of electrically controlling another type of delay time is provided in the plurality of second conversion circuits (CB), and the delay time of the second conversion circuit is reduced by controlling the delay circuit. You may make it adjust.

  Further, an odd number of second conversion circuits (CB) are provided, and the input and output of each second conversion circuit are connected so as to form a ring oscillator, and the time set by the first conversion circuit (CA) ( You may comprise so that it may have a period of L / M times (L and M are integers) of (tau).

  67 and 68 are circuit diagrams showing an eleventh embodiment of the delay circuit of the present invention, and FIG. 69 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 67 and 68.

  As shown in FIGS. 67 and 68, in the eleventh embodiment, an even number (four) of second conversion circuits (CB1 to CB4) are provided. Further, an odd number (one) of inverter gates are further provided, and the inputs and outputs of the second conversion circuits CB1, CB2; CB3, CB4 are connected to form a ring oscillator via the inverter gates. ing.

  That is, as shown in FIGS. 67 and 68, the signal OUT1 that is the output of the second conversion circuits CB1 and CB2 is directly supplied as the input signal IN2 of the second conversion circuits CB3 and CB4, and the inverter IFD2 And is supplied to the second conversion circuits CB3 and CB4 as the input signal / IN2 of the second conversion circuits CB3 and CB4. Similarly, the signal OUT2 that is the output of the second conversion circuits CB3 and CB4 is directly supplied as the input signal / IN1 of the second conversion circuits CB1 and CB2, and is inverted by the inverter IFD1 to be inverted by the second conversion circuit. The input signals IN1 of CB1 and CB2 are supplied to the second conversion circuits CB1 and CB2. As a result, as shown in FIG. 69, output signals OUT (OUT1, OUT2) having a period of L / M times (L and M are integers) the time difference τ set by the first conversion circuit CA are obtained. be able to.

  70 and 71 are circuit diagrams showing a twelfth embodiment of the delay circuit of the present invention. The twelfth embodiment shown in FIGS. 70 and 71 is different from the eleventh embodiment shown in FIGS. 67 and 68 in that a fine adjustment delay circuit DA (DA1, DA2) is provided.

  That is, the fine adjustment delay circuits DA1 and DA2 are provided immediately before taking out the outputs OUT1 and OUT2 for each of the plurality of second conversion circuits CB1 and CB2 and CB3 and CB4. By the fine adjustment delay circuits DA1 and DA2, output signals OUT1 and OUT2 having timing frequencies synchronized with the third input signal IN are taken out for each of the second conversion circuits (CB1, CB2; CB3, CB4). ing.

  Here, a delay circuit capable of electrically controlling another type of delay time is provided in the second conversion circuit (CB), and the output switching timing of any of the second conversion circuits is set to an external clock. The delay time of the delay circuit is controlled so as to synchronize with the output switching timing of the signal, and the cycle is set to L / M times (L and M are integers) times (τ) set by the first conversion circuit (CA). You may comprise so that it may have. Further, a delay circuit having a fixed time that reflects variations due to manufacturing conditions is provided in the second conversion circuit (CB), and the output of one of the second conversion circuits (CB) is switched. The delay time of the delay circuit may be controlled so that the timing is synchronized with the output switching timing of the external clock signal, and an internal clock that is switched earlier by the fixed time than the external clock signal may be created. it can.

It is a figure which shows the principle structure of the timing control circuit which concerns on this invention. It is a figure for demonstrating 1st Example of the timing control circuit of this invention. It is a figure for demonstrating the 2nd Example of the timing control circuit of this invention. It is a figure for demonstrating the 3rd Example of the timing control circuit of this invention. It is a figure for demonstrating the 4th Example of the timing control circuit of this invention. It is a figure for demonstrating the 5th Example of the timing control circuit of this invention. It is a figure for demonstrating the 6th Example of the timing control circuit of this invention. It is a figure for demonstrating the 7th Example of the timing control circuit of this invention. It is a figure for demonstrating the 8th Example of the timing control circuit of this invention. It is a figure for demonstrating the 9th Example of the timing control circuit of this invention. It is a figure for demonstrating 10th Example of the timing control circuit of this invention. It is a figure for demonstrating 11th Example of the timing control circuit of this invention. It is a figure for demonstrating 12th Example of the timing control circuit of this invention. It is a figure for demonstrating 13th Example of the timing control circuit of this invention. It is a figure for demonstrating 14th Example of the timing control circuit of this invention. It is a figure for demonstrating the application example of the timing control circuit of this invention. FIG. 2 is a circuit diagram (part 1) illustrating an example of a clock generation circuit to which the timing control circuit of the present invention is applied. FIG. 3 is a circuit diagram (part 2) illustrating an example of a clock generation circuit to which the timing control circuit of the present invention is applied. FIG. 6 is a circuit diagram (part 3) illustrating an example of a clock generation circuit to which the timing control circuit of the present invention is applied; FIG. 20 is a timing diagram (No. 1) illustrating each signal of the clock generation circuit illustrated in FIGS. 17 to 19; FIG. 20 is a timing diagram (part 2) illustrating each signal of the clock generation circuit illustrated in FIGS. 17 to 19; It is a figure for demonstrating an example of the conventional timing control circuit. It is a block diagram which shows roughly an example of the circuit structure to which a timing control circuit is applied. It is a figure for demonstrating the other example of the conventional timing control circuit. It is a block diagram which shows an example of the conventional delay circuit. It is a block diagram which shows the other example of the conventional delay circuit. It is a block diagram which shows an example of the conventional PLL circuit. It is a block diagram which shows the basic composition of the DLL circuit to which this invention is applied. It is a block diagram which shows the principle structure of the delay circuit to which this invention is applied. FIG. 30 is a waveform diagram showing a circuit example for generating a clock signal in the delay circuit of FIG. 29 and its operation. FIG. 3 is a circuit diagram illustrating a first embodiment of a delay circuit according to the present invention. FIG. 32 is a waveform diagram showing an operation of the delay circuit shown in FIG. 31. FIG. 6 is a circuit diagram (No. 1) showing a second embodiment of the delay circuit of the present invention; FIG. 6 is a circuit diagram (No. 2) showing a second embodiment of the delay circuit of the present invention; FIG. 35 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 33 and 34. It is a figure which shows the example of the unit circuit applied to the delay circuit of this invention. It is a figure which shows the other example of the unit circuit applied to the delay circuit of this invention. It is a figure which shows the further another example of the unit circuit applied to the delay circuit of this invention. It is a figure which shows the further another example of the unit circuit applied to the delay circuit of this invention. FIG. 6 is a circuit diagram showing a third embodiment of the delay circuit of the present invention. FIG. 41 is a waveform diagram showing an operation of the delay circuit shown in FIG. 40. FIG. 6 is a circuit diagram (No. 1) showing a fourth embodiment of the delay circuit according to the present invention; FIG. 6 is a circuit diagram (No. 2) showing a fourth embodiment of the delay circuit according to the present invention; 44 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 42 and 43. FIG. FIG. 6 is a circuit diagram (No. 1) showing a fifth embodiment of the delay circuit according to the present invention; FIG. 6 is a circuit diagram (No. 2) showing a fifth embodiment of the delay circuit according to the present invention; 47 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 45 and 46. FIG. FIG. 10 is a circuit diagram (No. 1) showing a sixth embodiment of the delay circuit according to the present invention; FIG. 12 is a circuit diagram (No. 2) showing a sixth embodiment of the delay circuit according to the present invention; FIG. 50 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 48 and 49. FIG. 12 is a circuit diagram (No. 1) illustrating a seventh embodiment of the delay circuit according to the present invention; FIG. 12 is a circuit diagram (No. 2) showing a seventh embodiment of the delay circuit according to the present invention; FIG. 53 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 51 and 52. It is a circuit diagram which shows an example of the array structure applied to the delay circuit of this invention. It is a circuit diagram which shows the other example of the array structure applied to the delay circuit of this invention. It is a circuit diagram which shows the further another example of the array structure applied to the delay circuit of this invention. It is a circuit diagram which shows the further another example of the array structure applied to the delay circuit of this invention. FIG. 12 is a circuit diagram (No. 1) showing an eighth embodiment of the delay circuit according to the present invention; FIG. 10C is a circuit diagram (No. 2) illustrating the eighth embodiment of the delay circuit according to the present invention; FIG. 60 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 58 and 59. It is a circuit diagram (the 1) which shows 9th Example of the delay circuit of this invention. It is a circuit diagram (the 2) which shows 9th Example of the delay circuit of this invention. FIG. 63 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 61 and 62. It is a circuit diagram (the 1) which shows 10th Example of the delay circuit of this invention. It is a circuit diagram (the 2) which shows 10th Example of the delay circuit of this invention. FIG. 66 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 64 and 65. It is a circuit diagram (the 1) which shows 11th Example of the delay circuit of this invention. It is a circuit diagram (the 2) which shows 11th Example of the delay circuit of this invention. FIG. 69 is a waveform diagram showing an operation of the delay circuit shown in FIGS. 67 and 68. It is a circuit diagram (the 1) which shows 12th Example of the delay circuit of this invention. It is a circuit diagram (the 2) which shows 12th Example of the delay circuit of this invention.

Explanation of symbols

1 First circuit (input buffer circuit)
2 Second circuit (delay circuit)
3 Time difference expansion circuit 4 Signal transmission part (long wiring delay)
5 Output buffer 21 Delay circuit (long wiring delay)
22 delay circuit 23 output buffer circuit 24 delay circuit (output fixed time setting circuit)
AA first gate row BB second gate row CLK-A first input signal CLK-B second input signal CA first conversion circuit CB second conversion circuit CD gate stage number information conversion circuit IN third Input signal N First gate stage number information N ′ Second gate stage number information UA First unit circuit UB Second unit circuit X First control signal Y Second control signal τ First switching time difference (time difference)
τ 'second switching time difference

Claims (6)

A plurality of first gate circuits connected in series, each receiving a first control signal and receiving a second control signal, the first control signal for a first time until a switching point of the second control signal. A first gate row that propagates the control signal in a first direction;
A plurality of second gate circuits connected in series, propagating a signal in a second direction opposite to the first direction, receiving an output signal from the first gate row, and receiving the first signal And a second gate row for generating a second time corresponding to the time.   2. The delay circuit according to claim 1, wherein an output signal from the first gate row is stored in a memory or a register.   3. The delay circuit according to claim 2, wherein the output signal stored in the memory or the register is updated according to a predetermined clock cycle.   The delay circuit according to claim 1, wherein each of the first gate circuits includes an inverter.   2. The delay circuit according to claim 1, wherein the number of the first gate circuits is the same as the number of the second gate circuits.   The delay circuit according to claim 1, wherein the first time is equal to the second time.

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