JP4053506B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit using CMOS, and is particularly suitable for realizing a semiconductor integrated circuit in which a logic circuit and a memory are formed on the same substrate without complicating the manufacturing process.

Japanese Patent Laid-Open No. 10-65517 discloses a conventional technique for increasing the speed of a logic circuit. In this conventional technology, the operation speed is improved by using a low threshold voltage transistor in a signal path that determines the operation speed, that is, a so-called critical path. The leakage current was reduced using a voltage transistor (see Patent Document 1).
JP-A-10-65517

  High performance of integrated circuits using CMOS has been realized by high performance and high integration of transistors by miniaturizing the gate length of NMOS and PMOS transistors and thinning the gate oxide film thickness. . Along with this, the power supply voltage has been reduced so that the electric field strength does not increase due to these miniaturization and thinning. For example, as a standard example in the industry, the power supply voltage is 3.3 V in the generation with a gate length of 0.35 μm, whereas the power supply voltage is 2.5 V in the generation with a gate length of 0.25 μm. ing.

  With further miniaturization in the future, it is expected that the power supply voltage will be further lowered. Therefore, unless the threshold voltage is lowered, the operation speed of the integrated circuit is significantly deteriorated. However, when the threshold voltage is lowered, the subthreshold current increases and the leakage current increases. Therefore, in the above-described prior art, a method is employed in which three types of threshold voltages of the logic circuit are provided, and in particular, the threshold value of the transistor in the signal path circuit that determines the operation speed is lowered. However, this conventional technique has a complicated manufacturing method because three kinds of threshold values are produced.

  On the other hand, integrated circuits in recent years tend to be large-scale, and not only logic circuits but also circuits such as fairly large scale memories, input / output interfaces, PLLs, clocks, and the like are mounted on one chip. It has become.

  However, such circuits have different characteristics, and the required transistor characteristics differ accordingly. For example, an SRAM memory cell composed of six transistors used together with a logic circuit cannot be lowered below a certain voltage in order to achieve electrical stability. In addition, in a DRAM memory cell composed of one capacitor and one transistor, the charge accumulated in the capacitor is discharged due to transistor leakage by lowering the threshold value. The threshold cannot be lowered. Since the input / output voltage is defined by the standard and is higher than the internal operating voltage, the input / output interface circuit inserted between them requires a channel length and a gate oxide film that can withstand even a high breakdown voltage.

  As described above, an optimum gate length, gate oxide film, and threshold voltage exist depending on the characteristics of each circuit in the integrated circuit. In a semiconductor integrated circuit in which these circuits are integrated on the same substrate, the manufacturing process becomes complicated when trying to manufacture according to each circuit characteristic, resulting in a decrease in yield and an increase in manufacturing cost due to an increase in manufacturing days. There is a risk.

  The present invention is low-cost without complicating the manufacturing process even in the case of a semiconductor integrated circuit in which the power supply voltage of the logic circuit is reduced as described above and more than one type of circuit exists on the same substrate. A semiconductor integrated circuit means that can be manufactured is provided.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes a memory cell array in which a large number of DRAM memory cells each having a first transfer NMOS transistor and a first capacitor are integrated, and an input / output circuit including a first PMOS transistor and a second NMOS transistor. The transfer NMOS transistor, the second NMOS transistor, and the first PMOS transistor have the same gate oxide film thickness, and the channel length of the first transfer NMOS transistor is larger than the channel length of the second NMOS transistor.

  The following is a brief description of another outline of the invention disclosed in the present application.

That is, the present invention includes a memory cell array in which a logic circuit and a memory cell are integrated in a semiconductor integrated circuit,
The logic circuit includes a first logic gate comprising an NMOS transistor having a first threshold voltage and a PMOS transistor having a third threshold voltage, an NMOS transistor having a second threshold voltage, and a fourth threshold voltage. Formed by a second logic gate comprising a PMOS transistor having
The memory cell array is a memory cell array in which static memory cells each composed of two load MOS transistors, two drive MOS transistors, and two transfer MOS transistors are integrated.
The two load MOS transistors are formed by PMOS transistors having the fourth threshold voltage,
The two driving MOS transistors are formed by NMOS transistors having the second threshold voltage,
The first threshold voltage is smaller than the second threshold voltage, and the absolute value of the third threshold voltage is smaller than the absolute value of the fourth threshold voltage. Design the cell.

  That is, in the present invention, two kinds of high and low threshold transistors are used in the logic circuit, and at least the driving MOS transistor of the SRAM memory cell is constituted by a transistor having the same threshold value as the high threshold value. As the transfer MOS transistor of the cell, a transistor having the same channel impurity amount as the above high threshold and a gate oxide film thickness is used, and the input / output circuit has the same channel impurity concentration as that of the above high threshold or low. A transistor having a gate oxide film thickness with the same channel impurity concentration as the threshold value is used. By the above means, a transistor optimum for each circuit can be manufactured without increasing the number of steps.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, in a semiconductor integrated circuit in which a logic circuit and a memory are integrated, it is possible to provide an optimum transistor for the operation of a DRAM memory cell without increasing the number of steps.

  Note that the logic circuit referred to in the present application refers to a circuit area formed by combining logic gates, excluding a memory cell array, and includes a register file, a data path including an arithmetic unit, control logic, and the like. The high (low) threshold value refers to a high (low) threshold value of the absolute value of the threshold value in the PMOS transistor. Since the threshold value is generally different between the PMOS transistor and the NMOS transistor, the two types of high and low are the two types of high and low in each channel type.

  FIG. 1 shows a schematic diagram of the first embodiment. The logic circuit area 2 and the SRAM area 3 are integrated in the same semiconductor integrated circuit 1. In particular, as shown in the figure, the transistors constituting the gate of the logic circuit region 2 include those having a high threshold value and those having a low threshold value.

  In the logic circuit region 2, the threshold value of the transistor constituting the logic gate may be selected according to the operation speed required for the gate. The portion using the gate of the low threshold transistor has an effect of increasing the operation speed. For circuit portions where operation speed is not so required, leakage current can be reduced by using a gate formed of a high threshold transistor. Specifically, transistors on the critical path of the logic circuit use low threshold transistors for speeding up, and transistors not on the critical path use high threshold transistors to reduce leakage current. For example, a transistor before diversion in the diversion path and a transistor after merging in the merge path are low threshold transistors. Also, if there is a current control switch that controls the current in the source / drain path of the transistor that constitutes the logic gate between the operating potential point and the logic gate for each block, the transistor that constitutes the switch is set to the high threshold value. A transistor constituting a logic gate to be controlled is a low threshold transistor. Japanese Patent Application No. 9-359277 has already described how to use high and low thresholds in such a logic circuit.

On the other hand, it is desirable to use a high threshold transistor as the transistor constituting the SRAM cell in the SRAM region 3 in order to ensure the stability of the SRAM cell. In order to explain the relationship between the threshold voltage of the SRAM memory cell transistor and its electrical stability, FIG. 2 shows the dependence of the SRAM cell noise margin on the power supply voltage. As a parameter, the threshold voltage V _th of the drive transistors (transistors 48 and 49 in FIG. 4) in the memory cell was used. When this cell noise margin is lower than 0V, the memory cell does not operate as an SRAM. As described above, the cell noise margin tends to decrease as the power supply voltage decreases, and the lower the threshold voltage _{Vth of the} driving transistor is, the lower the power supply voltage is. Regardless of the degree of difference depending on the manufacturing process, the threshold value of the transistor does not finish uniformly, and a distribution always occurs. Therefore, in order to pursue high speed in an integrated circuit with a low power supply voltage, if the threshold value of the drive transistor of the SRAM memory cell is designed and manufactured low, there is a high possibility that a memory cell that malfunctions due to no noise margin is generated.

  The SRAM memory cell composed of four NMOS transistors and two PMOS transistors as shown in FIG. 1 can be manufactured in the same manufacturing process as the logic circuit, and may be a memory integrated on the same substrate as the logic circuit. It is used. However, if a transistor of a logic circuit that lowers the threshold value is manufactured as it is as a transistor of an SRAM memory cell in order to ensure the operation speed, the SRAM may not operate electrically stably. In addition, it is well known that the threshold value of a transistor varies during the manufacturing process, so even if it is designed and manufactured as a memory cell threshold value that can maintain electrical stability on average, Since a transistor having a small threshold value is generated with a certain probability, it becomes difficult to electrically stabilize the memory cell.

  Therefore, the transistors in the SRAM cell are formed of transistors having the same configuration (the same gate length, gate width, gate oxide film thickness, and channel impurity amount) as the high threshold transistors in the logic circuit region 2. In that case, of course, the drive MOS composed of the NMOS of the memory cell in the SRAM, the transfer MOS is the same transistor as the high threshold transistor of the NMOS of the logic circuit, and the load MOS composed of the PMOS of the memory cell is It is composed of the same transistor as the high threshold transistor of the logic circuit PMOS. As a result, the transistors in the SRAM cell can be manufactured in the same process as the transistors in the logic circuit, and a semiconductor integrated circuit in which a high-speed, low-leakage current logic circuit and an electrically stable SRAM cell are integrated on the same substrate is minimized. It can be manufactured with limited manufacturing processes. The point that the manufacturing process can be simplified will be described later with reference to an embodiment of the manufacturing process.

  FIG. 3 shows a circuit diagram including peripheral circuits (decoder and word driver 31, precharge MOS 32, memory cell 33, and sense amplifier 34) of the SRAM. In the above description, it is described whether the transistor of the memory cell is configured as follows. Here, the relationship with the peripheral circuit is described. The SRAM circuit is a circuit in which high speed is particularly important. Therefore, the memory cell 33 is composed of a high threshold transistor used in the logic circuit region 2 for electrical stability as described above, and other circuit portions (decoder and word driver 31, pre-processor). The charging MOS 32 and the sense amplifier 34) are composed of transistors having the same configuration as the low threshold transistors used in the logic circuit region 2. Thereby, the high speed operation of the SRAM circuit is ensured. In particular, the sense amplifier 34 that requires high speed needs to be lower than the SRAM memory cell.

  FIG. 4 shows a circuit diagram of an SRAM memory cell array. In FIG. 4B and FIG. 4C, the range divided by the dotted line forms one bank. As shown in FIG. 4A, one memory cell 43 includes drive MOSs 48 and 49, load MOSs 52 and 53, and transfer MOSs 50 and 51. The word lines 55 are connected to the gates of the transfer MOSs 50 and 51, and the source / drain paths of the transfer MOSs 50 and 51 are connected between the drains of the drive MOSs 48 and 49 and the bit lines 41 and 42, respectively.

  Although FIG. 2 has already shown that the driving MOS of the SRAM memory cell affects the cell noise margin, the threshold value of the transfer MOS does not affect the cell noise margin. The magnitude and speed of the current Iread when reading from the memory cell depend on the current driving capability of the driving MOS rather than the transfer MOS. Therefore, an SRAM memory cell has differently configured transistors, but by reducing only the threshold value of the transfer MOS, it becomes possible to realize an SRAM memory cell having a large current value at the time of reading. .

  In other words, in order to mount the logic circuit and the SRAM memory at the same time, it is constituted by the same transistor as the threshold voltage of the driving MOS of the memory cell and the NMOS transistor of the high threshold value in the logic circuit, and the transfer MOS of the memory cell. An SRAM memory that is electrically stable and has a large read current Iread and is operated at high speed without complicating the manufacturing process by comprising the same transistor as the NMOS transistor of the threshold value and the low threshold value of the logic circuit. A cell can be produced. The load MOS affects the cell noise margin if not as much as the driving MOS, and in order to reduce leakage in the memory cell, it may be the same transistor as the high threshold PMOS transistor of the logic circuit.

  Thus, the operation of the memory cell is speeded up by lowering the threshold value of the transfer MOS. However, it is already known that when the number of memory cells connected to the bit lines 41 and 42 increases, another problem as described below occurs.

  In FIG. 4A, the memory cell connected to the word line 55-1 is accessed, and the word connected to the other word lines 55-2 to n (n: the number of memory cells connected to the bit line). The case where the memory cell connected to the line is not accessed is illustrated. In this case, the read current Iread flows through the memory cell 43-1 that has been accessed and the word line is "High". At this time, a leak current Ileak associated with the subthreshold current flows through the other unaccessed memory cells 43-2 to n connected to the same bit lines 41 and 42. Therefore, the total of the leakage currents is the maximum (n × Ileak). When this current becomes larger than Iread, that is, when the leakage current becomes larger than the signal current, reading of stored contents becomes impossible. This problem becomes prominent when the number n of memory cells connected to the bit line increases.

  Therefore, when the number of memory cells connected to the bit line increases, the bit lines are hierarchized using global bit lines as shown in FIG. 4B or 4C. In FIG. 4B, the global bit lines 46 and 47 are connected to the bit lines 41 and 42 via the switch MOSs 44 and 45, and the memory cells are divided for each bank. At this time, as the switch MOSs 44 and 45, those in which PMOS and NMOS source / drain paths are connected in parallel as described in JP-A-10-106269 can be used. The PMOS is turned on when a read operation is performed, and the NMOS is turned on when a write operation is performed. Here, the threshold values of the PMOS and NMOS of the switch MOS may be configured by the same high threshold transistors as the PMOSs 52 and 53 and the driving NMOSs 48 and 49 in the memory cell, respectively. In other words, the transistor may be the same as the high threshold transistor of the logic circuit.

  In FIG. 4C, a sense amplifier 54 is used instead of the switch MOSs 44 and 45. At this time, by configuring the sense amplifier 54 with the same transistor as the low threshold transistor in the logic circuit region 2, high-speed operation can be realized.

  The number of memory cells connected to the bit line can be reduced by hierarchization, and even when a large capacity SRAM is used, the problem of memory cell leakage current is avoided, and an electrically stable and high speed SRAM is realized. It becomes possible to do.

  Up to this point, it has been described that a circuit is configured using transistors having different threshold values, but a method for realizing the circuit has not been described. Therefore, a method for realizing this and a process for realizing a transistor having a plurality of threshold values in one integrated circuit will be described.

FIG. 5 shows the relationship between the threshold value V _th of the transistor and the gate oxide film thickness _Tox . Without increasing the number of channel implantations, the number of types of transistor thresholds can be increased. The threshold voltage V _th of the NMOS transistor is given by the following equation.

V _th = V _FB + 2Φ _FP + Q _B / C _o (1)
Where V _FB is the flat band voltage, Φ _FP is the difference in Fermi potential between the intrinsic semiconductor and the semiconductor containing impurities, Q _B is the charge amount per unit area of the depletion layer under the channel, and _Co is the gate oxide film The capacity per unit area is given by the following equation.

C _o = ε / T _ox (2)
ε is the dielectric constant of the gate insulating film, and _Tox is the gate oxide film thickness. Accordingly, as shown in FIG. 5, the threshold value _Vth increases as the gate oxide film thickness _Tox increases.

In FIG. 5, the first V _th 57-1 and the second V _th 57-2 have different dose amounts that are implanted into the channel by implantation. The first V _th 57-1 having a larger dose amount has a higher threshold value even if the gate oxide film thickness is the same as that of the second V _th 57-2 having a smaller dose amount. By utilizing this feature, by increasing the dose amount to the channel of the transistor a having a predetermined gate oxide film thickness, it is possible to obtain the MOS transistor b having the same gate oxide film pressure and a large threshold value. . For example, by configuring the logic circuit region 2 and the SRAM region 3 using the transistors a and b obtained by adjusting the dose amount, the logic circuit region 2 has a low leakage current and a high speed SRAM. In the region 3, an integrated circuit that is both electrically stable and high speed can be manufactured.

  Further, as can be seen from the relationship between the transistor c with respect to the transistor a or the transistor d with respect to the transistor b in FIG. 5, the threshold is increased by increasing the gate oxide film thickness even when the amount of impurities implanted into the channel is equal. The value voltage can be increased. Thus, by changing the channel dose or / and the gate oxide film thickness of the MOS transistor, a desired threshold voltage of the MOS transistor can be obtained. By utilizing this feature, it becomes possible to manufacture DRAM memory cells and interface circuits with a minimum number of steps. This will be shown in the following embodiment.

  FIG. 6 shows a second embodiment of the present invention, which is suitable for a memory array of DRAM cells. DRAM memory cells 62 and 63 are connected to the word line output from the word driver 61, and the charge stored in the capacity of the DRAM memory cell is read out by the sense amplifier 64 through the bit line.

A DRAM cell is composed of an NMOS transistor whose gate is connected to a word line and one capacitor. The capacity of the DRAM cell is written with a “0” potential when data is “0” and a power supply voltage V _cc when data is “1”. Writing is performed by turning on the gate of the NMOS transistor with the voltage of the word line, but even if writing is performed with the gate electrode of the NMOS transistor set to V _cc , only the voltage of (V _cc −V _th ) is written into the capacitor. . Therefore, by setting the voltage of the word line to (V _cc + V _th ), the voltage written to the capacitor can be set to V _cc . Since the voltage of the word line increases to (V _cc + V _th ), it is necessary to make the gate oxide film of the memory cell transistor of the DRAM thicker in order to ensure the gate breakdown voltage. Further, the threshold voltage of the transistor of the DRAM memory cell needs to be high so that the charge accumulated in the capacitor is not discharged by the leakage current of the transistor.

  Therefore, the property that the threshold voltage increases as the gate oxide film thickness of the MOS transistor shown in FIG. 5 increases is utilized. In the logic circuit region integrated on the same substrate, a low threshold transistor (transistor a in FIG. 5) is used as a transistor that requires high speed operation as described in the description of the logic circuit region in FIG. For transistors that are not required to operate at high speed, a high threshold transistor (transistor b in FIG. 5) is used to reduce leakage current. Transistors in the logic circuit area are formed of equal gate oxide film thickness transistors, both high and low threshold transistors. In order to realize two kinds of threshold values in the logic circuit, it is easiest to control the channel by changing the impurity amount of the channel. This is because, within the range adjusted by the current process, the change in threshold value when the gate length and gate width of the transistor are changed is smaller than that when the impurity amount is changed. Although the threshold value can be changed by changing the gate length and gate width of the transistor, these methods are easier than changing the oxide film thickness. When the oxide film thickness is changed, the handling of the step difference at the boundary where the oxide film thickness is different becomes a problem. Although it is not a problem to control the step over a certain area such as a memory cell, it is not easy to change the oxide film pressure at the transistor level. This is because the level difference causes disconnection of the wiring.

  Changing the oxide film thickness is not easy in the process, but due to the requirement of the characteristics described above, the NMOS in the DRAM memory cell has the same amount of impurities per unit area as the high threshold transistor of the logic circuit. A transistor having an oxide film thicker than that of the logic circuit is used. Even if the amount of impurities is equal to that of the low threshold transistor of the logic circuit, a threshold value higher than the low threshold value of the logic circuit is realized due to the difference in oxide film pressure. Therefore, a high threshold for reducing leakage current can be obtained by making the impurity amount equal to that of the high threshold transistor. (D in FIG. 5) It is possible to make the impurity amount equal in the logic circuit region and the memory region without increasing the number of masks, which is advantageous in manufacturing an integrated circuit. Of course, when the amount of impurities is equal, the range of variation that can naturally occur in manufacturing is included.

  A transistor having a configuration as necessary may be used for circuits other than the DRAM memory cell. Since the word driver 61 generates a high word line voltage, the gate oxide film pressure of the transistor is increased. On the other hand, in order to increase the operating speed, the threshold value should be kept low. Under these conditions, the transistor of the word driver 61 is a transistor (channel c in FIG. 5) having a channel implantation equal to the low threshold transistor of the logic circuit and a thick oxide film. Since a high voltage is not applied to the precharge MOS 65 and the sense amplifier 64, a transistor having the same gate oxide film thickness as that of the logic circuit transistor may be used. At this time, a low threshold transistor (transistor a in FIG. 5) is used when priority is given to the operation speed, and a high threshold transistor (transistor b in FIG. 5) is used when priority is given to a reduction in leakage current. That's fine.

  FIG. 7 shows a third embodiment of the present invention, which is suitable for a data input / output buffer circuit (IO). An area sandwiching the logic area 81 and the input / output circuit area 84 in FIG. 8 is shown. 71 is a data input / output pin, and 72 and 73 are output MOSs. Reference numeral 74 denotes an OE (output permission signal) generation circuit, and reference numeral 75 denotes a Dout (data) generation circuit. Data is output by the OE signal generated from the OE generation circuit. When the OE signal takes a logic level of “high”, the data signal output from the data generation circuit is output to the IO pin 71 via the level shifter and the output MOS.

In general, a data input / output buffer circuit that outputs data from the logic circuit area to the data input / output pin 71 is applied with a power supply voltage larger than the power supply voltage (V _dd ) of the logic circuit area. While the power supply voltage in the logic circuit area has been lowered as the oxide film thickness is reduced in accordance with the higher performance of the device, the data input / output buffer circuit has an applied power supply. This is because the voltage is determined by the standard. For example, in the generation of processes that can realize a gate length of 0.25um, the power supply voltage of the logic part is 1.8V to 2.5V, whereas the data input / output part is often 3.3V that can output a TTL level. .

  In this embodiment, the OE generation circuit and the Dout generation circuit are in the logic circuit area. Although a thin gate oxide film is used for this portion, as described above, a low threshold transistor and a high threshold transistor may be used separately. On the other hand, the level shifter unit is a circuit unit that converts a low-voltage amplitude signal into a high-voltage signal. Since a high voltage is applied to the transistor in this portion, a thick film is used to secure the gate withstand voltage. These transistors are used. Further, since a high voltage is also applied to the output MOS portion, a thick film transistor is used. Here, the high voltage is used for both the level shifter portion and the output MOS portion, so a thick high threshold transistor is used. However, the gate of the level shifter transistor receiving the output of the transistor in the logic circuit area has a low voltage amplitude. Therefore, it is necessary to use an exceptionally low threshold transistor. This is because the logic circuit region operates at a low voltage, so the output of the transistor in the logic circuit region is smaller than the voltage of the source / drain path of the level shifter transistor that receives the output. The channel of this transistor can be formed using the same amount of impurities as the low threshold value of the thin film.

  That is, in the present embodiment, the low threshold value of the thin film and the low threshold value of the thick film, the high threshold value of the thin film and the high threshold value of the thick film are formed by the same channel implantation, There is an effect that a high-speed output buffer can be formed with high reliability even at a high voltage without increasing the number of manufacturing steps.

  FIG. 8 shows a fifth embodiment of the present invention, in which a logic circuit area 81, an SRAM area 82, a DRAM area 83, and an input / output circuit area 84 are mounted on the same substrate. The table below shows the types of transistors in each region.

  As shown in the table, in the logic circuit region 81 and the SRAM region 82, a relatively low power supply voltage, for example, 1.5 V is set in order to use a high-performance transistor having a short gate length and a thin gate oxide film thickness. Transistors in the logic circuit area use low threshold transistors for about 10% of transistors in the logic circuit for speeding up, and the remaining about 90% of transistors in the logic circuit area have high threshold values for reducing leakage current. It has already been shown in Japanese Patent Application No. 9-359277 that a transistor may be used. In the transistors in the SRAM memory cell, the driving MOS transistor uses a high threshold transistor for electrical stability, and the transfer MOS transistor uses a low threshold value for speeding up. On the other hand, in the DRAM memory cell region, a large voltage is applied, so that the oxide film is thickened and the threshold voltage is further increased. Further, since a relatively high voltage is often applied to the input / output circuit according to the standard, the gate oxide film is thick and a high threshold value is used.

  In order to manufacture the above four circuit blocks without complicating the manufacturing process, the threshold values of the high threshold transistor of the logic circuit and the transistor of the SRAM cell are matched. In addition, the oxide film of the DRAM memory cell transistor and the input / output interface transistor can be made thick, and a channel can be formed using the same amount of impurities as the high and low threshold transistors used in the thin film transistor.

  FIG. 9 is a diagram showing a manufacturing process for realizing the present invention. In FIG. 9A, 90 is a semiconductor substrate, 91, 93, and 95 are P wells, 92, 94, and 96 are N wells, and 97 is an oxide region for element isolation. Here, 91 and 92 are NMOS and PMOS low threshold voltage transistors, 93 and 94 are NMOS and PMOS high threshold voltage transistors, and 95 and 96 are NMOS and PMOS transistors having thick oxide films, respectively. A transistor having a high threshold voltage is finally formed.

  As shown in this figure, in the integrated circuit, first, an element isolation region and a well are formed. In FIG. 9B, next, acceptor ions such as B, Al, Ga, and In are implanted into the P well regions 91, 93, and 95 using the resist 98 as a mask. Further, in FIG. 9C, ion implantation is performed only on the 93 and 95 P-well regions. As a result, the NMOSs in the P well regions 93 and 95 finally have a high threshold value.

  Next, in FIG. 9D, donors such as P, Sb and As are first implanted into the N well regions 92, 94 and 96 using the resist 98 as a mask. Further, in FIG. 9E, ion implantation is performed only on the N well regions 94 and 96. As a result, the N well regions 94 and 96 of the PMOS finally have a high threshold value in absolute value.

  Next, in FIG. 9 (f), a first gate oxidation is performed to form a gate oxide film 99. Further, when the nitrided oxide film 115 is formed and gate oxidation is performed using the nitrided oxide film 115 as a mask, the gate oxide film 99 becomes thick only on the right side. That is, the gate oxide films in the P well 95 and N well 96 portions are thick, and the gate oxide films in the other portions remain thin. Thereafter, a polysilicon layer 100 to be a gate electrode is formed in FIG. 9 (h), and gate electrodes 101, 102, 103, 104, 105, and 106 are formed by processing the polysilicon layer 100 in FIG. Next, n + type diffusion layers 108, 109, and 112 and p + type diffusion layers 110, 111, and 107 to be fixed to the well potential and serve as the drain or source electrode of the transistor are formed. Further, an interlayer insulating film is formed in FIG. 9 (k), and an electrode 114 in FIG. 10 (l) is formed to complete the transistor.

  According to the steps shown in the present embodiment, the thin film low threshold NMOS transistor 101 can be formed in the P well 91, and the thin film low threshold PMOS transistor 102 and P well can be formed in the N well 92. The thin film high threshold NMOS transistor 103 can be formed in the thin film 93, the P well 94 can be formed in the thin film high threshold PMOS transistor 104, and the P well 95 can be formed in the thick film high threshold NMOS. The transistor 105 and the P-well 96 can be a thick-film high-threshold PMOS transistor 106. As described above, the semiconductor integrated circuit can be constituted by the six types of transistors shown here. That is, the logic circuit is 101, 102, 103, 104 transistors, the SRAM driving MOS transistor is 103 transistor, the SRAM transfer MOS is 101 or, if necessary, 103 transistor, the DRAM cell transfer MOS is 105 transistor, The output MOS can be configured using 105 and 106 transistors. Although not shown here, a thick-film low-threshold transistor can be manufactured in the same process, but a thick-film low-threshold transistor may be used if necessary for the circuit. Needless to say.

  In this embodiment, the oxide film 99 has two types of thickness, and there are three types of threshold values, NMOS and PMOS. Having two kinds of threshold values in the logic circuit is inevitably necessary for obtaining high speed and low leakage current, and that there are two kinds of oxide film thickness, low voltage and high voltage can be applied simultaneously. There is inevitability in such an LSI. In the present invention, an optimal transistor can be provided for the operation of SRAM or DRAM memory cells without increasing the number of processes from the necessity of the manufacturing process. Therefore, a semiconductor having a memory array that operates at a low voltage without increasing the number of processes. There is an effect that an integrated circuit can be provided.

  FIG. 10 is a diagram showing the dependency of the threshold voltage Vth on the gate length Lg. In general, a MOS device has a phenomenon that a threshold voltage rapidly decreases as a gate length decreases. If this region is used, it is possible to obtain two kinds of threshold values such as d and e even if the amount of impurities in the channel is equal by changing the gate length. The ion implantation process shown in FIG. 9 (c) or FIG. 9 (e) can be omitted by changing the mask surface such as the length of the gate. That is, as shown in FIG. 11 (i), the gate electrodes 123 and 124 have a longer gate length than the gate electrodes 101 and 102, so that the threshold values of the 123 and 124 transistors are made higher than the threshold values of the 101 and 102 transistors. Can do. However, as described above, the threshold voltage changes greatly only in a certain limited region, so that the degree of freedom of control is lower than that of the implantation. In the sixth embodiment, there are two types of oxide films 99 and three types of threshold values, NMOS and PMOS. Having two kinds of threshold values in the logic circuit is inevitably necessary in order to obtain high speed and low leakage current. The present invention can provide an optimum transistor for the operation of an SRAM memory cell without increasing the number of steps from the necessity of the manufacturing process. Therefore, a semiconductor integrated circuit having a memory array that operates at a low voltage without increasing the number of steps. There is an effect that can provide.

  FIG. 12 shows conditions for realizing optimum threshold values when the logic circuit, SRAM, DRAM, and input / output circuit are realized on the same semiconductor substrate in the seventh embodiment of the present invention. . Of course, the process shown in FIG. In order to increase the speed of the transistors in the logic circuit, about 10% of the transistors in the logic circuit use transistors with a short channel length. On the other hand, in order to reduce leakage current, the remaining about 90% of transistors are transistors whose channel length is increased to a high threshold. In the transistor in the SRAM memory cell, the drive MOS transistor uses a high threshold transistor with a long channel length for electrical stability, and the transfer MOS transistor uses a channel length for speeding up. Use short transistors. On the other hand, in the memory cell region of the DRAM, a large voltage is applied, so that the oxide film is thickened and the gate length is further increased to raise the threshold value. In addition, since a relatively high voltage is often applied to the input / output circuit, a transistor having a high threshold value by using a thick gate oxide film and a long gate length is used.

  By doing so, it is possible to provide a transistor having an optimum threshold value for each circuit without increasing the manufacturing process of the channel implanter, and to provide a semiconductor integrated circuit having a high speed and a low leakage current.

  FIG. 13 is a diagram showing the structure of a transistor often used to alleviate the short channel effect and its threshold voltage characteristics. The transistor in the cross-sectional view of FIG. 13A is an example of an NMOS transistor using a P-type substrate. The source and drain electrodes are connected to the n + region, but a p-type region having a concentration higher than that of the p-type substrate is provided further inside the n− region for relaxing the electric field of the drain at the center side of each n + region. ing. The PMOS transistor can also be formed by providing a region having a lower impurity concentration than the drain electrode for relaxing the electric field of the drain on the center side of the P-type drain electrode and an n-type region having a concentration higher than that of the n-type substrate inside.

  FIG. 13B shows the dependency of the threshold voltage Vth of such a transistor on the gate length Lg. Here, Vth is a threshold voltage, and Vthleak is a value with a leak current, for example, a gate voltage with a gate width of 1 nA per um. The solid line and the dotted line correspond to the amount of impurity in the channel. Although not shown here, it is known that Vth and Vthleak exhibit substantially parallel characteristics in a transistor without a higher concentration p-type region of a conventional p-type substrate. However, the characteristics of the transistor having the structure of FIG. Vthleak decreases monotonously as the gate length decreases, whereas Vth increases once and then decreases. Further, when the impurity amount of the channel is changed, both are shifted almost in parallel as shown by the dotted line. It will be described below that a memory cell suitable for low voltage operation can be formed by utilizing this fact.

  FIG. 14 shows an eighth embodiment of the present invention, which shows that the characteristics of the memory cell of SRAM or DRAM can be further improved by using the characteristics of the MOS transistor of FIG. 13 compared with the embodiment shown in FIG. . In the figure, a, b, and f indicate that the transistors are configured with the conditions shown in FIG. The SRAM memory cell region 3 uses the transistor b shown in FIG. 13 as the driving MOS of the SRAM, thereby ensuring a certain level of Vth and electrical stability. The threshold has the same voltage as the high threshold in the logic circuit. The low threshold value in the logic circuit is composed of a transistor having the same gate length and the same oxide film thickness as the high threshold transistor and having a small amount of impurities in the channel.

  On the other hand, in the transfer MOS of the SRAM, as shown by f in FIG. 13, the channel length is reduced and the gate length is slightly increased. As a result, the threshold voltage can be lowered without changing the leakage current, and the characteristics of the SRAM can be improved without causing the problem caused by the leakage current of the SRAM transfer MOS as shown in FIG. It becomes possible. When the channel impurity amount takes a certain value using the transistor having the structure shown in FIG. 13A, two types of gate lengths may be selected in a region where Vthleak decreases even if the threshold value increases. . The threshold value of the transfer MOS is lower than the threshold value of the driving MOS, but a Vthleak corresponding to the leak current may be selected to be equal to or higher than the Vthleak of the driving MOS. In that case, the transfer MOS may be configured by the transistor f having the same channel impurity amount as the low threshold transistor of the logic circuit and the gate length being increased.

  Further, in the DRAM indicated by 141, a threshold voltage can be obtained without increasing leakage by using a transistor having the same channel impurity amount, the same gate length, and different gate oxide film thickness as the transistor shown in FIG. As a result, a DRAM memory cell having suitable characteristics can be realized.

  In general, there are two types of threshold voltage definitions. Some are obtained by extrapolation of a saturation current, and some are obtained from a gate voltage for allowing a constant current to flow in a region where the gate voltage is sufficiently low. The threshold voltage in the present application indicates the former, and Vthleak indicates the latter. Further, although it is written as MOSFET in the specification, a known MISFET may be used.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to the semiconductor integrated circuit manufacturing industry.

It is a schematic diagram of one embodiment of the present invention. It is explanatory drawing of the power supply voltage dependence of the noise margin of SRAM. It is a circuit diagram including peripheral circuits of SRAM. It is a circuit diagram of the array part of SRAM of the 2nd Embodiment of this invention. It is explanatory drawing which showed the relationship between a threshold value and a gate oxide film thickness. FIG. 10 is a circuit diagram of an example in which the present invention is applied to an array of DRAM cells in a third embodiment of the present invention. FIG. 10 is a circuit diagram in which the present invention is applied to an IO (data input / output buffer) in the fourth embodiment of the present invention. FIG. 10 is an explanatory diagram of an example in which a logic circuit, an SRAM array, a DRAM array, and an input / output circuit are mounted on the same substrate in the fifth embodiment of the present invention; (A)-(l) is explanatory drawing of the manufacturing process which implement | achieves the semiconductor integrated circuit which is embodiment of this invention. It is explanatory drawing of the gate length dependence of a threshold voltage. (A), (b), (d), (f)-(l) is another explanatory drawing of the manufacturing process which implement | achieves the semiconductor integrated circuit which is the 6th Embodiment of this invention. It is explanatory drawing of the semiconductor integrated circuit which is the 7th Embodiment of this invention. It is explanatory drawing of the structure of the transistor often used in recent years, and the characteristic of the threshold voltage. It is explanatory drawing of the semiconductor integrated circuit which is the 8th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Logic circuit 2 SRAM area 33 Memory cell 41, 42 Bit line 42, 47 Global bit line 62, 63 DRAM memory cell 72, 73 Output MOS
81 Logic circuit region 82 SRAM region 83 DRAM region 84 Input / output circuit region 90 Semiconductor substrates 91, 93, 95 P wells 92, 84, 96 N well 101 Thin film low threshold NMOS transistor 102 Thin film low threshold PMOS transistor 103 Thin film high threshold NMOS transistor 104 Thin film high threshold PMOS transistor 105 Thick film high threshold NMOS transistor 106 Thick film high threshold PMOS transistor 123 Thin film high threshold Value NMOS transistor 124 Thin film high threshold PMOS transistor

Claims (5)

A memory cell array in which a large number of DRAM memory cells each having a first transfer NMOS transistor and a first capacitor are integrated;
; And a input and output circuit having a first 1 PMOS transistor and the 2 NMOS transistors,
The gate oxide thicknesses of the first transfer NMOS transistor, the second NMOS transistor, and the first PMOS transistor are the same,
The amount of impurities in the channel of the first transfer NMOS transistor and the second NMOS transistor is the same,
A semiconductor integrated circuit, wherein a channel length of the first transfer NMOS transistor is larger than a channel length of the second NMOS transistor. 2. The semiconductor integrated circuit according to claim 1, wherein voltages supplied to the first transfer NMOS transistor and the second NMOS transistor are equal.   3. The semiconductor integrated circuit according to claim 1, wherein the input / output circuit is formed in a region surrounding a region where the memory cell array is formed. In a semiconductor integrated circuit including a logic circuit, a data input / output circuit, and a memory cell array in which a large number of dynamic memory cells each including one transfer MOS transistor and one capacitor are integrated,
The semiconductor integrated circuit is
Chi lifting a first thickness gate oxide film, and a NMOS transistor having a first threshold voltage,
An NMOS transistor having a gate oxide film of the first thickness and having a second threshold voltage greater than the first threshold voltage;
Chi lifting the first thickness gate oxide film, and a P MOS transistor having a third threshold voltage,
And P MOS transistors in which the having a first thickness gate oxide film, having a larger fourth threshold voltage of an absolute value in absolute value than the third threshold voltage,
An NMOS transistor having a fifth threshold voltage having a gate oxide film having a second thickness greater than the first thickness and having the same channel impurity amount as the NMOS transistor having the second threshold voltage; ,
It said having a second thickness gate oxide film, the impurity amount of the PMOS transistor and the channel with the fourth threshold voltage is the same, the PMOS transistor having a sixth threshold voltage,
The NMOS transistor having the second thickness, having the same channel impurity amount as the NMOS transistor having the fifth threshold voltage, and having a larger channel length than the NMOS transistor having the fifth threshold voltage. An NMOS transistor having a seventh threshold voltage ,
The aforementioned logic circuits, the NMOS transistor having a NMOS transistor and the second threshold voltage with a first threshold voltage, PMOS transistor and the fourth threshold voltage with the third threshold voltage PMOS transistor with
The aforementioned data input and output circuits, PMOS transistor having a NMOS transistor and the sixth threshold voltage with the fifth threshold voltage is used,
An NMOS transistor having the seventh threshold voltage is used as a transfer MOS transistor of the memory cell. A memory in which a logic circuit, a level shifter circuit for converting a low voltage signal voltage to a high voltage signal, a data input / output circuit, a dynamic MOS cell having one transfer MOS transistor and one capacitor are integrated. In a semiconductor integrated circuit comprising a cell array,
The semiconductor integrated circuit is
Chi lifting a first thickness gate oxide film, and a NMOS transistor having a first threshold voltage,
An NMOS transistor having a gate oxide film of the first thickness and having a second threshold voltage greater than the first threshold voltage;
Chi lifting the first thickness gate oxide film, and a P MOS transistor having a third threshold voltage,
And P MOS transistors in which the having a first thickness gate oxide film, having a larger fourth threshold voltage of an absolute value in absolute value than the third threshold voltage,
Has a gate oxide film of the first thickness thicker than the second thickness, the amount of impurities in the NMOS transistor and the channel is identical with the first threshold voltage, the NMOS transistor having a fifth threshold voltage ,
It said having a second thickness gate oxide film, the impurity amount of the NMOS transistor and the channel having the second threshold voltage is the same, and an NMOS transistor having a sixth threshold voltage,
Said having a second thickness gate oxide film, the impurity amount of the PMOS transistor and the channel with the third threshold voltage is the same, the PMOS transistor having a seventh threshold voltage,
Said having a second thickness gate oxide film, the impurity amount of the PMOS transistor and the channel with the fourth threshold voltage is the same, the PMOS transistor having the eighth threshold voltage,
The NMOS transistor having the second thickness, having the same channel impurity amount as the NMOS transistor having the sixth threshold voltage, and having a larger channel length than the NMOS transistor having the sixth threshold voltage. An NMOS transistor having a ninth threshold voltage ,
The aforementioned logic circuits, the NMOS transistor having a NMOS transistor and the second threshold voltage with a first threshold voltage, PMOS transistor and the fourth threshold voltage with the third threshold voltage PMOS transistor having a is used,
The aforementioned data input and output circuits, PMOS transistor having a NMOS transistor and the eighth threshold voltage with the sixth threshold voltage is used,
Of the above level shifter circuit, the MOS transistors for inputting a low voltage signal voltage is one lifting the fifth threshold voltage NMOS transistor is used,
An NMOS transistor having the ninth threshold voltage is used as a transfer MOS transistor of the memory cell.

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