JP4048597B2 - Optical disk device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an optical disk apparatus for driving an optical disk in which a groove wobble corresponding to a signal obtained by frequency-modulating biphase-modulated address information and a mark which is arranged in the groove wobble and has phase information is preformatted. About. Specifically, the data clock signal and the bi-phase bit oversampling clock signal frequency are in an integer ratio relationship, and the bi-phase bit oversampling clock signal is generated from the data clock signal by frequency division. The present invention relates to an optical disk apparatus in which address information can be demodulated only by having one PLL circuit in the system, and the configuration is extremely simple.
[0002]
[Prior art]
Conventionally, a magneto-optical disk has been proposed in which biphase-modulated address information ADM is frequency-modulated, the groove portion is wobbled in response to the modulated signal, and the modulated signal is recorded as groove wobble. Yes. In this case, as shown in FIG. 27, the groove wobble is, for example, 1 bit (biphase 1 bit) of the address information ADM, and when it is “1”, it becomes 4.25 waves (a sine wave of 4.25 period), When it is “0”, it is 3.75 waves (3.75 period sine wave). In this case, the amplitude of the groove wobble is constant regardless of the frequency of the modulated signal. For this reason, as shown in an enlarged view in FIG. 27, the inclination of the groove wobble corresponding to the junction of “1” and “0” of the address information ADM changes before and after the zero cross point.
[0003]
FIG. 28 shows a conventional configuration of a frequency demodulation circuit 300 for obtaining address information ADM from a groove wobble reproduction signal, that is, a wobble signal SWB. The frequency demodulating circuit 300 includes a direct current cut capacitor 301 and a comparator 302 that converts a wobble signal SWB having a direct current component cut with a threshold value = 0 into a pulse signal (binary signal) PWB.
[0004]
The frequency demodulating circuit 300 compares the phase of the voltage controlled oscillator 303a constituting a PLL (phase-locked loop) circuit 303 and the output signal of the voltage controlled oscillator 303a with the pulse signal PWB output from the comparator 302. And a low-pass filter 303c that extracts a low-frequency component of the phase error signal output from the phase comparator 303b and obtains a control signal for supply to the voltage controlled oscillator 303a.
[0005]
The frequency demodulation circuit 300 also includes a low-pass filter 304 for extracting a low-frequency component of the output signal of the low-pass filter 303c, a DC-cut capacitor 305, and a low-pass filter 304 with a DC component cut with a threshold value = 0. A comparator 306 for obtaining address information ADM from the output signal.
[0006]
The frequency demodulator circuit 300 also uses an edge detector 307 that detects rising and falling edges of the address information ADM output from the comparator 306 and an edge detection signal output from the edge detector 307 as a trigger signal. And a mono multivibrator 308 for obtaining a pulse signal having a width.
[0007]
Further, the frequency demodulating circuit 300 includes a voltage controlled oscillator 309a constituting the PLL circuit 309, and a phase comparator for performing phase comparison between the output signal of the voltage controlled oscillator 309a and the pulse signal output from the mono multivibrator 308. 309b, and a low-pass filter 309c that obtains a control signal for extracting a low-frequency component of the phase error signal output from the phase comparator 309b and supplying the low-frequency component to the voltage controlled oscillator 309a.
[0008]
The operation of the frequency demodulation circuit 300 shown in FIG. 28 will be described. The wobble signal SWB is supplied to the comparator 302 via the capacitor 301 and converted into a pulse signal (binary signal) PWB. As described above, the address information ADM after biphase modulation is frequency-modulated, and the modulated signal is recorded as a groove wobble on the magneto-optical disk. Therefore, the wobble signal SWB corresponds to 1 bit (biphase 1 bit) of the address information ADM, as shown in FIG. 29A, as in the signal after frequency modulation. When it is “0”, it has 3.75 waves. Therefore, the pulse signal PWB is obtained from the comparator 302 as shown in FIG. 29B.
[0009]
Since the frequency of the wobble signal SWB corresponding to “1” is different from the frequency of the wobble signal SWB corresponding to “0”, the output signal of the low-pass filter 303c constituting the PLL circuit 303 is as shown in FIG. 29C. Therefore, the address information ADM is obtained from the comparator 306 as shown in FIG. 29D. The edge of the address information ADM is detected by the edge detector 307, and the pulse signal output from the mono multivibrator 308 as a trigger signal is supplied to the PLL circuit 309 as a reference signal. Accordingly, a clock signal ACK synchronized with the address information ADM is obtained from the voltage controlled oscillator 309a constituting the PLL circuit 309 as shown in FIG. 29E.
[0010]
[Problems to be solved by the invention]
As described above, the frequency demodulating circuit 300 shown in FIG. 28 has two systems of PLL circuits 303 and 309 and has a complicated configuration.
[0011]
Therefore, an object of the present invention is to provide an optical disc apparatus capable of performing address information demodulation processing with a simple configuration having one PLL circuit in a data system.
[0012]
[Means for Solving the Problems]
In the optical disc apparatus according to the present invention, a groove wobble corresponding to a signal obtained by frequency modulating address information subjected to biphase modulation and a mark having phase information arranged in the groove wobble are preformatted and adjacent to each other. An optical disc apparatus for driving an optical disc in which the number of biphase bits between two marks is a (a is a natural number) and the number of channel bits between two adjacent marks is n (n is a natural number). A clock signal generating means for generating the first clock signal by multiplying the frequency of the reproduction signal of the clock mark by n, a wobble signal reproducing means for reproducing a wobble signal corresponding to the groove wobble from the optical disc, and a wobble signal Frequency demodulation means for obtaining address information by frequency demodulation It is. Then, the frequency demodulation means uses the oversampling value of the biphase bit as s (s is a natural number) clock, and uses the first clock signal supplied from the first clock signal generation means as 1 / M (M = n / (As), a clock signal generation unit that generates the second clock signal by dividing the frequency, a waveform shaping unit that obtains a binary signal by shaping the wobble signal, and a binary signal And a detector that obtains address information by performing processing using the second clock signal.
[0013]
In the present invention, the frequency demodulating means is configured so that the frequency of the first clock signal (data clock signal) and the second clock signal (bi-phase bit oversampling clock signal) are in an integer ratio relationship. The second clock signal is generated by dividing the clock signal. Then, address information is obtained by performing frequency demodulation on the wobble signal obtained by the wobble signal reproducing means using the second clock signal. As a result, the address information can be demodulated only by having one PLL circuit in the data system, and the configuration becomes extremely simple.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a magneto-optical disk device 10 as an embodiment.
[0015]
First, the magneto-optical disk 11 driven by the magneto-optical disk apparatus 10 will be described. FIG. 2 shows a sector layout of the magneto-optical disk 11. On the magneto-optical disk 11, tracks 0 to n are formed in a spiral shape from the inner peripheral side toward the outer peripheral side. The magneto-optical disk 11 is zoned, and each track in the inner zone X1 includes 0 to m1 sectors in the circumferential direction, and each track in the outer zone Z2 in the circumferential direction. 0 to m2 sectors are included.
[0016]
3A to 3D show a sector (wobble address frame) format. As shown in FIG. 3A, grooves 12G and lands 12L are alternately formed on the magneto-optical disk 11 in the radial direction, and data is recorded in either or both of the grooves 12G and lands 12L. The One side of the groove portion 12G is in a wobbling state according to, for example, the address information ADM after biphase modulation.
[0017]
In this case, the address information ADM is frequency modulated (FM), and the groove section 12G is wobbled so as to correspond to the modulated signal. That is, the modulated signal is recorded as a groove wobble. Since one side of the groove portion 12G is wobbled, as a result, one side of the land portion 12L is also wobbled according to the address information ADM.
[0018]
Note that the address information ADM is after bi-phase modulation, but the address information ADM is obtained by using the bi-phase modulation for the address information in order to prevent the generation of DC components as is well known ( DC free). Here, 1 bit of the address information before performing biphase modulation corresponds to 2 bits of biphase.
[0019]
As shown in FIG. 5, the groove wobble is 4 waves (4 sine waves) when “1” and 3 waves per 1 bit (biphase 1 bit) of the address information ADM and “0”. (3 period sine wave). In addition, the amplitude of the groove wobble is changed in accordance with the frequency of the modulated signal, and corresponds to the junction of “1” and “0” of the address information ADM as shown in an enlarged view in FIG. The inclination of the groove wobble before and after the zero cross point is prevented from changing.
[0020]
Here, the groove wobble during one sector (one wobble address frame) is address information (data) before bi-phase modulation, and has 42-bit data, for example. As shown in FIG. 4, the 42-bit data includes 4-bit synchronization signal data, 24-bit frame address data, and a 14-bit CRC (cyclic redundancy check) code.
[0021]
Further, as shown in FIG. 3B, one sector is composed of, for example, 42 segments. As shown in FIG. 3A, a clock mark CM is multiplexed into a groove wobble and preformatted at the boundary position of each segment. As shown in FIG. 3C, a 60-byte data area is provided in each segment, and a 6-byte fixed pattern area is provided corresponding to the boundary position of each segment. At the time of data writing, as described later, NRZI data is recorded in the data area, but a fixed pattern signal having a length of 2T synchronized with the NRZI data is recorded in the fixed pattern area (T is a data bit interval). . This fixed pattern signal is used to control the phase of the data clock signal when reading data.
[0022]
Here, in the magneto-optical disk 11, one sector is composed of 42 segments, and the clock mark CM is preformatted at the boundary position of each segment, so the number of biphase bits a between adjacent clock marks is 2. Become. In the magneto-optical disk 11, a 60-byte data area is provided in each segment, and a 6-byte fixed pattern area is provided corresponding to the boundary position of each segment. The number of bits n is 528.
[0023]
Returning to FIG. 1, the disk device 10 has a spindle motor 13 for rotationally driving the magneto-optical disk 11. The magneto-optical disk 11 is rotationally driven at a constant angular velocity during recording and reproduction. A frequency generator 14 for detecting the rotation speed is attached to the rotation shaft of the spindle motor 13.
[0024]
Further, the disk device 10 includes an external magnetic field generating magnetic head 15, a magnetic head driver 16 for controlling the magnetic field generation of the magnetic head 15, and an optical head 17 including a semiconductor laser, an objective lens, a photodetector, and the like. And a laser driver 18 for controlling the light emission of the semiconductor laser of the optical head 17. The magnetic head 15 and the optical head 17 are arranged to face each other so as to sandwich the magneto-optical disk 11.
[0025]
The laser driver 18 is supplied with a laser power control signal SPC from a servo controller 41, which will be described later, via a D / A converter 19, and the power of the laser beam output from the semiconductor laser of the optical head 17 is the recording power PW during recording. Therefore, during reproduction, the reproduction power PR is controlled to be lower than the recording power PW.
[0026]
At the time of data writing (recording), the recording data Dr and the fixed pattern signal SFP are supplied to the magnetic head driver 16 as described later, and a magnetic field corresponding to the recording data Dr and the fixed pattern signal SFP is generated from the magnetic head 15. Recording data Dr is recorded in the data area of the magneto-optical disk 11 in cooperation with a laser beam (laser light) from the optical head 17, and a fixed pattern area corresponding to the data area in which the recording data Dr is recorded. The fixed pattern signal SFP is recorded in
[0027]
FIG. 6 shows the configuration of the optical system of the optical head 17. The optical head 17 includes a semiconductor laser 31 for obtaining a laser beam LB, a collimator lens 32 for shaping the laser beam LB output from the semiconductor laser 31 into parallel light from divergent light, and the laser beam as transmitted light. A beam splitter 33 for separating the reflected light into two, a reflection mirror 34 for changing the optical path of the laser beam, and an objective for irradiating the recording surface (recording film) of the magneto-optical disk 11 with the laser beam LB. And a lens 35.
[0028]
Further, the optical head 17 is a Wollaston prism (polarization plane detection prism) 36 for separating the laser beam reflected by the reflecting surface 33b of the beam splitter 33 and emitted to the outside into three laser beams according to the difference in polarization direction. A condensing lens 37 for condensing three laser beams (parallel light) output from the Wollaston prism 36, and a photodetector 39 irradiated with the three laser beams emitted from the condensing lens 37. And a multi-lens 38 disposed between the condenser lens 37 and the photodetector 39.
[0029]
The multi lens 38 is configured by a combination of a concave lens and a cylindrical lens. The cylindrical lens is used in order to obtain a focus error signal by a known astigmatism method. As shown in FIG. 7, the photodetector 39 includes a four-divided photodiode portion 39m and two photodiode portions 39i and 39j.
[0030]
FIG. 8 shows a configuration example of the Wollaston prism 36. The prism 36 is constituted by joining right-angle prisms 36a and 36b made of a uniaxial crystal, for example, quartz. In this case, the optical axis Axb of the prism 36b is set to be inclined by 45 ° with respect to the optical axis Axa of the prism 36a.
[0031]
In such a configuration, the quartz crystal has two different refractive indices relative to the plane of polarization of the incident light. Therefore, when linearly polarized light La having a polarization plane Ppo inclined by 45 ° with respect to the optical axis Axa is incident on the prism 36a, the prism 36a has a polarization component having a polarization plane perpendicular to the optical axis Axa as shown in FIG. It is separated into a polarization component Lb2 having a polarization plane parallel to Lb1 and the optical axis Axa. Further, in the prism 36b, the polarization component Lb1 is separated into a polarization component Lc1 having a polarization plane parallel to the optical axis Axb and a polarization component Lc2 having a polarization plane perpendicular to the optical axis Axb, and the polarization component Lb2 is separated from the optical axis Axb. Are separated into a polarization component Lc3 having a polarization plane parallel to and a polarization component Lc4 having a polarization plane perpendicular to the optical axis Axb.
[0032]
Here, the polarization components Lc1 and Lc2 have a polarization plane perpendicular to the optical axis Axa of the prism 36a, and the amount of each light is ¼ of the linearly polarized light La. On the other hand, the polarization components Lc3 and Lc4 have a polarization plane parallel to the optical axis Axa of the prism 36a, and the amount of each light is ¼ of the linearly polarized light La. The outgoing angles of the polarization components Lc2 and Lc3 from the prism 36b are equal, and as a result, the three laser beams Li, Lm, and Lj are obtained separately from the prism 36b and hence the Wollaston prism 36.
[0033]
The operation of the optical system of the optical head 17 shown in FIG. 6 will be described. The laser beam LB as diverging light emitted from the semiconductor laser 31 is shaped into parallel light by the collimator lens 32 and is incident on the beam splitter 33. The laser beam that has passed through the multilayer film 33 a of the beam splitter 33 has its optical path changed at right angles by the reflection mirror 34, and is irradiated onto the recording surface of the magneto-optical disk 11 through the objective lens 35.
[0034]
The laser beam reflected by the recording surface of the magneto-optical disk 11 is incident on the beam splitter 33 via the objective lens 35 and the reflection mirror 34. The laser beam Lr reflected by the multilayer film 33 a of the beam splitter 33 is further reflected by the reflecting surface 33 b of the beam splitter 33, is emitted to the outside, and enters the Wollaston prism 36.
[0035]
As described above, the laser beam Lr related to the reflection on the recording surface of the magneto-optical disk 11 is incident on the Wollaston prism 36, but the polarization plane rotation (Kerr rotation) on the recording surface of the magneto-optical disk 11 is not described above. ) Is set to be inclined by 45 ° with respect to the optical axis Axa (see the relationship between the polarization plane Ppo of the linearly polarized light La and the optical axis Axa in FIG. 8). As a result, the three laser beams Li, Lm, and Lj are obtained by separating the laser beam Lr from the laser beam Lr by the Wollaston prism 36 as in the case where the linearly polarized light La described above is incident.
[0036]
Here, the plane of polarization of the laser beam Lr is slightly rotated clockwise or counterclockwise according to the magnetization direction of the recording film of the magneto-optical disk 11, and the recording film of the magneto-optical disk 11 has a light quantity of the laser beams Li and Lj. A magnitude relationship occurs according to the direction of magnetization. Therefore, a reproduction signal corresponding to magneto-optically recorded data (signal) can be obtained by detecting the light amounts of the laser beams Li and Lj and taking the difference therebetween. Note that the amount of light of the laser beam Lm is constant even if the polarization plane of the laser beam Lr rotates.
[0037]
As described above, the three laser beams Li, Lm, and Lj emitted from the Wollaston prism 36 are incident on the photodetector 39 via the condenser lens 37 and the multi lens 38. As shown in FIG. 7, spots SPi, SPm, and SPj by laser beams Li, Lm, and Lj are formed in the photodiode portions 39i, 39m, and 39j that constitute the photodetector 39, respectively.
[0038]
In this case, the detection signals of the four photodiodes Da to Dd constituting the four-divided photodiode portion 39m are Sa to Sd, respectively, and the detection signals of the photodiodes Di and Dj constituting the photodiode portions 39i and 39j are Si, When Sj is set, an amplification circuit unit (not shown) of the optical head 17 performs the following calculation to generate a reproduction signal SMO, an astigmatism focus error signal SFE, and a push-pull signal SPP from the recording area. The
[0039]
SMO = Si-Sj
SFE = (Sa + Sc)-(Sb + Sd)
SPP = (Sa + Sb) − (Sc + Sd)
[0040]
Returning to FIG. 1, the disk device 10 has a servo controller 41 having a central processing unit (CPU). A focus error signal SFE generated by the optical head 17 is supplied to the servo controller 41 via the A / D converter 42. The push-pull signal SPP generated by the optical head 17 includes a tracking error signal STE by the push-pull method, a wobble signal (FM signal) SWB corresponding to the groove wobble of the magneto-optical disk 11, and a clock of the magneto-optical disk 11. And a clock mark reproduction signal SCM corresponding to the mark CM. Here, the signals STE, SWB, and SCM are in different frequency bands. Therefore, the signals STE, SWB, and SCM can be extracted from the push-pull signal SPP by using a low-pass filter and a band-pass filter, respectively.
[0041]
A tracking error signal STE extracted by the low pass filter 43 from the push-pull signal SPP is supplied to the servo controller 41 via the A / D converter 44. The servo controller 41 is further supplied with a frequency signal SFG output from the frequency generator 14 described above.
[0042]
The operation of the servo controller 41 is controlled by a system controller 51 described later. The servo controller 41 controls a tracking coil, a focus coil, and an actuator 45 including a linear motor for moving the optical head 17 in the radial direction to perform tracking and focusing servo, and the radius of the optical head 17. Movement in the direction (radial direction) is controlled. Further, the spindle motor 13 is controlled by the servo controller 41 so that the magneto-optical disk 11 rotates at a constant angular velocity during recording and reproduction as described above.
[0043]
The disk device 10 also includes a system controller 51 having a CPU, a data buffer 52, and a SCSI (Small Computer System Interface) 53 for transmitting and receiving data and commands to and from the host computer. The system controller 51 is for controlling the entire system.
[0044]
Further, the disk device 10 adds an error correction code to the write data supplied from the host computer via the SCSI 53, and also performs ECC (error) to perform error correction on the output data of the data demodulator 59 described later. correction code) circuit 54 and write data to which error correction code is added by the ECC circuit 54 are converted into NRZI (Non Return to Zero Inverted) data to obtain the recording data Dr, and the fixed pattern signal SFP described above is generated. And a data modulator 55.
[0045]
The disk device 10 also includes an equalizer circuit 56 for compensating the frequency characteristics of the reproduction signal SMO generated by the optical head 17, and an A / D converter 57 for converting the output signal of the equalizer circuit 56 into a digital signal. A data discriminator 58 that digitally performs data discrimination processing on the output data of the A / D converter 57 to obtain reproduction data Dp, and NRZI for the reproduction data Dp output from the data discriminator 58. And a data demodulator 59 for obtaining read data by performing inverse conversion. The data discriminator 58 is composed of a binarization circuit, a Viterbi decoder, and the like.
[0046]
The disk device 10 includes an ADIP (Address In Pre-groove) decoder 60 that obtains a frame synchronization signal FD and frame address data FAD from a wobble signal SWB included in a push-pull signal SPP generated by the optical head 17, and a push-pull. A data clock for obtaining a pulse signal PCM and a data clock signal DCK indicating the timing of the zero cross point of the reproduction signal SCM from the clock mark reproduction signal SCM included in the signal SPP and the reproduction signal SMO corresponding to the fixed pattern area of the magneto-optical disk 11 A timing generator that generates a timing signal necessary for each part of the system, such as a read gate signal and a write gate signal, using the regenerator 70 and the frame synchronization signal FD, the frame address data FAD, the pulse signal PCM, and the data clock signal DCK With 90 The The frame address data FAD is also supplied to the servo controller 41, and the data clock signal DCK is supplied to the A / D converter 57 as a sampling clock.
[0047]
FIG. 10 shows the configuration of the ADIP decoder 60. The ADIP decoder 60 includes a band-pass filter 61 for extracting the wobble signal SWB from the push-pull signal SPP, a DC cut capacitor 62, and sets the wobble signal SWB to a pulse signal (binary signal) PWB with threshold = 0. And a comparator 63 for conversion.
[0048]
The ADIP decoder 60 is output from a voltage controlled oscillator 64a constituting the PLL circuit 64, a frequency divider 64b that divides the clock signal CK24 output from the voltage controlled oscillator 64a by 1/24, and a comparator 63. The phase comparator 64c for comparing the phase of the pulse signal PWB and the output signal of the frequency divider 64b, and the low-frequency component of the phase error signal output from the phase comparator 64c are extracted to the voltage controlled oscillator 64a. A low-pass filter 64d for obtaining a control signal to be supplied.
[0049]
The ADIP decoder 60 performs demodulation processing using the clock signal CK24 output from the voltage controlled oscillator 64a on the pulse signal PWB output from the comparator 63 to obtain address information ADM. A detection circuit 67 for obtaining a synchronized clock signal ACK, and a frame synchronization by performing synchronization detection, biphase demodulation, error detection, etc. on the address information ADM output from the detection circuit 67 using the clock signal ACK. An address converter 68 for obtaining a signal FD and frame address data FAD.
[0050]
Next, the operation of the ADIP decoder 60 shown in FIG. 10 will be described. Push-pull signal S _PP Thus, the band pass filter 61 extracts the wobble signal SWB. The wobble signal SWB is supplied to the comparator 63 via the capacitor 62 and converted into a pulse signal PWB. As described above, on the magneto-optical disk 11, the address information ADM after biphase modulation is frequency-modulated, and the modulated signal is recorded as a groove wobble. Therefore, the wobble signal SWB, like the signal after frequency modulation, has 4 waves when it is “1” corresponding to 1 bit (biphase 1 bit) of the address information ADM, as shown in FIG. 11A. , “0” has three waves. Therefore, a pulse signal (binary signal) PWB is obtained from the comparator 63 as shown in FIG. 11B. Note that the amplitude of the wobble signal SWB is proportional to the amplitude of the groove wobble of the magneto-optical disk 11.
[0051]
When the frequency of the wobble signal SWB corresponding to the bit “1” is fa and the frequency of the wobble signal SWB corresponding to the bit “0” is fb, the oscillation frequency of the voltage controlled oscillator 64a is a common multiple of fa and fb. It is set to change in the vicinity of the frequency (= 6fa = 8fb). Therefore, from the voltage controlled oscillator 64a, as shown in FIG. 11C, a clock signal CK24 having a frequency of fc = 6fa = 8fb, and thus 24 times the bit frequency of the biphase, and synchronized with the pulse signal PWB is obtained. . Although not described above, the clock signal CK24 is a clock signal for oversampling of the biphase bit, and the oversampling value s of the biphase bit is 24 clocks.
[0052]
Using this clock signal CK24 as a reference, the pulse signal PWB (for one cycle) corresponding to biphase 1 bit = “1” is 6T composed of a value “1” for three clocks and a value “0” for three clocks. The pulse signal PWB corresponding to the biphase 1 bit = “0” has an 8T pattern including a value “1” for 4 clocks and a value “0” for 4 clocks.
[0053]
When detecting a continuous 8T pattern from the pulse signal PWB, the detection circuit 67 outputs “0” in the next biphase 1-bit period in synchronization with the clock signal ACK (shown in FIG. 11D), while the pulse signal When detecting a continuous 6T pattern from the PWB, “1” is output in the next biphase 1-bit period in synchronization with the clock signal ACK.
[0054]
That is, the detection circuit 67 performs demodulation processing on the pulse signal PWB, and the detection circuit 67 outputs the address information ADM corresponding to the groove wobble in synchronization with the clock signal ACK. (Illustrated in FIG. 11E). FIG. 11F shows the reproduction signal SCM of the clock mark CM.
[0055]
This address information ADM is supplied to the address converter 68. The address converter 68 performs synchronization detection, biphase demodulation, error detection, and the like on the address information ADM to obtain a frame synchronization signal FD and frame address data FAD. As a result, the address converter 68 outputs frame address data FAD obtained from the address information ADM together with the frame synchronization signal FD.
[0056]
FIG. 12 shows the configuration of the detection circuit 67. The detection circuit 67 uses the clock signal CK24 to detect a break (change) between the biphase bits “1” and “0” by pattern determination of the pulse signal PWB, and generates the clock signal CKBP having a biphase bit period. It has a biphase period detection circuit 102 for obtaining, and a 5-bit counter 103 to which the clock signal CKBP is supplied as a reset signal and the clock signal CK24 is supplied as a clock signal for counting.
[0057]
The detection circuit 67 generates a window pulse PW0 for the biphase bit “0” and a window pulse PW1 for the biphase bit “1” based on the count output of the 5-bit counter 103. A pulse generation circuit 104 is included. Here, the window pulse PW0 is a pulse output corresponding to the rising edge and falling edge of the regular 8T pattern pulse signal PWB, and six pulses are generated in the biphase 1-bit period. . Similarly, the window pulse PW1 is a pulse output corresponding to the rising edge and the falling edge of the pulse signal PWB of the regular 6T pattern, and 8 pulses are generated in the biphase 1-bit period. .
[0058]
The detection circuit 67 includes an edge detection circuit 110 that detects the rising edge and the falling edge of the pulse signal PWB using the clock signal CK24 and outputs an edge detection pulse Pe.
[0059]
FIG. 13 shows the configuration of the edge detection circuit 110. The edge detection circuit 110 includes two-stage D flip-flop circuits 111 and 112 that operate in response to a clock signal CK24, and an exclusive OR circuit 113. The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 111, and a signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 111 is supplied to the data terminal D of the D flip-flop circuit 112. Then, the signal obtained at the non-inverting output terminal Q of the D flip-flop circuits 111 and 112 is supplied to the input side of the exclusive OR circuit 113, and the edge detection pulse Pe is output from the output side of the exclusive OR circuit 113. .
[0060]
Returning to FIG. 12, the detection circuit 67 gates the edge detection pulse Pe using the window pulses PW0 and PW1 generated by the window pulse generation circuit 104 as gate signals, and functions as a coincidence detection circuit 121. 122, edge pulse counters 123 and 124 that count edge detection pulses Pe gated by AND gates 121 and 122, respectively, and count values x of edge pulse counters 123 and 124 counted in the previous biphase 1-bit period , Y are compared, and in the next biphase 1-bit period, the comparator circuit 125 outputs address information ADM based on the comparison result.
[0061]
Here, each of the edge pulse counters 123 and 124 is supplied with a clock signal CKBP having a bi-phase bit period as a reset signal. The clock signal CKBP is also supplied to the comparison circuit 125 as a timing signal. The comparison circuit 125 outputs bit “0” as address information ADM when x> y, and outputs bit “1” as address information ADM when x <y.
[0062]
The detection circuit 67 has a frequency divider 126 that divides the clock signal CK24 by 1/24 and outputs the clock signal ACK (see FIG. 11D) synchronized with the address information ADM by referring to the clock signal CKBP. is doing.
[0063]
The operation of the detection circuit 67 shown in FIG. 12 will be described. A pulse signal PWB and a clock signal CK24 are supplied to the biphase cycle detection circuit 102, and a clock signal CKBP having a biphase bit cycle is obtained. The 5-bit counter 103 is supplied with the clock signal CKBP as a reset signal and the clock signal CK24 as a clock signal for counting. As a result, the 5-bit counter 103 is first reset in each bit period of the biphase, and after that, the count operation is performed by the clock signal CK24, and “0” to “23” is counted in the decimal system. It becomes.
[0064]
The count output of the 5-bit counter 103 is supplied to the window pulse generation circuit 104. Based on the count output of the 5-bit counter 103, the window pulse PW0 for the biphase bit “0” and the biphase bit “1” are output. Window pulse PW1 is generated and supplied to the AND gates 121 and 122 as gate signals, respectively.
[0065]
On the other hand, the pulse signal PWB and the clock signal CK24 are supplied to the edge detection circuit 110, the rising edge and the falling edge of the pulse signal PWB are detected, and the edge detection pulse Pe is obtained. , 122. The edge detection pulses Pe gated by the AND gates 121 and 122 are supplied to the edge pulse counters 123 and 124, respectively, and are counted for each biphase 1-bit period.
[0066]
Then, the comparison circuit 125 compares the count values x and y of the edge pulse counters 123 and 124 counted in the previous biphase 1 bit period, and in the next biphase 1 bit period, addresses based on the comparison result are compared. Information ADM is output.
[0067]
For example, when the wobble signal SWB in a certain biphase 1-bit period corresponds to the biphase bit “0” as shown in FIG. 14A, the pulse signal (binary signal) PWB has an 8T pattern as shown in FIG. 14B. Are continuous three times, and an edge detection pulse Pe is obtained as shown in FIGS. 14D and 14D ′. FIG. 14C shows the clock signal CK24.
[0068]
Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 14E, the gate output P00 as the coincidence pulse supplied to the edge pulse counter 123 is as shown in FIG. 14F. x = 6. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 14E ', the gate output P01 as the coincidence pulse supplied to the edge pulse counter 124 is shown in FIG. 14F'. And y = 2. Therefore, bit “0” is output from the comparison circuit 125 as the address information ADM in the next biphase 1-bit period.
[0069]
Further, when the wobble signal SWB in a certain biphase 1 bit period corresponds to the biphase bit “1” as shown in FIG. 15A, the pulse signal (binary signal) PWB has a 6T pattern as shown in FIG. 15B. Are continuous four times, and an edge detection pulse Pe is obtained as shown in FIGS. 15D and 15D ′. FIG. 15C shows the clock signal CK24.
[0070]
Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 15E, the gate output P00 supplied to the edge pulse counter 123 is as shown in FIG. 15F, and x = 2. Become. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 15E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. 8 Therefore, bit “1” is output from the comparison circuit 125 as the address information ADM in the next biphase 1-bit period.
[0071]
Next, a case where the magneto-optical disk 11 has a defect such as a scratch and the wobble signal SWB is deformed will be described.
[0072]
For example, when the wobble signal SWB in a certain biphase 1 bit period corresponds to the biphase bit “0” and there is a deformation due to a defect as shown in FIG. 16A, the pulse signal (binary signal) PWB is 16B and an edge detection pulse Pe is obtained as shown in FIGS. 16D and 16D ′. FIG. 16C shows the clock signal CK24.
[0073]
Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 16E, the gate output P00 supplied to the edge pulse counter 123 is as shown in FIG. 16F, and x = 6. Become. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 16E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. 3 Therefore, bit “0” is output from the comparison circuit 125 as the address information ADM in the next biphase 1-bit period.
[0074]
When the wobble signal SWB in a certain biphase 1 bit period corresponds to the biphase bit “1” and there is a deformation due to a defect as shown in FIG. 17A, the pulse signal (binary signal) PWB is The edge detection pulse Pe is obtained as shown in FIGS. 17D and 17D ′. FIG. 17C shows the clock signal CK24.
[0075]
Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 17E, the gate signal P00 supplied to the edge pulse counter 123 is as shown in FIG. 17F, and x = 1. Become. On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 17E ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. 6 Therefore, bit “1” is output from the comparison circuit 125 as the address information ADM in the next biphase 1-bit period.
[0076]
As described above, in the detection circuit 67 shown in FIG. 12, even when the wobble signal SWB is deformed due to the defect as shown in FIGS. 16A and 17A, it is the same as when the wobble signal SWB is not deformed due to the defect. In addition, the address information ADM can be obtained satisfactorily.
[0077]
By the way, when there is a deformation due to a defect as shown in FIGS. 16A and 17A, the difference between x and y becomes large as described above. Therefore, the bit “0” or the bit “1” depends only on the magnitude of x and y. ", The address information ADM can be obtained correctly. However, when there is not much difference between x and y, it may be difficult to determine whether the bit is “0” or “1”.
[0078]
For example, when the wobble signal SWB in a certain biphase 1-bit period is modified as shown in FIG. 18A, the pulse signal (binary signal) PWB becomes as shown in FIG. 18B, and FIG. 18D (= FIG. 18E = As shown in FIG. 18E ′), an edge detection pulse Pe is obtained. FIG. 18C shows the clock signal CK24.
[0079]
Since the window pulse PW0 supplied to the AND gate 121 is formed as shown in FIG. 18F, the gate output P00 supplied to the edge pulse counter 123 is as shown in FIG. 18G, and x = 4. Become. Assuming bit “0”, x = 6.
[0080]
On the other hand, since the window pulse PW1 supplied to the AND gate 122 is formed as shown in FIG. 18F ', the gate output P01 supplied to the edge pulse counter 124 becomes as shown in FIG. 6 If bit “1” is assumed, then y = 8.
[0081]
Therefore, in the case of a simple comparison, x <y, so that it is determined that the bit is “1”. However, it cannot be immediately determined that the bit is really “1”. This is because each has the same error in that both counts are two shorts compared to the numbers that should be detected.
[0082]
Therefore, more accurate determination can be made by adding more conditions to the window and separating and detecting the rising edge and the falling edge.
[0083]
FIG. 19 shows a detection circuit 67A having another configuration, in which rising edges and falling edges are detected separately. In FIG. 19, parts corresponding to those in FIG.
[0084]
The detection circuit 67A uses the clock signal CK24 to detect a break (change) between the biphase bits “1” and “0” by pattern discrimination of the pulse signal PWB, and generates the clock signal CKBP having a biphase bit period. It has a biphase period detection circuit 102 for obtaining, and a 5-bit counter 103 to which the clock signal CKBP is supplied as a reset signal and the clock signal CK24 is supplied as a clock signal for counting.
[0085]
In addition, based on the count output of the 5-bit counter 103, the detection circuit 67A generates the window pulses PW0u and PW0d for the biphase bit “0” and the window pulses PW1u and PW1d for the biphase bit “1”. A window pulse generation circuit 104A for generation is provided.
[0086]
Here, the window pulse PW0u is a pulse output corresponding to the rising edge of the regular 8T pattern pulse signal PWB, and three pulses are generated in the biphase 1-bit period. The window pulse PW0d is a pulse output corresponding to the falling edge of the regular 8T pattern pulse signal PWB, and three pulses are generated in the biphase 1-bit period.
[0087]
The window pulse PW1u is a pulse output corresponding to the rising edge of the regular 6T pattern pulse signal PWB, and four pulses are generated in the biphase 1-bit period. The window pulse PW1d is a pulse output corresponding to the falling edge of the regular 6T pattern pulse signal PWB, and four pulses are generated in the biphase 1-bit period.
[0088]
The detection circuit 67A uses the clock signal CK24 to detect the rising edge of the pulse signal PWB and outputs the edge detection pulse Peu. Similarly, the detection circuit 67A uses the clock signal CK24 to generate a pulse. And an edge detection circuit 140 that detects a falling edge of the signal PWB and outputs an edge detection pulse Ped.
[0089]
FIG. 20 shows the configuration of the rising edge detection circuit 130. The edge detection circuit 130 includes two-stage D flip-flop circuits 131 and 132 that operate on the clock signal CK24, and an AND circuit 133. The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 131, and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 131 is supplied to the data terminal D of the D flip-flop circuit 132. The signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 131 and the signal obtained at the inverting output terminal Q bar of the D flip-flop circuit 132 are supplied to the input side of the AND circuit 133. An edge detection pulse Peu is output from the output side.
[0090]
FIG. 21 shows the configuration of the falling edge detection circuit 140. The edge detection circuit 140 includes two-stage D flip-flop circuits 141 and 142 that operate with a clock signal CK24, and an AND circuit 143. The pulse signal PWB is supplied to the data terminal D of the D flip-flop circuit 141, and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 141 is supplied to the data terminal D of the D flip-flop circuit 142. The signal obtained at the inverting output terminal Q bar of the D flip-flop circuit 141 and the signal obtained at the non-inverting output terminal Q of the D flip-flop circuit 142 are supplied to the input side of the AND circuit 143. An edge detection pulse Ped is output from the output side.
[0091]
Referring back to FIG. 19, the detection circuit 67A functions as a coincidence detection circuit by gating the edge detection pulses Peu and Ped using the window pulses PW0u and PW0d generated by the window pulse generation circuit 104A as gate signals. AND gates 151 and 152, and gate pulses PW1u and PW1d generated by the window pulse generation circuit 104A are used as gate signals to gate edge detection pulses Peu and Ped, respectively, and AND gates 153 and 154 functioning as coincidence detection circuits have.
[0092]
The detection circuit 67A also includes edge pulse counters 155 and 156 that count edge detection pulses Peu and Ped gated by AND gates 151 and 152, and edge detection pulses Peu and Ped gated by AND gates 153 and 154, respectively. Edge pulse counters 157 and 158, an adder 159 for adding the count values of the edge pulse counters 155 and 156, and an adder 160 for adding the count values of the edge pulse counters 157 and 158.
[0093]
In addition, the detection circuit 67A includes the total value of the count values of the edge pulse counters 155 and 156 (output value of the adder 159) x counted in the previous biphase 1 bit period, and similarly the previous biphase 1 bit period. Are compared with the total value (output value of the adder 160) y of the edge pulse counters 157 and 158 counted in step, and address information ADM based on the comparison result is output in the next biphase 1-bit period. And a comparison circuit 161.
[0094]
Here, each of the edge pulse counters 155 to 158 is supplied with a clock signal CKBP having a bi-phase bit period as a reset signal. The clock signal CKBP is also supplied to the comparison circuit 161 as a timing signal. The comparison circuit 161 outputs bit “0” as the address information ADM when x> y, and outputs bit “1” as the address information ADM when x <y.
[0095]
Further, the detection circuit 67A has a frequency divider 126 that divides the clock signal CK24 by 1/24 and outputs the clock signal ACK (see FIG. 11D) synchronized with the address information ADM by referring to the clock signal CKBP. is doing.
[0096]
The operation of the detection circuit 67A shown in FIG. 19 will be described. A pulse signal PWB and a clock signal CK24 are supplied to the biphase cycle detection circuit 102, and a clock signal CKBP having a biphase bit cycle is obtained. The 5-bit counter 103 is supplied with the clock signal CKBP as a reset signal and the clock signal CK24 as a clock signal for counting. As a result, the 5-bit counter 103 is first reset in each bit period of the biphase, and after that, the count operation is performed by the clock signal CK24, and “0” to “23” is counted in the decimal system. It becomes.
[0097]
The count output of the 5-bit counter 103 is supplied to the window pulse generation circuit 104A. Based on the count output of the 5-bit counter 103, the window pulses PW0u and PW0d for the biphase bit “0” and the biphase bit “ 1 ″ window pulses PW1u and PW1d are generated and supplied to the AND gates 151 to 154 as gate signals, respectively.
[0098]
On the other hand, the rising edge detection circuit 130 is supplied with the pulse signal PWB and the clock signal CK24, and the rising edge of the pulse signal PWB is detected to obtain the edge detection pulse Peu. Supplied. Similarly, the pulse signal PWB and the clock signal CK24 are supplied to the falling edge detection circuit 140, the falling edge of the pulse signal PWB is detected, and the edge detection pulse Ped is obtained. , 154.
[0099]
The edge detection pulses Peu and Ped gated by the AND gates 151 and 152 are supplied to the edge pulse counters 155 and 156, respectively, and counted for each biphase 1-bit period. Similarly, the edge detection pulses Peu and Ped gated by the AND gates 153 and 154 are supplied to the edge pulse counters 157 and 158, respectively, and counted for each biphase 1-bit period.
[0100]
Then, in the comparison circuit 161, the edge pulse counters 157, 157, 157, 157, 157, 157, 157, 157, which are counted in the previous biphase 1-bit period, are counted. The total value y of the count values of 158 is compared, and address information ADM based on the comparison result is output in the next biphase 1-bit period.
[0101]
In the detection circuit 67A shown in FIG. 19, a case where the wobble signal SWB in a certain biphase 1-bit period is modified as shown in FIG. 22A (= FIG. 18A) will be described. In this case, the pulse signal (binary signal) PWB is as shown in FIG. 22B, and an edge detection pulse Peu corresponding to the rising edge is obtained as shown in FIG. 22E (= FIG. 22E ′), and FIG. As shown in FIG. 22G ′), an edge detection pulse Ped corresponding to the falling edge is obtained. FIG. 22C shows the clock signal CK24, and FIG. 22D shows the edge detection pulse Pe that is a combination of the edge detection pulses Peu and Ped.
[0102]
Since the window pulses PW0u and PWOd supplied to the AND gates 151 and 152 are formed as shown in FIGS. 22F and 22H, the gate outputs A0u, A0d is as shown in FIG. 22I, and x = 1. On the other hand, since the window pulses PW1u and PW1d supplied to the AND gates 153 and 154 are formed as shown in FIGS. 22F 'and H', gate outputs as coincidence pulses supplied to the edge pulse counters 157 and 158 are provided. A1u and A1d are as shown in FIG. 22I ', and y = 6. In this case, since the difference between x and y is sufficiently large, even if the comparison result is used as it is, a correct detection result is obtained.
[0103]
Therefore, the comparison circuit 161 uses the comparison result of x and y as it is, and outputs bit “1” as the address information ADM in the next biphase 1-bit period.
[0104]
In this way, not only the window pulse but also the edge information of the pulse signal PWB is taken into account, so that there is an advantage that more accurate determination is possible.
[0105]
Now, the ADIP decoder 60 shown in FIG. 10 has a PLL circuit 64 and has a relatively complicated circuit configuration.
[0106]
Incidentally, as described above, the number of biphase bits a between adjacent clock marks is 2, the number of channel bits n between adjacent clock marks is 528, and the oversampling value s of the biphase bits is 24 clocks. It is. As will be described later, the data clock regenerator 70 multiplies the reproduction signal SCM of the clock mark CM by n = 528 to obtain the data clock signal DCK. In this case, the frequency of the data clock signal DCK and the frequency of the clock signal CK24 for bi-phase bit oversampling have an integer ratio relationship. That is, if the frequency of the data clock signal DCK is fdck and the frequency of the clock signal CK24 is f24, fdck = 11 × f24. Therefore, the clock signal CK24 can be generated by dividing the data clock signal DCK.
[0107]
FIG. 23 shows an ADIP decoder 60A having another configuration, which divides the data clock signal DCK to obtain the clock signal CK24. In FIG. 23, portions corresponding to those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0108]
The ADIP decoder 60A has a frequency divider 69 that divides the data clock signal DCK reproduced by the data clock regenerator 70 by 1 / M to generate a clock signal CK24 for bi-phase bit oversampling. is doing. Here, M = n / (a · s), and in the present embodiment, M = 528 / (2 · 24) = 11. The clock signal CK24 generated by the frequency divider 69 is used by the detection circuit 67 (67A). 24A to 24C show the timing relationship between the reproduction signal SCM of the clock mark CM, the data clock signal DCK, and the clock signal CK24.
[0109]
Other configurations of the ADIP decoder 60A shown in FIG. 23 are the same as those of the ADIP decoder 60 shown in FIG. Therefore, although a detailed description is omitted, the ADIP decoder 60A operates in the same manner as the ADIP decoder 60 shown in FIG. 10, and the frame address data FAD and the frame synchronization signal FD are obtained from the address converter 68.
[0110]
As described above, the ADIP decoder 60A shown in FIG. 23 can eliminate the need for a PLL circuit to obtain the clock signal CK24, and has the advantage of a simpler circuit configuration than the ADIP decoder 60 shown in FIG.
[0111]
FIG. 25 shows the configuration of the data clock regenerator 70. The data clock regenerator 70 indicates the timing of the zero cross point of the band mark filter 71 for extracting the clock mark regenerated signal SCM from the push-pull signal SPP, the DC cut capacitor 72, and the clock mark regenerated signal SCM. And an edge detector 73 for obtaining a pulse signal PCM.
[0112]
The data clock regenerator 70 also includes a capacitor 74 that cuts the DC component of the regenerative signal SMO, a comparator 75 that converts the regenerative signal SMO into a pulse signal (binary signal) PMO with a threshold = 0, and the pulse signal PMO. An AND circuit 76 that gates the pulse signal PFP corresponding to the reproduction signal SMO of the fixed pattern area of the magneto-optical disk 11 using the fixed pattern gate signal SGo supplied from the timing generator 90. In this case, as shown in FIG. 3D, the fixed pattern gate signal SGo is “1” during a period in which the reproduction signal SMO of the fixed pattern region is obtained, and is “0” in other periods.
[0113]
The timing generator 90 is supplied with a pulse signal PCM indicating the timing of the zero cross point of the clock mark reproduction signal SCM described above. The timing generator 90 generates the fixed pattern gate signal SGo by counting the data clock signal DCK using the pulse signal PCM as a timing reference.
[0114]
The data clock regenerator 70 divides the voltage control oscillator 77 constituting the PLL circuit and the data clock signal DCK output from the voltage control oscillator 77 into 1 / N (here, N = n = 528). A frequency divider 78 for phase comparison, a phase comparator 79 for performing phase comparison between the pulse signal PCM output from the edge detector 73 and the output signal of the frequency divider 78, and a phase output from the phase comparator 79 A low-pass filter 80 for extracting a low-frequency component of the error signal.
[0115]
The data clock regenerator 70 also outputs a phase comparator 81 for comparing the phase of the pulse signal PFP output from the AND circuit 76 and the output signal of the frequency divider 78, and the phase comparator 81. A high-pass filter 82 that extracts a high-frequency component of the phase error signal, and a control signal that is supplied to the voltage-controlled oscillator 77 by adding the output signal of the low-pass filter 80 and the output signal of the high-pass filter 82 supplied via the connection switch 83 And an adder 84 for obtaining. The connection switch 83 is supplied with a switch control signal SW from the system controller 51. As a result, the connection switch 83 is turned off at the time of data writing (recording) and turned on at the time of data reading (reproduction).
[0116]
Next, the operation of the data clock regenerator 70 shown in FIG. 25 will be described. A clock mark reproduction signal SCM (shown in FIG. 26A) is extracted from the push-pull signal SPP, and this clock mark reproduction signal SCM is supplied to the edge detector 73 via the capacitor 72. Then, the edge detector 73 obtains a pulse signal PCM (shown in FIG. 26B) indicating the timing of the zero cross point of the clock mark reproduction signal SCM.
[0117]
The reproduction signal SMO output from the optical head 17 (see FIG. 1) is supplied to the comparator 75 via the capacitor 74 and converted into a pulse signal (binary signal) PMO. In the AND circuit 76, a pulse signal (binary signal) PFP (FIG. 26D) corresponding to the reproduction signal SMO of the fixed pattern area of the magneto-optical disk 11 from the pulse signal PMO by a fixed pattern gate signal SGo (shown in FIG. 26C). Is taken out).
[0118]
Since the connection switch 83 is turned off at the time of data writing (recording), the voltage-controlled oscillator 77, the frequency divider 78, the phase comparator 79, and the low-pass filter 80 constitute a PLL circuit for voltage control. The phase error signal output from the phase comparator 79 is supplied to the oscillator 77 through the low pass filter 80 as a control signal. For this reason, the voltage controlled oscillator 77 obtains the data clock signal DCK whose phase is controlled by the phase information of the clock mark reproduction signal SCM.
[0119]
Since the connection switch 83 is turned on at the time of data reading (reproduction), the PLL circuit is constituted by the voltage controlled oscillator 77, the frequency divider 78, the phase comparators 79 and 81, the low-pass filter 80, and the high-pass filter. The voltage control oscillator 77 is supplied with a control signal as an addition signal of the low frequency component of the phase error signal output from the phase comparator 79 and the high frequency component of the phase error signal output from the phase comparator 81. The Therefore, the voltage controlled oscillator 77 obtains the data clock signal DCK whose phase is controlled by the phase information of the clock mark reproduction signal SCM and the phase information of the reproduction signal SMO in the fixed pattern area. FIG. 26E shows the data clock signal DCK.
[0120]
Next, the operation of the magneto-optical disk device 10 shown in FIG. 1 will be described. When a data write command is supplied from the host computer to the system controller 51, data writing (recording) is performed. In this case, the ECC circuit 54 adds an error correction code to the write data from the host computer received by the SCSI 53 and stored in the data buffer 52, and further converted into NRZI data by the data modulator 55. Is done. Then, the recording data Dr and the fixed pattern signal SFP are supplied from the data modulator 55 to the magnetic head driver 16, and the recording data Dr is recorded in the data area as the target position of the magneto-optical disk 11, and the recording data Dr is recorded. The fixed pattern signal SFP is recorded in the fixed pattern area corresponding to the data area to be processed.
[0121]
When a data read command is supplied from the host computer to the system controller 51, data reading (reproduction) is performed. In this case, the reproduction signal SMO is obtained from the data area as the target position of the magneto-optical disk 11 and the fixed pattern area corresponding to the data area. The reproduction signal SMO is compensated for the frequency characteristic by the equalizer circuit 56, converted into a digital signal by the A / D converter 57 using the data clock signal DCK, and then the data is discriminated by the data discriminator 58 and reproduced. Data Dp is obtained. The reproduced data Dp is subjected to NRZI inverse conversion by the data demodulator 59 and further subjected to error correction by the ECC circuit 54 to obtain read data. The read data is temporarily stored in the data buffer 52 and then transmitted to the host computer via the SCSI 53 at a predetermined timing.
[0122]
In the data writing and data reading, the magnetic head 15 and the optical head 17 are sought to the target position by the servo controller 41. In this case, the seek operation is performed with reference to the frame address data FAD output from the ADIP decoder 60. At the time of data writing (recording), a data clock signal DCK whose phase is controlled by the low frequency component of the phase information of the clock mark reproduction signal SCM is obtained from the data clock regenerator 70, and this data clock signal DCK. Data writing is performed in synchronization with. On the other hand, at the time of data reading (reproduction), the phase is determined by the low frequency component of the phase information that the clock mark reproduction signal SCM has from the data clock regenerator 70 and the high frequency component of the phase information that the reproduction signal SMO of the fixed pattern region has. Is obtained, and data is read out in synchronization with the data clock signal DCK.
[0123]
In the disk device 10 shown in FIG. 1, at the time of data reading (reproduction), the phase is determined by the phase information held by the clock mark reproduction signal SCM and the phase information held by the reproduction signal SMO in the fixed pattern area from the data clock regenerator 70. Is obtained (see FIG. 25), and even if the amplitude of the clock mark reproduction signal SCM is small and the S / N is bad, a clock signal synchronized with the reproduction data is obtained with high accuracy. Therefore, the processing accuracy of data reading can be increased.
[0124]
Further, the amplitude of the groove wobble of the magneto-optical disk 11 is changed in accordance with the frequency of the modulated signal, and the zero cross point of the groove wobble corresponding to the junction of “1” and “0” of the address information ADM. The inclination before and after is not changed (see FIG. 5). Therefore, the jitter in the time axis direction of the wobble signal SWB corresponding to the junction of “1” and “0” of the address information ADM can be reduced, and the address information ADM can be obtained favorably by the ADIP decoder 60 (see FIG. 10). it can. In the present embodiment, as described above, the wave numbers of the groove wobbles corresponding to “1” and “0” of the address information ADM are respectively integers, and are set to “1” and “0” of the address information ADM. The joints of the corresponding groove wobbles are all effective because they are all zero cross points.
[0125]
Further, the ADIP decoder 60 uses a clock signal CK24 having a frequency fc (= 6fa = 8fb) which is a common multiple of the frequencies fa and fb of the wobble signal SWB corresponding to the data “1” and “0” of the address information ADM, respectively. The address information ADM is obtained by the demodulating process (see FIG. 10). Therefore, there is an advantage that the configuration can be configured with only one PLL circuit and the configuration of the ADIP decoder 60 is simplified.
[0126]
In this case, the wave number of the groove wobble corresponding to “1” and “0” of the address information ADM is an integer, and the comparator 63 corresponds to the data of “1” and “0” of the address information ADM, respectively. Since the output pulse signal PWB always has the same shape, demodulation processing using the clock signal CK24 in the detection circuit 67 can be easily performed.
[0127]
The frequency of the data clock signal DCK and the frequency of the clock signal CK24 for bi-phase bit oversampling are in an integer ratio, and the data data clock signal DCK is divided to generate a bi-phase bit oversampling clock. By obtaining the signal CK24, the configuration of the ADIP decoder 60A can be simplified (see FIG. 23).
[0128]
In addition, since the detection circuit 67 of the ADIP decoder 60 detects a bit “0” and a bit “1” using a window pulse, even if the wobble signal SWB is deformed due to a defect. The address information ADM can be obtained satisfactorily as in the case without the deformation.
[0129]
In the above-described embodiment, the wobbling state is shown only on one side of the groove portion 12G of the magneto-optical disk 11, but the wobbling may be performed on both sides of the groove portion 12G.
[0130]
In the above-described embodiment, the clock mark CM is preformatted on the wobbling side of the groove portion 12G. However, the clock mark CM may be preformatted on the non-wobbling side, Further, clock marks CM may be preformatted on both sides.
[0131]
In the above embodiment, the wave numbers of the groove wobble corresponding to “1” and “0” of the address information ADM are “4” and “3”, respectively, but the present invention is not limited to this.
[0132]
In the above-described embodiment, the fixed pattern area of the recording area is provided in one-to-one correspondence with the recording position of the clock mark CM. For example, the number of fixed pattern areas may be smaller than the number of clock marks CM.
[0133]
In the above embodiment, a fixed pattern signal of 2T is recorded in the fixed pattern area of the magneto-optical disk 11, but a fixed pattern signal of 1T or 3T or more may be recorded. Good. However, when the pattern interval is shortened, the amplitude of the reproduction signal SMO is small due to MTF (Modulation Transfer Function), and the S / N is deteriorated. Conversely, when the pattern interval is long, in order to obtain the same number of edges for phase comparison, the fixed pattern area needs to be widened, and the data area in which data is recorded becomes narrow.
[0134]
In the above-described embodiment, ADIP decoders 60 and 60A have frequencies fc (= 6fa = 8fb) which are common multiples of frequencies fa and fb of wobble signal SWB respectively corresponding to data “1” and “0” of address information ADM. However, similar demodulation processing can be performed using a clock signal having other common multiples of the frequencies fa and fb.
[0135]
【The invention's effect】
According to the present invention, an optical disc in which a groove wobble corresponding to a signal obtained by frequency-modulating biphase-modulated address information and a mark having phase information arranged in the groove wobble is pre-formatted is driven. The frequency of the data clock signal and the bi-phase bit oversampling clock signal are in an integer ratio relationship, and the bi-phase bit over-sampling clock signal (first clock signal) ( The second clock signal) is generated by frequency division. Therefore, the address information can be demodulated only by having one PLL circuit in the data system, and there is an advantage that the configuration becomes very simple.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a magneto-optical disk device as an embodiment.
FIG. 2 is a diagram showing a sector layout of a magneto-optical disk.
FIG. 3 is a diagram for explaining a sector (wobble address frame) format;
FIG. 4 is a diagram showing address information of one sector (wobble address frame) before bi-phase modulation.
FIG. 5 is a diagram illustrating a configuration example of a groove wobble.
FIG. 6 is a diagram showing an optical system of the optical head.
FIG. 7 is a diagram showing a configuration of a photodetector that constitutes an optical system of an optical head and spots formed thereon.
FIG. 8 is a diagram illustrating a configuration example of a Wollaston prism configuring an optical system of an optical head.
FIG. 9 is a diagram showing a state of separation of light rays by a Wollaston prism.
FIG. 10 is a block diagram showing a configuration of an ADIP decoder.
FIG. 11 is a timing chart for explaining the operation of the ADIP decoder.
FIG. 12 is a block diagram illustrating a configuration of a detection circuit.
FIG. 13 is a block diagram illustrating a configuration of an edge detection circuit.
FIG. 14 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 15 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 16 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 17 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 18 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 19 is a block diagram showing another configuration of the detection circuit.
FIG. 20 is a block diagram illustrating a configuration of a rising edge detection circuit.
FIG. 21 is a block diagram showing a configuration of a falling edge detection circuit.
FIG. 22 is a waveform diagram for explaining the operation of the detection circuit;
FIG. 23 is a block diagram showing another configuration of the ADIP decoder.
FIG. 24 is a timing chart for explaining clocks used in the ADIP decoder.
FIG. 25 is a block diagram showing a configuration of a data clock regenerator.
FIG. 26 is a timing chart for explaining the operation of the data clock regenerator.
FIG. 27 is a diagram illustrating a configuration example of a conventional groove wobble.
FIG. 28 is a block diagram showing a configuration of a conventional frequency demodulation circuit.
FIG. 29 is a timing chart for explaining the operation of the frequency demodulation circuit;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Magneto-optical disk apparatus, 11 ... Magneto-optical disk, 12G ... Groove part, 12L ... Land part, 15 ... Magnetic head for external magnetic field generation, 16 ... Magnetic head driver , 17 ... Optical head, 18 ... Laser driver, 41 ... Servo controller, 51 ... System controller, 55 ... Data modulator, 58 ... Data discriminator, 59 ... Data Demodulator, 60, 60A ... ADIP decoder, 64 ... PLL circuit, 67, 67A ... detector circuit, 68 ... address converter, 69 ... frequency divider, 70 ... data clock Regenerator, 90 ... Timing generator

Claims (2)

A groove wobble corresponding to a signal obtained by frequency-modulating the bi-phase modulated address information and a mark having phase information arranged in the groove wobble are preformatted,
An optical disc for driving an optical disc in which the number of biphase bits between two adjacent marks is a (a is a natural number) and the number of channel bits between the two adjacent marks is n (n is a natural number) A device,
Clock signal generating means for generating a first clock signal by multiplying the frequency of the reproduction signal of the clock mark by n;
Wobble signal reproducing means for reproducing a wobble signal corresponding to the groove wobble from the optical disc;
Frequency demodulation means for obtaining the address information by performing frequency demodulation on the wobble signal,
The frequency demodulation means includes
Dividing the first clock signal supplied from the clock signal generating means to 1 / M (M = n / (a · s)), where the oversampling value of the biphase bit is s (s is a natural number) clock. A clock signal generation unit for generating a second clock signal,
A waveform shaping unit that obtains a binary signal by shaping the wobble signal;
An optical disc apparatus comprising: a detection unit that obtains the address information by processing the binary signal using the second clock signal. An information signal recording / reproducing means for recording or reproducing an information signal with respect to a recording track formed on the optical disc along the groove wobble;
2. The optical disc apparatus according to claim 1, wherein the information signal recording / reproducing means records or reproduces the information signal based on the first clock signal.

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