JP4047515B2 - Semiconductor device - Google Patents

Description

【０１２４】
これらの大小関係は、（１/２）* ｎ * ｙ(Block) ＜ ｘ(Block)の場合には、ｌ（１行）＜ｌ（２行）であり、１行構成が有利である。逆の場合は２行構成が有利となる。
但し、上の式はブロック数ｎが偶数の場合であり、ｎが奇数の場合には（ｎ＋１）をｎの代わりに代入すれば良い。
以上の構成により、フリーバンク方式及びフリーコア方式における最密なレイアウトを実現することができる。
【０１２５】
［実施の形態１６］
図４４は、図３６に示したレギュレータ電源２６０ａを変形した実施の形態である。演算増幅器ＯＰ１，ＯＰ２は、電源出力端子に接続された抵抗Ｒ１，Ｒ２による検出電圧ＶＩＮＴＥＲが帰還されて、内部電源電位ＶＩＮＴが所定の制御レベルになったときに、ＶＩＮＴＥＲ＝Ｖｒｅｆとなるように全体を制御する。演算増幅器ＯＰ１，ＯＰ２に設けられたダイオード接続のトランジスタＱＮ４２，ＱＮ４３はリーク用である。演算増幅器ＯＰ１により制御される電流源ＰＭＯＳトランジスタＱＰ４１の電流を基準として、チャージポンプ回路出力ＶＣＰにより負荷容量に電流を供給する駆動能力の異なる二つのドライブ回路４０１，４０２が設けられている。
【０１２６】
ドライブ回路４０１，４０２のＰＭＯＳトランジスタＱＰ４８，ＱＰ４９は、スイッチ回路４０３，４０４により選択的に演算増幅器ＯＰ１により制御される電流源のノードＮ３又は昇圧電圧ＶＣＰの端子に接続される。ドライブ回路４０１，４０２のＮＭＯＳトランジスタＱＮ４６，ＱＮ４７のゲートは、スイッチ回路４０５，４０６により選択的に演算増幅器ＯＰ２の出力ノードＮ２又は接地電位に接続される。
【０１２７】
スイッチ回路４０３と４０５は、制御信号ＳＥＬ１とこれと補の信号ＳＥＬ１Ｂにより制御される。スイッチ回路４０４と４０６は、制御信号ＳＥＬ２とこれと補の信号ＳＥＬ２Ｂにより制御される。
制御信号ＳＥＬ１＝“Ｈ”のとき、ドライブ回路４０１のＰＭＯＳトランジスタＱＰ４８，ＮＭＯＳトランジスタＱＮ４６がそれぞれノードＮ３，Ｎ２により制御されて、電圧ＶＣＰから出力端子に電流を供給する。制御信号ＳＥＬ２＝“Ｈ”のとき、ドライブ回路４０２のＰＭＯＳトランジスタＱＰ４９，ＮＭＯＳトランジスタＱＮ４７がそれぞれノードＮ３，Ｎ２により制御されて、電圧ＶＣＰから出力端子に電流を供給する。また、制御信号ＳＥＬ１，ＳＥＬ２を共に“Ｈ”にすることにより、ドライブ回路４０１，４０２を共に活性化することも可能である。
【０１２８】
例えば、一方のドライブ回路４０１の駆動能力は、他方のドライブ回路４０２のそれの２倍に設計されているものとする。これらのドライブ回路４０１，４０２は、負荷容量に応じて、制御信号ＳＥＬ１，ＳＥＬ２により切り換えられる。即ち、負荷容量の小さい動作モードでは、ドライブ回路４０２が活性化され、負荷容量の大きい動作モードではドライブ回路４０１が活性化されるようにすることで、電源電位の遷移の遅れや発振等を防止することができる。
【０１２９】
この様な電源の駆動能力の切り換え制御を行うことの有効性を、以下に具体的に説明する。図４５は、電源の負荷容量（Ｃ）と駆動能力（Ｗ）の比と、電源遷移時間の関係を示している。最も早い遷移が可能なＣ／ＷをＸとして、Ｃ／Ｗ＜Ｘのときは発振等による遷移の遅れが生じる。Ｃ／Ｗ＞Ｘでは安定動作をするが、Ｃ／Ｗが大きくなるほど遷移時間が比例的に大きくなるという、理論直線にのる。Ｃ／ＷがＸに近づくにつれて徐々に理論直線からずれてくるのは、内部電源のオーバーシュートやアンダーシュートにより安定までに時間がかかるためである。内部電源をある遷移時間Ｔ１以下で安定に遷移させるためには、Ｘ＜Ｃ／Ｗ＜Ｘ１となるように設定しなければならない。従って、負荷容量Ｃが複数の異なる値を持つ場合には、駆動能力Ｗを切り換え制御することが有効になる。
【０１３０】
具体的に、図４４の電源レギュレータ回路において、制御信号ＳＥＬ１が“Ｈ”のときは、ＳＥＬ２が“Ｈ”のときに比べて、負荷容量が２倍になるものとする。また図４４においてドライブ回路が一つだけであるとして、その駆動能力が、制御信号ＳＥＬ２＝“Ｈ”の負荷条件を基本として時間Ｔ１で電源遷移させるため、Ｃ／Ｗ＝Ｘ１になるように設定されたとする。そうすると、制御信号ＳＥＬ１＝“Ｈ”の負荷条件の下では、Ｃ／Ｗが２・Ｘ１となり、規定の遷移時間を大きく超えてしまう。従って上述のように、制御信号ＳＥＬ２で制御されるドライブ回路４０２と別の、制御信号ＳＥＬ１で選択されるドライブ回路４０１を用意して、その駆動能力をドライブ回路４０２の２倍に設定することにより、負荷容量によらず、規定の遷移時間を得ることができる。
【０１３１】
この実施の形態は、外部電源レベルの変動に対しても有効である。図４６は、内部電源のＣ／Ｗと電源遷移時間の関係を、異なる外部電源レベルについて示している。即ち、外部電源が低いときには、発振を起こさず最も速い遷移が可能なＣ／ＷがＸであるのに対し、外部電源が高くなると、これがＸ′となる。これは、内部電源の負荷容量と駆動能力が同じであっても、外部電源が高いときは駆動トランジスタの能力が高くなり、充放電が速くなるため、内部電源が発振しやすくなることを示している。内部電源を時間Ｔ１で遷移させたい場合、外部電源が低いときは、Ｘ＜Ｃ／Ｗ＜Ｘ１であるのに対し、外部電源が高いときは、Ｘ′＜Ｃ／Ｗ＜Ｘ１′となり、Ｃ／Ｗが高い方にスライドする。
【０１３２】
従って、駆動能力を可変としない場合には、発振しない時間Ｔ１での遷移の条件を満たすため、駆動能力と負荷をＸ′＜Ｃ／Ｗ＜Ｘ１の範囲に設定しなければならず、設計の許容範囲が狭いものとなる。これに対して、図４４のように駆動能力を切り換え制御することにより、設定の幅を広げることができる。この場合、制御信号ＳＥＬ１，ＳＥＬ２としては、外部電源検知回路の出力等を用いることになる。
【０１３３】
［実施の形態１７］
ここまでの実施の形態では専らフラッシュメモリについて説明した。図１に示したように、大規模のフラッシュメモリで多数のコアを配列する場合、各コアに共通に用いられるデータバス線、アドレスバス線等は通常コアの領域外部に配置される。同様のレイアウトは、フラッシュメモリに限らず、複数の機能ブロックを配列する各種半導体集積回路で利用されている。しかし、コアや機能ブロック数が増加すると、バス線領域のチップに占める面積が増大し、エリアペナルティが大きくなる。
【０１３４】
そこで、この様なエリアペナルティの低減、従ってチップサイズ縮小を可能とした実施の形態を図４７に示す。図４７では、複数の機能ブロックＢＬＫｉ（図の場合、ｉ＝０〜３）が行（Ｘ）方向に配列させている。各機能ブロックＢＬＫｉは、先の実施の形態で説明したような同種のメモリコア回路であってもよいし、メモリ回路以外の例えば論理回路ブロックであってもよい。即ち、機能ブロックＢＬＫｉは、それぞれがある回路機能の固まりとしてまとめられている。各機能ブロックＢＬＫｉには、それぞれ外部との信号授受を行うための信号線１１０が形成されている。
【０１３５】
この実施の形態においては、各機能ブロックＢＬＫｉに共通に用いられる共通バス線１０１は、各機能ブロックＢＬＫｉの領域上に、Ｘ方向に各機能ブロックＢＬＫｉにまたがって配設されている。各機能ブロックＢＬＫｉの領域の信号線１１０は下層配線であり、共通バス線１０１は信号線１１０上に層間絶縁膜を介して形成された上層配線であって、共通バス線１０１は適当な箇所でコンタクト１１１により各機能ブロックＢＬＫｉの信号線１１０に接続されている。
【０１３６】
この様なレイアウトを採用することにより、機能ブロックＢＬＫｉの領域と別に共通バス線領域を設ける場合に比べて、チップサイズの縮小が可能になる。また共通バス線を各機能ブロックＢＬＫｉに引き込むための引き込み配線も不要となる。
【０１３７】
［実施の形態１８］
図４８は、上の実施の形態１７と同様の手法を、図１で説明したフラッシュメモリに適用した実施の形態である。即ち、図４７の機能ブロックＢＬＫｉに相当するものとして、フラッシュメモリのセルアレイを構成するコアがＸ方向に配列されている。各コアに付属して、アドレス信号をデコードするデコード回路（図１における行列デコーダ２に相当）として、コア選択を行うプリデコーダ１０５と、このプリデコーダ１０５の出力デコード信号を更にデコードしてコア内の行列選択をする行（Ｘ）デコーダ１０３及び列（Ｙ）デコーダ１０４を有する。
【０１３８】
そしてこの実施の形態では、各コアに付属するプリデコーダ１０５の領域上に、Ｘ方向に連続して、全コアで共通に用いられる共通バス線１０２が配設される。
これにより、コア領域の外に共通バス線領域を設ける場合に比べて、チップサイズの縮小が可能になる。また共通バス線を各コア領域に引き込むための引き込み配線も不要となる。
【０１３９】
［実施の形態１９］
図４９は、図４８の実施の形態を変形した実施の形態である。コアは行列状に配置されており、Ｘ方向に隣接するコアは互いに線対称をなし、Ｙ方向に隣接するコアも同様にＸデコーダ１０３とプリデコーダ１０５を間に挟んで線対称をなすようにレイアウトされている。図における“Ｆ”字パターンはそのコアレイアウトの対称性を示している。図４９では、Ｙ方向の上部にある複数コア（００，０１，０２，０３）で共通に利用される共通バス線１０２ａと、下部にある複数コア（１０，１１，１２，１３）で共通に利用される共通バス線１０２ｂとが設けられている。
【０１４０】
この様なレイアウトを採用した上で、隣接するコアのデコード回路の一部導電型ウェル領域を共有化している。即ち、Ｘ方向に隣接するコアのＹデコーダ１０４は、ＰＭＯＳトランジスタを形成するＮウェルとＮＭＯＳトランジスタを形成するＰウェルを有するが、それらの一方、図４９の例ではＰウェルを素子分離領域を介在させることなく、一体に形成して共有Ｐウェルとしている。同様に、Ｙ方向に隣接するコアのプリデコーダ１０５についても、ＮウェルとＰウェルのうち、Ｐウェルを共有化している。
この様に、コアを線対称に行列配置して、デコーダのウェルを共有化することにより、エリアペナルティは一層低減される。
【０１４１】
［実施の形態２０］
図４９では、上下のコアに対して別々の共通バス線１０２ａ，１０２ｂを配設したが、これらの共通バス線１０２ａ，１０２ｂを共有化することもできる。そのような実施の形態のレイアウトを図５０に示す。図５０では、図４９におけるＹ方向の上下コアのプリデコーダ１０５の部分を拡大して示している。各プリデコーダ１０５は、Ｎウェル１０７とＰウェル１０６にそれぞれＰＭＯＳトランジスタＱＰとＮＭＯＳトランジスタＱＮを形成して構成される。前述のように、上下のプリデコーダ１０５のＰウェル１０６は、共有化される。
【０１４２】
そして、上下コアで共有化された共通バス線１０２が、上下コアのプリデコーダ１０５の境界領域上に配設されている。共通バス線１０２は、各プリデコーダ１０５に配設される信号線１０８の上層配線として形成されて、適当な箇所でコンタクトを介して信号線１０８に接続される。図の例は、信号線１０８がプリデコーダ１０５の各トランジスタにゲートにつながるアドレス信号線であり、従って共通バス線１０２もアドレスバス線である。
この様に共通バス線をコアで共有化することにより、図４９の実施の形態に比べて消費電流を低減することができる。
【０１４３】
［実施の形態２１］
図５１Ａ及び図５１Ｂは、図４９の実施の形態を変形した実施の形態であり、図４９におけるＹ方向に隣接するコア０１，１１の部分を抜き出して示している。図４９においては、Ｙ方向の上下コアのプリデコーダ１０５はＹ方向に対向して隣接している。これに対して、この実施の形態では、上下コアのプリデコーダ１０５を、Ｘ方向に並べて配置している。図４９における上下コアの二つのプリデコーダ１０５の面積をほぼ変えないとすれば、図５１Ａの場合、一つのプリデコーダ１０５の領域は、図４９のそれに対して、Ｘ方向の寸法が約１／２、Ｙ方向の寸法が約２倍になる。
【０１４４】
また、図５１Ｂに示すように、この実施の形態では共通バス線１０２の下にプリデコーダ１０５のトランジスタＱＰ，ＱＮが配置されるようにしている。この場合、共通バス線１０２はコンタクトを介して直接トランジスタのゲート電極１０９に接続することができる。これにより、エリアペナルティをより一層低減することが可能になる。
但し、この実施の形態では図５１Ａａに示す二つのプリデコーダ１０５は、Ｘ方向に線対称ではないから、各プリデコーダ１０５からのデコード出力線２０１は、同じＸ方向に引き出されて上下コアのＹデコーダ１０４に入る。従って、Ｙデコーダ１０４への入力部でデコード出力線２０１が集中する。
【０１４５】
［実施の形態２２］
図５２Ａ及び図５２Ｂは、図５１Ａ及び図５１Ｂの実施の形態でのデコード出力線２０１の集中を回避するようにした実施の形態である。これは、図５１Ａ及び図５１Ｂの実施の形態における上下コアのプリデコーダ１０５をＸ方向に線対称となるようにレイアウトし、且つ上下コアの本体部とＹデコーダ１０４が回転対称となるようにレイアウトしたものである。
【０１４６】
このとき、各Ｙデコーダ１０５のデコード出力線２０１は、図５２Ａに示すように、Ｘ方向の両側に引き出されて、Ｙデコーダ１０４に入る。従って、図５１Ａ及び図５１Ｂの実施の形態に比べてＹデコーダ１０４への配線の集中が緩和され、それだけエリアペナルティを低減することができる。
【０１４７】
［実施の形態２３］
次に、図５２Ａ及び図５２Ｂの実施の形態で説明した共通バス線の配設手法を、冗長回路方式のフラッシュメモリに適用した実施の形態を説明する。トンネル電流を利用して電気的書き込み・消去を行うスタックト・ゲート構造の不揮発性メモリセルを用いたフラッシュメモリでは、一括消去の単位であるブロックの中に一つでもワード線がチャネルとショートしたロウ不良があると、そのブロックは不良となる。データ消去の際の消去電圧が一本のワード線のショートのために全ブロックについてかからなくなるためである。そこで、この様な不良に対して冗長ブロックを設けて、不良救済を行うブロック・リダンダンシーが用いられる。
【０１４８】
実施の形態１で説明したように複数ブロックの集合によるコアを構成した場合に、ブロック・リダンダンシーを実現するには、冗長ブロックをコアに付属させず、独自のデコーダ回路を備えて、コア内の任意のブロックと置換できるようにすることが好ましい。その様な冗長ブロックを備えた実施の形態のレイアウトを図５３に示す。
【０１４９】
図５３では、それぞれ複数のブロックから構成される二つのコアを示している。冗長ブロック３０１には、前述のようにコアとは独立にＸデコーダ３０２とＹデコーダ３０３及びこれらの前段になるプリデコーダ３０４が設けられている。そして、コア本体用のプリデコーダ１０５と、冗長ブロック３０１のプリデコーダ３０３とが、先の図５２Ａ及び図５２Ｂの実施の形態の上下コアの二つのプリデコーダと同様の関係でレイアウトされている。
【０１５０】
即ち、コア側のプリデコーダ１０５と、冗長ブロック３０１側のプリデコーダ３０４とは、本体コアと冗長ブロック３０１の間の領域に、Ｘ方向に並べて線対称に配置されている。そして、これらのプリデコーダ１０５，３０４の領域上に共通バス線３０５がＸ方向に連続するように配設されている。共通バス線３０５は、先の実施の形態２２と同様に、コンタクトを介して各プリデコーダ１０５，３０４の入力信号線に接続されている。各プリデコーダ１０５，３０４のデコード出力線２０１，３０６は図５２Ａの場合と同様に、それぞれコア及び冗長ブロック３０１のＹデコーダ１０４，３０３に振り分けて接続される。
この様に冗長回路方式のフラッシュメモリにおいても、共通バス線の配置を考慮することにより、エリアペナルティを効果的に低減することが可能になる。
【０１５１】
［実施の形態２４］
次に、実施の形態１で説明したような、データ書き込み・消去とデータ読み出しを同時に行うことを可能としたフラッシュメモリに適用される好ましいセンスアンプ回路の実施の形態を説明する。通常、この種のフラッシュメモリに用いられるデータ読み出し系統は、図５４に示すように構成される。セルアレイ４０１からカラムゲート４０２により選択されたデータ線ＤＬがデータ比較回路４０３の一方の入力端子に入る。データ比較回路４０３の他方の入力端子につながる参照データ線ＲＥＦは、ダミーカラムゲート４０４を介して定電流源４０５に接続れている。これにより、データ線ＤＬの電流と参照データ線ＲＥＦの電流の比較により、データ“０”，“１”の判別が行われる。
【０１５２】
例えば、フラッシュメモリがＮＯＲ型であるとする。このとき、図５６に示すように、メモリセルはドレイン側からのホットエレクトロン注入により浮遊ゲートＦＧに電子が蓄積されて、しきい値電圧の高い状態（例えば“０”状態）になる。また、浮遊ゲートＦＧの電子をチャネル側に放出させることにより、しきい値電圧の低い状態（例えば、“１”状態）となる。このしきい値電圧の差による電流引き込みの有無をデータ比較回路４０３で比較検出することにより、データが判別される。データ比較回路４０３は例えば、図５５に示すように、ＣＭＯＳ差動アンプＤＡを主体として構成される。
【０１５３】
データ書き込み・消去動作では、書き込み又は消去状態を確認する確認読み出し動作が行われるが、一般にこの確認読み出しに用いられる定電流源として、通常のデータ読み出しに用いられるものと共有とすることが可能である。しかし、データ書き込み・消去とデータ読み出しを同時に行うことを可能としたフラッシュメモリでは、通常のデータ読み出しと確認読み出しとが非同期で行われる。この場合、データ線イコライズの必要から、定電流源を共有とすることは難しくなる。データ線イコライズとは、データ読み出しの高速化のために、図５４に示すデータ線ＤＬと参照データ線ＲＥＦを短絡してこれらを同電位状態に初期化することをいう。
【０１５４】
そこで通常は、通常のデータ読み出し系と確認読み出し系の定電流源を別々に用意することになるが、これは別の問題を派生する。即ちそれぞれの定電流源にばらつきがあると、確認読み出し動作で検出されるメモリセルのしきい値電圧と、通常読み出し動作で検出されるしきい値電圧とが異なることになり、誤読み出しの原因となるからである。
【０１５５】
そこでこの実施の形態では、通常読み出し動作での定電流源と確認読み出し動作での定電流源とが同じ電流値となるような読み出しシステム構成とする。その読み出しシステム構成を図５７に示す。ここでは、データ書き込み・消去モードにあるコア０と、データ読み出しモードにあるコア１との二つのコアの読み出し系を示している。各コアの４０１ａ，４０１ｂのビット線は、カラムゲート４０２ａ，４０２ｂにより選択される。各系統の出力は、データ線スイッチ４０７により任意に切り換えられる。データ線スイッチ４０７により選択されて有効となるデータ線ＤＬａ，ＤＬｂはそれぞれデータ比較回路４０３ａ，４０３ｂに入る。各データ比較回路４０３ａ，４０３ｂの参照信号線ＲＥＦａ，ＲＥＦｂはそれぞれダミーカラムゲート４０４ａ，４０４ｂを介して、共通の定電流源４０６に接続される。
【０１５６】
定電流源４０６は、図５８のように構成されている。基準定電流源５０１は、ＰＭＯＳトランジスタＱＰ１，ＱＰ２の対を用いたＰＭＯＳカレントミラーと、ＰＭＯＳトランジスタＱＰ１にスイッチングＮＭＯＳトランジスタＱＮ１を介して接続される基準電流源トランジスタＴ０、ＰＭＯＳトランジスタＱＰ２にスイッチングＮＭＯＳトランジスタＱＮ２を介して接続されるＮＭＯＳトランジスタＱＮ３を有する。ＮＭＯＳトランジスタＱＮ１，ＱＮ２は制御信号ＳＷにより駆動されて、基準定電流源５０１の活性、非活性が制御される。ＮＭＯＳトランジスタＱＮ３は、ＮＭＯＳトランジスタＱＮ２を介してダイオード接続されることになる。
【０１５７】
基準電流源トランジスタＴ０に流れる電流Ｉ０が基準電流である。ＰＭＯＳトランジスタＱＰ１，ＱＰ２が同じ素子パラメータであれば、このＰＭＯＳカレントミラーの作用により、ＮＭＯＳトランジスタＱＮ３には、基準電流Ｉ０が流れる。そして、この基準電流Ｉ０により決まる基準定電流源５０１の出力ノードＮの電位により並列に駆動される二つの電流源ＮＭＯＳトランジスタＴ１，Ｔ２が設けられている。これら二つのＮＭＯＳトランジスタＴ１，Ｔ２は、同じ素子パラメータを有するものとし、ドレインがそれぞれ参照信号線ＲＥＦａ，ＲＥＦｂに接続されることになる。
【０１５８】
これにより、電流源トランジスタＴ１，Ｔ２には同じ電流が流れるため、設定電流値がずれたとしても、通常の読み出し動作と確認読み出し動作における参照信号線ＲＥＦａ，ＲＥＦｂの電流値が常に同じになり、高い読み出しマージンが得られる。
【０１５９】
この実施の形態において、基準電流源５０１の基準電流源トランジスタＴ０として、好ましくは、メモリセルアレイに用いられる不揮発性メモリセルと同じ電気的書き換え可能な不揮発性メモリセルを用いる。この場合、基準電流源トランジスタＴ０の書き換えを行うことにより、基準電流値Ｉ０を変更することができ、従って参照信号線ＲＥＦａ，ＲＥＦｂの電流値を変更することができる。この様に基準電流値Ｉ０を変更しても、参照信号線ＲＥＦａ，ＲＥＦｂの電流値は同値となる。
以上のようにこの実施の形態によると、通常読み出し系と確認読み出し系の参照信号線に流れる電流を常に同じに保つことができ、読み出しマージンの低下や誤読み出し等を確実に防止することが可能になる。
【０１６０】
【発明の効果】
以上述べたようにこの発明によれば、フラッシュメモリの消去単位をブロックとし、１乃至複数ブロックのかたまりを１コアとして、複数のコアによりメモリセルアレイが構成され、且つ任意のコアを選択してデータ書込み又は消去を実行し、同時に他の任意のコアでデータ読出しを可能としたフリーコア方式のフラッシュメモリが得られる。従来のように、データ書込み又は消去動作とデータ読み出し動作を同時に実行できる範囲が固定されず、自由度が高いフラッシュメモリとなる。
またこの発明によると、バンク設定用記憶回路により、任意に選択したコアを第１バンクとし、残りのコアを第２バンクとして、バンクサイズを任意に設定することができるフリーバンク方式のフラッシュメモリが得られ、第１のバンク内で任意のブロックにデータ書込み又は消去動作を行っている間、第２のバンクでのデータ読出しが可能となる。
【図面の簡単な説明】
【図１】この発明の実施の形態によるフラッシュメモリの要部構成を示す図である。
【図２Ａ】同実施の形態のアドレス線スイッチ回路の構成を示す図である。
【図２Ｂ】アドレス線スイッチ回路の他の構成を示す図である。
【図３】同実施の形態の非選択コアでアドレス線を非活性化する回路の構成を示す図である。
【図４】同実施の形態のデータ線スイッチ回路の構成を示す図である。
【図５】同実施の形態の電源線スイッチ回路の構成を示す図である。
【図６】同実施の形態のアドレスバッファの構成を示す図である。
【図７】同実施の形態のコアブロックレジスタとコアビジー出力回路の構成を示す図である。
【図８】同実施の形態のメモリセルアレイのコアの具体構成を示す図である。
【図９】同実施の形態のセルアレイ及びカラムゲートの具体構成を示す図である。
【図１０】同実施の形態の出力回路部の構成を示す図である。
【図１１】同実施の形態での複数コア選択の動作を説明するための図である。
【図１２】フリーバンク方式の実施の形態に用いられるバンク構成ＲＯＭ回路の構成を示す図である。
【図１３】同実施の形態の一つのバンクビジー出力回路の構成を示す図である。
【図１４】同実施の形態の他のバンクビジー出力回路の構成を示す図である。
【図１５】同実施の形態のコアビジー出力回路の構成を示す図である。
【図１６】同実施の形態のバンク構成回路の一例を示す図である。
【図１７】バンク構成回路の他の例を示す図である。
【図１８】バンク構成回路の他の例を示す図である。
【図１９】バンク構成回路の他の構成例を示す図である。
【図２０】バンク構成ＲＯＭ回路の他の構成例を示す図である。
【図２１】高速読出しを行う実施の形態でのコアビジー出力端子の切り換え回路の構成を示す図である。
【図２２】同じく高速読出しを行う実施の形態での電源線スイッチ回路への入力信号切り換え回路の構成を示す図である。
【図２３】同じく高速読出しを行う実施の形態でのアドレスバッファの構成を示す図である。
【図２４】同実施の形態のアドレスバッファの制御タイミング図である。
【図２５】同実施の形態の出力切り換え回路部の構成を示す図である。
【図２６】同実施の形態での高速読出し動作を示すタイミング図である。
【図２７】メモリセルの各動作モードの電圧関係を示す図である。
【図２８】メモリセルの各動作モードでの電圧印加系統を示す図である。
【図２９】他の実施の形態による電源システムの構成を示す図である。
【図３０】同実施の形態における電源線スイッチ回路の構成を示す図である。
【図３１】同実施の形態のチャージポンプ制御回路の構成を示す図であるる
【図３２】同実施の形態の電源線スイッチ回路の構成を示す図である。
【図３３】同実施の形態の他の電源線スイッチ回路の構成を示す図である。
【図３４】ダミー負荷を付加したレギュレータ型電源制御回路の構成を示す図である。
【図３５】ダミー負荷を負荷したレギュレータ型電源制御回路の他の構成例を示す図である。
【図３６】駆動能力切り換え可能としたレギュレータ型電源制御回路の構成を示す図である。
【図３７】駆動能力切り換え可能としたレギュレータ型電源制御回路の他の構成を示す図である。
【図３８】図３０の構成を変形した電源線スイッチ回路の構成を示す図である。
【図３９】全コアのビジー出力回路を示す図である。
【図４０】電源切り換えの問題を説明するための波形図である。
【図４１】好ましい電源切り換え方式の実施の形態を説明するための波形図である。
【図４２】好ましいコアのレイアウト例を示す図である。
【図４３】他の好ましいコアのレイアウト例を示す図である。
【図４４】電源回路の他の実施の形態を示す図である。
【図４５】電源回路の負荷容量及び駆動能力と遷移時間の関係を示す図である。
【図４６】電源回路の負荷容量及び駆動能力と遷移時間の関係を外部電源との関係で示す図である。
【図４７】他の実施の形態による半導体装置のレイアウトを示す図である。
【図４８】他の実施の形態によるフラッシュメモリのレイアウトを示す図である。
【図４９】他の実施の形態によるフラッシュメモリのレイアウトを示す図である。
【図５０】図４９の実施の形態を変形した実施の形態のレイアウトを示す図である。
【図５１Ａ】図４９の実施の形態を変形した他の実施の形態のレイアウトを示す図である。
【図５１Ｂ】同実施の形態のプリデコーダ部のレイアウトを示す図である。
【図５２Ａ】図４９の実施の形態を変形した他の実施の形態のレイアウトを示す図である。
【図５２Ｂ】同実施の形態のプリデコーダ部のレイアウトを示す図である。
【図５３】冗長ブックを持つ他の実施の形態によるフラッシュメモリのレイアウトを示す図である。
【図５４】フラッシュメモリの一般的な読み出し系統を示す図である。
【図５５】同読み出し系統に用いられるデータ比較回路の構成例である。
【図５６】メモリセルの書き込み・消去動作を示す図である。
【図５７】実施の形態の読み出し系統を示す図である。
【図５８】同読み出し系統に用いられる定電流源の構成を示す図である。
【符号の説明】
１…メモリセルアレイ、２…デコード回路、３…アドレス線（及び電源線）スイッチ回路、４…ローカルデータ線、６ａ…リード用アドレスバス線、６ｂ…ライト／イレーズ用アドレスバス線、７ａ…リード用データバス線、７ｂ…ライト／イレーズ用データバス線、８ａ…リード用電源線、８ｂ…ライト／イレーズ用電源線、１０…アドレスバッファ、１１ａ…リード用センスアンプ回路、１１ｂ…ベリファイ用センスアンプ回路、１２ａ…リード用電源、１２ｂ…ライト／イレーズ用電源、１４…インタフェース回路、１５…ライト／イレーズ制御回路、３２ａ，３２ｂ…コア選択回路、４２…コアブロックレジスタ、４３…コアビジー出力回路。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as an electrically rewritable non-volatile semiconductor memory device (EEPROM flash memory), and more particularly to a flash memory system capable of simultaneously executing a data write or erase operation and a data read operation.
[0002]
[Prior art]
Conventionally, there are various electronic device systems configured by incorporating a plurality of memory devices. For example, an EEPROM flash memory and an SRAM are incorporated, data in the flash memory is stored in the SRAM, and data is exchanged between the CPU and the flash memory via the SRAM, and directly in the flash memory without going through the SRAM. There is an electronic system that can rewrite data.
[0003]
On the other hand, recently, in order to reduce the number of memory chips necessary for the system, it is possible to read or write data in one memory area while simultaneously writing or erasing data in another memory area. A memory system called “Read While Write” type is known. In order to configure this type of memory device, it is only necessary to provide two completely independent memory areas inside the memory device.
[0004]
However, a problem remains as an RWW type memory system simply by providing an independently accessed area within one memory device. First, since a decoder and a sense amplifier are required independently for each memory region, the layout area is large. Secondly, if bit lines and word lines are continuously wired independently for each memory area, it is not possible to further divide the memory area into blocks and read and write data in units of blocks. . That is, the range in which data reading and data writing are executed in parallel is fixed and cannot be used for many purposes. In order to cope with various applications, it is necessary to prepare a plurality of products having different memory area capacities.
[0005]
[Problems to be solved by the invention]
In a conventional flash memory in which data write or erase data operation and read operation can be performed simultaneously, the memory cell array is physically fixed in two banks. For example, when considering a 32 Mbit flash memory chip, the capacity is fixed such that one bank is 0.5 Mbit and the other bank is 31.5 Mbit. Therefore, for users, if they needed a different bank size, they had to purchase another chip.
[0006]
As a circuit configuration, dedicated address lines and data lines are provided for each bank. When a write or erase operation is performed in a block of one bank, the power line of that bank is connected to the power line for writing or erasing by the power switch, and the power line of the other bank is connected to the power supply for reading by the power switch. Connected. When a reverse operation command is input, each bank is connected to the reverse power line by each power switch.
Further, one set of sense amplifiers for detecting the memory cell data is provided for each bank. Therefore, while writing or erasing is being executed in a block in one bank, it is possible to execute reading from the memory cell in the other bank, but it is not possible to simultaneously execute writing or erasing and reading in the same bank. It was possible.
In addition, since the banks are physically fixed, restrictions on addresses that can be executed simultaneously are severe, and the size of each bank is also fixed, and the degree of freedom is very low.
[0007]
The present invention has a plurality of cores that are a set of blocks as data erasing units, and can simultaneously execute data write or erase operations in any core and data read operations in any other core. An object of the present invention is to provide a non-volatile semiconductor memory device.
The present invention is also capable of setting a bank size in which an arbitrarily selected core range is set as one bank, and capable of simultaneously executing data writing or erasing operation and data reading in two banks. It is an object to provide a conductive semiconductor memory device.
A further object of the present invention is to provide a semiconductor device capable of reducing the chip size by an efficient common bus line arrangement for a plurality of functional blocks.
[0008]
[Means for Solving the Problems]
A semiconductor device according to the present invention has electrically rewritable nonvolatile memory cells, a range of memory cells as a unit of data erasure is one block, and a set of one to a plurality of blocks is one core. A memory cell array, core selecting means for selecting an arbitrary number of cores for data writing or erasing among the plurality of cores, and selected memory cells in the core selected by the core selecting means Data writing means for performing data writing, data erasing means for erasing data of a selected block in the core selected by the core selecting means, and memory cells in the core not selected by the core selecting means And a data reading means for reading data.
[0009]
According to the present invention, for a plurality of cores each of which is a block of one to a plurality of blocks, an arbitrary core is selected and data writing or erasing is executed, and at the same time, data reading can be performed by other arbitrary cores. Flash memory can be obtained. As in the prior art, the range (bank) in which the data write or erase operation and the data read operation can be executed simultaneously is not fixed, and the flash memory has a high degree of freedom.
[0010]
The semiconductor device according to the present invention also has electrically rewritable nonvolatile memory cells, and a range of memory cells as a unit of data erasure is one block, and a set of one to a plurality of blocks is one core. A memory cell array in which cores are arranged; a bank setting storage circuit that selects any number of cores from among the plurality of cores as a first bank and sets the remaining cores as second banks; and Based on the core selection means for selecting an arbitrary number of cores for data writing or erasing and the stored data of the core selection means and the bank setting storage circuit, one of the first and second banks can write or A bank busy output circuit for outputting a bank busy output indicating that the memory cell is in the erase mode; and a selected memory cell in one of the first bank and the second bank. Data writing means for performing data writing, data erasing means for erasing data of one selected block of the first bank and the second bank, and no data writing or erasing mode among the first and second banks. Data read means for reading data from the bank is provided.
[0011]
According to the present invention, the bank setting storage circuit can provide a free bank flash memory capable of arbitrarily setting the bank size by arbitrarily selecting the core as the first bank and the remaining core as the second bank. Thus, data can be read from the second bank while a data write or erase operation is being performed on an arbitrary block in the first bank.
[0012]
In the present invention, the core is a set of blocks as a unit of data erasure as described above. More specifically, the core is a block of a plurality of blocks sharing the address line, the power supply line, and the data line. , It is defined as a set of a plurality of blocks in which access to other blocks is prohibited when one of the blocks is accessed.
In the present invention, in order to realize the free core system, specifically, a first data bus line which is provided in common for a plurality of cores and used for data reading, and the first data bus A first sense amplifier circuit which is connected to the line and used when reading data, a second data bus line which is provided in common to a plurality of cores and used when writing or erasing data, and And a second sense amplifier circuit connected to the second data bus line and used for verify reading at the time of data writing or erasing.
More preferably, the first address bus line that is commonly provided for a plurality of cores and used for data reading, and the first address bus line that is commonly provided for a plurality of cores for data writing or erasing. A second address bus line to be used is prepared separately.
[0013]
In addition, in order to realize a free core system, each core has a decoding circuit that enables simultaneous execution of data writing or erasing in an arbitrary core and data reading in another core, and each core is in a data reading mode. An address line switch circuit that switches the address signal of the first address bus line and the address signal of the second address bus line and supplies the address signal to the decode circuit according to whether it is in the data write or erase mode, and each core A data line switch circuit that switches between the first data bus line and the second data bus line and connects to the data line in each core according to whether the data read mode or the data write or erase mode is set. Prepare.
[0014]
More specifically, a first power supply line that is commonly provided for a plurality of cores and used for data reading, and a common common power supply for the plurality of cores for data writing or erasing. The second power supply line used for the first power supply line is prepared separately, and depending on whether each core is in the data read mode or the data write or erase mode, the data read power supply for the first power line A power supply line switch circuit is provided that switches between the potential and the power supply potential for data writing or erasing of the second power supply line and supplies them to the decoder circuit.
[0015]
According to the present invention, the address buffer passes through the input address signal at the time of data reading and latches the input address signal to the first address bus line at the time of data writing, thereby latching the second address bus. When data is erased, the internal address signal generated by the counter circuit is supplied to the second address bus line.
[0016]
Still preferably, in the present invention, in order to inform the outside that a certain core is busy as a data writing or erasing mode, a data writing or erasing command is input to each block for each core. Or a core busy output circuit having a core block register for holding a data write or erase flag during an erase operation, and monitoring the data write or erase flag of the core block register and outputting a core busy output as a data write or erase enable signal Is provided.
[0017]
Further, in each address line switch circuit, the core is in the data write or erase mode when a data read request is input to the core while the core is selected as the data write or erase mode. It is preferable to provide a data polling signal generating circuit for generating a data polling signal for informing the outside.
[0018]
In the present invention, the first address bus line used for normal data reading, the first data bus line, and the first sense amplifier circuit connected to the first data bus line are used as the first data reading. A second data read path includes a second address bus line, a second data bus line, and a second sense amplifier circuit connected to the second data bus line, which are used for normal data writing or erasing. As described above, a high-speed data reading mode for performing high-speed data reading by causing these data reading paths to overlap each other every half cycle is provided.
In this high-speed data read mode, the address buffer alternately detects the transition of the input address and generates a clock and the input address in synchronization with the clock generated by the clock generation circuit. And first and second latches that latch and transfer to the first and second address bus lines.
[0019]
In the present invention, it is preferable that (a) a dummy load capacitor connected according to the number of selected cores is added to the second power supply line used for data writing or erasing, or (b) second The power supply for data writing or erasing connected to the power supply line is switched according to the number of selected cores. Thereby, power supply transition can be made constant irrespective of the number of cores selected.
[0020]
In the present invention, it is preferable that the power switch circuit is controlled to be switched in a state where the power is changed so that the first power line and the second power line have the same potential. Thereby, useless power supply fluctuation | variation accompanying power supply switching is prevented.
[0021]
Furthermore, in the present invention, preferably, the plurality of cores are arranged in the row direction in which a plurality of blocks are arranged in one column or two columns in the column direction. This enables a close-packed layout of the core.
In this case, the first and second address bus lines and the first and second data bus lines are wired in the row direction in parallel with the core array. Similarly, the first and second power supply lines are arranged in the row direction in parallel with the arrangement of the cores.
[0022]
The nonvolatile semiconductor memory device according to the present invention also has a power supply control circuit that detects and maintains the internal power supply voltage at a set level, and the power supply control circuit selects according to the load capacity of the internal power supply. It has a dummy load capacity that is connected to each other. Alternatively, the power supply control circuit detects an external power supply voltage and changes the dummy load capacitance connected based on the detection signal.
[0023]
The nonvolatile semiconductor memory device according to the present invention further includes a power supply control circuit that detects and maintains the internal power supply voltage at a set level, and the power supply control circuit includes an internal power supply according to the load capacity of the internal power supply. It has a means to change power supply drive capability, It is characterized by the above-mentioned. Alternatively, the power supply control circuit detects an external power supply voltage and changes the internal power supply drive capability based on the detection signal.
[0024]
The semiconductor device according to the present invention also provides a signal exchange between a plurality of functional blocks each arranged as a block of circuit functions and the outside of each functional block arranged in the area of each functional block. And a common bus which is arranged as an upper wiring of the signal line and is connected to the signal line through a contact on the region of the plurality of functional blocks and in common with the plurality of functional blocks. And a line.
[0025]
In the present invention, each of the plurality of functional blocks may be a core that is a block of the same type of memory cell circuit, or each functional block may have a different circuit function. In any case, the common bus line that is commonly used for each functional block is arranged on the functional block area as the upper wiring of the signal line in each functional block, so that the common bus line is outside the functional block area. The chip size can be greatly reduced as compared with the case where the area is provided.
[0026]
In addition, when the functional block is a plurality of cores composed of a set of the same type of memory cells, for example, a predecoder attached to each core to decode the address signal and select the core, and an output decode signal of this predecoder Further, a decoding circuit including a row decoder and a column decoder for decoding and selecting the matrix of each core is provided, and the common bus line is arranged over the area of the core predecoder arranged in the row direction.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[Embodiment 1]
FIG. 1 shows a chip configuration of a flash memory using the free core system of the present invention. The memory cell array 1 is composed of m cores 0 to m-1 each formed by arranging n blocks B0 to Bn-1. Each of the blocks B0 to Bn-1 is a minimum unit for erasing data, and a plurality of memory cells are arranged in each block. The memory cell is, for example, a non-volatile memory cell having a stacked gate structure. The core is defined as a set of one to a plurality of blocks. In the example shown in the figure, the core is composed of n blocks B0 to Bn-1.
[0028]
Each core is provided with a decode circuit 2 including a row decoder and a column decoder for selecting a memory cell, and a local data line 4 is provided.
A common first address bus line (read address bus line) 6a for selecting a memory cell at the time of data read operation and an auto operation at the time of data write or erase are common to all the cores of such a memory cell array 1. A second address bus line (write / erase address bus line) 6b necessary for the above is provided.
[0029]
The address signal is input from the outside by an address input circuit in the interface circuit 14 and supplied to the address buffer circuit 10. From the address buffer 10, a read address, a write or erase address are supplied to the address bus lines 6a and 6b, respectively, according to the operation mode. The address supplied to each address bus line 6a, 6b is selectively transferred to the decode circuit 2 of each core by the switch circuit 3 for switching the address line and the power supply line provided for each core.
[0030]
Common to all cores, a first data bus line (read data bus line) 7a used for data read operation and a second data bus line (write / erase data used for data write or erase operation) Bus line) 7b is provided. Corresponding to the data bus lines 7a and 7b, the first sense amplifier circuit (read sense amplifier circuit) 11a used for data read operation and the first sense amplifier circuit used for verify read at the time of data writing or erasing. 2 sense amplifier circuits (verification sense amplifier circuits) 11b are provided.
[0031]
The local data line 4 wired for each core is connected to the read data bus line 7a by the data line switch circuit 16 at the time of data reading, and connected to the write / erase data bus line 7b at the time of data writing or erasing. Is done. That is, the data of the selected memory cell of each core is read to the local data line 4 and transferred to the data bus line 7a or 7b by the data line switch circuit 16 according to the operation mode, and the read sense amplifier circuit 11a, verify circuit respectively. Detected and amplified by the sense amplifier circuit 11b.
The read result of the verify sense amplifier circuit 11 b is sent to the write / erase control circuit 15. The write / erase control circuit 15 determines whether or not writing or erasing is sufficient. If it is insufficient, rewriting or erasing is controlled.
[0032]
In addition, a first power supply line (read power supply line) 8a to which a read power supply potential is supplied from the read power supply 12a is provided in common to all the cores, and separately from the write or erase power supply 12b. A second power supply line (write / erase power supply line) 8b to which a data writing or erasing power supply potential is supplied is provided. The read power line 8a is supplied with a voltage boosted from the power supply VCC at the time of data reading, and is supplied to the gate of the memory cell to enable high-speed reading. These power supply lines 8a and 8b are also selectively switched by the switch circuit 3 and supplied to the decode circuit 2 of each core.
[0033]
With the configuration described above, even when data reading and data writing or erasing are executed simultaneously, each operation can be controlled by independent address bus lines, data bus lines, sense amplifier circuits, and power supply circuits. .
Specifically, the operation when data writing and reading in the flash memory of this embodiment are executed simultaneously will be described. Now, a case where data is written to the core 0 and cell data in another core is read will be described. When a selection address signal for core 0 is input from the outside of the chip and a write command is input, the write command is determined by the interface circuit 14 and a write flag is set. With this flag, the switch circuit 3 in the core 0 unit inputs the address signal of the write / erase address bus line 6b to the decode circuit 2 in the core 0, and the power of the write / erase power supply 12b is supplied. The data line switch circuit 16 connects the data line 4 of the core 0 unit to the write / erase data bus line 7b connected to the verifying sense amplifier circuit 11b.
[0034]
By setting the address bus line, the data bus line, and the power supply line in this way, the boosted write voltage is applied to the selected word line in the core 0, and the write control circuit according to the write data is applied to the bit line. A high voltage or a low voltage is applied from 15. As a result, when the memory cell has a floating gate type MOS transistor structure, data is written by injecting photoelectrons into the floating gate of the selected memory cell. When one writing is completed, the data is read and detected by the verifying sense amplifier circuit 11b. Then, a verify determination is made by the write control circuit 15, and if the write is sufficient, the operation is terminated, and if the write is insufficient, additional writing is further performed.
[0035]
During the above-described data writing to the core 0, it is possible to read data in another arbitrary core, for example, the core 1. That is, the address signal of the read address bus line 6a is supplied to the decode circuit 2 of the core 1 including the memory cell to be read by the address inputted from the outside, and the power output of the read power supply 12a is supplied. The data line 4 is connected to the read data bus line 7a through the switch circuit 16. The address signal is not input and the data bus line is not connected to the decode circuit 2 of the other cores in which neither data writing nor data reading is performed. Data read from the selected memory cell of the core 1 is detected and amplified by the read sense amplifier circuit 11a via the read line data bus line 7a. This read data is output to the outside of the chip via the interface circuit 14.
[0036]
In the case of this embodiment, in the above operation, there is no image obtained by dividing an area called a conventional bank. That is, any core other than the core 0 performing data writing can be arbitrarily read by the core 2, the core 3, or the core m-1. It is prohibited to read data by inputting the address of core 0 to which data is being written. As described above, when there is a read request to the core that is writing data, a polling signal indicating that the selected core is performing a write operation is output to notify the outside. It is like that.
[0037]
The operation when data erasing and data reading are executed simultaneously is basically the same. For example, a case where data is erased from a selected block of core 0 and cell data in another core is read will be described. When the selection address signal of the block in the core 0 is inputted from the outside of the chip and the erase command is inputted, the erase command is judged by the interface circuit 14 and the erase flag is set. With this flag, the address signal of the write / erase address bus line 6b is input to the decode circuit 2 of the core 0 by the switch circuit 3 of the core 0, and the erasing power supply potential of the write / erase power supply 12b is supplied. The data line switch circuit 16 connects the data line 4 of the core 0 unit to the write / erase data bus line 7b connected to the verifying sense amplifier circuit 11b.
[0038]
By setting the address bus line, data bus line, and power supply line in this way, a negative voltage is applied to all the word lines of the selected block of the selected core 0, the bit lines are open, and the source lines are for erasing. Is applied and erased in units of blocks. When one data erasure is completed, the data is read and detected by the verifying sense amplifier circuit 11b. The control circuit 15 determines whether or not erasure is sufficient. If it is sufficient, the operation is terminated, and if it is NG, additional erasure is performed. During the data erasure with respect to the core 0 described above, when a data read request is input to another arbitrary core, the data is read from that core.
[0039]
In the above description of the operation, the NOR type memory cell that erases by applying a high voltage to the source is taken as an example, but even in the case of a memory cell that erases by applying a high voltage to the substrate side of the memory cell. The same operation control is possible for the NAND type memory cell.
[0040]
Next, a specific configuration of each unit in FIG. 1 will be described.
FIG. 2A shows the configuration of the address line switch circuit section in the switch circuit 3 in each core. The switch circuit 3 includes two selection switch groups 31a and 31b and core selection circuits 32a and 32b that selectively drive them. The core selection circuits 32a and 32b are activated by enable signals ENBa and ENBb, respectively. The enable signal ENBb is a write or erase enable signal that becomes “H” when a write or erase command is input as will be described later. The enable signal ENBa that is inverted by the inverter I1 is “H” when data is read. Is a read enable signal.
[0041]
One core selection circuit 32b includes an AND gate G3 that is activated by an enable signal ENBb = “H” at the time of data writing or erasing. The AND gate G3 receives a core selection address signal for the write / erase address bus line 6b, and outputs a core selection signal SELb = "H" for the selected core. By this core selection signal SELb, the selection switch group 31b is turned on when data is written or erased. As a result, the address signal ADb for writing or erasing of the write / erase address bus line 6b is supplied to the decode circuit 2 of the selected core.
[0042]
The other core selection circuit 32a is configured by an AND gate G1 activated by a read enable signal ENBa, and the core selection address of the read address bus line 6a is input to the AND gate G1. Since the enable signal ENBa is “L” when the enable signal ENBb is “H”, the core selection signal SELa output from the AND gate G1 is “L” when the core is selected for data writing or erasing. " At this time, the selection switch group 31a is kept off. When the core is selected for data reading, the selection signal SELa = "H" is set, whereby the selection switch group 31a is turned on, and the read address signal ADa of the read address bus line 6a is sent to the decode circuit 2. .
[0043]
That is, in this embodiment, for one core, it is prohibited that the core selection signal SELb for writing or erasing and the core selection signal SELa for reading simultaneously become “H” (glitch). As a result, when data is written or erased for a certain core, data cannot be read by the same core.
[0044]
In the core selection circuit 32a, another AND gate G2 for receiving the same core selection address signal for reading as the AND gate G1 is provided. The AND gate G2 is a data polling signal generation circuit for notifying that the core is in the process of writing or erasing data when a read request is input to the core in which data is being written or erased. A write or erase enable signal ENBb is input to the AND gate G2 as an activation signal. Therefore, the AND gate G2 outputs the data polling signal POL = “H” while holding the core selection signal SELa = “L” when a read request is input to the core that is writing or erasing. To do.
[0045]
When the two core selection signals SELa and SELb are both “L”, this indicates that the core is not selected. This is detected by the NOR gate G4 and outputs a signal DISABLE which deactivates the address line of the non-selected core.
FIG. 3 shows a circuit unit for forcibly grounding an address signal line or the like in the non-selected core by the signal DISABLE. As shown in the figure, a shorting transistor 383 for grounding the address line and the data line 4 is provided in each core. The shorting transistor 383 is controlled by a NOR gate G4. When the core is not selected, DISABLE = “H”, the shorting transistor 383 is turned on, and the charges of all address lines and data lines in the core are discharged.
As described above, the address line and the data line are prevented from floating in the non-selected core. As a result, malfunction due to electrostatic noise or the like, destruction of each part gate insulating film, data destruction, and the like are prevented.
[0046]
In the address line switch circuit shown in FIG. 2A, when the two core selection signals SELa and SELb are both “L”, both the address line switch groups 31a and 31b are turned off, and the read address bus line 6a and the write / erase signal are used. A method in which an unnecessary wiring capacity of a non-selected core is not connected to the address bus line 6b is used.
On the other hand, as shown in FIG. 2B, the address line switch groups 31a and 31b may be controlled by enable signals ENBa and ENBb, respectively.
[0047]
In the system of FIG. 2B, when writing or erasing is executed in the core, the address line switch group 31b is turned on, and the address signal ADb for writing or erasing of the write / erase address bus line 6b is supplied to the decoding circuit 2. Is done. When writing or erasing is not executed in the core, the address line switch group 31a is always turned on, and the read address signal ADa of the read address bus line 6a is supplied to the decode circuit 2. In the unselected core, the disable signal DISABLE is set to “H”, the decoder circuit is completely unselected, and the data line is also discharged.
In this method, it is not necessary to turn on the address line switch group 31a at the time of data reading, the switching time can be omitted, and the data reading speed can be increased.
[0048]
FIG. 4 shows a data line switch circuit for switching the connection between the local data lines 4 and the read data bus line 7a and the write / erase data bus line 7b, focusing on the adjacent cores i and i + 1. 16 configurations are shown. The group of NMOS transistors Q3 is controlled by the core selection signal SELa that is the output of the core selection circuit 32a, and the connection between the local data line 4 and the read data bus line 7a is switched. The group of NMOS transistors Q4 is controlled by the core selection signal SELb which is the output of the core selection circuit 32b, and the connection / disconnection between the local data line 4 and the write / erase data bus line 7b is switched.
[0049]
That is, when a certain core is in the data writing or erasing mode, the core selection signal SELb (i) is "H" in that core, thereby turning on the transistor Q4 and the local data line 4 is the write / erase data. Connected to bus line 7b. On the contrary, when a certain core is in the data read mode, the core selection signal SELa (i) is “H” in the core, thereby turning on the transistor Q3, and the local data line 4 is connected to the read data bus line 7b. Connected.
[0050]
FIG. 5 shows a configuration of the power line switch circuit 41 included in the switch circuit 3 in each core of FIG. The power supply line switch circuit 41 is controlled by level shifters 402a and 402b that are selectively activated by the core selection circuit 32b in the address line switch circuit 3 shown in FIG. 2A, and outputs of these level shifters 402a and 402b, respectively. Transfer gates 403a and 403b. Transfer gates 403a and 403b selectively connect read power line 8a and write / erase power line 8b to decode circuit 2, respectively.
[0051]
For example, when the core selection signal SELb, which is the output of the core selection circuit 32b, is “H”, that is, when the core is in the data write or erase mode, the level shifter 402b is activated. Thus, the transfer gate 403b is turned on by the control signal obtained by shifting the voltage level obtained from the level shifter 402b, and the write / erase power supply potential (for example, the boosted potential VSW) of the write / erase power supply line 8b is decoded. To be supplied. When the core is in the read mode, the core selection signal SELb is “L”. At this time, the level shifter 402a is activated and the transfer gate 403a is turned on. As a result, the read power supply potential Vddr of the read power supply line 8a is supplied to the decode circuit 2 via the transfer gate 403a.
[0052]
FIG. 5 shows a generation path of enable signals ENBa and ENBb omitted in FIG. 2A. The data write signal WRITE or erase signal ERASE obtained by decoding the command in the interface circuit 14 is information indicating which block in the core is selected for writing or erasing in the core block register 42 prepared for each core. Held as. Based on the information in the core block register 42, the core busy output circuit 43 outputs the enable signal ENBb = “H” as a busy output indicating that the core is in the write or erase mode. Details of the core block register 42 and the core busy output circuit 43 will be described later.
[0053]
FIG. 6 shows the configuration of the address buffer 10 of FIG. The address buffer 10 has a three-stage configuration including a first buffer stage 501, a second buffer stage 502, and third buffer stages 503 and 504. The first buffer stage 501 has functions of reducing noise of an address signal supplied from the outside of the chip and internal protection. In the second buffer stage 502, the supplied address signal is directly passed through and supplied to the third buffer stage 503 and also supplied to the latch circuit 505.
[0054]
In the data read mode, the address signal that has passed through the second buffer stage 502 is converted into a complementary signal in the third buffer stage 503 and supplied to the read address bus line 6a. When writing data, the address signal is held in the latch circuit 505 until the end of the operation, and the address signal is supplied to the third buffer stage 504, converted into a complementary signal, and supplied to the write / erase address bus line 6b. The The counter 506 in the second buffer stage 502 is for incrementing the address during the verify operation in the data erase mode. That is, in the erase verify, the address signal sequentially updated by the counter 506 is supplied to the write / erase address bus line 6b via the buffer stage 504.
[0055]
FIG. 7 shows a configuration example of the core block register 42 and the core busy output circuit 43 shown in FIG. The core flock register 42 has a number of registers R0 to Rn-1 equal to the number n of blocks in the core for each core. When the data write signal WRITE or the erase signal ERASE is input, the flag “H” is held in the register corresponding to the selected block of the selected core until the operation is completed. The core busy output circuit 43 has an OR gate 431 that takes the logical sum of the outputs of the registers of the core register block 42. When at least one block for writing or erasing is selected for a certain core, in the core busy output circuit 43, the OR gate 431 outputs a core busy output (that is, a writing or erasing enable signal) ENBb = “H”. In a core that is not selected for writing or erasing, ENBb = “L”, which indicates that reading is enabled.
[0056]
FIG. 8 shows a specific configuration in the core, and FIG. 9 further shows a configuration in the block. In each of the blocks B0 to Bn-1, as shown in FIG. 9, a plurality of bit lines BL and word lines WL are arranged so as to intersect with each other, and memory cells MC are disposed at the intersections. In each of the blocks B0 to Bn-1, a bit line BL and a word line WL are continuously arranged to be a unit for batch erase. A main row decoder 701 for selecting a word line is arranged at the end of the arrangement of the blocks B0 to Bn-1, and a row sub-decoder 702 for selecting a block is arranged between the blocks. The column decoder is composed of a column gate 704 and a column predecoder 703 which are arranged at the bit line end portions of the respective blocks B0 to Bn-1 and perform bit line selection.
[0057]
FIG. 10 shows the configuration of the input / output circuit portion arranged between the read sense amplifier circuit 11a and the verify sense amplifier circuit 11b in FIG. 1 and the external input / output pads. The OR gates 901 and 902 are the data polling output circuit for sequentially adding and outputting the data polling signal POLi (i = 0 to m−1) output from the core selection circuit 32a of each core described in FIG. 2A. It is composed. The output switching circuit 904 switches the read output of the read sense amplifier circuit 11a and the data polling signal and transfers them to the output buffer 906.
[0058]
The data comparison circuit 905 determines the output data read-verified by the verifying sense amplifier circuit 11b at the time of data writing or erasing. In the case of writing, the write data supplied from the input buffer 907 is compared with the verify read data. If the determination result is NG, the determination result is sent to the write / erase control circuit 15 and rewriting is controlled. Similarly, at the time of erasure, if the verify result is NG, it is sent to the write / erase control circuit 15 and re-erasure is performed.
[0059]
In the flash memory configured as described above, details of the simultaneous execution of the data write operation and the data read operation, specifically, the operation when performing data read in another core during data write for a certain core are as follows: Explained.
When a write command is input to the chip, a write flag WRITE is output from the interface circuit 14. In response to this internal signal, the address buffer 10 latches the address signal of the memory cell to be written until the writing is completed, and simultaneously outputs the address data latched to the write / erase address bus line 6b. At the same time, information on the block including the cell to be written is written as busy information “H” in the corresponding register of the core block register 42. The core selected in this way is, for example, core A. In the core A, the core busy output circuit 43 outputs the core busy output “H” (that is, the enable signal ENBb = “H”). As a result, the core selection signal SELb of the core A becomes “H”, and a read request to the core A is prohibited.
[0060]
Further, the write address signal on the write / erase address bus line 6b is input to the selected decode circuit 2 of the core A by the enable signal ENBb and the core selection signal SELb, and at the same time, the power of each decode circuit 2 is supplied to the power source. The power supply potential of the write / erase power supply line 8 b is supplied, and the write / erase data bus line 7 b is connected to the data line 4 of the core A. As a result, data writing in the selected memory cell of the selected core A is executed.
[0061]
In the write mode, the write load circuit is controlled corresponding to the write data input from the I / O pad and latched by the data comparison circuit 905 via the data input buffer 907. In the meantime, when a data read request is input to a memory cell other than core A, for example, core B, in core B, the core busy output, that is, enable signal ENBb is “L”, and core selection signal SELb is “L”. Data read is executed. That is, the address signal of the read address bus line 6a is supplied to the decode circuit of the core B, and at the same time, the read power supply potential is supplied to the decode circuit. The data of the selected memory cell is read out to the data line 4, which is transferred to the read sense amplifier circuit 11a via the read data bus line 7a to be detected and amplified.
[0062]
When an address in the core A during execution of writing is input as a read address, the enable signal ENBb is “H” in the core A, so the data polling signal POL in the core A is “H”. This data polling signal is output to the outside by the output switching circuit 904.
The data read operation can be executed anywhere regarding the data of the memory cells other than the core A being written, and the bank area is not limited.
[0063]
Next, a circuit operation when a data read operation is performed during the data erase operation will be described. When a data erase command instruction is input, an erase flag ERASE is output from the interface circuit 14. As a result, busy information “H” is written into the block register to be erased. At the same time, the counter circuit 506 operates in the address buffer 10 and searches all the block registers in order. When the address of the core A including the block in which the busy information “H” is written is matched, the core selection signal SELb becomes “H”, and the write / erase power supply is supplied to the decoder circuit of the core A as in the case of writing. The erasing power of the line 8b is supplied, the address of the write / erase address bus line 6b is supplied, and the local data line is connected to the write / erase data bus line 7b. Thereby, an erase voltage is applied to the target block. Thereafter, the memory cells of the target block are incremented by the counter circuit 506 and sequentially verified.
The above-described read operation during execution of erasure is the same as that during the above-described write execution.
[0064]
Next, the data polling circuit operation will be described. When a read command is input to the core A during execution of writing or erasing in the core A, the enable signal ENBa of the core A is “L”, and the selection signal SELa of the core A is also “L”. As a result, the read operation in the core A is prohibited. At this time, in the core A, the data polling signal POL becomes “H”, which is output to the polling bus line and input to the output switching circuit 904 as the data polling signal. The output switching circuit 904 receives the signal and outputs polling data to the output buffer circuit 906 instead of the output of the sense amplifier circuit 11a.
[0065]
FIG. 11 shows the operation when there is a data erasure command for a plurality of cores A, B, and C at the same time. In this case, busy information is stored in the core block registers 42 of the cores A, B, and C. As a result, the core busy output circuit 43 of the cores A, B, and C including the block to be erased outputs the busy information “H”, that is, the enable signal ENBb = “H”, and reading execution is prohibited for these cores. And data polling.
[0066]
[Embodiment 2]
Next, a description will be given of an embodiment of a free bank system in which a bank of an arbitrary size is configured with an arbitrary combination of cores in the flash memory described in the above embodiment.
In order to realize the free bank system, a bank configuration ROM circuit 110 as shown in FIG. 12 is prepared for each core. The bank configuration ROM circuit 110 constitutes a memory circuit in which an arbitrary number of nonvolatile memory cells MC1, MC2,. In principle, a single memory cell is possible, but a plurality of memory cells are used here for safety reasons.
[0067]
Data is selectively written into the bank configuration ROM circuit 110 from the outside of the chip via the interface circuit 14. That is, when writing is not performed, the threshold value Vth of the memory cells MC1 to MCn of the bank configuration ROM circuit 110 is low. Therefore, by reading this, the node A becomes “L”. When data is written to all the memory cells MC1 to MCn and Vth is increased, the memory cells MC1 to MCn are turned off and the node A becomes “H”. That is, a plurality of cores are written in the bank configuration ROM circuit 110 so that a group in which the node A is “L” (hereinafter, “L” group) and a group in which the node A is “H” (hereinafter, “H”). “Group” is divided into two.
[0068]
The bank busy output circuit 120A of the “L” group and the bank busy output circuit 120B of the “H” group are configured as shown in FIGS. 13 and 14, respectively. As shown in FIG. 13, the bank busy output circuit 120A of the “L” group has an “H” output obtained by inverting the output of the bank configuration ROM circuit 110 by the inverter 122 by an AND gate 121A provided for each core. The product of the core busy output of the core busy output circuit 43 is taken. Then, the sum of the outputs of the corresponding AND gates 121A in all other cores is taken by the OR gate 123A. As a result, an “H” output is obtained from the OR gate 123A when any of the cores in the “L” group of banks is in the write or erase mode (ie, when the core busy output is “H”). This becomes the bank busy output “H” via the transistor Q11.
[0069]
However, the bank busy output is issued when the write command WRITE or the erase command ERASE is input and the free bank command is input. At this time, the output of the AND gate 124A becomes “H”, and the transistor Q11 is turned on. In other cases, the transistor Q11 is turned off. Instead, the reset transistor Q12 is turned on via the inverter 125A, and the bank busy output terminal is reset to “L”.
[0070]
As shown in FIG. 14, the bank busy output circuit 120B of the “H” group takes the product of the output “H” of the bank configuration ROM circuit 110 and the core busy output of the core busy output circuit 43 by the AND gate 121B. Then, the OR gate 123B takes the sum of the outputs of the corresponding AND gates 121B in all other cores. As a result, an “H” output is obtained from the OR gate 123B when any of the cores in the bank of the “H” group is in the write or erase mode (ie, when the core busy output is “H”).
[0071]
FIG. 15 is provided for each core for making all the cores in the bank busy when a data write or erase operation is performed in an arbitrary block in the bank in the free bank system of this embodiment. This is a configuration of a core busy output circuit. The outputs of the bank busy output circuits 120A and 120B shown in FIGS. 13 and 14 are OR-connected through transfer gate transistors Q21 and Q22. One transistor Q21 is directly controlled by a signal obtained by inverting the output of the bank configuration ROM circuit 110 by the inverter 141, and the other transistor Q22 is directly controlled by the output of the bank configuration ROM circuit 110.
[0072]
Therefore, in the case of the “L” group, the output of the bank “L” busy circuit 120A enters the OR gate 142 through the transistor Q21. On the other hand, in the case of the “H” group, the output of the bank “H” busy circuit 120B enters the off gate 142 through the transistor Q22. Each register information of the block register of each core is also entered in the OR gate 142. As a result, if any bank is busy, a core busy output “H” is obtained for all the cores belonging to that bank. As a result, data reading from the bank is prohibited, and a data polling signal is output outside the chip.
[0073]
When the data writing or erasing operation is completed, the outputs of the AND gates 124A and 124B shown in FIG. 13 or FIG. 14 become “L”, and the bank busy output is reset. At this time, all the register outputs of the block register are also "L", so the core busy output in FIG. 15 is also reset to "L".
The change from the free bank system to the free core system can be realized by setting the free bank instruction entering the bank busy output circuits 120A and 120B to "L" and turning off the bank busy output circuits 120A and 120B. The free bank instruction can be stored using, for example, a rewritable ROM circuit. By rewriting this ROM circuit, it is possible to freely set the free bank method and the free core method.
[0074]
FIG. 16 shows a connection example of the entire bank configuration circuit. As apparent from the description of FIGS. 13 to 15, the bank busy output of each bank is fed back to the core busy output circuit 43 of each core, whereby the cores of the “H” group are linked together to form one bank. The L ″ group cores can be linked together to form another bank.
The operation of simultaneous execution of data writing or erasing and data reading in each bank is basically the same as in the case of the free core system.
In the case of this embodiment, the bank configuration of the “L” group and the “H” group can be arbitrarily changed by rewriting data in the bank configuration ROM circuit 110.
[0075]
[Embodiment 3]
FIG. 17 shows a modified embodiment of the bank configuration circuit of FIG. In the configuration of FIG. 16, a number of busy signal lines entering the OR gates 123A and 123B of the bank busy output circuits 120A and 120B are wired. On the other hand, in FIG. 17, one busy signal line 163, 164 is provided for each bank. These busy signal lines 163 and 164 are set to "H" level when pull-up PMOS transistors Q43 and Q44 are provided and bank busy is not output. In each core, transistors Q41 and Q42 controlled by outputs of the AND gates 121A and 121B are provided between the busy signal lines 163 and 164 and the ground, respectively. Accordingly, when the bank is busy, the transistor Q41 or Q42 is turned on and the signal line 163 or 164 is set to "L", which is inverted by the inverters 161 and 162, and any of the bank busy output circuits 120A and 120B is bank busy. Output "H".
According to this embodiment, the number of signal lines is greatly reduced.
[0076]
[Embodiment 4]
FIG. 18 is an embodiment in which the bank configuration circuit of FIG. 16 is similarly modified. In this embodiment, OR gates 123A and 123B in FIG. 16 are dispersed in each core part and OR gates 171 and 172 are arranged. This also reduces signal lines. In the embodiment of FIG. 17, current consumption is generated by the transistors Q41 and Q42. In this embodiment, such consumption current disappears, which is preferable.
[0077]
[Embodiment 5]
FIG. 19 shows an embodiment in which a bank read output circuit 391 is provided by modifying the bank configuration circuit of FIG. 16, FIG. 17 or FIG. In the embodiment of FIG. 16, FIG. 17, or FIG. 18, the free bank method is realized by feeding back each bank busy output to the core busy output circuit of the core that constitutes the bank. On the other hand, in this embodiment, bank busy information is not fed back, and each bank busy information is compared with each bank read information obtained by the bank read output circuit 391 on the output side, so that a data write / erase mode is obtained. The free bank system is apparently realized by detecting the read address input (read information) in the bank and performing data polling.
[0078]
That is, when this core is selected as the data write / erase mode by the core busy output circuit 43 and the core busy output ENBb = "H" is output, information on the "H" group and "L" group determined by the bank configuration ROM circuit 110 In response to this, a bank busy output is obtained at one of the AND gates G17 and G16. These outputs are summed with the bank busy outputs of other cores by OR gates G19 and G18.
[0079]
The AND gate G20 detects the coincidence between the output of the core busy output circuit 43 and the core selection signal from the read address line, and when this core is in the data write / erase mode and then a read request is received, the data The polling output “H” is output.
On the other hand, in the bank read output circuit 391, the core selection signal from the read address bus line is detected by the AND gate G11. When the output of the AND gate G11 is “H”, that is, read information is output, the bank read information is sent to one of the AND gates G12 and G13 according to the “H” group and “L” group information from the bank configuration ROM circuit 110. “H” is output. These are also summed with the read information in the other cores by the OR gates G14 and G15 and transferred to the output stage.
[0080]
In the output stage, the AND gates G23 and G24 detect the coincidence between the bank busy information and the read information of the “H” group and the coincidence of the bank busy information and the read information of the “L” group, respectively. The outputs of the AND gates G20, G23, and G24 are summed by an OR gate G22. As a result, one bank is in the data write or erase mode, and when a read request is received, data polling is performed to substantially obtain the free bank system.
[0081]
[Embodiment 6]
FIG. 20 shows an embodiment in which the bank configuration ROM circuit 110 is modified. In this embodiment, the bank configuration ROM circuit 110 is configured using a fuse FS. Also in this case, after the memory chip is formed, by selectively cutting the fuse FS, a bank configuration of “L” group and “H” group of any size can be realized. However, in this method, once the bank configuration is set, the bank size cannot be changed, and the free core method cannot be restored.
[0082]
[Embodiment 7]
Next, embodiments in which data is read at high speed in the flash memory described in the above embodiments will be described. In the high-speed data read mode, the read address bus line 6a, the read data bus line 7a, and the read sense amplifier circuit 11a connected to the data bus line 7a are used as the first data read path, and the write / erase address is used. The bus line 6b, the write / erase data bus line 7b, and the verify sense amplifier circuit 11b connected to the data bus line 7b are used as a second data read path, and these data read paths are overlapped by half a cycle. To perform high-speed data reading.
In order to realize such a high-speed data read operation, the core selection circuits 32a and 32b of each core shown in FIG. 2A, the power supply line switch circuit 41 shown in FIG. 5, the address buffer 10 shown in FIG. Changes to the output switching circuit 904 and the like are required.
[0083]
First, when a high-speed read command is input, as shown in FIG. 21, the terminals of the enable signals ENBa and ENBb that enter the core selection circuits 32a and 32b of each core are connected to the core busy output circuit 43 by NMOS transistors QN211 and QN212. The pull-up PMOS transistors QP21 and QP22 are turned on so that both are fixed to the “H” state. At the same time, as shown in FIG. 22, the NMOS transistor QN221 on the path to the power line switch circuit 41 of the core selection circuit 32b is turned off and the short-circuit NMOS transistor QN222 is turned on and fixed to “L” by the high-speed read command. So that
Thereby, the core selection signals SELa and SELb for all the cores are determined only by the core address signals of the address bus lines 6a and 6b, and the decoder power supply is always connected to the read power supply line 8a.
[0084]
The address buffer 10 is modified so that the second buffer stage 502 shown in FIG. 6 has two sets of latch circuits 191 and 192 as shown in FIG. These latch circuits 191 and 192 are for alternately latching the address of the memory cell to be read by the timing signals PULSEb and PULSEa and supplying them to the address bus lines 6a and 6b.
[0085]
In order to generate the timing signals PULSEa and PULSEb, as shown in FIG. 23, the clock generation circuit 193 that detects the address transition and generates the clock CLK, and the output of the clock generation circuit 193 is counted and the cycle is 2 A counter circuit 194 that outputs a double count output COUNT is provided. Then, AND gates 196 and 197 activated by the clock CLK are provided. The count output COUNT is directly input to the AND gate 196, and the AND gate 197 is inverted by the inverter 195, thereby shifting the timing signal PULSEa shifted by a half cycle. , PULSEb is generated.
[0086]
FIG. 24 is a circuit operation timing chart of FIG. As shown, a clock CLK is generated in synchronization with the input address, and timing signals PULSEa and PULSEb are generated based on the clock CLK. By controlling the latch circuits 192 and 191 with the timing signals PULSEa and PULSEb, addresses are alternately transferred to the address bus lines 6a and 6b.
[0087]
As shown in FIG. 6, a third buffer stage is provided at the outputs of the latch circuits 191 and 192. In this case, the latch circuits 191 and 192 and the third buffer stage are omitted in the figure. An output comparison circuit is provided. This is because when the input address is the same core, the data polling signal is output without outputting the address input later to the third buffer stage. Such data polling prevents circuit destruction and malfunction due to simultaneous selection of the same core.
[0088]
Further, as shown in FIG. 25, an output switching circuit 210 for switching the output of the verify sense amplifier circuit 11b and the output of the read sense amplifier circuit 11a is required. The output switching circuit 210 is controlled by the clock CLK to alternately switch the verify sense amplifier circuit 11b and the output and the output of the read sense amplifier circuit 11a, and outputs data to the output buffer circuit.
[0089]
FIG. 26 shows an operation timing chart of high-speed data reading in this embodiment. Read data obtained by shifting by half a period to each sense amplifier circuit 11a, 11b corresponding to the addresses (1), (2),... Shown in FIG. The
In the system of this embodiment, high-speed data reading is possible in which reading to a random address is possible in a normal half cycle. However, reading to the same core is prohibited and data polling is performed. Further, since the address cycle from the outside of the chip is doubled inside the chip, the output data is shifted by one cycle. However, if such a system is known and a system is made, high-speed chip access can be realized.
[0090]
Note that the high-speed read command is controlled by a command from the outside of the chip, for example. Alternatively, if used as an OTP, a data storage circuit composed of ROM cells may be provided in the chip, and a high-speed read command may be controlled depending on whether data is written therein.
[0091]
Next, a specific embodiment of the power supply system in the flash memory according to the present invention will be described. Prior to the description, the relationship between the operating voltages of the memory cells is shown in FIG. At the time of data reading, a boosted potential 5V is applied to the gate (word line) of the memory cell, 1V is applied to the drain, and 0V is applied to the source, and the current flowing through the cell is detected by a sense amplifier. At the time of writing, a boosted potential is applied to the word line, 5 V is applied to the drain, and 0 V is applied to the source, and hot electrons generated between the drain and source are injected into the floating gate. When erasing data, the drain is opened, -7V is applied to the word line, and 5V is applied to the source, and electrons are emitted by FN tunneling by the high voltage between the floating gate and the source.
[0092]
FIG. 28 shows an outline of a voltage application system at the time of reading, writing and erasing the memory cell. The word line of the memory cell is driven by a row decoder. The high potential level of the decoder is connected to Vddr = 5V at the time of reading and VSW = 8V at the time of writing by the switch SW1. The low potential level of the row decoder is connected to VBB = -7V at the time of erasure by the switch SW3. Thus, 5V is applied to the word line, that is, the gate G of the memory cell, 8V at the time of writing, and -7V at the time of erasing.
[0093]
The drain D of the memory cell is connected to a sense amplifier at the time of reading and 1 V is applied via the sense amplifier, and at the time of writing, it is connected to the load LOAD and 5 V is applied thereto. At the time of erasing, the drain is opened.
The source S of the memory cell is applied with 5V through LOAD at the time of erasing, and is grounded in other modes. LOAD is connected to Vdd and the charge pump output Vddp via the switch SW2.
[0094]
[Embodiment 8]
FIG. 29 shows a configuration example of the read power supply 12a and the write / erase power supply 12b. The read power supply 12a and the write / erase power supply 12b generate desired levels based on the output of the reference potential generation circuit 320 using, for example, a band gap reference (BGR) circuit. At this time, there are the following three cases in the generation method of a desired level.
Case (1): The charge pump circuit is on / off controlled.
Case (2): The output obtained in case (1) is further controlled by a regulator. Case (3): The output obtained in case (1) and a constant potential (for example, VSS) are switched.
[0095]
In FIG. 29, among the three power lines 8b (1) to (3) of the read power source 12a and the write / erase power source 12b, the power line (2) corresponds to the case (1). That is, the read power supply 12a and the write / erase power supply line 6b {circle around (2)} are constituted by control circuits 322 and 324b for controlling on / off of the charge pump circuit and charge pump circuits 323 and 325b controlled by these circuits. In these power supply circuits, if the power supply level is below a desired level, the charge pump circuit is driven, and the charge pump circuit is controlled to stop operating when it reaches the desired level.
[0096]
The write / erase power supply line 8b {circle around (1)} corresponds to the case (2) and includes an on / off control circuit 324a, a charge pump circuit 325a controlled thereby, and a regulator control circuit 326 for controlling the output level of the charge pump circuit 325a. . Specifically, this is used for an automatic data write operation in which writing and verification are repeated using a write voltage of 8V and a verify read voltage of 6.5V. The regulator control circuit 326 is used for such voltage control. Is used.
[0097]
The write / erase power supply line 8b {circle over (3)} corresponds to the case (3), and switches the control circuit 324c for on / off control, the charge pump circuit 325c for negative potential and the output of the charge pump circuit 325c controlled thereby. A switch circuit 327 is provided. The switch circuit 327 is provided for outputting VSS when the charge pump circuit 325c is not operating.
The three write / erase power supplies described above are activated according to the write / erase operation mode by the auto control signal output from the write state machine 321.
[0098]
FIG. 30 shows a configuration of the power supply line switch circuit 16 that is a part of the address line switch circuit 3 that switches the power supply lines of the power supply circuit shown in FIG. As shown in the figure, the power supply line switch circuit 16 includes three switch circuits SW1 to SW3. In this example, these switches SW1 to SW3 are controlled by a write / erase enable signal ENBb which is an output of the core switch control circuit 250 (specifically, corresponding to the core busy output circuit 42 described in FIGS. 5 and 7). Is done.
[0099]
FIG. 31 is a configuration example of a control circuit 324 (same for 322) that performs on / off control of the charge pump in FIG. An operational amplifier 331 is used which detects the output VCP obtained from the charge pump circuits 323, 325 and the like by a voltage dividing circuit of resistors Rload and Rref and compares it with a reference voltage Vref. The output of the operational amplifier 331 is taken out as a charge pump enable signal CPENB via the buffer 332.
[0100]
FIG. 32 shows switch circuits SW1 and SW2 for switching between the read power supply obtained for the read power supply line 8a and the positive write / erase power supply obtained for the write / erase power supply lines 8b (1) and (2). It is a structural example. A level shifter 230 controlled by an enable signal SWENB (corresponding to the enable signal ENBb in FIG. 29) is controlled so that the voltage level is shifted from the VCC system to a voltage between the positive high potential power supply VCP and VSS from the charge pump circuit. A signal is generated. This control signal controls the output stage transistors QP3, QN3, and QP4 via the inverters 233 and 234. That is, if the output of the inverter 233 is “H”, the NMOS transistor QN3 and the PMOS transistor QP4 are turned on, and the read power supply Vddr is output. If the output of the inverter 233 is “L”, the PMOS transistor QP3 is turned on and the boosted power supply VSW is output.
[0101]
FIG. 33 shows a configuration example of the switch circuit SW3 for switching between the negative power supply potential VBB and the ground potential VSS obtained on the write / erase power supply line 8b (3). A level shifter 240 controlled by the enable signal SWENB generates a control signal whose voltage level is shifted from the VCC system between the intermediate potential power supply VSW and the negative power supply potential VBB. This control signal controls the output stage transistors QN17, QN18, and QP15 through inverters 243 and 244, respectively. That is, if the output of the inverter 243 is “H”, the NMOS transistor QN17 is turned on and the negative power supply VBB is output. If the output of the inverter 243 is “L”, the PMOS transistor QP15 and the NMOS transistor QN18 are turned on and VSS is output.
[0102]
In the power switch control system described with reference to FIG. 30, the power supply of each core is fixed to the read power supply or the write / erase power supply during the data write or erase operation, so that writing / erasing is performed across a plurality of cores. In the case of the free bank system, power supply transition can be performed regardless of the core-selected address switching. However, in the free bank system, the capacity for driving the power source differs depending on the number of cores selected in the block register. For this reason, the power supply transition time varies depending on the number of selected cores, or the power supply transition may oscillate when the number of selected cores is small.
[0103]
There are two possible methods for solving such problems. The first is to keep the load of the power supply control circuit (regulator) substantially constant regardless of the number of cores selected. Specifically, a dummy load capacitor that is selectively connected to the power supply control circuit is provided, the internal power supply voltage or the external power supply voltage is detected, and the load capacitance is controlled according to the detection result. Secondly, the driving capability is switched according to the number of cores selected. In this case as well, specifically, the internal power supply voltage or the external power supply voltage is detected, and the driving capability is switched according to the detection signal.
Specifically, the voltage control circuit of such an embodiment will be described below.
[0104]
[Embodiment 9]
FIG. 34 shows a voltage addition type power supply control circuit according to an embodiment of the first method. The regulator main body 260 includes PMOS transistors QP21 and QP22 and NMOS transistors QN21 and QN22 having a differential circuit configuration for taking out the output VCP of the charge pump circuit by level control, and two operational amplifiers for controlling this according to the output level. It has OP1 and OP2. The output level is monitored as a divided voltage output of the resistors Rload and Rref, and this is fed back to the operational amplifiers OP1 and OP2 to obtain a predetermined voltage level. The resistor Rload can be switched by a switch 261 controlled by the mode signals MODE1 to MODE4, thereby controlling a necessary power supply level.
[0105]
In this embodiment, a plurality of dummy core capacitors C are arbitrarily selected and connected to the output terminal of such a voltage control type regulator body 260. The dummy core capacitor C is selectively connected to the output terminal by a PMOS transistor QP23 controlled by a core selection signal. Specifically, the dummy core capacitor C is connected so that the load of the regulator always matches the capacity when all the cores are selected.
By the additional control of the dummy core capacity as described above, it is possible to realize a constant power supply transition regardless of the number of core selections.
[0106]
Specifically, when the capacity of one core is C (core), the number of selected cores is m (selct), and the total number of cores is m (total), the added dummy core capacity C (dummy) What is necessary is just to control so that it may satisfy | fill.
[0107]
[Expression 1]
C (dummy) = {m (tatal)-m (select)} · C (core)
[0108]
[Embodiment 10]
FIG. 35 shows another embodiment according to the first method, in which the same device is added to the current addition type power supply control circuit. The regulator body 280 is also known, and uses an R / 2R ladder circuit and a current addition method using a switch 271 for switching a current path for monitoring an output voltage. Also in this case, the dummy core capacitor C is selectively connected to the output terminal of the regulator 208 so that the load capacity is always the same as when all the cores are selected, as in the above embodiment.
As a result, a constant power supply transition can be realized regardless of the number of cores selected.
[0109]
[Embodiment 11]
FIG. 36 shows an embodiment according to the second method. The regulator 260a is based on the voltage addition type regulator main body 260 shown in FIG. 34, and includes a drive PMOS transistor QP22 and NMOS transistors QN22 in parallel in a plurality of systems. In each of these systems, a switching PMOS transistor QP24 and an NMOS transistor QN24 are inserted, and these are selectively turned on / off according to the state of core selection.
[0110]
Specifically, the number of selected cores is m (selct), the unit driver / load transistor size is W (unit), and the driver / load transistor size controlled according to the number of selected cores is W (control). Control may be performed so as to satisfy (control) = m (select) · W (unit).
As a result, the drive capability of the power supply control circuit is switched (specifically, the transistor size is switched substantially) according to the number of cores selected, and a constant power supply transition can be realized regardless of the number of cores.
[0111]
[Embodiment 12]
FIG. 37 shows another embodiment according to the second method. The regulator 280a is based on the current addition type regulator body 280 shown in FIG. 35, and a load PMOS transistor QP22 and a driver NMOS transistor QN22 are arranged in parallel in a plurality of systems. Provided. In each of these systems, a switching PMOS transistor QP24 and an NMOS transistor QN24 are inserted, and these are selectively turned on / off according to the state of core selection.
As a result, as in FIG. 36, the drive capability of the power supply control circuit is switched according to the number of selected cores, and a constant power supply transition can be realized regardless of the number of cores.
[0112]
[Embodiment 13]
FIG. 38 shows a modified embodiment of the power line switch control system of the embodiment of FIG. In this embodiment, the AND gate 302 detects the coincidence between the output of the busy output circuit 301 and the core address signal, and controls the power supply line switch 16. In this case, it is assumed that the busy output circuit 301 ORs all the registers of each core block register 42 and outputs a busy output as shown in FIG.
[0113]
In the system of this embodiment, the number of cores connected to the write / erase power supply line 8b is always limited to one. Therefore, the capacity added to the write / erase power supply is always constant, and the controllability (level fluctuation in a short time) and the stability (oscillation resistance) of the write / erase power supply are excellent. On the other hand, the number of cores connected to the read power line is the number of cores excluding all cores or one core in the write / erase mode. As a result, the capacity added to the read power supply is also substantially constant, and the controllability and stability are excellent.
[0114]
[Embodiment 14]
Next, a preferred control method when switching between the read power supply and the write / erase power supply will be described.
In both the free core system and the free bank system, only one set of read power and power lines, write / erase power and power lines in the chip is prepared. For this reason, if switching from the write / erase power source to the read power source is performed at the end of the data write or erase operation, a power supply potential fluctuation occurs due to the switching. This is shown in FIG. When data write / erase with respect to core A and data read with respect to core B are performed at the same time, when the operation of core A is completed and the power supply is switched, the power supply potential for reading is set as shown in FIG. In the core B in which the bump is generated and the reading operation is performed, there is a possibility that an access delay or erroneous data output may occur due to the power supply fluctuation.
[0115]
In order to prevent this, as shown in FIG. 41, the write / erase power supply is set prior to switching so that the selected core is already at the same potential as the read power supply when the selected core is switched to the read power supply. Power supply transition. By performing such switching control, fluctuations in the read power supply potential are prevented, and at the same time, malfunctions in the core during the read operation are prevented.
[0116]
[Embodiment 15]
Next, an embodiment of an arrangement of cell array blocks in the core and an efficient and preferable arrangement relationship of address bus lines, data bus lines, power supply lines, etc. will be described. 42 and 43 are examples of such a preferable layout.
When one core is composed of n array blocks, one core is composed of 1 row × n columns as shown in FIG. 42, or 2 rows × (n / 2) columns as shown in FIG. Consists of.
[0117]
As shown in FIG. 43, when one core is configured with two rows, there is a merit because local bus lines (including address lines, data lines, and power supply lines) in the core can be made common between facing blocks. The layout area of bus lines (including address lines, data lines, and power supply lines) increases. Whether to select the one-line or two-line configuration takes into consideration the entire layout area. If one core is composed of three or more rows, the length of the common bus line increases, so the layout is not minimized.
When one core is composed of two rows, if n is an odd number, 2 rows × [(n + 1) / 2]
It becomes a column structure.
[0118]
A common bus common to each core is wired in the row direction, and a switch circuit (address line switch, data line switch, and power line switch) is arranged in each core, so that the shortest distance between the common bus and each core Thus, since the address, data, and power supply lines are wired, the layout is efficient. Furthermore, as the switch circuit of each core, an address line switch, a data line switch, and a power line switch are arranged in the row direction, so that the layout becomes a denser pattern. The local address line switch of each core is arranged in parallel with the common bus line, or is arranged below the common bus line when multilayer wiring is used.
[0119]
When the one-row core shown in FIG. 42 is compared with the two-row core shown in FIG. 43, the layout of the common bus line and the switch circuit is smaller in the one-row core, but the local bus line is longer.
Whether to select the one-row configuration or the two-row configuration is determined by the common bus line length + local bus line length of the entire chip. This point will be specifically described below.
[0120]
As shown in FIG. 1, the total number of cores is m (total), the number of blocks in one core is n, the length of one block in the row direction is x (Block), and the length of one block in the column direction Let y be (Block). At this time, the common bus line length + local bus line length l (one row) in the one-row configuration core is expressed by the following formula 2.
[0121]
[Expression 2]
l (1 line) = y (Block) * n * m (total) + x (Block) * m (total)
[0122]
On the other hand, the common bus line length + local bus line length l (two rows) in the two-row configuration core is expressed by the following formula 3.
[0123]
[Equation 3]

[0124]
These magnitude relationships are (1/2) * n * y (Block) <x (Block) where l (1 row) <l (2 rows), and a 1 row configuration is advantageous. In the opposite case, a two-row configuration is advantageous.
However, the above equation is for the case where the number of blocks n is an even number. When n is an odd number, (n + 1) may be substituted for n.
With the above configuration, it is possible to realize the densest layout in the free bank method and the free core method.
[0125]
[Embodiment 16]
FIG. 44 shows an embodiment in which the regulator power supply 260a shown in FIG. 36 is modified. The operational amplifiers OP1 and OP2 are all arranged so that VINTER = Vref when the detection voltage VINTER by the resistors R1 and R2 connected to the power supply output terminals is fed back and the internal power supply potential VINT reaches a predetermined control level. To control. Diode-connected transistors QN42 and QN43 provided in the operational amplifiers OP1 and OP2 are for leakage. Two drive circuits 401 and 402 having different driving capabilities for supplying current to the load capacitance by the charge pump circuit output VCP are provided with reference to the current of the current source PMOS transistor QP41 controlled by the operational amplifier OP1.
[0126]
The PMOS transistors QP48 and QP49 of the drive circuits 401 and 402 are connected to the node N3 of the current source selectively controlled by the operational amplifier OP1 by the switch circuits 403 and 404 or the terminal of the boost voltage VCP. The gates of the NMOS transistors QN46 and QN47 of the drive circuits 401 and 402 are selectively connected to the output node N2 of the operational amplifier OP2 or the ground potential by the switch circuits 405 and 406, respectively.
[0127]
The switch circuits 403 and 405 are controlled by a control signal SEL1 and a complementary signal SEL1B. The switch circuits 404 and 406 are controlled by a control signal SEL2 and a complementary signal SEL2B.
When the control signal SEL1 = "H", the PMOS transistor QP48 and the NMOS transistor QN46 of the drive circuit 401 are controlled by the nodes N3 and N2, respectively, to supply current from the voltage VCP to the output terminal. When the control signal SEL2 = "H", the PMOS transistor QP49 and the NMOS transistor QN47 of the drive circuit 402 are controlled by the nodes N3 and N2, respectively, to supply current from the voltage VCP to the output terminal. It is also possible to activate both the drive circuits 401 and 402 by setting both the control signals SEL1 and SEL2 to “H”.
[0128]
For example, it is assumed that the drive capability of one drive circuit 401 is designed to be twice that of the other drive circuit 402. These drive circuits 401 and 402 are switched by control signals SEL1 and SEL2 according to the load capacity. In other words, the drive circuit 402 is activated in the operation mode with a small load capacity, and the drive circuit 401 is activated in the operation mode with a large load capacity, thereby preventing a delay in transition of power supply potential, oscillation, and the like. can do.
[0129]
The effectiveness of such switching control of the driving capability of the power supply will be specifically described below. FIG. 45 shows the relationship between the load capacity (C) and drive capability (W) ratio of the power supply and the power supply transition time. If C / W capable of the earliest transition is X, and C / W <X, a transition delay due to oscillation or the like occurs. A stable operation is performed when C / W> X, but the transition time increases proportionally as C / W increases. The reason why C / W gradually deviates from the theoretical line as it approaches X is that it takes time to stabilize due to overshoot or undershoot of the internal power supply. In order to make the internal power supply transition stably within a certain transition time T1, it is necessary to set X <C / W <X1. Therefore, when the load capacity C has a plurality of different values, it is effective to switch and control the driving capability W.
[0130]
Specifically, in the power supply regulator circuit of FIG. 44, when the control signal SEL1 is “H”, the load capacitance is doubled compared to when SEL2 is “H”. In FIG. 44, assuming that there is only one drive circuit, the drive capability is set so that C / W = X1 because the power supply transitions at time T1 based on the load condition of the control signal SEL2 = “H”. Suppose that Then, under the load condition of the control signal SEL1 = “H”, C / W becomes 2 · X1, which greatly exceeds the specified transition time. Therefore, as described above, by preparing a drive circuit 401 selected by the control signal SEL1 that is different from the drive circuit 402 controlled by the control signal SEL2, and setting its drive capability to twice that of the drive circuit 402, Regardless of the load capacity, a prescribed transition time can be obtained.
[0131]
This embodiment is also effective against fluctuations in the external power supply level. FIG. 46 shows the relationship between the C / W of the internal power supply and the power supply transition time for different external power supply levels. That is, when the external power supply is low, C / W that can make the fastest transition without causing oscillation is X, whereas when the external power supply is high, this is X ′. This shows that even if the load capacity and drive capability of the internal power supply are the same, the drive transistor's capability is high when the external power supply is high, and charge / discharge is accelerated, so the internal power supply tends to oscillate. Yes. When it is desired to transition the internal power supply at time T1, X <C / W <X1 when the external power supply is low, whereas X ′ <C / W <X1 ′ when the external power supply is high, and C Slide to the higher / W.
[0132]
Therefore, if the drive capability is not variable, the drive capability and the load must be set in the range of X ′ <C / W <X1 in order to satisfy the transition condition at the time T1 during which oscillation does not occur. The allowable range is narrow. On the other hand, the setting range can be widened by switching and controlling the driving capability as shown in FIG. In this case, the output of the external power supply detection circuit or the like is used as the control signals SEL1 and SEL2.
[0133]
[Embodiment 17]
In the embodiments so far, only the flash memory has been described. As shown in FIG. 1, when a large number of cores are arranged in a large-scale flash memory, data bus lines, address bus lines and the like commonly used for the respective cores are usually arranged outside the core area. A similar layout is used not only in a flash memory but also in various semiconductor integrated circuits in which a plurality of functional blocks are arranged. However, as the number of cores and functional blocks increases, the area occupied by the bus line area on the chip increases and the area penalty increases.
[0134]
FIG. 47 shows an embodiment in which such an area penalty can be reduced, and thus the chip size can be reduced. In FIG. 47, a plurality of functional blocks BLKi (i = 0 to 3 in the figure) are arranged in the row (X) direction. Each functional block BLKi may be the same type of memory core circuit as described in the previous embodiment, or may be a logic circuit block other than the memory circuit. That is, the functional blocks BLKi are grouped as a certain block of circuit functions. Each functional block BLKi is formed with a signal line 110 for exchanging signals with the outside.
[0135]
In this embodiment, the common bus line 101 used in common for each functional block BLKi is arranged across the functional blocks BLKi in the X direction on the area of each functional block BLKi. The signal line 110 in each functional block BLKi region is a lower layer wiring, the common bus line 101 is an upper layer wiring formed on the signal line 110 through an interlayer insulating film, and the common bus line 101 is at an appropriate place. A contact 111 is connected to the signal line 110 of each functional block BLKi.
[0136]
By adopting such a layout, the chip size can be reduced as compared with the case where the common bus line region is provided separately from the functional block BLKi region. In addition, a lead-in wiring for drawing the common bus line into each functional block BLKi becomes unnecessary.
[0137]
[Embodiment 18]
FIG. 48 is an embodiment in which the same technique as that of the above-described seventeenth embodiment is applied to the flash memory described in FIG. That is, the cores constituting the cell array of the flash memory are arranged in the X direction as corresponding to the functional block BLKi in FIG. As a decoding circuit (corresponding to the matrix decoder 2 in FIG. 1) that is attached to each core and decodes an address signal, a predecoder 105 that performs core selection, and an output decoded signal of the predecoder 105 are further decoded to generate an internal signal in the core. A row (X) decoder 103 and a column (Y) decoder 104 for selecting the matrix.
[0138]
In this embodiment, a common bus line 102 that is used in common by all the cores is arranged continuously in the X direction on the area of the predecoder 105 attached to each core.
As a result, the chip size can be reduced as compared with the case where the common bus line region is provided outside the core region. In addition, no lead-in wiring for drawing the common bus line into each core region is required.
[0139]
[Embodiment 19]
FIG. 49 shows an embodiment obtained by modifying the embodiment of FIG. The cores are arranged in a matrix, and the cores adjacent in the X direction are line symmetric with each other, and the cores adjacent in the Y direction are also line symmetric with the X decoder 103 and the predecoder 105 in between. It is laid out. The “F” pattern in the figure indicates the symmetry of the core layout. In FIG. 49, the common bus line 102a commonly used by the plurality of cores (00, 01, 02, 03) in the upper portion in the Y direction and the plurality of cores (10, 11, 12, 13) in the lower portion are commonly used. A common bus line 102b to be used is provided.
[0140]
After adopting such a layout, a partly conductive type well region of the decoding circuit of the adjacent core is shared. That is, the core Y decoder 104 adjacent in the X direction has an N well for forming a PMOS transistor and a P well for forming an NMOS transistor. On the other hand, in the example of FIG. The common P well is formed as a single body without being formed. Similarly, for the core predecoder 105 adjacent in the Y direction, of the N well and the P well, the P well is shared.
In this way, the area penalty is further reduced by arranging the cores in a line-symmetric matrix and sharing the wells of the decoder.
[0141]
[Embodiment 20]
In FIG. 49, separate common bus lines 102a and 102b are provided for the upper and lower cores. However, these common bus lines 102a and 102b can be shared. The layout of such an embodiment is shown in FIG. In FIG. 50, the portion of the pre-decoder 105 of the upper and lower cores in the Y direction in FIG. 49 is shown enlarged. Each predecoder 105 is configured by forming a PMOS transistor QP and an NMOS transistor QN in an N well 107 and a P well 106, respectively. As described above, the P wells 106 of the upper and lower predecoders 105 are shared.
[0142]
A common bus line 102 shared by the upper and lower cores is disposed on the boundary region of the predecoder 105 of the upper and lower cores. The common bus line 102 is formed as an upper layer wiring of the signal line 108 disposed in each predecoder 105, and is connected to the signal line 108 through a contact at an appropriate location. In the example shown in the figure, the signal line 108 is an address signal line connected to the gate of each transistor of the predecoder 105. Therefore, the common bus line 102 is also an address bus line.
Thus, by sharing the common bus line with the core, current consumption can be reduced compared to the embodiment of FIG.
[0143]
[Embodiment 21]
FIG. 51A and FIG. 51B show an embodiment obtained by modifying the embodiment of FIG. 49, and shows the cores 01 and 11 adjacent to each other in the Y direction in FIG. In FIG. 49, upper and lower core predecoders 105 in the Y direction are adjacent to each other in the Y direction. In contrast, in this embodiment, the upper and lower core predecoders 105 are arranged in the X direction. If the area of the two predecoders 105 of the upper and lower cores in FIG. 49 is not substantially changed, in the case of FIG. 51A, the area of one predecoder 105 is approximately 1 / dimension in the X direction compared to that of FIG. 2. The dimension in the Y direction is approximately doubled.
[0144]
In addition, as shown in FIG. 51B, in this embodiment, the transistors QP and QN of the predecoder 105 are arranged below the common bus line 102. In this case, the common bus line 102 can be directly connected to the gate electrode 109 of the transistor through a contact. As a result, the area penalty can be further reduced.
However, in this embodiment, the two predecoders 105 shown in FIG. 51Aa are not line symmetric in the X direction, so that the decode output lines 201 from the respective predecoders 105 are drawn in the same X direction, and the upper and lower cores Y The decoder 104 is entered. Therefore, the decode output lines 201 are concentrated at the input section to the Y decoder 104.
[0145]
[Embodiment 22]
52A and 52B are embodiments in which the concentration of the decode output lines 201 in the embodiment of FIGS. 51A and 51B is avoided. 51A and 51B, the upper and lower core predecoders 105 are laid out so as to be line symmetric in the X direction, and the upper and lower core main body portions and the Y decoder 104 are laid out so as to be rotationally symmetric. It is a thing.
[0146]
At this time, the decode output line 201 of each Y decoder 105 is drawn to both sides in the X direction and enters the Y decoder 104 as shown in FIG. 52A. Therefore, compared to the embodiment of FIGS. 51A and 51B, the concentration of wiring on the Y decoder 104 is alleviated, and the area penalty can be reduced accordingly.
[0147]
[Embodiment 23]
Next, an embodiment in which the common bus line arrangement method described in the embodiment of FIGS. 52A and 52B is applied to a redundant circuit type flash memory will be described. In a flash memory using a stacked gate structure nonvolatile memory cell that performs electrical writing and erasing using a tunnel current, a row in which at least one word line is short-circuited to a channel in a block that is a unit of batch erasing. If there is a defect, the block becomes defective. This is because the erase voltage at the time of erasing data is not applied to all blocks due to a short of one word line. Therefore, block redundancy is used in which redundant blocks are provided for such defects to repair the defects.
[0148]
As described in the first embodiment, in the case of configuring a core by a set of a plurality of blocks, in order to realize block redundancy, a redundant block is not attached to the core, and an original decoder circuit is provided. It is preferable that an arbitrary block can be substituted. FIG. 53 shows a layout of an embodiment having such redundant blocks.
[0149]
FIG. 53 shows two cores each composed of a plurality of blocks. As described above, the redundant block 301 is provided with the X decoder 302, the Y decoder 303, and the predecoder 304 at the preceding stage independently of the core. The predecoder 105 for the core body and the predecoder 303 of the redundant block 301 are laid out in the same relationship as the two predecoders of the upper and lower cores of the embodiment of FIGS. 52A and 52B.
[0150]
That is, the predecoder 105 on the core side and the predecoder 304 on the redundant block 301 side are arranged in line symmetry in the X direction in the region between the main body core and the redundant block 301. A common bus line 305 is arranged on the regions of these predecoders 105 and 304 so as to be continuous in the X direction. The common bus line 305 is connected to the input signal lines of the predecoders 105 and 304 through contacts, as in the previous twenty-second embodiment. Similarly to the case of FIG. 52A, the decode output lines 201 and 306 of the predecoders 105 and 304 are distributed and connected to the Y decoders 104 and 303 of the core and redundant block 301, respectively.
As described above, even in the redundant circuit type flash memory, the area penalty can be effectively reduced by considering the arrangement of the common bus lines.
[0151]
[Embodiment 24]
Next, an embodiment of a preferred sense amplifier circuit applied to a flash memory capable of simultaneously performing data writing / erasing and data reading as described in the first embodiment will be described. Normally, a data read system used for this type of flash memory is configured as shown in FIG. A data line DL selected by the column gate 402 from the cell array 401 enters one input terminal of the data comparison circuit 403. A reference data line REF connected to the other input terminal of the data comparison circuit 403 is connected to a constant current source 405 via a dummy column gate 404. Thereby, the data “0” and “1” are discriminated by comparing the current of the data line DL and the current of the reference data line REF.
[0152]
For example, assume that the flash memory is a NOR type. At this time, as shown in FIG. 56, in the memory cell, electrons are accumulated in the floating gate FG by hot electron injection from the drain side, and the threshold voltage is high (for example, “0” state). Further, by discharging electrons of the floating gate FG to the channel side, a state with a low threshold voltage (for example, “1” state) is obtained. Data is discriminated by comparing and detecting the presence or absence of current draw due to the difference in threshold voltage by the data comparison circuit 403. For example, as shown in FIG. 55, the data comparison circuit 403 is composed mainly of a CMOS differential amplifier DA.
[0153]
In the data write / erase operation, a confirmation read operation for confirming the write or erase state is performed. Generally, a constant current source used for this confirmation read can be shared with that used for normal data read. is there. However, in a flash memory that can perform data writing / erasing and data reading simultaneously, normal data reading and confirmation reading are performed asynchronously. In this case, since it is necessary to equalize the data line, it is difficult to share the constant current source. Data line equalization means that the data line DL and the reference data line REF shown in FIG. 54 are short-circuited and initialized to the same potential state in order to speed up data reading.
[0154]
Therefore, normally, constant current sources for a normal data read system and a confirmation read system are prepared separately, but this leads to another problem. That is, if each constant current source varies, the threshold voltage of the memory cell detected in the confirmation read operation and the threshold voltage detected in the normal read operation will be different, which may cause erroneous reading. Because it becomes.
[0155]
Therefore, in this embodiment, the read system configuration is such that the constant current source in the normal read operation and the constant current source in the confirmation read operation have the same current value. The readout system configuration is shown in FIG. Here, a read system of two cores, core 0 in data write / erase mode and core 1 in data read mode, is shown. The bit lines of 401a and 401b of each core are selected by column gates 402a and 402b. The output of each system is arbitrarily switched by a data line switch 407. The data lines DLa and DLb which are selected and enabled by the data line switch 407 enter the data comparison circuits 403a and 403b, respectively. The reference signal lines REFa and REFb of the data comparison circuits 403a and 403b are connected to a common constant current source 406 via dummy column gates 404a and 404b, respectively.
[0156]
The constant current source 406 is configured as shown in FIG. The reference constant current source 501 includes a PMOS current mirror using a pair of PMOS transistors QP1 and QP2, a reference current source transistor T0 connected to the PMOS transistor QP1 via a switching NMOS transistor QN1, and a switching NMOS transistor QN2 connected to the PMOS transistor QP2. The NMOS transistor QN3 is connected via The NMOS transistors QN1 and QN2 are driven by the control signal SW, and the activation and deactivation of the reference constant current source 501 are controlled. The NMOS transistor QN3 is diode-connected through the NMOS transistor QN2.
[0157]
A current I0 flowing through the reference current source transistor T0 is a reference current. If the PMOS transistors QP1 and QP2 have the same element parameters, the reference current I0 flows through the NMOS transistor QN3 due to the action of the PMOS current mirror. Two current source NMOS transistors T1 and T2 driven in parallel by the potential of the output node N of the reference constant current source 501 determined by the reference current I0 are provided. These two NMOS transistors T1 and T2 have the same element parameters, and their drains are connected to the reference signal lines REFa and REFb, respectively.
[0158]
Thereby, since the same current flows through the current source transistors T1 and T2, even if the set current value is deviated, the current values of the reference signal lines REFa and REFb in the normal read operation and the confirmation read operation are always the same. A high read margin can be obtained.
[0159]
In this embodiment, as the reference current source transistor T0 of the reference current source 501, preferably, the same electrically rewritable nonvolatile memory cell as that used in the memory cell array is used. In this case, by rewriting the reference current source transistor T0, the reference current value I0 can be changed, and accordingly, the current values of the reference signal lines REFa and REFb can be changed. Thus, even if the reference current value I0 is changed, the current values of the reference signal lines REFa and REFb are the same.
As described above, according to this embodiment, the currents flowing through the reference signal lines of the normal read system and the confirmation read system can always be kept the same, and the read margin can be reliably prevented from being lowered or erroneously read. become.
[0160]
【The invention's effect】
As described above, according to the present invention, a memory cell array is constituted by a plurality of cores with a flash memory erase unit as a block and a block of one or more blocks as one core, and an arbitrary core is selected and data is selected. It is possible to obtain a free-core flash memory that executes writing or erasing and at the same time allows data reading by any other core. As in the prior art, the range in which the data write / erase operation and the data read operation can be executed simultaneously is not fixed, and the flash memory has a high degree of freedom.
Further, according to the present invention, there is provided a free bank type flash memory capable of arbitrarily setting a bank size by using a bank setting memory circuit as a first bank and a remaining core as a second bank. As a result, while a data write or erase operation is being performed on an arbitrary block in the first bank, data can be read from the second bank.
[Brief description of the drawings]
FIG. 1 is a diagram showing a main configuration of a flash memory according to an embodiment of the present invention.
FIG. 2A is a diagram showing a configuration of an address line switch circuit according to the same embodiment;
FIG. 2B is a diagram showing another configuration of the address line switch circuit;
FIG. 3 is a diagram showing a configuration of a circuit that deactivates an address line in the non-selected core according to the embodiment;
FIG. 4 is a diagram showing a configuration of a data line switch circuit according to the same embodiment;
FIG. 5 is a diagram showing a configuration of a power line switch circuit according to the embodiment;
FIG. 6 is a diagram showing a configuration of an address buffer according to the same embodiment;
FIG. 7 is a diagram illustrating a configuration of a core block register and a core busy output circuit according to the embodiment;
FIG. 8 is a diagram showing a specific configuration of a core of the memory cell array according to the same embodiment;
FIG. 9 is a diagram showing a specific configuration of the cell array and column gate of the same embodiment;
FIG. 10 is a diagram illustrating a configuration of an output circuit unit according to the embodiment;
FIG. 11 is a diagram for explaining an operation of selecting a plurality of cores in the embodiment;
FIG. 12 is a diagram showing a configuration of a bank configuration ROM circuit used in an embodiment of a free bank system.
FIG. 13 is a diagram showing a configuration of one bank busy output circuit of the same embodiment;
FIG. 14 is a diagram showing a configuration of another bank busy output circuit according to the embodiment;
FIG. 15 is a diagram illustrating a configuration of a core busy output circuit according to the embodiment;
FIG. 16 is a diagram showing an example of a bank configuration circuit according to the embodiment;
FIG. 17 is a diagram illustrating another example of a bank configuration circuit.
FIG. 18 is a diagram illustrating another example of a bank configuration circuit.
FIG. 19 is a diagram illustrating another configuration example of the bank configuration circuit.
FIG. 20 is a diagram showing another configuration example of the bank configuration ROM circuit.
FIG. 21 is a diagram illustrating a configuration of a core busy output terminal switching circuit in an embodiment in which high-speed reading is performed;
FIG. 22 is a diagram showing a configuration of an input signal switching circuit to a power line switch circuit in an embodiment that similarly performs high-speed reading.
FIG. 23 is a diagram showing a configuration of an address buffer in the embodiment in which high-speed reading is performed in the same manner.
FIG. 24 is a control timing chart of the address buffer according to the embodiment;
FIG. 25 is a diagram showing a configuration of an output switching circuit unit according to the same embodiment;
FIG. 26 is a timing chart showing a high-speed read operation in the embodiment.
FIG. 27 is a diagram showing a voltage relationship in each operation mode of the memory cell.
FIG. 28 is a diagram showing a voltage application system in each operation mode of a memory cell.
FIG. 29 is a diagram showing a configuration of a power supply system according to another embodiment.
FIG. 30 is a diagram showing a configuration of a power line switch circuit in the same embodiment;
FIG. 31 is a diagram showing a configuration of a charge pump control circuit according to the same embodiment;
32 is a diagram showing a configuration of a power line switch circuit according to the embodiment; FIG.
33 is a diagram showing a configuration of another power supply line switch circuit of the embodiment; FIG.
FIG. 34 is a diagram showing a configuration of a regulator type power supply control circuit to which a dummy load is added.
FIG. 35 is a diagram showing another configuration example of a regulator-type power supply control circuit loaded with a dummy load.
FIG. 36 is a diagram showing a configuration of a regulator-type power supply control circuit capable of switching drive capability.
FIG. 37 is a diagram showing another configuration of the regulator-type power supply control circuit capable of switching the driving capability.
38 is a diagram showing a configuration of a power line switch circuit obtained by modifying the configuration of FIG. 30;
FIG. 39 is a diagram illustrating a busy output circuit for all cores.
FIG. 40 is a waveform diagram for explaining a problem of power supply switching.
FIG. 41 is a waveform diagram for explaining an embodiment of a preferred power supply switching system;
FIG. 42 is a diagram showing a preferred core layout example.
FIG. 43 is a diagram showing another preferred core layout example.
FIG. 44 is a diagram showing another embodiment of the power supply circuit.
FIG. 45 is a diagram showing the relationship between the load capacity and drive capability of the power supply circuit and the transition time.
FIG. 46 is a diagram showing the relationship between the load capacity and drive capability of the power supply circuit and the transition time in relation to the external power supply.
FIG. 47 is a diagram showing a layout of a semiconductor device according to another embodiment.
FIG. 48 is a diagram showing a layout of a flash memory according to another embodiment.
FIG. 49 is a diagram showing a layout of a flash memory according to another embodiment.
50 is a diagram showing a layout of an embodiment obtained by modifying the embodiment of FIG. 49. FIG.
51A is a diagram showing a layout of another embodiment obtained by modifying the embodiment of FIG. 49. FIG.
FIG. 51B is a diagram showing a layout of a predecoder unit according to the embodiment;
FIG. 52A is a diagram showing a layout of another embodiment obtained by modifying the embodiment of FIG. 49;
52B is a diagram showing a layout of a predecoder unit in the embodiment. FIG.
FIG. 53 is a diagram showing a layout of a flash memory according to another embodiment having a redundant book.
FIG. 54 is a diagram showing a general read system of a flash memory.
FIG. 55 is a configuration example of a data comparison circuit used in the readout system.
FIG. 56 is a diagram showing a write / erase operation of a memory cell.
FIG. 57 is a diagram illustrating a read system according to the embodiment;
FIG. 58 is a diagram showing a configuration of a constant current source used in the readout system.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Decoding circuit, 3 ... Address line (and power supply line) switch circuit, 4 ... Local data line, 6a ... Read address bus line, 6b ... Write / erase address bus line, 7a ... Read Data bus line, 7b ... Data bus line for write / erase, 8a ... Power supply line for read, 8b ... Power supply line for write / erase, 10 ... Address buffer, 11a ... Sense amplifier circuit for read, 11b ... Sense amplifier circuit for verify , 12a: read power supply, 12b: write / erase power supply, 14: interface circuit, 15: write / erase control circuit, 32a, 32b: core selection circuit, 42: core block register, 43: core busy output circuit.

Claims (9)

A memory cell array having electrically rewritable nonvolatile memory cells, a memory cell range as a unit of data erasure as one block, a set of one to a plurality of blocks as one core, and a plurality of cores arranged;
Core selecting means for selecting an arbitrary number of cores for data writing or erasing among the plurality of cores;
Data writing means for writing data to the selected memory cell in the core selected by the core selecting means;
Data erasing means for erasing data of a selected block in the core selected by the core selecting means;
Data reading means for reading data from memory cells in the core not selected by the core selecting means;
A first data bus line arranged in common for the plurality of cores and used for reading data;
A first sense amplifier circuit connected to the first data bus line and used for reading data;
A second data bus line arranged in common for the plurality of cores and used for data writing or erasing;
A semiconductor device comprising: a second sense amplifier circuit connected to the second data bus line and used for verify reading at the time of data writing or erasing . A first address bus line arranged in common for the plurality of cores and used for reading data;
A second address bus line arranged in common for the plurality of cores and used for data writing or erasing ;
The semiconductor device according to claim 1, wherein a. A decoding circuit that is provided for each core and enables simultaneous execution of data writing or erasing in an arbitrary core and data reading in another core;
The address signal of the first address bus line and the address signal of the second address bus line provided for each core and depending on whether each core is in a data read mode or a data write or erase mode Address line switch circuit for switching to supply to the decoding circuit,
Provided for each core, the first data bus line and the second data bus line are switched according to whether each core is in a data read mode or a data write or erase mode. 3. A semiconductor device according to claim 2 , further comprising a data line switch circuit connected to the data line in the semiconductor device. When data is read, the input address signal is passed through to the first address bus line. When data is written, the input address signal is latched and input to the second address bus line. When data is erased, a counter circuit is provided. 4. The semiconductor device according to claim 2 , further comprising an address buffer for supplying the internal address signal generated in step ( 2 ) to each of the second address bus lines. A core block register that is provided for each block in each core and holds a data write or erase flag during a data write or erase operation when a data write or erase command is input to the block, and the core block register a data write or erase flag watching the semiconductor device according to any one of claims 1 to 4, characterized in that it has a, a Koabiji output circuit issuing an Koabiji output as a data write or erase enable signal. In each address line switch circuit, when a data read request is input to the core while the core is selected as a data write or erase mode, the core is in a data write or erase mode. 4. The semiconductor device according to claim 3, further comprising a data polling signal generation circuit for generating a data polling signal to be notified to the outside. An arbitrary number of cores among the plurality of cores are selected as a first bank, and a bank setting storage circuit for setting the remaining cores as second banks is provided, and data writing or writing is performed on one of the first and second banks. the semiconductor device according to any one of claims 1 to 6, wherein during the other by which enables data reading operation is performed erase operation. The plurality of cores include a plurality of blocks arranged in one or two columns in the column direction and in the row direction in each core, and the first and second address bus lines, and the first and second 3. The semiconductor device according to claim 2, wherein the second data bus line is wired in a row direction in parallel with the array of the cores. The plurality of cores includes a plurality of blocks arranged in one or two columns in a column direction and in a row direction in each core, the first and second address bus lines, and the first and first columns. Two data bus lines are wired in the row direction in parallel with the array of cores, and the address line switch circuit and the data line switch circuit are arranged in the row direction in parallel with the array of cores. The semiconductor device according to claim 3 .

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