JP4046744B2 - Switching element failure detection circuit - Google Patents

Description

  The present invention relates to a failure detection circuit that is incorporated in a transmission unit of a time-division transmission / reception track circuit device of a railway and is suitable for detecting a failure of a switching element of a transmission line, and more specifically, a state in which diodes are arranged in parallel. The present invention relates to a switching element failure detection circuit that performs failure detection for a pair of switching elements.

FIG. 8 is a schematic configuration diagram of a railway time-division transmission / reception track circuit device. Such a device is incorporated in a train detection device using a track circuit (for example, Non-Patent Document 1 and Patent Document 1). See).
This time division transmission / reception type track circuit device 20 detects in which section of the sections T1, T2, T3,... A transmission unit 21 and a reception unit connected to each section of the track 10 with a cable or the like, and a control unit that performs operation control thereof are provided.

Among them, the transmission unit 21 is provided with an amplification unit 22 having an AC signal source 31 and a switching unit 23 having a transformer 32, a switching element pair 33, and a transformer 34.
The AC signal source 31 continuously outputs the AC transmission signal I1, and a typical example of the AC transmission signal I1 has a sine wave waveform, a frequency of 120 Hz, and a voltage of 100V to 200V. The current is 200 mA to 400 mA.
The transformer 32 is connected to an AC signal source 31 on the primary side so that an AC transmission signal I1 flows. The primary side and the secondary side are insulated from each other, and a typical turns ratio is 1: 1. In this case, a typical example of the line current I2 on the secondary side is the same as the AC transmission signal I1 described above. Typical characteristics of the transformer 32 are an inductance of several H and a pure resistance of several tens of Ω.

The primary side of the load-side transformer 34 is connected to the secondary side of the transformer 32 via a pair of lines (lines). For example, the section T1 of the track 10 serving as the load 35 is connected to the secondary side of the transformer 34 via a cable. The load current I3 corresponding to the line current I2 is supplied to the load 35. The typical characteristic of the equivalent circuit that combines the transformer 34 and the load 35 is that the impedance is 100 to 300Ω∠70 ° to 80 ° (@ 120 Hz), but the resistance value varies greatly depending on whether or not the train enters.
A switching element pair 33 is inserted and connected to the above line pair, and when the switching element pair 33 is turned on and becomes conductive, the circuit 32 makes a circuit of the transformer 32, the switching element pair 33, and the transformer 34 to make a line current I2. And the load current I3 flows to the load 35. When the switching element pair 33 is turned off and the circuit is cut off, the transformer 34 is disconnected from the transformer 32 by the switching element pair 33 and the line current I2 does not flow to the transformer 32. The load current I3 does not flow through 35 as well.

  A plurality of pairs of switching element pairs 33, transformers 34, and loads 35 connected to the secondary side of the transformer 32 are provided and distributed to the sections T1, T2, T3,. It operates in a time division manner according to the signals S1, S2, S3,. For example (see the short wave line in FIG. 8), the pair of switching elements 33 having the section T1 as the load 35 is turned on (conductive) or turned off according to whether the command value of the control signal S1 is on or off. The pair of switching elements 33 having the section T2 as the load 35 is turned on / off in response to the on / off of the command value of the control signal S2, and the section T3 is connected to the load 35. The pair of switching elements 33 to be turned on / off in response to the on / off of the command value of the control signal S3, and the control signals S1, S2, S3,. The ones that are turned on are switched in order.

  When the load current I3 flows in the section T1, the sufficiently large load current I3 reaches the receiving unit unless the train 11 enters the section T1 (see the long wave line in FIG. 8). When the train 11 enters T1, since the left and right rails are short-circuited by the axle of the train 11 and the like in the section T1, the load current I3 reaching the receiving unit is attenuated. Can be detected. The presence or absence of a train is similarly detected for other track sections, but the train can be detected without confusing the sections by time division.

  FIGS. 9A and 9B relate to a conventional switching element failure detection circuit 30 incorporated in such a time division transmission / reception type track circuit device 20, wherein FIG. 9A is a basic circuit diagram and FIG. 9B is a discrimination table. is there.

  The switching element failure detection circuit 30 (see FIG. 9A) includes a current detection circuit 36 and a failure determination unit 37 in addition to the AC signal source 31, the transformer 32, the switching element pair 33, the transformer 34, and the load 35 described above. It has. The current detection circuit 36 is connected to a current transformer attached to the insertion line of the switching element pair 33, detects the line current I2 with the current transformer, and performs filtering such as full-wave rectification and smoothing on the detected current. To obtain an average current, and further compare the current value with a threshold value to obtain a binary detection value J2.

  The failure determination unit 37 receives the detection value J2 of the line current I2 and the command value of the control signal S1, and determines whether the switching element pair 33 is normal or failure based on these input values. Yes, for example, it is classified according to whether the command value of the control signal S1 is OFF or ON and whether the detection value J2 is no current or there is a current, and it is determined in advance whether each case is normal or failure By referring to the table, it is determined whether or not there is a failure (see FIG. 9B).

  Such failure determination is provided separately on the secondary side of the transformer 32, and both have one end connected to the secondary side of the transformer 32 and the other end connected to the load side, and the on / off control signal S1 is common. The pair of switching elements 33a and 33b is made up of an open / close member such as a relay, and if the failure detection related to the switching element pair 33 is performed together without separating the switching elements 33a and 33b, it has been made accurately. .

JP-A-2-234875 Published by Hiroshi Yoshimura "Signal 17th Edition", published by Koyusha Co., Ltd., p.732-p.733

By the way, in the railway field, semiconductor elements are often used instead of relays as circuit elements, and semiconductor elements such as MOS-FETs are also used in the switching elements 33a and 33b of the conventional switching element failure detection circuit 30 described above. It is possible to do. However, the body diode D1 is parasitic and associated with such a semiconductor element, and the switching elements 33a and 33b both have a parallel diode (see the circuit diagram of the main part in FIG. 10A).
The presence of the body diode D1 (parallel diode) is hidden by the switching element in the conducting state and does not affect the flow of the line current I2 in the case of an on-failure (short-circuit failure, failure that continues to take on state / closed state / conducting state). However, in the case of an off-failure (open failure, failure that continues to take off state / open state / cut-off state), it becomes obvious and affects the flow of the line current I2.

  For example, when the switching element 33a is normally turned on when the command value of the control signal S1 is on but the switching element 33b is not turned on due to an off failure (continuation of shutoff) (see FIG. 10A), the body of the switching element 33b A half-wave line current I2 flows through the diode D1 (see FIG. 10B). For this reason, if there is no body diode D1, it is easy to determine whether or not the line current I2 flows “full wave” or “none”, but the presence of the body diode D1 causes the line current I2 to flow. Since it is necessary to determine the presence / absence of current even when the flow of current is half-wave, it is difficult to discriminate and even if discrimination is possible, the reliability of discrimination is reduced.

  More specifically, when the threshold value of the current detection circuit 36 is set so that the detection value J2 becomes “none” when the line current I2 is “half wave”, a conventional discrimination table (see FIG. 9B). But it can detect all kinds of failures. That is, (see FIG. 10C), assuming that the AC transmission signal I1 is “present” and the switching elements 33a and 33b are both normal and the command value of the control signal S1 is ON (state 1), Since the line current I2 is “full wave” and the detection value J2 is “present”, the switching element pair 33 is determined to be “normal”. When the switching elements 33a and 33b are both normal and the command value of the control signal S1 is OFF (OFF) (state 2), the line current I2 is “none” and the detection value J2 is “none”. 33 is determined to be “normal”.

When the switching element 33a is ON failure (continuation of conduction), the switching element 33b is normal and the command value of the control signal S1 is ON (state 3), the line current I2 becomes “full wave”, and the detection value J2 is Since it is “present”, the switching element pair 33 is determined to be “normal” instead of a failure. In this case (Note 1), the command value is on, so the problem of the circuit function is caused even if the switching element pair 33 remains on. As described later, when the command value of the control signal S1 is turned off (state 6), a failure is detected.
When the switching element 33a is off-failure (continuation of interruption), the switching element 33b is normal and the command value of the control signal S1 is ON (state 4), the line current I2 becomes “half wave” and the detection value J2 is Since it is “none”, the switching element pair 33 is determined to be “failure”.

When the switching element 33a is off failure (continuous interruption), the switching element 33b is normal, and the command value of the control signal S1 is OFF (state 5) (state 5), the line current I2 becomes “none” and the detection value J2 is “ “No”, the switching element pair 33 is determined to be “normal” rather than a failure. In this case (note 2), there is a problem in the function of the circuit even if the switching element pair 33 remains off because the command value is off. If the command value of the control signal S1 is turned on (state 4), a failure is detected.
When the switching element 33a is ON failure (continuation of conduction), the switching element 33b is normal and the command value of the control signal S1 is OFF (state 6) (state 6), the line current I2 becomes “half wave” and the detection value J2 is Since it is “none”, the switching element pair 33 is determined to be “failure”.

  In this way, if the detection value J2 is set to “None” not only when the line current I2 is really “None” but also “Half wave”, it is possible to detect one type of failure. When setting the threshold value of the current detection circuit 36, etc., it is necessary to distinguish between the full-wave state and the half-wave state so that the half-wave state where the halfway current flows is not “present” but “absent”. Compared to the conventional case where it was only necessary to distinguish between the state of full wave and the state of no wave, the allowable range of the setting value is narrow, and taking into account various fluctuation factors such as load fluctuation and secular change, the setting that meets expectations can be ensured Therefore, the reliability of discrimination is reduced.

  In this way, when one side of the switching element pair 33 is off-failed (continuous interruption), a “half-wave” line current I2 flows through the body diode D1, which makes it difficult to grasp the failure state. This is a problem when semiconductor elements are employed as the switching elements 33a and 33b of the switching element failure detection circuit 30. Therefore, even if the switching elements 33a and 33b have a parallel diode D1 and the line current I2 flows in a “half-wave” state, it is improved so that failure detection can be performed reliably. One challenge.

In addition, the conventional switching element failure detection circuit 30 detects the AC signal by rectification or filtering processing, and thus has a dissatisfaction such that the circuit scale is increased and the response of failure detection is delayed. Therefore, it is a second problem to reduce the circuit scale and speed up the response of failure detection.
Further, there is a problem that it is difficult to detect a failure with high accuracy because the load 35 varies depending on the approach condition of the train 11 in the corresponding section of the track 10, and the load current I3 and further the line current I2 vary accordingly. Therefore, the third problem is to improve the accuracy of failure detection by eliminating / releasing the influence of load fluctuations.

  The switching element failure detection circuit of the present invention (Solution 1) was created to solve such a problem, and a transformer in which an AC signal source that outputs an AC transmission signal is connected to the primary side, Provided separately on the secondary side of this transformer, each one is connected to the secondary side of the transformer and the other end is connected to the load side to turn on / off (on state / off state, closed state / open state, conduction state / shut off) Switching element failure detection circuit comprising a pair of switching elements that share a common control signal (that is, the control signals are the same or equivalent) and a failure determination unit that determines the presence or absence of a failure associated with the switching element pair The switching elements each include a parallel diode, and a direct current check current is caused to flow in the reverse direction of the parallel diode through a path that passes through the switching element and removes the transformer and the load. And at least when the switching element is in the ON state, the verification current flows in the reverse direction and makes a round of the path). The failure determination is performed based on the detected value of the verification current and the command value of the control signal.

The switching element failure detection circuit according to the present invention is (the solution means 2), the switching element failure detection circuit of the solution means 1, wherein each of the check circuits is provided with a current reducing resistor, The failure determination unit is as follows.
That is, in addition to detecting a constant state in which the current equal to or higher than the threshold continues for the verification current, an alternating state in which the current flows up and down, and a zero state in which the current hardly flows, Detecting a delay state in which the time until the verification current exceeds the threshold when the control signal transitions from OFF to ON is longer than the period of the AC transmission signal, and determining a failure according to these states Is supposed to do.

  The current reducing resistance is determined so that the resistance value satisfies the following two conditions. One of the two conditions is that when the verification current flows around the secondary side of the transformer, the current change rate of the transient current due to the magnetizing inductance of the transformer is the time elapsed for the verification current at that time. That is, the resistance value of the current reducing resistor is determined so as to increase with time. Further, the remaining of the above two conditions is that when the verification current flows around the secondary side of the transformer, the threshold current is set to the threshold over a period longer than the period of the AC transmission signal. That is, the resistance value of the current reducing resistor is determined so as to be lower.

  In addition, in the switching element failure detection circuit according to the present invention, the failure determination unit may determine which of the switching elements has failed when determining the failure, thereby making it more conventional than the conventional one. Various detailed discrimination results can be obtained.

  In such a switching element failure detection circuit of the present invention (Solution 1), when a switching element of the conventional switching element failure detection circuit having a parallel diode is employed, a conventional AC signal detection circuit is further used. In place of the current detection circuit, a direct current application check circuit in the reverse direction to the parallel diode is provided for each switching element. The second and third problems described above are solved by using the detected value of the verification current flowing through another verification path for failure determination.

  In other words, since a direct current power supply independent of the AC transmission signal and line current is used for checking, even if the load and line current fluctuate, there is little change in the checking current, so stable checking is possible. The third problem of improving the accuracy of fault detection by eliminating and mitigating the influence of fluctuations can be solved. In addition, since the current to be detected in the verification circuit is not direct current but direct current, there is no need for rectification or filtering, so the circuit scale is reduced, the response is faster, the circuit scale is reduced, and the fault detection response The second problem of speeding up can be solved. Furthermore, by providing a check circuit with an independent path for each switching element and allowing a direct current to flow independently for each switching element, it is possible to determine which switching element of the pair of switching elements has failed in failure determination. You can also.

  In the switching element failure detection circuit according to the present invention (solution 2), the current state is classified into “alternate” in addition to “constant” and “zero” when determining the failure. Even if a line current in a half-wave state caused by the presence of the parallel diode flows at the time of failure and the direct current check current becomes an alternating current state due to the influence, the state is distinguished and detected. Therefore, it is possible to solve the first problem that a failure is accurately detected even when a line current flows through the parallel diode.

  Furthermore, a failure can also be detected when a sneak current of the verification current caused by the combination of the presence of the transformer and the direct current verification current (detailed in Example 1 described later) appears. In other words, for the check current when it wraps around, the current change rate of the transient current increases as time passes and falls below the threshold for a long time, so that the check current rises. In addition to being able to detect the delay state of the current, the current state is divided into “delay” in addition to “constant”, “zero”, and “alternating” when determining the failure, so that the verification current can be detected by the verification circuit. Even if it flows out through the secondary side of the transformer, it is possible to accurately grasp the manifestation of the phenomenon. Further, in combination with the use of a DC power supply independent of the AC transmission signal and the line current for checking, it is possible to detect a failure when there is an AC transmission signal and when there is no AC transmission signal.

With regard to such a switching element failure detection circuit of the present invention, specific modes for carrying out this will be described with reference to Examples 1 to 4 below.
The embodiment 1 shown in FIGS. 1 to 4 embodies all the above-mentioned solving means, and is shown in the embodiment 2 shown in FIG. 5, the embodiment 3 shown in FIG. Example 4 is a modification thereof.
In addition, since the same code | symbol was attached | subjected and shown to the component similar to the past at the time of those illustrations, the overlapping description is abbreviate | omitted and it demonstrates below centering on difference with the past.

  A specific configuration of the switching element failure detection circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows the structure of the switching element failure detection circuit 50, where (a) is a basic circuit diagram and (b) is a discrimination table. FIG. 2A is a detailed circuit diagram of the verification circuits 54 to 56, and shows one-round paths (round-path for verification) of the verification currents Ia and Ib in a normal state by two-dot chain lines. Shows the wraparound path of the verification current Ia when the switching element 33a is off and is indicated by a two-dot chain line, and (c) is a waveform example of the verification current Ia and the detection value J3 when the switching element 33a is off.

  The switching element failure detection circuit 50 is different from the conventional switching element failure detection circuit 30 described above in that the switching elements 33a and 33b of the switching element pair 33 both have body diodes D1 (parallel diodes). A point in which verification circuits 51 to 53 are newly provided for the switching element 33a, and a point in which verification circuits 54 to 56 are provided in place of the current detection circuit 36 for the switching element 33b. The failure discriminating unit 37 is expanded to become the fault discriminating unit 57. The AC signal source 31, the transformer 32, the switching element pair 33, the transformer 34, and the load 35 described above are provided so that an AC transmission signal is selectively transmitted according to the control signal S 1. This is the same as the element failure detection circuit 30.

  The check circuits 51 to 53 (see FIG. 1A) are provided with an insulation type DC power source 51, a current detection circuit 52, and a current reducing resistor 53, and are provided for the switching element 33a. 51, the switching element 33a, the current reducing resistor 53, and the current detection circuit 52 are provided in the order of a current path. The transformer 32, the load 35, and the load-side transformer 34 are out of the round circuit for verification. In addition, the voltage application direction of the isolated DC power supply 51 is opposite to the forward direction of the body diode D1 of the switching element 33a. Therefore, if the switching element 33a is turned on and becomes conductive, the direct current check current Ia Flows around the above path (see two-dot chain line). The current detection circuit 52 detects the verification current Ia and binarizes it to generate a detection value J3.

  The check circuits 54 to 56 (see FIG. 1A) include an isolated DC power supply 54, a current detection circuit 55, and a current reducing resistor 56, and are provided for the switching element 33b. 54, the switching element 33b, the current reducing resistor 56, and the current detection circuit 55 are provided in the order of a current path. The transformer 32, the load 35, and the load-side transformer 34 are also removed from the verification round path. Since the voltage application direction of the isolated DC power supply 54 is also opposite to the forward direction of the body diode D1 of the switching element 33b, the DC check current Ib makes a round of the above path if the switching element 33b is turned on and becomes conductive. (See the two-dot chain line). The current detection circuit 55 detects the verification current Ib and binarizes it to generate a detection value J4.

  As described above, the verification circuits 51 to 53 and the verification circuits 54 to 56 are different in their attachment destinations and have the same structure. Therefore, the verification circuits 54 to 56 will be described in more detail (see FIG. 2A). In order to prevent the flowing line current I2 from flowing into the path of the verification current Ib, backflow prevention diodes D2 and D3 are provided where the path of the verification current Ib branches from the path of the line current I2. In addition, the current detection circuit 55 connects, for example, a series circuit of a shunt resistor 55a and a photocoupler 55b in parallel to the current reducing resistor 56 for voltage division, insulation, and the like, and the current output is a voltage signal by the photocoupler load resistor 55c. The detected value J4 of the verification current Ib is generated by comparing with the failure detection threshold voltage Vr corresponding to the failure detection threshold current Ie and binarizing it with the comparator 55e. Further, when there is a concern about temperature change or aging change of CTR (current transmission rate) of the photocoupler 55b, an appropriate CTR follower circuit 55d is provided between the resistor 55c and the comparator 55e.

  By the way, with respect to the verification currents Ia and Ib flowing through these verification circuits, if the switching element pair 33 is normal (see FIG. 2A), the verification current Ia flows through one circuit of the verification circuits 51 to 53 (two points). (Refer to chain line) The verification current Ib flows in one circuit of the verification circuits 54 to 56 (refer to the two-dot chain line). However, depending on the failure state, the verification current Ib may flow out of each verification circuit and flow through the transformers 32 and 34. (Checking current wraparound phenomenon). In order to explain this phenomenon with a specific example, assuming that the switching element 33b is normal but the switching element 33a is in an off-failure state (continuation of interruption) (see FIG. 2B), the command value of the control signal S1 is turned on. Since the switching element 33b is turned on (ON) and becomes conductive, the switching element 33a remains in the cut-off state, so that the verification current Ia flows from the insulated DC power supply 51 to the secondary side of the transformer 32 and further switches the switching element 33b. The current flows through the current reducing resistor 53 through the primary side of the transformer 34. In order to be able to detect such a sneak current of the check current, the switching element failure detection circuit 50 changes the transition states of the check current Ia of the check circuits 51 to 53 and the check current Ib of the check circuits 54 to 56 as follows. It is regulated.

  First, regarding the verification current Ia, when the switching element 33b is turned on in accordance with the command value of the control signal S1 in a situation where the switching element 33a is in an off-failure state, the verification current Ia is changed from the insulated DC power supply 51 to the secondary of the transformer 32. When the current flows back through the switching element 33b and the primary side of the transformer 34 and flows back through the current reducing resistor 53 (see FIG. 2B), then (see FIG. 2C), the transformer 32 is excited. The resistance value of the current reducing resistor 53 is determined so that the current change rate of the transient current due to the inductance (transient verification current Ia) increases with time (see times t1 to t3). Further, in the transient state, the verification current Ia at that time is lower than the failure detection threshold current Ie over a longer time (preferably more than several cycles) than the cycle of the AC transmission signal I1 (time t1 to t2). The resistance value of the current reducing resistor 53 is determined.

  The verification current Ia at the time of wraparound will be described in further detail (see FIG. 2 (c)). This current represents the initial current due to the parallel resistance of the transformers 32 and 34 (in the vicinity of time t1) and the exciting inductance of the transformers 32 and 34. When L is L and the resistance value of the current reducing resistor 53 is R, a transient response current that increases with a time constant τ = L / R (near times t1 to t2), and a sudden rise current due to saturation of the transformers 32 and 34 (time) In order to ensure a sufficient difference between the failure detection threshold current Ie and the standard current Is, the initial current is desired to be as small as possible. Therefore, the parallel resistance is increased and the current reducing resistance 53 It is desirable to reduce the resistance value R. Further, since it is required to increase the time constant τ, it is desirable to increase the exciting inductance L and decrease the resistance value R of the current reducing resistor 53. Furthermore, in order to sufficiently secure the time during which the verification current Ia is lower than the failure detection threshold current Ie, in order to lengthen the time until the rising current is reached, transformers 32 and 34 having high magnetic flux saturation density are employed. Alternatively, it is desirable to increase the resistance value R of the current reducing resistor 53 to reduce the verification current Ia. Considering these conditions, the resistance value of the current reducing resistor 53 is determined.

  As for the verification current Ib, when the switching element 33a is turned on in accordance with the command value of the control signal S1 in a situation where the switching element 33b is in an off-failure state, the verification current Ib is changed from the insulation type DC power supply 54 to the secondary of the transformer 32. When the current flows back through the switching element 33a and the primary side of the transformer 34 and then flows through the current reducing resistor 56, the current change rate of the transient current (transient check current Ib) due to the excitation inductance of the transformer 32 is obtained. The resistance value of the current reducing resistor 56 is determined so that becomes larger as time elapses. Further, in the transient state, the current reducing resistance 56 is such that the checking current Ib at that time is lower than the failure detection threshold current Ie over a period longer than the period of the AC transmission signal I1 (preferably more than several periods). The resistance value is determined. Since these conditions regarding the verification current Ib are the same as those of the verification current Ia, the resistance values of the current reducing resistors 53 and 56 are determined to be the same.

In short, the voltage of the isolated DC power sources 51 and 54 in the verification circuits 51 to 53 and 54 to 56 is reduced so that the verification currents Ia and Ib that enable the detection of the delay state in the failure determination unit 61 described below can be made to flow. The resistance values of the flow resistors 53 and 56 and the value of the failure detection threshold current Ie are set.
As a typical example of such checking currents Ia and Ib, when the transformers 32 and 34 are left as they are, the voltage is 6 V to 12 V and the current is 50 mA to 100 mA. At that time, typical resistance values of the current reducing resistors 53 and 56 are 50Ω to 100Ω.

  The failure discriminating unit 57 receives the detection values J3 and J4 and the command value of the control signal S1, and determines whether the switching element pair 33 is normal or fault based on these input values. (See FIG. 1 (a)), the state of the detection value J3 of the verification current Ia and the detection value J4 of the verification current Ib in order to determine which one of the switching elements 33a and 33b has failed in determining the failure. Are classified into one of “constant” state, “alternating” state, “zero” state, and “delayed” state, and “normal” (◯ in the discrimination table) or “failure” for each of the switching elements 33a and 33b. A discrimination result such as (X in the discrimination table) or “other abnormality” (− in the discrimination table) is output (see the discrimination table in FIG. 1B).

  The “constant” state of the detection values J3 and J4 corresponds to a state in which the current exceeding the failure detection threshold current Ie continues for the verification currents Ia and Ib, and the “zero” state of the detection values J3 and J4 indicates the verification current Ia, This corresponds to a state in which Ib hardly flows, and the “alternate” state of the detection values J3 and J4 corresponds to a state in which the check currents Ia and Ib flow while moving up and down the failure detection threshold current Ie. The “delayed” state corresponds to a state in which the time until the check currents Ia and Ib exceed the failure detection threshold current Ie when the command value of the control signal S1 changes from OFF to ON is longer than the cycle of the AC transmission signal I1. (See waveform J3 in FIG. 2C).

  In the determination table of the failure determination unit 57 (see FIG. 1B), when the command value of the control signal S1 is on (ON) and the detection value J3 and the detection value J4 are “constant”, both the switching element 33a and the switching element 33b When it is determined that “○ is normal”, the command value of the control signal S1 is ON, the detected value J3 is “constant”, and the detected value J4 is “alternating”, the switching element 33a is “normal” but the switching element 33b is When it is determined as “× failure”, the command value of the control signal S1 is ON, the detection value J3 is “alternate”, and the detection value J4 is “constant”, the switching element 33a is determined as “× failure” and the switching element 33b is determined to be “normal”, and when the command value of the control signal S1 is ON (ON) and the detection value J3 and the detection value J4 are “alternate”, both the switching element 33a and the switching element 33b are determined to be “× failure”. When the command value of the control signal S1 is ON (ON), the detected value J3 is also detected value J. Is also “zero”, both the switching element 33a and the switching element 33b are determined to be “× failure”, the command value of the control signal S1 is on (ON), the detection value J3 is “delayed”, and the detection value J4 is “constant”. The switching element 33a is determined to be “× failure”, and the switching element 33b is determined to be “normal”.

  Further, when the command value of the control signal S1 is OFF and the detection value J3 and the detection value J4 are “constant”, both the switching element 33a and the switching element 33b are determined as “× failure”, and the command value of the control signal S1 is When the detection value J3 is OFF and the detection value J3 is “constant” and the detection value J4 is “alternating”, the switching element 33a is determined as “× Fault”, the switching element 33b is determined as “normal”, and the control signal S1 command When the value is OFF, the detected value J3 is “alternating”, and the detected value J4 is “constant”, the switching element 33a is determined to be “normal” but the switching element 33b is determined to be “× failure”, and the control signal S1 command When the detection value J3 and the detection value J4 are “alternating” when the value is off (OFF), both the switching element 33a and the switching element 33b are determined as “× failure”, and the command value of the control signal S1 is off (OFF). Switching element 33 when both J3 and detected value J4 are "zero" It is adapted to be also determined switching element 33b as "○ normal" as well. In other cases, it is determined as “−another abnormality”.

  The use mode and operation of the switching element failure detection circuit 50 according to the first embodiment will be described with reference to the drawings.

  FIG. 3 shows the operation when the AC transmission signal I1 is present. (A) is a waveform example of the verification current Ia and the digital detection value J3 when the switching element is OFF, and (b) is the verification current Ia when the switching element is ON. Waveform example of digital detection value J3, (c) is a circuit diagram when one side switching element 33a is off, (d) is a waveform example of verification current Ia and digital detection value J3 when one side switching element 33a is off, ( e) is a table summarizing the discrimination status for typical examples. 4 shows the operation when there is no AC transmission signal I1, etc. (a) is a waveform example of the verification current Ia and the detected value J3 when the switching element is OFF, and (b) is the verification current when the switching element is ON. A waveform example of Ia and the detected value J3, (c) is a table summarizing the verification current Ia and the detected value J3 at the time of one-side switching element 33a off failure, and (d) is a table summarizing the discrimination status for a typical example.

First, an operation when the AC transmission signal I1 is present will be described with reference to FIG.
When the switching elements 33a and 33b are both normal and the command value of the control signal S1 is off (OFF), the line current I2 does not flow. Since the check currents Ia and Ib do not flow, the detection values J3 and J4 become “zero” (see FIG. 3A), and the switching elements 33a and 33b are both determined to be “normal” (FIG. 3E). State 2).
When the switching elements 33a and 33b are both normal and the command value of the control signal S1 is ON, the line current I2 flows normally. The checking currents Ia and Ib also flow, and since both maintain the standard current Is exceeding the failure detection threshold current Ie, the detection values J3 and J4 become “constant” (see FIG. 3B), and the switching elements 33a, Both 33b are determined to be “normal” (state 1 in FIG. 3E).

  When the switching element 33a is OFF failure (continuation of interruption, open failure, failure that continues to take off state / open state / interruption state) and the switching element 33b is normal and the command value of the control signal S1 is ON (ON), the line current I2 Flows through the body diode D1 on the side of the switching element 33a that is turned off (see FIG. 3C), so that a half-wave state is reached. As a result, the verification current Ia increases and decreases the failure detection threshold current Ie in the same cycle as the line current I2, so that the detection value J3 becomes “alternate” (see FIG. 3D). On the other hand, the verification current Ib on the side of the switching element 33b that is on (ON) maintains the standard current Is, and thus the detection value J4 becomes “constant”. Then, the switching elements 33a and 33b are discriminated as “failure” and “normal” from the command value and detection values J3 and J4 of the control signal S1 based on the discrimination table (see FIG. 3E). State 4). Similarly, when the switching element 33a is normal, the switching element 33b is off-failure, and the command value of the control signal S1 is on (ON), it is accurately and similarly determined.

  When the switching element 33a is normal due to an on-failure (continuation continuity, short-circuit failure, failure in which the on-state / closed state / continuity state is maintained) and the command value of the control signal S1 is off (OFF) (FIG. 3 ( e) State 6), the line current I2 becomes “half wave”, the verification current Ia and the detection value J3 become “constant”, and the verification current Ib and the detection value J4 become “alternate”. Based on the discrimination table, the switching elements 33a and 33b are discriminated as “failure” and “normal”, respectively. Similarly, when the switching element 33a is normal, the switching element 33b is on-failure, and the command value of the control signal S1 is off (OFF), the determination is accurately performed in the same manner.

  When the switching element 33a is ON failure (continuation of conduction), the switching element 33b is normal, and the command value of the control signal S1 is ON (state 3 in FIG. 3E), the line current I2 flows in the full wave state. Since the verification currents Ia and Ib both flow at the standard current Is level, the detection values J3 and J4 become “constant”, and the switching elements 33a and 33b are determined to be “normal” and not faulty. In the case (note 1), since the command value is on, there is no problem in the function of the circuit even when the switching elements 33a and 33b are kept on, and the command value of the control signal S1 as described above is turned off (FIG. 3). (E) State 6) A failure is detected.

When the switching element 33a is off-failure (continuation of interruption), the switching element 33b is normal, and the command value of the control signal S1 is OFF (state 5 in FIG. 3E), the line current I2 does not flow and the verification current Since Ia and Ib do not flow, the detection values J3 and J4 become “zero”, and the switching elements 33a and 33b are both determined to be “normal”. Even if the elements 33a and 33b remain off, there is no problem in the function of the circuit, and a failure is detected when the command value of the control signal S1 as described above is turned on (state 4 in FIG. 3 (e)). .
Other simultaneous failure of both elements and single failure of the switching element 33b will be omitted, but the failure determination of the switching element pair 33 is performed accurately. At that time, of the switching elements 33a and 33b, It is also determined which one has failed.

Next, the operation when there is no AC transmission signal I1 will be described with reference to FIG. In this case, the line current I2 does not flow in any state, but the verification currents Ia and Ib flow depending on the situation, so that the failure of the switching element pair 33 can be detected.
When the switching elements 33a and 33b are both normal and the command value of the control signal S1 is OFF (state 2 in FIG. 4 (d)), since the verification currents Ia and Ib do not flow, the detection values J3 and J4 are “ It becomes “zero” (see FIG. 4A), and both the switching elements 33a and 33b are determined to be “normal”.
When the switching elements 33a and 33b are both normal and the command value of the control signal S1 is ON (state 1 in FIG. 4D), the verification currents Ia and Ib both maintain the standard current Is level. As a result, the detection values J3 and J4 become “constant” (see FIG. 4B), and both the switching elements 33a and 33b are determined to be “normal”.

When the switching element 33a is OFF failure (continuous interruption), the switching element 33b is normal, and the command value of the control signal S1 is ON (state 4 in FIG. 4 (d)), Since the verification current Ib maintains the standard current Is, the detection value J4 becomes “constant”.
On the other hand, the verification current Ia on the side of the switching element 33a which is turned off due to a failure cannot pass through the switching element 33a on the original path, and goes around the detour path. In other words (see FIG. 3C), the verification current Ia flows through an undesired detour path passing through the AC signal source transformer 32, the switching element 33b, and the load transformer 34. At this time, the rise of the verification current Ia is greatly blunted by the inductance of the transformer 32 and the like.

  Therefore (see the left part of FIG. 4 (c)), when the command value of the control signal S1 is switched from OFF to ON, the rising waveform of the verification current Ia appears at the start time t1 due to the parallel resistance component on the load side and the like. Apart from a slight rapid rise (because the voltage of the insulation type DC power supplies 51 and 54 and the resistance value of the current reducing resistors 53 and 56 are set so as not to exceed the failure detection threshold current Ie), slowly It rises and reaches the failure detection threshold current Ie at t2 when one cycle or more of the AC transmission signal I1 has passed. After that, it rises to the standard current Is without falling below the failure detection threshold current Ie (t3).

Then, the delay time between the OFF-ON transition timing of the command value of the control signal S1 and the corresponding transition timing of the detection value J4 becomes longer than the cycle of the AC transmission signal I1, and the detection value J3 becomes “delayed”. (See the right part of FIG. 4 (c)).
For this reason, the input state of the failure determination unit 57 is such that the command value of the control signal S1 is ON (ON), the detection value J3 is “delayed”, and the detection value J4 is “constant”. Based on the determination table, the switching element 33a is determined to be “failed” and the switching element 33a is determined to be “normal”.

  When the switching element 33a is ON failure (continuation of conduction), the switching element 33b is normal, and the command value of the control signal S1 is OFF (state 6 in FIG. 4D), the switching element 33a that remains ON due to the failure. Since the side verification current Ia maintains the standard current Is, the detection value J3 becomes “constant”. Since the switching element 33b is normally turned off, the verification current Ib does not flow, and thus the detection value J4 becomes “zero”. Then, based on the determination table of the failure determination unit 57, the switching elements 33a and 33b are separately determined as “failure” and “normal”.

  When the switching element 33a is ON failure (continuation of conduction), the switching element 33b is normal and the command value of the control signal S1 is ON (state 3 in FIG. 4D), the verification currents Ia and Ib are both standard. Since it flows at the current Is level, the detection values J3 and J4 become “constant”, and the switching elements 33a and 33b are both determined to be “normal” and not faulty. In this case (Note 1), the command value is on. Therefore, there is no problem in the function of the circuit even when the switching elements 33a and 33b are kept on, and a failure is detected when the command value of the control signal S1 as described above is turned off (state 6 in FIG. 3 (e)). Is done.

  When the switching element 33a is off-failure (continuous interruption), the switching element 33b is normal and the command value of the control signal S1 is OFF (state 5 in FIG. 4 (d)), both the verification currents Ia and Ib flow. Therefore, the detection values J3 and J4 become “zero” and the switching elements 33a and 33b are both determined to be “normal”. However, in this case (note 2), the command value is off, so that the switching elements 33a and 33b There is no problem in the function of the circuit even when it is turned off, and a failure is detected when the command value of the control signal S1 as described above is turned on (state 4 in FIG. 4D).

  As described above, in the switching element failure detection circuit 50, the failure determination of the switching element pair 33 is accurately performed for all states regardless of the presence / absence of the AC transmission signal I1, and the switching is performed at that time. It is also determined which of the elements 33a and 33b has failed. Further, since the combination of the command value of the control signal S1 and the detected values J3 and J4 that is not supposed to be a failure of the switching element pair 33 is determined as “-another abnormality”, the check circuit and the failure determination unit It turns out that there is a problem.

  A specific configuration of the switching element failure detection circuit according to the second embodiment of the present invention will be described with reference to the drawings. 5A and 5B show the structure and operation of the switching element failure detection circuit, where FIG. 5A shows a determination table of the failure determination unit 57, and FIG. 5B shows an overvoltage with no AC transmission signal I1 when the command value of the control signal S1 is off. (C) is a waveform example of the verification current Ib and the detection value J4 when the AC transmission signal I1 flows excessively when the command value of the control signal S1 is turned on. is there.

  This switching element failure detection circuit is different from the switching element failure detection circuit 50 of the first embodiment described above in that the determination table of the failure determination unit 57 is partially changed, and the other is the same as described above. is there. In this new discrimination table (see FIG. 5 (a)), when the command value of the control signal S1 is ON, when the detection value J3 is “constant” and the detection value J4 is “alternating”, “ Or “overcurrent”, and when the detection value J3 is “alternating” and the detection value J4 is “constant”, a determination result of “△ failure or overcurrent” is issued for the switching element 33a, and the detection value J3 is “alternating”. When the detected value J4 is “alternating”, a determination result of “Δ failure or overcurrent” is output for the switching elements 33a and 33b.

  Further, when the command value of the control signal S1 is OFF, when the detection value J3 is “constant” and the detection value J4 is “alternating”, a determination result of “▲ failure or overvoltage” is given to the switching element 33a, and the detection value J3 is When the detected value J4 is “constant” in “alternating”, the determination result of “▲ failure or overvoltage” is issued for the switching element 33b. When the detected value J3 is “alternating” and the detected value J4 is “alternating”, the switching element 33a, A determination result of “▲ failure or overvoltage” is output for 33b. The other cases are the same as described above (see FIG. 1B).

  In the switching element failure detection circuit 50 configured as described above, when there is no AC transmission signal I1 and the command value of the control signal S1 is OFF, even if the switching element pair 33 is normal, the switching element pair 33 is switched due to some other problem. When a voltage exceeding the reverse breakdown voltage of the element pair 33 is applied to the path of the line current I2, breakdown occurs in the switching element pair 33. Since the switching element pair 33 is composed of two switching elements 33a and 33b having different directions of the body diode D1, breakdown occurs alternately. The verification current Ib flows when the switching element 33a is broken down, and does not flow when the switching element 33b is broken down. Then, the detected value J4 becomes “alternate” (see FIG. 5B). The verification current Ia does not flow when the switching element 33a is broken down, but flows when the switching element 33b is broken down. The detected value J3 becomes “alternate”.

  Such an “alternate” detection state at the time of no signal appears not only when an overvoltage is applied but also when the switching elements 33a and 33b are turned on as described above. ”State. Therefore, when such automatic determination is made, an engineer or other operator checks whether the circuit is in an overvoltage application state before performing repairs or replacements due to a failure. By removing the cause of the trouble, unnecessary repair or replacement can be avoided.

  Further, in the switching element failure detection circuit 50, when the AC transmission signal I1 is present and the command value of the control signal S1 is ON, even if the switching element pair 33 is normal, for example, the AC transmission signal I1 is generated due to some other problem. Abnormally large or a large noise current flows into the path of the line current I2 from the load 35 side, and the steady current of the line current I2, for example, an abnormal current greatly exceeding 200 mA to 400 mA as described above, enters the path of the line current I2. When the ripple current superimposed on the verification current Ib becomes excessive due to the flow and the verification current Ib falls below the failure detection threshold current Ie, the detection value J4 becomes “alternate” (see FIG. 5C). ).

  Such an “alternate” detection state at the time of applying a signal is manifested not only when an overcurrent flows, but also when the switching elements 33a and 33b are in an on-failure state as described above. It is determined as a “failure or overcurrent” state. For this reason, when such automatic determination is made, an engineer or other operator checks whether the circuit is in an overcurrent state before repairing or replacing it due to a failure. By removing the cause of the trouble, unnecessary repair or replacement can be avoided.

A specific configuration of the switching element failure detection circuit 80 according to the third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a circuit diagram showing an application example of a time-division transmission / reception track circuit device for a railway to a transmission unit.
In the time-division transmission / reception track circuit device 20 described above, a set of AC signal sources 31 and transformers 32 are shared by a plurality of / multiple switching element pairs 33, transformers 34 and loads 35. When the present invention is applied to the circuit, the insulation type DC power supplies 51 and 54 of the verification circuit can be shared, so only one is provided on the secondary side of the transformer 32, and the remaining 52 + 53 and 55 + 56 of the verification circuit and the failure determination unit A plurality 57 is provided corresponding to the switching element pair 33.
In this way, an increase in circuit scale and cost can be suppressed by sharing the insulated DC power supply.

The switching element failure detection circuit 90 of the present invention whose basic circuit is shown in FIG. 7 is different from the above-described embodiments in that the load-side transformer 34 is omitted and the switching circuit failure detection circuit 90 is directly connected to the path of the line current I2. This is a point where a load 35 is inserted.
A detailed description that will be repeated is omitted, but in this case as well, the same determination result as described above can be obtained.

[Others]
In the above embodiment, the photocoupler 55b is used for the current detection circuits 52 and 55. However, the detection of the direct current is performed by a current sensor using a Hall element or a current detection circuit combining a current reducing resistor and an insulation amplifier. You may make it do.

  The switching element failure detection circuit according to the present invention satisfies the condition of switching a medium speed of several tens of ms or more in an AC line using several tens Hz to several hundreds Hz in addition to the above-described railway time division transmission / reception type track circuit device. If applicable, it can be applied. For example, it can also be applied to a power supply switching device and various control devices that require high reliability. Examples of such control devices include elevators, door opening / closing devices, and plant equipment.

In the first embodiment of the present invention, the structure of the switching element failure detection circuit is shown, (a) is a basic circuit diagram, and (b) is a discrimination table. (A) is a detailed circuit diagram of the verification circuit, (b) is a wraparound path of the verification current when the switching element one side fails, and (c) is a waveform example of the verification current and detection value when the switching element one side fails. The operation when there is an AC transmission signal is shown, (a) is a waveform example of the verification current and the detection value when the switching element is OFF, (b) is a waveform example of the verification current and the detection value when the switching element is ON, (c) Is a circuit diagram when one side of the switching element is broken, (d) is a waveform example of the verification current and the detected value at the time of failure, and (e) is a table summarizing the discrimination status for typical examples. The operation when there is no AC transmission signal is shown. (A) is a waveform example of the verification current and detection value when the switching element is OFF, (b) is a waveform example of the verification current and detection value when the switching element is ON, (c ) Is an example of a waveform of a verification current and a detected value when one side of the switching element is broken down, and (d) is a table summarizing the discrimination status for typical examples. Example 2 of the present invention shows the structure and operation of a switching element failure detection circuit, (a) is a discrimination table, (b) is a verification current and detection value when an overvoltage is applied in the absence of an AC transmission signal. (C) is a waveform example of a verification current and a detected value when an AC transmission signal flows excessively. It is a circuit diagram which shows the example applied to the transmission part of the time-division transmission / reception type track circuit apparatus of a railroad about Example 3 of the switching element failure detection circuit of this invention. It is a circuit diagram of a switching element failure detection circuit about Example 4 of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic block diagram about the time division transmission / reception type track circuit apparatus of a railway. (A) is a basic circuit diagram and (b) is a discrimination table for a conventional switching element failure detection circuit. For a conventional switching element failure detection circuit employing a switching element with a parallel diode, (a) is a circuit diagram when one side of the switching element fails, (c) is a waveform example of a signal current at the time of failure, (d) is It is the table | surface which summarized the discrimination | determination condition when there exists an alternating current transmission signal about a typical example.

Explanation of symbols

10 ... track, 11 ... train,
20 ... time-division transmission / reception track circuit device, 21 ... transmission unit, 22 ... amplification unit, 23 ... switching unit
30 ... Switching element failure detection circuit, 31 ... AC signal source,
32 ... Transformer, 33 ... Switching element pair, 33a, 33b ... Switching element,
34 ... Transformer, 35 ... Load, 36 ... Current detection circuit, 37 ... Failure determination unit,
50. Switching element failure detection circuit,
51 ... Insulation type DC power supply, 52 ... Current detection circuit, 53 ... Current reduction resistor,
54 ... Insulation type DC power supply, 55 ... Current detection circuit, 56 ... Current reducing resistor, 57 ... Failure determination unit,
80: switching element failure detection circuit, 90: switching element failure detection circuit,
D1 ... Body diode (parallel diode), D2, D3 ... Backflow prevention diode

Claims (3)

  An AC signal source that outputs an AC transmission signal is provided on the primary side of the transformer, and is provided separately on the secondary side of this transformer. Both are connected to the secondary side of the transformer and the other end is connected to the load side. In the switching element failure detection circuit comprising a pair of switching elements having a common on / off control signal and a failure determination unit for determining the presence or absence of a failure related to the switching element pair, each of the switching elements is a parallel diode. Each of the switching elements is provided with a checking circuit for passing a DC checking current in a reverse direction of the parallel diode through a path that passes through the switching element and removes the transformer and the load. The switching element failure detection circuit, wherein the failure determination unit performs failure determination based on a detection value of the verification current and a command value of the control signal.   When the verification current flows around the secondary side of the transformer, the verification current at that time is such that the rate of change of the transient current due to the magnetizing inductance of the transformer increases with time and the verification current is increased. A current reducing resistor whose resistance value is determined so that the current is below the threshold for a time longer than the period of the AC transmission signal is provided in each of the verification circuits, and the failure determination unit includes In addition to detecting a constant state in which the current equal to or higher than the threshold is continued with respect to the verification current, an alternating state in which current flows up and down, and a zero state in which current hardly flows, the control signal is turned off. It also detects a delay state in which the time until the verification current exceeds the threshold when it is turned on is longer than the period of the AC transmission signal, and these states Switching element fault detection circuit according to claim 1, characterized in that performing the failure determination according.   3. The switching element failure detection circuit according to claim 2, wherein the failure determination unit is configured to determine which of the switching elements has failed in determining the failure.

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