JP4044999B2 - Array substrate for flat display device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an array substrate used in a flat display device such as a liquid crystal display device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, flat-type display devices that replace CRT displays have been actively developed, and liquid crystal display devices are particularly attracting attention because of their advantages such as light weight, thinness, and low power consumption.
[0003]
For example, a light transmission type active matrix liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. An active matrix type liquid crystal display device is formed by holding a liquid crystal layer between an array substrate and a counter substrate via an alignment film. The array substrate has a plurality of signal lines and scanning lines arranged in a lattice pattern on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) or the like at each intersection. A thin film transistor (hereinafter abbreviated as TFT) using the semiconductor thin film is connected. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to a transparent conductive material constituting the pixel electrode, for example, ITO (Indium-Tin-Oxide). Has been.
[0004]
The counter substrate includes a counter electrode made of ITO on a transparent insulating substrate such as glass, and a color filter layer if a color display is realized.
[0005]
Here, normally, a first gate insulating film made of silicon oxide is disposed on the gate electrode and the scanning line in order to insulate the semiconductor layer and the like above the gate electrode and the scanning line. A two-gate insulating film is provided. An interlayer insulating film made of silicon nitride is disposed between the transparent conductive material layer and a metal wiring layer such as a signal line.
[0006]
In reducing the manufacturing cost of such an active matrix liquid crystal display device, there is a problem that the number of steps for manufacturing the array substrate is large, and therefore the cost ratio of the array substrate is high.
[0007]
Therefore, in Japanese Patent Application No. 8-260572, the pixel electrode is arranged in the uppermost layer, and along with this, the semiconductor film and the like are patterned together with the signal line, source and drain electrodes based on the same mask pattern. After that, it has been proposed to simultaneously produce a contact hole for exposing a connection end of a signal line or a scanning line, together with the production of a contact hole for connecting a source electrode and a pixel electrode. Thereby, productivity can be improved with a small number of masks, and the manufacturing yield is not reduced.
[0008]
However, as described above, in the case where the part of the pixel electrode layer is a pixel-mounted type that covers the source electrode, there is a problem as described below.
[0009]
FIG. 11 is a schematic vertical cross-sectional view of a TFT portion showing the occurrence of a connection failure between a source electrode and a pixel electrode in a conventional array substrate.
[0010]
The source electrode (126b) of the TFT is connected to the ITO film constituting the pixel electrode (131) by a contact hole (129) disposed on the upper surface thereof. Since the contact hole (129) is entirely disposed on the source electrode (126b), the edge (126c) on the pixel electrode side of the source electrode (126b) is the source electrode (126b) layer and the pixel electrode ( 131) is covered with an interlayer insulating film (127) between the layers.
[0011]
As the metal for the upper layer metal wiring including the source electrode (126b) and the drain electrode, molybdenum metal or an alloy containing molybdenum metal in an amount of 55 atomic% (mol%) or more, preferably 70 atomic% or more is hillock resistance and etching residue. Excellent in that there is no. However, when such a metal is used, as shown in the figure, the edge (126c) of the source electrode (126b) may be etched into a shape that is almost vertical or overhang, As a result, the following problems may occur.
[0012]
When an interlayer insulating film (127) is deposited on the edge (126c) portion of the source electrode (126b) having such a shape, a void (128) is often formed, and thereby ITO The part which a film cannot cover is generated. In addition, the etchant that has penetrated into the void (128) during the ITO film patterning process may corrode the ITO film and cause the ITO film to break.
[0013]
The manufacturing process of the conventional array substrate will be described in more detail with reference to FIGS. Here, the description of the first to fifth steps is omitted, and the description starts from the sixth step.
[0014]
(1) Sixth step
FIG. 12 is a cross-sectional view showing the state after the fifth step is finished. In the sixth step, an interlayer insulating film (127) made of a silicon nitride film is deposited thereon, and then exposed and developed using a fourth mask pattern, so that a part of the region corresponding to the source electrode (126b) is obtained. By removing the interlayer insulating film (127), contact holes (129, 163-166) are formed as shown in FIG.
[0015]
The plan view of FIG. 14 shows over-etching (size expansion by side etching) when the source electrode contact hole (129) is formed. The contact hole (129-0) at the initial stage of etching has a position and dimensions corresponding to the resist pattern. Although enlarged by over-etching, in the normal design, the edge of the contact hole (129) does not protrude from the area of the source electrode. The source electrode (126b) has three straight lines at the edge (126c) on the side connected to the pixel electrode (edge other than the side connected to the drain electrode). That is, in the source electrode (126b), the portion surrounded by the pixel electrode has a rectangular planar shape.
[0016]
(2) Seventh step
The laminated sectional view of FIG. 15 and the plan view of FIG. 16 show a state in which the pixel electrode 131 is formed by patterning after depositing the ITO film.
[0017]
[Problems to be solved by the invention]
Therefore, in view of the above problems, the present invention provides an array substrate for a display device in which the ITO film constituting the pixel electrode (131) does not break off on the edge (126c) of the source electrode (126b), And a manufacturing method thereof.
[0018]
[Means for Solving the Problems]
The display device array substrate according to claim 1, wherein the scanning lines disposed on the substrate, the first and second insulating films disposed thereon, the semiconductor film disposed thereon, and the semiconductor film A thin film transistor including a source electrode and a drain electrode that are electrically connected, a signal line that is derived from the drain electrode and is substantially orthogonal to the scanning line, and a signal line that covers the signal line, the source electrode, and the drain electrode The source electrode through a third insulating film, a source electrode contact hole provided in the third insulating film so that a part of the upper surface of the source electrode is exposed, and a conductive layer covering the source electrode contact hole And a pixel electrode electrically connected to the pixel electrode, wherein the source electrode contact hole is connected to the pixel electrode on the side connected to the pixel electrode. Is formed so as to expose the edge of the electrode, through the conductive layer portion covering the edge directly between the source electrode and the pixel electrode, characterized in that it is connected.
[0019]
With such a configuration, even if the pixel electrode side edge of the source electrode is substantially vertical or slightly overhanged, no void is formed in this portion by the insulating film layer. Therefore, it is possible to prevent a point defect defect of the display device due to the breakage of the ITO film at the pixel electrode side edge of the source electrode or the penetration of the etching solution.
[0020]
3. The array substrate for a display device according to claim 2, wherein, in the array substrate according to claim 1, an edge of the source electrode has a substantially arc shape on the side connected to the pixel electrode, and the substantially arc-shaped end. An edge is disposed close to the inside of the substantially circular edge of the source electrode contact hole.
[0021]
With such a configuration, a desired contact hole can be easily manufactured by overetching. In particular, by increasing the etching rate difference between the third insulating film (Pass-SiN) and the second insulating film (g-SiN) by 5 times or more, it is possible to sufficiently damage the underlying insulating film due to overetching. Can be prevented.
[0022]
The array substrate for a display device according to claim 3 is the array substrate according to claim 1, wherein the source electrode is made of molybdenum or an alloy containing 55 atomic% or more of molybdenum.
[0023]
5. The method of manufacturing an array substrate for a display device according to claim 4, further comprising: forming a first conductive layer pattern including a scanning line disposed on the substrate; and a first insulating film and a second insulating film thereon. A second conductive layer including a step of forming a semiconductor film, a source electrode and a drain electrode connected to the semiconductor film to form a thin film transistor, and a signal line derived from the drain electrode and substantially orthogonal to the scanning line. A step of forming a layer pattern; a step of forming a third insulating film covering the second conductive layer pattern; and a contact hole for a source electrode in the third insulating film so that a part of the upper surface of the source electrode is exposed. And a method of manufacturing an array substrate for a display device, comprising: forming a pixel electrode electrically connected to the source electrode through the source electrode contact hole In the step of forming the source electrode contact hole, the source electrode contact hole extends from the dimension in the resist pattern to a dimension including the edge of the source electrode on the side far from the drain electrode by side etching. Thus, in the step of forming the pixel electrode, the edge of the source electrode is directly covered with the layer forming the pixel electrode.
[0024]
With such a configuration, it is possible to prevent a point defect of the display device due to the breakage of the ITO film at the edge of the source electrode or the penetration of the etching solution.
[0025]
6. The method for manufacturing an array substrate for a display device according to claim 5, wherein in the array substrate manufacturing method according to claim 4, a first contact exposing a wiring belonging to the first conductive layer pattern at a peripheral portion of the array substrate. Simultaneously with the step of forming a hole and the step of forming the source electrode contact hole, the second insulating layer is removed in a region in contact with the outer edge of the first contact hole, thereby forming the second conductive layer pattern. Simultaneously with the step of forming the second contact hole exposing the wiring to which it belongs and the step of forming the pixel electrode, the first conductive layer exposed by the first contact hole and the second contact hole are exposed. Connecting the second conductive layer to the pixel electrode by the same layer as the pixel electrode. .
[0026]
With the above-described configuration, it is possible to reliably prevent poor connection with respect to the contact hole at the peripheral edge of the array substrate and to simplify the contact hole forming process.
[0027]
7. The method for manufacturing an array substrate for a display device according to claim 6, wherein the source electrode contact hole or the second contact hole is formed together with the source electrode contact hole in the array substrate manufacturing method according to claim 4 or 5. The step is performed by a single etching process using a single etching solution containing hydrogen fluoride or a salt thereof.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
<Configuration of array substrate>
Hereinafter, the configuration of the array substrate for a display device of the present invention will be described with reference to FIGS. 1 to 3 and FIG.
[0029]
FIG. 1 is a schematic plan view of an array substrate (100), in which the lower side in the figure is located on the upper side of the screen of the liquid crystal display device, and the scanning lines are directed from the lower side to the upper side in the figure. They are selected sequentially.
[0030]
The array substrate (100) includes 480 scanning lines (111) arranged on the glass substrate (101), and one end of each scanning line (111) is on one end side (101a) side of the glass substrate (101). And is electrically connected to the scanning line pad (152) via the oblique wiring part (150).
[0031]
The array substrate (100) includes 1920 signal lines (110) substantially orthogonal to the scanning lines (111) on the glass substrate (101), and each signal line (110) is the other end of the glass substrate (101). It is pulled out to the side (101b) side, and is electrically connected to the signal line pad (162) through the oblique wiring portion (160).
[0032]
A TFT (112) is arranged near the intersection of the scanning line (111) and the signal line (110).
[0033]
(1) TFT structure
The laminated structure of the TFT (112) will be described with reference to the schematic sectional perspective view of FIG.
[0034]
The TFT (112) is an inverted stagger type having a scanning line (111) as a lower layer metal wiring as a gate, and an extended portion from a signal line (110) as an upper layer metal wiring is a drain electrode (126a) And has a channel protective film (122) in the channel portion. The TFT (112) is a pixel-mounted type, and the source electrode (126b) is connected to the pixel via a contact hole (129) provided in the interlayer coating insulating film (127) so as to expose the upper surface. Connected to the electrode (131).
[0035]
As shown in the figure, the edge (129a) on the side connected to the pixel electrode of the contact hole (129), that is, the edge other than the side connected to the drain electrode is the edge (126c) of the corresponding source electrode. A little outside. That is, the contact hole (129) is formed so as to protrude from the upper surface of the source electrode (126b) to the pixel electrode side. Therefore, the bottom surface of the contact hole (129) includes an edge (126c) of the source electrode on the side connected to the pixel electrode, which forms a step portion in the bottom surface.
[0036]
Therefore, the edge (126c) on the side of the source electrode connected to the pixel electrode is not covered with the interlayer coating insulating film (127), but is covered only with the ITO film constituting the pixel electrode (131). . As shown in the drawing, the edge (126c) on the pixel electrode connection side of the source electrode is formed in advance in an arcuate planar shape so as to easily fit in the circular region of the contact hole.
[0037]
In the above, ITO (Indium Tin Oxide) has much better coating filling properties than the interlayer coating insulating film (127). Therefore, even if the edge (126c) of the source electrode is substantially vertical or overhanged, no void is formed in the portion along the edge (126c) of the source electrode. For this reason, the ITO film constituting the pixel electrode (131) does not break off on the edge (126c) of the source electrode.
[0038]
(2) Structure of signal line side outer periphery
The structure near the outer periphery of the signal line (110) will be described with reference to FIGS.
[0039]
As shown in FIG. 1, a lower layer wiring part (111b) formed of the same material in the same process as the scanning line (111) is connected to one end side of the glass substrate (101) corresponding to each signal line (110). The signal lines (110) on the 101b) side are disposed on the diagonal wiring portions (160) and the signal line pads (162).
[0040]
As shown in FIG. 9, in the oblique wiring section (160), two layers of insulating films (115) and (117) are arranged on the lower wiring section (111b). Further, an upper wiring portion (125b) extending from the semiconductor coating (119), the low resistance semiconductor coating (123), and the signal line (110) is formed on the two insulating films (115) and (117). The interlayer insulating film (127) is disposed on the upper wiring portion (125b).
[0041]
In the oblique wiring part (160), the upper layer wiring part (125b) extending from the signal line (110) and the lower layer wiring part (111b) formed of the same material in the same process as the scanning line (111) These two layers electrically connect the base of the diagonal wiring portion (160) and the signal line pad (162).
[0042]
Therefore, in the diagonal wiring part (160), even if one of the upper layer wiring part (125b) or the lower layer wiring part (111b) is disconnected, the other is connected, so that a disconnection failure occurs in the diagonal wiring part (160). That is alleviated.
[0043]
In the base portion of the oblique wiring portion (160) and the signal line pad (162), the first contact holes (164) and (164) are respectively formed in the regions where the second contact holes (163) and (165) are formed. 166) is formed. The signal line connection layer (131b) formed of ITO of the same material in the same process as the pixel electrode (131) is disposed in the contact hole region, thereby extending from the signal line (110). The upper wiring portion (125b) and the lower wiring portion (111b) are electrically connected. The first contact holes (164) and (166) have two layers of insulating films (115) and (117) and a semiconductor coating (119) so as to expose a part of the main surface of the lower wiring part (111b). The second contact holes (163) and (165) expose a part of the main surface of the upper layer wiring portion (125b) through the low resistance semiconductor film (123) and the upper layer wiring portion (125b). Thus, the opening penetrates the interlayer insulating film (127).
[0044]
As schematically shown in the longitudinal sectional perspective view of FIG. 3, the bottom surface (163b) of the second contact hole (163) has a donut shape, and the outer edge (164b) of the first contact hole (164) The inner edge of the bottom surface (163b) of the donut shape.
[0045]
As described above, since the first contact hole is arranged in the region where the second contact hole is formed, the area for forming the contact hole is the minimum in the case where both contact holes are connected by the connection layer (131b). It can be an area.
[0046]
Although the connection layer (131b) is made of ITO and has a high resistivity, the connection layer (131b) covering the lower wiring portion (111b) at the bottom of the first contact hole and the bottom of the second contact hole. The connection layer (131b) covering the upper wiring portion (125b) is coupled only via the connection layer (131b) on the step surface of the first contact hole. Therefore, the wiring length of the connection layer (131b) is minimized. Moreover, such a connection is made over the entire circumference of the outer edge of the first contact hole. Therefore, display defects such as crosstalk are not caused by the resistance of the connection layer (131b).
[0047]
Note that the structure of the outer peripheral portion on the scanning line side is the same as the structure of the outer peripheral portion in the vicinity of the signal line described above.
[0048]
In this embodiment, as shown in FIG. 1, the auxiliary capacitor (Cs) is described as being formed by the extending portion (113) of the scanning line. However, the auxiliary capacitor parallel to the scanning line (111) is described. A line (Cs line) may be arranged. In this case, one end or both ends of each auxiliary capacitance line (Cs line) formed from the same material in the same process as the scanning line (111) is formed from the same material in the same process as the signal line (110). It is connected to the bundled wire via a contact hole. This contact hole can also be the same as the structure at the outer periphery of the signal line described above.
[0049]
<Array substrate manufacturing process>
Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS. In the following description, the manufacturing process of the outer peripheral part near the scanning line is the same as the manufacturing process of the outer peripheral part near the signal line, and is omitted.
[0050]
(1) First step
A Mo—W film (molybdenum-tungsten alloy film) is deposited on the glass substrate (101) to a thickness of 300 nm by sputtering.
[0051]
On this laminated film, a scanning line pattern and a part of the auxiliary capacitance wiring are formed using photolithography, and CF _Four / O ₂ The system CDE is dry-etched into a tapered shape to complete the scanning line and the auxiliary capacitance wiring pattern (first patterning).
[0052]
As a result, 480 scanning lines (111) are formed on the glass substrate (101), and at the one end side (101a) side, the oblique wiring portion (150) of the scanning line (111) and the scanning line pad (152). The lower wiring part (111a) constituting the, the oblique wiring part (160) of the signal line (110) and the lower wiring part (111b) constituting the signal line pad (162) at one end side (101b) are simultaneously produced.
[0053]
Further, in the TFT region, a gate electrode that is integrated with the scanning line (111) and led out in a direction orthogonal to the scanning line (111) is manufactured. In addition, an extension region (113) for forming an auxiliary capacitor (Cs) derived in a direction orthogonal to the scanning line (111) at the time of patterning of the scanning line (111) is also prepared at the same time (FIG. 1). reference).
[0054]
(2) Second step
After the first step, the glass substrate (101) is heated to 300 ° C. or higher, and then a first gate insulating film (115) made of a silicon oxide film (SiOx film) having a thickness of 350 nm is deposited by atmospheric pressure plasma CVD. Further, a second gate insulating film (117) made of a silicon nitride film having a thickness of 50 nm, a semiconductor film (119) made of a-Si: H having a thickness of 50 nm, and a channel protection made of a silicon nitride film having a thickness of 200 nm by low pressure plasma CVD. The film (121) is formed without continuously exposing to the atmosphere.
[0055]
Here, when the second gate insulating film (117), which is a silicon nitride film, is formed, the low pressure plasma CVD conditions are set such that the ratio of nitrogen element to silicon (silicon) element in the film composition (composition of nitrogen / silicon) The ratio N / Si) is adjusted to be 1.5 or more.
[0056]
Instead of the SiOx film, the glass substrate (101) is heated to 300 ° C. or higher, and then SiO 2 by thermal CVD ₂ A membrane may be used.
[0057]
(3) Third step
After the second step, the channel protective film (121) is patterned in a self-aligned manner on the scanning line (111) by a backside exposure technique using the scanning line (111) as a mask, and the second step is performed so as to correspond to the TFT region. An island-shaped channel protective film (122) is formed through exposure using a mask pattern, development, and patterning (second patterning).
[0058]
(4) Fourth step
After the third step, as shown in FIG. 4, the exposed semiconductor film (119) surface is treated with a hydrofluoric acid (HF) solution so as to obtain a good ohmic contact, and phosphorus is used as an impurity by plasma CVD. Including 30 nm thick n ⁺ A low resistance semiconductor film (123) made of a-Si: H is deposited, and a 300 nm thick Mo film (molybdenum film) (125) is deposited by sputtering.
[0059]
(5) Fifth process
After the fourth step, as shown in FIG. 5, after exposure and development using a third mask pattern, patterning is performed on the Mo film (125), the low-resistance semiconductor film (123), and the semiconductor film (119). Perform (third patterning). At this time, the Mo film (125) is patterned by wet etching using a mixed acid of phosphoric acid, nitric acid, acetic acid and water. Further, the low resistance semiconductor film 123 and the semiconductor film 119 are formed by etching the first gate insulating film 115 or the second gate insulating film 117 formed of a silicon nitride film and the channel protective film 122. Patterning is performed by plasma etching by controlling the ratio.
[0060]
As a result, in the TFT region, the source electrode (126b) and the low-resistance semiconductor film portion (124a) below the source electrode (126b) are integrally manufactured, and the signal line (110) and drain electrode (126a) and the low-resistance semiconductor film below the source electrode (126b) The membrane portion (124b) is manufactured integrally.
[0061]
At the base of the signal line pad (162) and the diagonal wiring part (160), the upper layer wiring part extended from the signal line (110) by patterning the Mo film (125) along the lower layer wiring part (111b) (125b) is formed, and the low resistance semiconductor film (123) and the semiconductor film (119) are collectively patterned along the upper wiring portion (125b).
[0062]
At the same time, the upper layer wiring portion (125b), the low resistance semiconductor film (123) and the opening (164a) penetrating the semiconductor film (119) corresponding to the first contact holes (164) and (166) described above, (166a) is prepared.
[0063]
Here, the patterning of the Mo film (125), the low-resistance semiconductor film (123), and the semiconductor film (119) was performed by a continuous process of wet etching and subsequent dry etching, but only dry etching or wet etching. It can also be performed only by etching.
[0064]
(6) Sixth step
After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited thereon.
[0065]
Here, when forming the interlayer insulating film (127), the conditions of the low pressure plasma CVD are adjusted so that the element ratio of nitrogen to silicon is 1.28 or more.
[0066]
Then, exposure and development are performed using the fourth mask pattern, and a part of the interlayer insulating film (127) corresponding to the source electrode (126b) is removed to form a contact hole (129, 164-166) (first 4 patterning).
[0067]
As an etching treatment agent for forming the contact hole, a hydrogen fluoride agent is used. Particularly preferred is a hydrogen fluoride-ammonium fluoride buffer (buffered hydrofluoric acid, BHF). Buffered hydrofluoric acid is an aqueous solution containing 6% hydrogen fluoride and 30% ammonium fluoride.
[0068]
The interlayer insulating film (127) and the second gate insulating film (117) are both made of silicon nitride, but the rate at which the interlayer insulating film (127) is etched by the buffered hydrofluoric acid is the same as that of the second gate insulating film (117). About 10 times that. That is, the etching rate ratio is about 10 times. This is because even when the films are formed by the same low pressure CVD method, the film forming conditions are different, and the density and the nitrogen / silicon weight composition ratio are greatly different.
[0069]
Hereinafter, an etching process for forming contact holes in the interlayer insulating film (127) will be described with reference to FIGS.
[0070]
a. Before over-etching (before dimension expansion by side etching)
First, FIG. 6 shows a laminated cross-sectional structure of a TFT portion at the initial stage of etching.
[0071]
The size of the contact hole at this stage is almost the same as the contact hole portion in the resist pattern formed according to the mask pattern as described above.
[0072]
At this time, the contact hole (129) in the source electrode portion is entirely within the region of the source electrode (126b). That is, the edge (126c) on the pixel electrode side of the source electrode (126b) remains covered with the interlayer insulating film (127).
[0073]
On the other hand, at the base of the signal line pad (162) and the diagonal wiring portion (160), the first and second gate insulating films (115) and (117) corresponding to the openings (164a) and (166a) are provided. The interlayer insulating film (127) is removed in a lump to form first contact holes (164), (166) (fourth patterning).
[0074]
b. After over-etching (after dimension expansion by side etching)
Next, FIG. 7 shows a laminated cross-sectional structure of the TFT portion after completion of etching, that is, after over-etching.
[0075]
After the size of each contact hole is increased by over-etching, the pixel electrode side edge (129a) of the contact hole (129) is replaced with the pixel electrode side edge (126c) of the source electrode (126b). Coming over and beyond. Therefore, the interlayer insulating film (127) does not remain at the edge (126c) on the pixel electrode side of the source electrode (126b).
[0076]
On the other hand, at this time, the interlayer insulating film (127) in the region surrounding the first contact holes (164), (166) is removed at the base of the signal line pad (162) and the oblique wiring part (160), and the second Contact holes (163) and (165) are formed.
[0077]
FIG. 8 is a plan view of a TFT portion for schematically showing overetching.
[0078]
As shown in the figure, by adjusting the design size of the contact hole portion in the resist pattern and the over-etching time, the contact hole expands to a point slightly exceeding the edge (126c) on the pixel electrode side of the source electrode. To be done.
[0079]
Further, the edge (126c) of the source electrode on the side connected to the pixel electrode is formed in a substantially arc shape, and is arranged close to the inside of the edge of the substantially circular contact hole (129). .
[0080]
Since the planar arrangement is as shown in FIG. 8, the time for overetching can be minimized, and the gate insulating film (119) is not damaged during the overetching.
[0081]
(7) Seventh step
After the sixth step, as shown in FIG. 9, an ITO film having a thickness of 40 nm is deposited thereon by sputtering at a substrate temperature of 230 ° C., exposed and developed using a fifth mask pattern, and then the pixel electrode (131 ) Is manufactured (fifth patterning). The patterning of the ITO film may be wet etching or dry etching.
[0082]
As shown in FIG. 9, the contact hole (129) formed in the sixth step covers a part of the upper surface of the source electrode (126b) and is connected to the ITO film (131a). Through the ITO film that directly covers the edge (126c) of the electrode on the pixel electrode side and the valley portion (129a) between this and the edge (129a) of the contact hole (129) on the pixel electrode side, the pixel electrode ( 131).
[0083]
At the same time, as shown in FIG. 9, the second contact holes (163) and (165) and the first contact holes (164) and (166) are formed at the base of the signal line pad (162) and the diagonal wiring portion (160). A patch-like connection layer (131b) is formed so as to cover the region. Thereby, the signal line (110) and the signal line connection pad (162) are electrically connected by the diagonal wiring part (160) having a two-layer structure of the lower layer wiring part (111b) and the upper layer wiring part (125b).
[0084]
The plan view of FIG. 10 schematically shows the TFT portion after the pixel electrode is formed. As already described, the edge of the contact hole is located outside the arcuate edge of the source electrode on the pixel electrode side.
[0085]
In the above embodiment, the case where the semiconductor film (119) is made of a-Si: H has been described, but the same applies to a polycrystalline silicon film or the like. Further, the signal line pad (162) and the scanning line pad (152) pads (152) and (162) are described as being provided in the peripheral area of the array substrate. However, the drive circuit unit is integrated in the peripheral area of the array substrate. It may be formed and an input connection portion to this drive circuit portion may be formed.
[0086]
<Specific Examples>
(1) Design for over-etching
Specific examples of the adjustment of the contact hole design size and etching time in the resist pattern are as follows.
[0087]
a. The arc edge on the pixel electrode side of the contact hole in the resist pattern for the fourth patterning (sixth step) is the pixel electrode of the source electrode in the resist pattern for the third patterning (fifth step) Each mask pattern is adjusted to be 4 μm inside from the arcuate edge on the side.
[0088]
b. In the fifth step, side etching is 0.75 μm in the third patterning for forming the source electrode.
[0089]
c. In the sixth step, etching conditions are set so that the contact hole side etching rate is 1.8 μm / min, and etching is performed for 120 seconds. For example, buffered hydrofluoric acid is used at 28 ° C. for the interlayer coating insulating film (127).
[0090]
As a result of the above a. To c., The distance from the edge of the contact hole to the edge of the source electrode on the pixel electrode side is as follows.
[0091]
4 μm−0.75 μm− (1.8 μm × 120/60) = − 0.35 μm
That is, the edge of the contact hole is located outside the edge of the source electrode by 0.35 μm.
[0092]
(2) ITO film formation and patterning
d. In the seventh step, an ITO film having a thickness of 40 nm is deposited by sputtering at a substrate temperature of 230 ° C., exposed, developed, and then sprayed with 26% hydrochloric acid (26% HCl · aq) at a liquid temperature of 37 ° C. for 120 seconds. A pixel electrode (131) is produced by spray etching.
[0093]
(3) Inspection for point defects
e. When the final inspection of the array substrate manufacturing process was performed on the array substrate manufactured as described above, point defect defects due to ITO film stepping or etching solution penetration at the edge of the source electrode were not observed at all. There wasn't.
[0094]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the occurrence of disconnection in the pixel electrode pattern and the like, thereby reducing product defects.
[Brief description of the drawings]
FIG. 1 is a partial schematic plan view of an array substrate according to an embodiment of the present invention.
FIG. 2 is a schematic cross-sectional perspective view showing a laminated structure of a contact hole forming region in a TFT portion of an array substrate of an example.
FIG. 3 is a schematic cross-sectional perspective view showing a laminated structure of a contact hole forming region in a connection pad portion of an array substrate of an example.
4 is a cross-sectional view of the laminated layer after the fourth step when manufacturing the array substrate of the embodiment shown in FIGS.
FIG. 5 is a cross-sectional view after lamination of the fifth step when manufacturing the array substrate of the embodiment shown in FIGS.
FIG. 6 is a cross-sectional view of the lamination at the initial stage of etching in the sixth step when manufacturing the array substrate of the embodiment shown in FIGS.
FIG. 7 is a cross-sectional view of the laminated layer after over-etching in the sixth step when manufacturing the array substrate of the embodiment shown in FIGS.
FIG. 8 is a plan view of a TFT portion for schematically showing over-etching when manufacturing the array substrate of the example.
FIG. 9 is a cross-sectional view after lamination of the seventh step when manufacturing the array substrate of the embodiment shown in FIGS.
FIG. 10 is a plan view similar to FIG. 8 for further explaining the state of FIG. 9;
FIG. 11 is a schematic longitudinal sectional view showing a laminated structure of a contact hole forming region in a TFT portion of a conventional array substrate.
12 is a cross-sectional view of the stacked layers after the fifth step when the conventional array substrate shown in FIG. 11 is manufactured. FIG.
FIG. 13 is a cross-sectional view after lamination of the sixth step when manufacturing the conventional array substrate shown in FIG. 11;
FIG. 14 is a plan view of a TFT portion for schematically illustrating over-etching when a conventional array substrate is manufactured.
FIG. 15 is a cross-sectional view after lamination of the seventh step in manufacturing the conventional array substrate shown in FIG. 11;
16 is a plan view similar to FIG. 14 for further explaining the state of FIG. 15;
[Explanation of symbols]
110 Signal line (Mo film)
111 Scanning line (Mo-W film)
112 Thin film transistor (TFT)
113 Scanning line extension region
115 First gate insulating film (SiOx)
117 Second gate insulating film (SiN)
119 Semiconductor coating (a-Si: H)
123 Low resistance semiconductor coating (n ⁺ a-Si: H)
126a Drain electrode (Mo film)
126b Source electrode (Mo film)
126c Arc edge on the pixel electrode side of the source electrode
127 Interlayer insulation film (passivation film, SiN)
131 Pixel electrode (ITO film)
131a ITO film coated and connected to source electrode
131b connection
129 Contact hole for connection between source electrode and pixel electrode
129a Edge of contact hole on pixel electrode connection side
153, 155 First contact hole for scanning line pad
154, 156 Second contact hole for scan line pad
163, 165 First contact hole for signal line pad
164,166 Second contact hole for signal line pad

Claims (1)

A scanning line disposed on the substrate;
A thin film transistor including first and second insulating films disposed thereon, a semiconductor film disposed thereon, a source electrode and a drain electrode electrically connected to the semiconductor film;
A signal line derived from the drain electrode and substantially orthogonal to the scanning line;
A third insulating film covering the signal line and the source and drain electrodes;
A source electrode contact hole provided in the third insulating film so that a part of the upper surface of the source electrode is exposed;
In an array substrate for a display device comprising a pixel electrode electrically connected to the source electrode via a conductive layer covering the contact hole for the source electrode,
The source electrode contact hole is formed to expose an edge of the source electrode on a side connected to the pixel electrode;
On the side connected to the pixel electrode, the edge of the source electrode has a substantially arc shape, and the substantially arc-shaped edge is adjacent to the inside of the substantially circular edge of the contact hole for the source electrode. Are arranged,
An array substrate for a display device, wherein the source electrode and the pixel electrode are connected via the conductive layer in a portion that directly covers the edge.

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