JP3916631B2 - Node equipment - Google Patents

Description

  The present invention relates to a node device, and more particularly to a node device that switches from an active system to a standby system when a failure occurs.

  In recent years, with the development of communication, information has been increased in speed, capacity, and multimedia. In a network that transmits such information, in order to improve the reliability and operability of the network, it is important how quickly a fault location that has occurred is identified to restore the network.

  FIG. 10 shows a general network adopting the ring switching method. This network includes add / drop multiplexer (ADM) devices 101 and 201 and relay node devices (hereinafter also referred to as THRU nodes) 3001 and 3002.

  Both the insertion / branch multiple conversion node devices 101 and 201 have insertion and branching functions. FIG. 2 particularly shows a case where a signal is transmitted from the node device 101 to the node device 201. The node device (hereinafter sometimes referred to as an ADD node) 101 shows only the insertion function. The node device (hereinafter sometimes referred to as a DROP node) 201 shows only a branch function.

  The ADD node 101, the THRU node 3001, the DROP node 201, and the THRU node 3002 are connected in a ring shape in this order through outer high-speed transmission lines (line or section) 4001 to 4004 (hereinafter may be collectively referred to as reference numeral 400). In the reverse order, they are connected in a ring shape with inner high-speed transmission lines 5001 to 5004 (hereinafter sometimes collectively referred to as reference numeral 500).

  The ADD node 101 includes a working low-speed interface 201, a backup low-speed interface 202, a selector 24, and an insertion function unit 110. The DROP node 201 includes a branch function unit 210, a selector 41, a working low-speed interface 401, and a backup low-speed interface 402. I have. An operation terminal 700 is connected to the ADD node 101.

  In the ADD node 101, main signals (for example, VC3 / VC4 / VC4-4C) in units of paths input from the low-speed transmission paths 6001 and 6002 are given to the selector 24 via the low-speed interfaces 201 and 202, respectively.

  The selector 24 selects the main signal from the working low-speed interface 201, and sends the selected main signal to the outer high-speed transmission path 4001 and the inner high-speed transmission path 5001 via the insertion function unit 110.

  The main signal sent to the outer high-speed transmission line 4001 is transmitted to the DROP node 201 via the THRU node 3001 and the transmission line 4002, and the main signal sent to the inner high-speed transmission line 5001 is the THRU node 3002, the inner high-speed. The data is transmitted to the DROP node 201 via the transmission path 5002.

  In the DROP node 201, the branch function unit 210 gives the main signal separated from the transmission lines 4002 and 5002 to the selector 41. For example, the selector 41 selects a main signal separated from the current transmission line 4002 and sends it to the low-speed transmission lines 6003 and 6004 via the working low-speed interface 401 and the backup low-speed interface 402.

  As a result, the main signal input from the low-speed transmission line 6001 is sent to the low-speed transmission line 6003 via the current low-speed interface 201, the current transmission lines 4001 and 4002, and the current low-speed interface 401.

  The same main signal is sent to the low-speed transmission line 6004 via the backup interface 402.

  The DROP node 201 monitors the transmission quality on a path-by-path basis. If an abnormality (signal degradation, etc.) occurs in the current high-speed transmission line 4001 or 4002, the selector 41 has a good quality (a failure has occurred). Instructed to select the main signal via the spare high-speed transmission lines 5001 and 5002. This makes it possible to provide a stable service with good quality.

  However, in the ADD node 101, when an error due to an abnormality of the working low-speed interface 201 occurs in the main signal, the main signal including this error is sent to both the working transmission line 4001 and the spare transmission line 5001.

  In the DROP node 201, even if the selector 41 switches from the main signal via the transmission line 4002 to the main signal via the transmission line 5002, the main signal via the transmission lines 5001 and 5002 also includes an error. The main signal error continues. Further, this meaningless switching significantly deteriorates transmission quality.

  In addition, switching of the main signal extraction transmission path due to the main signal delay (time difference from the ADD node 101 to the DROP node 201) due to the outer / inner transmission path length (active / backup transmission path length) occurs alternately. Subsequently, frequent occurrence of switching notifications to the operation system may cause an increase in control communication traffic and confusion in maintenance work.

  Accordingly, an object of the present invention is to determine whether a failure that degrades transmission quality has occurred in a node device or a transmission line in a node device that switches from a working system to a standby system when a failure occurs.

(1) In order to solve the above-mentioned problem, a node device (for example, a DROP node) as an application example of the present invention is simultaneously sent from the opposite node device (for example, an ADD node) to the active transmission line and the standby transmission line. A relative phase difference detection unit that receives the main signal and detects a relative phase difference between the two, a path error detection unit that detects a path error passing through each transmission path, and the relative phase difference and each path error that are opposite to each other. and a, a transmission unit for transmitting to the node device (ADD node).

  That is, in FIG. 3, for example, the DROP node 200 can transmit “relative phase difference” and “path error” to the opposite ADD node 100.

  The relative phase difference detection unit 37 detects the relative phase difference between the main signals sent from the ADD node 100 to the active transmission line 400 and the standby transmission line 500 simultaneously. The path error detection unit detects the path error of both transmission paths, for example, the number of B3 byte errors of POH (Path OverHead) in SDH (Synchronous Digital Hierarchy), and the transmission unit detects the relative phase difference and each path error, for example Send to ADD node 100 in G1 byte.

  As a result, the ADD node 100 can determine whether a failure has occurred in the working transmission line, the standby transmission line, or the own apparatus based on the relative phase difference and each path error.

  That is, the ADD node 100 compares both path errors with the same phase based on the relative phase difference. Then, for example, 1) When each path error does not indicate “error”, the ADD node 100 determines that both the working / protection transmission line and the own device are normal, and 2) only one path error is “error”. It is determined that a failure has occurred in the transmission line corresponding to this path error. 3) When each path error indicates the same “error”, it can be determined that a failure has occurred in the device itself.

Therefore, since this determination is made based on the path errors of the same phase, it is possible to eliminate the switching error due to the transmission delay difference between the working and backup transmission paths.
(2) In the (1) above, further comprising a main signal error calculation unit which performs error calculation for each main signal from the transmission line and the backup transmission line for the developing, the transmission section, said relative position The phase difference, each path error, and each main signal error calculation result can be transmitted to the opposite node device (ADD node).

  That is, in FIG. 3, for example, the DROP node 200 can transmit “relative phase difference”, “path error”, and “main signal error calculation result” to the opposite ADD node 100.

  The ADD node 100 simultaneously sends main signals to the working transmission line and the backup transmission line. In the DROP node 200 that has received this, the relative phase difference detector 37 detects the relative phase difference between the two main signals.

  The main signal error calculation unit performs error calculation, for example, CRC calculation, of each main signal received from the working transmission line or the backup transmission line. The path error detection unit detects a path error passing through the working transmission line and the backup transmission line. The transmission unit transmits the relative phase difference, the two path errors, and the two main signal error calculation results to the opposing ADD node 100.

  Based on these relative phase differences, path errors, and main signal error calculation results, the opposite ADD node 100 can determine whether or not the own device itself has failed.

  The main signal error calculation unit does not necessarily calculate whether or not the main signal is transmitted without error. For example, if the two main signals are equal because the remainders of the CRC calculation of the two main signals are equal. An operation may be performed to determine.

When the same error occurs in two main signals, the CRC calculation results (remainder) of the two main signals are the same.
(3) In addition, a node device (for example, DROP node 200) as another application example of the present invention is a main device that is simultaneously sent from the opposite node device (for example, ADD node 100) to the active transmission line and the standby transmission line. A relative phase difference detection unit that receives a signal and detects a relative phase difference between them, a path error detection unit that detects a path error of each transmission path, and detects a failure based on the relative phase difference and each path error It includes a failure detection unit, a transmission unit for notifying the fault to the counter node device (ADD node 100), the.

  That is, in the figure, for example, the DROP node 200 detects a failure based on the “relative phase difference” and the “path error”, and this failure (for example, transmission path failure, failure of the opposite ADD node) is opposed to the ADD. The node 100 can be notified.

  As in the first aspect of the present invention, the relative phase difference detection unit detects the relative phase difference, and the path error detection unit detects path errors in both transmission lines. The present invention is different from the invention of claim 1 in that, instead of the ADD node 100 determining the failure of its own device, the failure detection unit detects a failure of the ADD node 100, for example, and transmits this failure to the transmission unit Is to notify the ADD node 100.

  As a result, the ADD node 100 can know whether or not a failure has occurred in its own device.

For example, when the network configuration is such that the ADD node 100 is also involved in switching between the active transmission line and the standby transmission line, the failure detection unit of the DROP node 200 detects a failure in the active transmission line or the standby transmission line. Then, this failure is notified to the ADD node 100. As a result, the ADD node 100 can switch between the active transmission line and the standby transmission line.
(4) Further, in the above SL (3), further comprising a main signal error calculation unit which performs error calculation of the main signal from the transmission path, the failure detection unit, said relative phase difference, each path errors and each A failure is detected based on the main signal error calculation result, and the transmission unit can notify the opposite node device (for example, ADD node 100) of the failure.

  That is, in the figure, for example, the DROP node 200 determines a failure based on the “relative phase difference”, “path error”, and “main signal error calculation result” to the opposite ADD node 100, and the failure is assigned to the ADD node 100. Can be notified.

  In the invention of claim 3, the main signal error calculation unit further performs error calculation of each main signal from the active transmission line and the backup transmission line, and the failure detection unit includes a relative phase difference, each path error, Based on each main signal error calculation result, a failure in the ADD node 100, the active transmission line, or the backup transmission line is detected, and the transmission unit notifies the ADD node 100 of the failure.

This also makes it possible for the ADD node 100 to know the failure of the device itself.
(5) In (1) above, the transmission unit may transmit using an unused portion of the relative phase difference path overhead.
(6) Further, a node device (for example, ADD node 100) as still another application example of the present invention is provided between an active transmission line and a standby transmission line sent from an opposite node device (for example, DROP node 200). A receiving unit that receives the relative phase difference of each channel and the path error of each transmission path, a delay control unit that performs phase alignment of each path error based on the relative phase difference, and a failure in the own device based on each path error of the same phase A failure determination unit that determines whether or not the occurrence of a failure has occurred .

  That is, in the figure, for example, the ADD node 100 can determine the failure of the own device based on the “relative phase difference” and “path error” transmitted from the opposite DROP node 200.

  The receiving unit of the ADD node 100 receives the relative phase difference between the working transmission line and the backup transmission line and the path error of each transmission line sent from the DROP node 200. The delay control unit of the ADD node 100 matches the phases of both path errors based on the relative phase difference, and the failure determination unit of the ADD node 100 determines, for example, the active main signal transmission unit of its own device based on each path error of the same phase. Determine whether a failure has occurred.

As a result, the ADD node 100 can determine that a failure has occurred in its own device.
(7) Further, in the above SL (6), the receiving unit further receives the main signal error calculation result of the transmission paths from the counter node device (DROP node 200), the delay control section, said relative position Based on the phase difference, the phase of each path error and each main signal error calculation result is matched, and the failure determination unit determines whether or not a failure has occurred based on each path error and each main signal error calculation result of the same phase. It is possible.

  That is, in the figure, the ADD node 100 determines its own failure based on the “relative phase difference”, “path error”, and “main signal error calculation result” transmitted from the opposite DROP node 200. can do.

  In the ADD node 100, the receiving unit further receives each main signal error calculation result of the working transmission line and the backup transmission line from the opposite DROP node 200. The delay control unit matches the phase of the relative phase difference, each main signal error calculation result, and each path error.

  The failure determination unit determines, for example, whether or not a failure has occurred in the own device, based on the output of the delay control unit, that is, both main signal error calculation results and the both path errors in the same phase.

  That is, for example, the failure determination unit compares both main signal error calculation results, and when the result is “match”, it recognizes that there is no failure in the transmission path, and further, the path error is “error”. It is possible to recognize that a failure has occurred in the active main signal transmission unit (for example, the interface unit) of the own device.

  The failure determination unit can also determine whether a failure has occurred in the active transmission line or the backup transmission line.

However , in the ADD node 100, if an error has already occurred in the main signal path input from the low-speed transmission path 600, it is determined that the working low-speed interface 201 has failed. Therefore, when a path error of the low-speed interface 20 is detected, it is necessary to exclude the failure determination of the working low-speed interface 201.
(8) Therefore, in the above (6) , the present invention provides a path error detection unit that detects an error on the low-speed transmission path side of the path, and the low-speed transmission when the relative phase difference is the first relative phase difference. A relative phase difference detection unit for detecting a second relative phase difference indicating a relative phase difference between a roadside path error and the path error from the opposite node device (DROP node 200); When a control unit is used, a second delay control unit that matches the phase of the path error from the opposite node device (DROP node 200) and the low-speed transmission path side path error based on the second relative phase difference. In addition, the failure determination unit is characterized by determining whether or not a failure has occurred in the own apparatus based on each path error of the same phase.

  That is, in the figure, for example, the ADD node 100 has a “first relative phase difference” and a “path error” given from the opposite DROP node 200 and a “second relative phase difference” detected by the own apparatus. Also, the failure of the own device is determined based on the “low-speed path error”.

  The ADD node 100 further includes a path error detection unit, a relative phase difference detection unit, and a second delay control unit. The path error detection unit detects a path error on the low-speed transmission path side of the same path as the working / protection transmission path.

  The relative phase difference detection unit detects a second relative phase difference indicating a relative phase difference between the low-speed transmission path side path error and each path error from the DROP node 200. The second delay control unit matches the phase of the path error from the DROP node 200 with the low-speed transmission path side path error based on the second relative phase difference.

  The failure determination unit determines whether or not a failure has occurred in its own device based on each path error from the DROP node 200 and the low-speed transmission path side path error.

  At this time, when the low-speed transmission path side path error indicates “error”, for example, it is assumed that the failure has not occurred in the own apparatus.

Thereby, the failure determination unit can detect the failure of the ADD node or the transmission line in the same manner as described above in a state where the path error failure on the low-speed transmission line side is excluded.
(9) Further, according to the present invention, in the above-described present invention, the receiving unit further receives a main signal error calculation result of each transmission path from the opposite node device (DROP node 200), and the first delay control. The unit matches the phase of each path error and each main signal error calculation result based on the first relative phase difference, and the failure determination unit determines that the own device based on each path error and each main signal error calculation result of the same phase It is possible to determine whether or not a failure has occurred.

  That is, for example, the ADD node 100 detects the “first relative phase difference”, the “path error”, and the “main signal error calculation result” given from the opposite DROP node 200, and the “second” detected by the own device. Is determined based on the “relative phase difference” and “low-speed path error”.

  In the ADD node 100, the receiving unit receives the “first relative phase difference”, each path error, and each main signal error calculation result from the DROP node 200. The first delay control unit makes the phase of each path error and each main signal error calculation result the same based on the first relative phase difference.

  The second delay control unit sets the path error on the low-speed transmission path side to the same phase as each path error from the DROP node 200 based on the second relative phase difference.

  The failure determination unit determines whether or not a failure has occurred in the own apparatus based on the path error on the low-speed transmission path side of the same phase, each path error from the DROP node 200, and each main signal error calculation result. At this time, when the low-speed transmission path side path error indicates “error”, for example, it is assumed that the failure has not occurred in the own apparatus.

As a result, when an error has already occurred in the main signal path input from the low-speed transmission path side, the ADD node 100 does not determine that a failure has occurred in its own device based on this path error .

  FIG. 1 shows an embodiment of a node device according to the present invention, in particular, an ADD node 100 that transmits a main signal to an opposite node device. In this embodiment, only the functional unit that processes the control signal received by the ADD node 100 from the low-speed transmission line 600 and the high-speed transmission lines 400 and 500 is shown, and the functional part that processes the main signal is omitted.

  The ADD node 100 includes an inner loop detection control unit 102 connected to the inner loop high speed transmission line 500, an outer loop detection control unit 101 connected to the outer loop high speed transmission path 400, and a section multiplexing unit 22 connected together with the high speed transmission paths 400 and 500. A transmission J1MF control unit 21 connected to the detection control units 101 and 102 and the section multiplexing unit 22, a selector 24 connected to the low-speed interfaces 201 and 202 (hereinafter may be collectively referred to as reference numeral 20), and detection control. A failure determination unit 23 and a low-speed input B3 error detection unit 25 connected to the units 101 and 102 and the selector 24, respectively.

  The detection control unit 102 detects the J1MF byte (J1 multiframe byte), CRC (Cyclic Redundancy Check) value, and B3 byte from the inner high-speed transmission path 500, respectively, the MF byte detection unit 11, the CRC detection unit 15, and the opposite B3. CR / LF detector 12 that detects the “CR” and “LF” codes from the J1MF byte detected by the detector 16 and the MF byte detector 11, and the inner / outer relative relative to the detection result of the CR / LF detector 12 A relative delay detector 13 for detecting a delay is provided.

  Further, the inner loop detection control unit 102 detects the transmission path delay detection unit 14 that detects the delay of the transmission path based on signals from the transmission J1MF control unit 21, the CR / LF detection unit 12, and the relative delay detection unit 13. Delay control units 17 to 19 that delay the signals detected by the CRC detection unit 15, the opposite B3 detection unit 16, and the low-speed input B3 error detection unit 25 and give them to the failure determination unit 23 by the transmission path delay amount, respectively. .

  The outer loop detection control unit 101 has the same configuration as the inner loop detection control unit 102, but the MF byte detection unit 11, the CRC detection unit 15, and the opposing B3 detection unit 16 are respectively connected from the inner loop high-speed transmission path 500 to the J1MF byte, CRC. The value is different from detecting the opposite B3 byte.

  FIG. 2 shows an embodiment of a DROP node 200 that receives a main signal from a node device or an opposite node device (ADD node) according to the present invention. In this embodiment, in particular, only the functional unit that processes the control signal received from the opposite node device is shown, and the functional unit that processes the main signal is omitted.

  This DROP node 200 includes a main signal detector 311 and a J1MF detector 351 that detect the main signal and the J1MF byte from the outer high-speed transmission path 400, respectively, and a CRC that calculates the CRC value D3a and B3 byte D3b of the detected main signal, respectively. Control information for inserting the calculation unit 321 and the B3 calculation unit 331, the calculated CRC value D4a and the B3 byte D4b (hereinafter, the CRC value D3a and the B3 byte D3b may be referred to as control information D3) into the unused byte 3. An insertion unit 341 and a CR / LF detection unit 361 for detecting a “CR” + “LF” code from the J1 multiframe are provided.

  The DROP node 200 also includes a main signal detection unit 312, a J1MF detection unit 352, a CRC calculation unit 322, a control information insertion unit 342, a B3 calculation unit 332, and a CR / LF detection unit 362. These functions are the same as the main signal detection unit 311, J1MF detection unit 351, CRC calculation unit 321, control information insertion unit 341, B3 calculation unit 331, and CR / LF detection unit 361, respectively. The detection unit 312 and the J1MF detection unit 352 detect the main signal and the J1 multiframe on the inner high-speed transmission path 500 instead of the outer high-speed transmission path 400, respectively, and the control information insertion unit 342 detects the CRC value D4a and the B3 byte D4b ( Hereinafter, the CRC value D4a and the B3 byte D4b may be referred to as control information D4.

  Furthermore, the DROP node 200 detects the phase difference between “CR” + “LF” detected by the CR / LF detection unit 361 and “CR” + “LF” detected by the CR / LF detection unit 361. “CR” + “LF” and “phase difference” (hereinafter, “CR” + “LF” + “phase difference”) detected by the detection unit 37 and the CR / LF detection unit 361 may be referred to as control information D1. .) Is inserted into unused MF byte 1 and the CR / LF detection unit 362 detects “CR” + “LF” and the phase difference (hereinafter referred to as “CR” + “LF”). The control information insertion unit 382 that inserts the phase difference into the unused MF byte 2 and the section multiplexing unit 39 that multiplexes the control information D1 to D4 into the sections.

Example of operation (1)
An operation embodiment (1) when the ADD node 100 (see FIG. 1) and the DROP node 200 (see FIG. 2) of the present invention are applied to the network shown in FIG. 10 will be described below with reference to FIGS. explain.

  FIG. 3 shows the flow of control signals from the ADD node 100 to the DROP node 200.

  In the ADD node 100, the working low speed interface 201 and the backup low speed interface 201 give the control signals received from the low speed transmission lines 6001 and 6002 to the selector 24, respectively. The selector 24 selects a control signal from the working low-speed interface 201 and gives it to the transmission J1MF control unit 21.

  The transmission J1MF control unit 21 creates, for example, 64 J1 multiframes, and inserts a “CR” code and an “LF” code into the 30th and 31st frames of the J1 multiframe, respectively. FIG. 4 (1) shows a J1 multiframe created by the transmission J1MF control unit 21.

  The transmission J1MF control unit 21 transmits the same multiframe to the outer high-speed transmission path 400 and the inner high-speed transmission path 500.

  In DROP node 200, J1MF detection sections 351 and 352 extract J1 multiframes included in main signal paths received from outer high-speed transmission lines 400 and 500, respectively. The CR / LF detectors 361 and 362 detect “CR” and “LF” inserted in the J1 multiframe.

  FIGS. 2 (2) and 3 (3) show examples of reception timings of J1 multiframes extracted by the J1MF detection units 352 and 351, and “CR” and “LF” inserted therein.

  Since the transmission delay between the outer high-speed transmission line 400 and the inner high-speed transmission line 500 is different, the outer “CR” code and the “LF” code in FIG. It is received one frame later than the code and “LF” code.

  The relative phase difference detection unit 37 obtains a relative phase difference between the outer and inner turns. That is, the detection unit 37 detects how late the outer loop “CR” code and “LF” code received later are based on the inner loop “CR” code and “LF” code received earlier.

  The control information insertion units 381 and 382 use the J1 multiframe byte extracted by the J1MF detection units 351 and 352 for each frame as an unused multiframe byte (inner phase difference information) and an unused multiframe byte (outer phase difference). Information) and the relative phase difference information detected by the relative phase difference detection unit 37 is multiplexed, for example, on the next frame (frame number 32) of “CR” “LF”.

  FIGS. 4 (4) and 5 (5) show an example of an inner frame and an outer frame in which phase difference information is inserted. “0” and “1” are inserted in frame number 32, respectively. Hereinafter, the inner / outer transmission path delay information shown in FIGS. 4 (4) and 5 (5) may be referred to as control information D2 and D1, respectively.

  The CRC calculation unit 321 and the B3 calculation unit 331 calculate the CRC value D3a and the error bit number D3b of the B3 byte of the main signal received from the outer high-speed transmission path 400, respectively. The control information insertion unit 341 inserts the CRC value D3a and the B3 error bit number D3b into the control information D3.

  Similarly, the CRC calculation unit 322 and the B3 calculation unit 332 calculate the CRC value D4a of the main signal received from the inner high-speed transmission path 500 and the error bit number D4b of the B3 byte, respectively, and the control information insertion unit 342 D4a and the number of B3 error bits D4b are inserted into the control information D4.

  The section multiplexing unit 39 multiplexes the control information D1 and D2 into the unused bytes of the multiframe, and sends the signal in which the control information D3 and D4 are multiplexed into the unused bytes together with the outer high-speed transmission line 400 and the inner high-speed transmission line 500. .

  FIG. 5 shows an operation in which the control information D1 to D4 is transmitted from the DROP node 200 (see FIG. 2) to the ADD node 100 (see FIG. 1) and processed in the ADD node 100.

  The control information D1 to D4 is transmitted from the DROP node 200 to the ADD node 100 via the outer high-speed transmission lines 4003 and 4004 and the inner high-speed transmission lines 5003 and 5004.

  In ADD node 100, MF byte detectors 11 and 11 ′ receive control information D1 to D4 from inner high-speed transmission path 500 and outer high-speed transmission path 400, respectively.

  In the ADD node 100, delay control and data processing can be performed based on the control information D1 to D4 received by one of the MF byte detection units 11 and 11 ′.

  In the figure, the MF byte detection unit 11 performs delay control and data processing on the control information D1 to D4 received from the inner loop high-speed transmission path 500.

  The relative delay detection unit 27 (corresponding to the detection units 12 to 14 in FIG. 1) detects the control information D1 and D2, and based on these control information D1 and D2, the inner high-speed transmission path 500 and the outer high-speed transmission path 400 Relative phase (delay time) difference is extracted.

  6 (1) and 6 (2) show control information D2 and D1 received by the relative delay detection unit 27, respectively. The relative delay detection unit 27 includes a 64-hexadecimal counter (not shown) that counts the multi-frame number. "," LF ", and" internal and external phase difference information = 0 "are extracted.

  The relative delay detection unit 27 recognizes that the inner main signal has reached the DROP node 200 earlier than the outer main signal because the phase difference information = “0”.

  The 64-hexadecimal counter is a self-running counter, and the count number (multiframe number shown in the figure) is irrelevant to the multiframe number of the DROP node 200. The case where the same number as the multiframe number is shown.

  Further, the relative delay detection unit 27 outputs the outer loop J1 byte = “CR”, “LF”, “inner and outer phase difference information = 1 at the timing of the multiframe numbers =“ 31 ”,“ 32 ”, and“ 33 ”. ”Is extracted.

  Thus, the relative delay detection unit 27 recognizes that the outer main signal reaches the DROP node 200 after the inner main signal, and the difference (relative phase difference) is one frame.

  The control information detection unit 26 (corresponding to the CRC detection unit 15 and the counter B3 detection unit 16 in FIG. 1) detects the control information D3 (“outside CRC value D3a” + “outside B3 error bit number D3b”), “CRC value D3a” and “B3 error bit number D3b” are applied to CRC delay control unit 17 and B3 delay control unit 18, respectively.

  The CRC delay control unit 17 and the B3 delay control unit 18 respectively provide the “outer CRC value” and the “outer B3 error bit number” to the failure determination unit 23 without delay control.

  Similarly, the control information detection unit 26 ′ (corresponding to the CRC detection unit 15 ′ and the opposing B3 detection unit 16 ′ in FIG. 1) has control information D4 (“inner CRC value D4a” + “inner B3 error bit number D4b”). “)” And “inner CRC value D4a” + “inner B3 error bit number D4b” are supplied to CRC delay control unit 17 ′ and B3 delay control unit 18 ′, respectively.

  The CRC delay control unit 17 ′ and the B3 delay control unit 18 ′ delay the “inner CRC value D4a” + “inner B3 error bit number D4b” by one frame, respectively, and then give the delay determination unit 23.

  As a result, the phase difference between the “outer CRC value D3a” and the “outer B3 error bit number D3b” and the “inner CRC value D4a” and the “inner B3 error bit number D4b” is eliminated.

  FIG. 7 shows the delay control in the delay control units 17, 17 ′, 18, 18 ′ and the determination of the failure determination unit 23.

  (1) shows control information (inner CRC value D4a and inner B3 error bit number D4b) D4 included in data DATA01 to DATA91, and (2) shows control information included in data DATA02 to DATA82 ( The outer CRC value D3a and the outer B3 error bit number D3b) D3.

  The failure determination unit 23 receives the control information D4 shown in FIG. 4 (4) obtained by delay-controlling the control information D4 of FIG. 1 (1) by one frame, and receives the control information D3 without delay control. As a result, the failure determination unit 23 indirectly outputs the main signal of the same (the same phase in which the delay difference (phase difference) between the outer high-speed transmission line 400 and the inner high-speed transmission line 500 is absorbed) when reaching the DROP node 200 based on the CRC value. Therefore, comparison ((3) in the figure) can be performed.

  FIG. 5 (5) shows a comparison result (“match” or “mismatch”) between the outer CRC value D3a and the inner CRC value D4a. (6) in the figure shows the presence or absence of a B3 error (logical sum = “0: no error”) determined based on the logical sum operation result of “outer B3 error bit number D3b” and “inner B3 error bit number D4b”, “ Other than 0: There is an error ”).

  FIG. 7 (7) shows determination results (A1) to (A4) in which the failure determination unit 23 determines a failure based on the comparison result of FIG. 5 (5) and the determination result of FIG. 6 (6).

(A1): "Comparison result match"&"Noerror" = "Sender normal" and "Transmission path normal"
(A2): “Comparison result does not match” & “There is an error” = “Failure occurred in outer high-speed transmission line 400 or inner high-speed transmission line 500” → Supported by conventional ring switching
(A3): “Comparison result match” & “There is an error” = “Abnormal working low-speed interface 201” is judged (During protection time: In this embodiment, the number of protection stages = “3” is set)
(A4): “Comparison result match” & “With error” = “Package error of ADD node 100” determined (protection time elapses) → Control selector 24 to switch from current low speed interface 201 to spare low speed interface 202 .

Example of operation (2)
In the above embodiment (1), it is determined whether or not a main signal error has already occurred on the ADD node 100 side and whether or not an error has occurred due to a high-speed transmission path failure. The low speed interfaces 201 and 202 of the node 100 are switched, or the high speed transmission lines 400 and 500 are switched.

  However, in the ADD node 100, when an error has already occurred in the main signal input from the low-speed transmission path 600, it is determined that the working low-speed interface 201 and the switched low-speed interface 202 have failed, and the failure has occurred. The switching operation of the low-speed interface 20 that is not present is repeated.

  Therefore, when an error occurs in the main signal input from the low-speed transmission path 600, it is necessary to suppress the switching of the low-speed interface 20 without performing the failure determination of the low-speed interface 20.

  An operation in which the failure determination unit 23 suppresses switching of the active low-speed interface 20 when there is an error in the main signal of the low-speed transmission path 600 will be described below.

  In FIG. 5, a low-speed input B3 error detection unit 25 calculates B3 of the main signal input from the low-speed transmission path 600 and detects the low-speed B3 error bit number D5b.

  The relative delay detection unit 27 detects the delay amount around the ring, and provides this delay amount to the B3 delay control unit 19. The B3 delay control unit 19 sets the number of low-speed B3 error bits so as to be the same timing as other “CRC values D3a, D4a” and “B3 error bit numbers D3b, D4b”, that is, to be information of the same frame. D5b is delay-controlled and provided to the failure determination unit 23.

  8 (1) shows the timing at which the transmission J1MF control unit 21 (see FIG. 1) inserts data “CR” + “LF” into the inner high-speed transmission path 500 via the section multiplexing unit 22 in the ADD node 100. Show. This timing is notified from the transmission J1MF control unit 21 to the transmission line delay detection unit 14.

  In the figure (2), the CR / LF detector 12 (see FIG. 1) goes around the inner high-speed transmission path (ADD node 100 → DROP node 200 → ADD node 100) 500 via the MF byte detector 11. The timing of extracting the data “CR” + “LF” that has returned is shown. This timing is also notified from the CR / LF detector 12 to the transmission line delay detector 14.

  The transmission line delay detection unit 14 can determine the transmission delay time (phase difference) of one round of the inner high-speed transmission line 500 by comparing the two timings. That is, it can be seen that the round-trip transmission delay amount = 61−1 = 60 frames.

  By performing the next delay control based on this round-trip transmission delay amount, it becomes possible to compare the number of B3 error bits of the same main signal component when received by the ADD node 100 and the DROP node 200.

  For example, when control information D2 (inner circuit information phase difference) = 0 frame and control information D1 (outer circuit information phase difference) = 1 frame, delay control for “1” frames of outer circuit control information D1 is performed. Further, since it is necessary, the B3 delay control unit 19 performs delay control for “60 frames (for one round of the ring) +1 frame” with respect to “the number of low-speed B3 error bits D5b”.

  Further, by performing the following delay control (1) to (4) as in the embodiment (1), it becomes possible to handle all information as the same main signal frame information.

(1) The inner CRC value is delayed by +1 frame, (2) The inner B3 error bit number is delayed by +1 frame, (3) No outer CRC value delay, and (4) Outer B3 error bit number In contrast, when control information D2 (inner circuit information phase difference) = 1 frame and control information D1 (outer circuit information phase difference) = 0 frame, the following delay control (1) to (5) I do.

(1) No inner CRC value delay control, (2) No inner B3 error bit delay control, (3) One outer frame CRC delay control, (4) One outer B3 error bit frame (5) Delay control of 60 frames of the low-speed B3 error bit number of the ADD node FIG. 9 (5) and (6) are respectively FIGS. 7 (5) and (6) of the embodiment (1). ), CRC value comparison results (match, mismatch, or don't care = X) after delay control of the control information D3, D4 shown in (1) to (4) in FIG. Yes, no, or don't care = X). FIG. 9 (8) shows the presence / absence of an error in the number of low-speed B3 error bits.

  FIG. 9 (9) shows determination results (B1) to (B5) of the failure determination unit 23 based on FIGS. 5 (5), (6), and (8). The determination results (B1) to (B5) will be described below.

(B1): "Comparison result match"&"Noerror"&"No slow error"
= Normal transmission source, normal transmission path
(B2): “Comparison result mismatch” & “Error” & “No low speed error”
= Failure in either outer high-speed transmission line 400 or inner high-speed transmission line 500 → Supported by conventional ring switching
(B3): "Comparison result match"&"ErrorERR"&"Slowerror"
= Determined that the working low-speed interface 201 is abnormal (during protection time: in this example (2), when the number of protection stages = "3")
(B4): "Comparison result match"&"There is an error"&"No slow error"
= Determine that the current low-speed interface 201 is abnormal (protection time has elapsed)
→ The working low-speed interface 201 is switched to the spare low-speed interface 202 by the selector 24 to relieve the main signal.

 (B5): “There is a low-speed error” = It is determined that an error has already occurred from the low-speed transmission path 600, and failure determination and switching by the selector 24 are not performed.

  As described above, according to the node device of the present invention, the relative phase difference detection unit detects the relative phase difference between the transmission delays of the active transmission line and the standby transmission line, and the path error detection unit detects each transmission line. An error is detected in the path through which one of the opposing node devices detects a failure based on each path error that has the same phase based on the relative phase difference. Alternatively, it is possible to determine whether or not a failure has occurred in the device itself.

  In addition, the main signal error calculation unit performs error calculation of each main signal from the working transmission line and the standby transmission line, and based on each calculation result and each path error having the same phase with the relative phase difference, the working transmission line, It is possible to determine whether or not a failure has occurred in the backup transmission path or the device itself.

  Also, since the path error on the low-speed transmission path side and each path error on the active high-speed transmission path and the backup high-speed transmission path are compared with the same phase, the path error generated on the low-speed transmission path side It will not be mistaken for a path error occurring on the transmission line side.

  For example, in a ring switching type network, in the case where a main signal error occurs intermittently at the DROP node due to a package failure on the ADD node side, the main signal error and transmission path quality caused by the failure of the ADD node It is possible to distinguish from the main signal error caused by the deterioration.

  As a result, even in cases where the main signal path switching (ring switching) cannot be remedied in the past, the main signal can be remedied by switching the abnormal package on the ADD node side. Can be improved.

It is the block diagram which showed the Example of a structure of the node apparatus concerning this invention, especially an ADD node. It is the block diagram which showed the Example of a structure of the node apparatus based on this invention, especially a DROP node. It is the figure which showed the processing operation | movement of the control information transmitted to the DROP node from the ADD node in the ring network using the node apparatus (ADD node and DROP node) which concerns on this invention. It is the figure which showed the data example of the multi-frame for calculating | requiring the transmission delay in the ring network using the node apparatus which concerns on this invention. It is the figure which showed the processing operation | movement of the control information transmitted to the ADD node from the DROP node in the ring network using the node apparatus (ADD node and DROP node) which concerns on this invention. It is the figure which showed the example of the multi-frame which the node apparatus (ADD node) concerning this invention received. It is the figure which showed the example of determination of the failure determination part of the ADD node in operation | movement Example (1) of the node apparatus based on this invention. It is the figure which showed the example of transmission line round-trip transmission delay amount judgment in operation | movement Example (2) of the node apparatus which concerns on this invention. It is the figure which showed the example of determination of the failure determination part of the ADD node in operation | movement Example (2) of the node apparatus based on this invention. It is the block diagram which showed the general ring type network comprised with the conventional node apparatus.

Explanation of symbols

100, 101 ADD node 110 Insertion function
200, 201 DROP node 210 Branch function
3001, 3002 THRU node
400, 4001 to 4004 Outer high-speed transmission path
500, 5001 to 5004 Inner high-speed transmission line
600, 6001 to 6004 Low-speed transmission line 700 Operation terminal
101 Outer loop detection control unit 102 Inner loop detection control unit
11, 11 'MF byte detector 12 CR / LF detector
13 Relative delay detector 14 Transmission line delay detector
15, 15 'CRC detector 16, 16' Counter B3 detector
17, 17 'CRC delay controller 18, 18' B3 delay controller
19 Delay controller 20, 201, 202 Low speed interface
21 Transmission J1MF control section 22 Section multiplexing section
23 Failure judgment part 24 Selector
25 Low-speed input B3 error detector 26, 26 'Control information detector
27 Relative delay detector
311, 312 Main signal detector 321, 322 CRC calculator
331, 332 B3 calculation unit 341, 342 Control information insertion unit
351, 352 J1MF detector 361, 362 CR / LF detector
37 Relative phase difference detector 381, 382 Control information inserter
39 Section multiplexing section
401 Current low speed interface 402 Backup low speed interface
41 selector
D1-D4 control information
D3a Outer circuit CRC value D3b Outer circuit B3 error bit number
D4a inner CRC value D4b inner B3 error bit number
D5b Number of low-speed B3 error bits In the figure, the same symbols indicate the same or corresponding parts.

Claims (2)

A receiver that receives the first relative phase difference between the active transmission line and the backup transmission line and the path error of each transmission line that are sent from the opposite node device;
On the basis of the first relative phase difference, a first delay control section for phase alignment of each path error,
A failure determination unit that determines whether or not a failure has occurred in the device based on each path error of the same phase;
A path error detection unit for detecting an error on the low-speed transmission path side of the path;
A relative phase difference detector that detects a second relative phase difference indicating a relative phase difference between the low-speed transmission path side path error and the path error from the opposite node device;
A second delay control unit that adjusts the phase of the path error from the opposite node device and the low-speed transmission path side path error based on the second relative phase difference;
The failure determination section, based on each path errors of the same phase, the node device characterized by determining whether the self-device failure. In claim 1,
The receiving unit further receives a main signal error calculation result of each transmission path from the opposite node device, and the first delay control unit receives each path error and each main signal based on the first relative phase difference. A node device , wherein the phases of error calculation results are matched, and the failure determination unit determines whether a failure has occurred in the own device based on each path error and each main signal error calculation result of the same phase .

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