JP3913530B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which, when a metal having hydrogen storage properties is used as a barrier metal layer, the charge on the surface of the substrate is suppressed by hydrogen treatment to improve characteristics.
[0002]
[Prior art]
An aluminum-based metal material such as an aluminum alloy is generally used as the wiring of the semiconductor device on the silicon substrate. In this case, however, silicon is mixed in the aluminum alloy in order to suppress interdiffusion between aluminum and silicon, which is called a spike, and there is a problem that contact defects due to silicon grains (silicon nodules) increase. there were. Therefore, before forming the wiring layer, a barrier metal layer made of a titanium-based metal (for example, Ti, TiN, TiON, TiW, etc.) is formed to suppress Si nodules and at the contact portion between the wiring layer and the semiconductor substrate surface. Mutual diffusion is prevented.
[0003]
With reference to FIGS. 8 to 10, a conventional semiconductor device manufacturing method will be described by taking a trench-type power MOSFET as an example.
[0004]
In FIG. 8, the drain region 22 is formed by laminating an N ⁻ type epitaxial layer on the N ⁺ type silicon semiconductor substrate 21. After the oxide film is formed on the surface, the oxide film in the portion of the planned channel layer 24 is etched. Using this oxide film as a mask, boron is implanted over the entire surface with a dose of 1.0 × 10 ¹³ , and then diffused to form a P-type channel layer 24.
[0005]
Next, a trench is formed. An NSG (Non-doped Silicate Glass) CVD oxide film is formed on the entire surface by CVD, and the resist oxide mask is removed except for the trench opening, and the CVD oxide film is partially removed by dry etching. Then, a trench opening in which the channel region 24 is exposed is formed.
[0006]
Further, using the CVD oxide film as a mask, the silicon semiconductor substrate in the trench opening is dry-etched with CF-based gas and HBr-based gas to form a trench 27 that penetrates the channel layer 24 and reaches the drain region 22.
[0007]
In FIG. 9, a gate oxide film 31 and a gate electrode 33 are formed. First, dummy oxidation is performed to form a dummy oxide film on the inner wall of the trench 27 and the surface of the channel layer 24 to remove etching damage during dry etching. By removing the dummy oxide film and the CVD oxide film formed by this dummy oxidation simultaneously with an oxide film etchant such as hydrofluoric acid, a stable gate oxide film can be formed. In addition, the thermal oxidation at a high temperature has an effect of rounding the opening of the trench 27 and avoiding electric field concentration at the opening of the trench 27. Thereafter, a gate oxide film 31 is formed. That is, the entire surface is thermally oxidized to form the gate oxide film 31 with a thickness of, for example, about 700 mm according to the threshold value.
[0008]
Thereafter, a non-doped polysilicon layer is deposited on the entire surface, phosphorus is implanted and diffused at a high concentration to increase the conductivity, and the polysilicon layer deposited on the entire surface is dry-etched without a mask and embedded in the trench 27. The gate electrode 33 left is left.
[0009]
In addition, a body contact region 34 and a source region 35 for stabilizing the substrate potential are formed. First, boron is selectively ion-implanted with a mask made of a resist film to form a P ⁺ -type body contact region 34, and then the resist film is removed. Further, a new resist film is used to mask the planned source region 35 and gate electrode 33 so that arsenic is ion-implanted to form an N ⁺ -type source region 35 on the surface of the channel layer 24 adjacent to the trench 27. Then, the resist film is removed. Thereafter, a BPSG (Boron Phosphorus Silicate Glass) layer is deposited on the entire surface by a CVD method to form an interlayer insulating film 36, and the interlayer insulating film 36 is left at least on the gate electrode 33 using the resist film as a mask.
[0010]
In FIG. 10, a barrier metal layer 37 is first provided to form a wiring layer. This is because the silicon substrate is exposed at portions other than the interlayer insulating film 36, and when the aluminum alloy to be the wiring layer 38 is sputtered, the silicon grains (silicon nodules) included in the aluminum alloy are fine regions. The contact area 34 may be blocked. In order to suppress this silicon nodule and to prevent mutual diffusion between a metal called a spike and the silicon substrate, a barrier metal layer 37 made of a titanium-based material (for example, Ti / TiN) is provided.
[0011]
A barrier metal layer 37 is formed by sputtering Ti / TiN or the like on the entire surface, and subsequently, an aluminum alloy to be the wiring layer 38 is sputtered on the entire surface. Thereafter, an alloying heat treatment is performed to stabilize the metal and silicon surfaces. This heat treatment is performed in a hydrogen-containing gas at a temperature of 300 to 500 ° C. (for example, about 400 ° C.) that does not exceed the melting point of the aluminum alloy for about 30 minutes to remove crystal distortion in the metal film and stabilize the interface. .
[0012]
Thereafter, a passivation film made of SiN or the like is formed as a surface protective film. Thereafter, in order to remove damage, heat treatment is performed at 300 to 500 ° C. (for example, 400 ° C.) for about 30 minutes, and the previous step is completed.
[0013]
Referring to FIG. 10, the structure of a trench type power MOSFET is shown. A drain region 22 made of an N ⁻ type epitaxial layer is provided on an N ⁺ type silicon semiconductor substrate 21, and a P type channel layer 24 is provided on the surface thereof. A trench 27 that penetrates the channel layer 24 and reaches the drain region 22 is provided, an inner wall of the trench 27 is coated with a gate oxide film 31, and a gate electrode 33 made of polysilicon filled in the trench 27 is provided. An N ⁺ type source region 35 is formed on the surface of the channel layer 24 adjacent to the trench 27, and a P ⁺ type body region 34 is provided on the surface of the channel layer 24 between the source regions 35 of two adjacent cells. Further, when the gate electrode 33 is applied, a channel region (not shown) is formed from the source region 35 along the trench 27. The gate electrode 33 is covered with an interlayer insulating film 36, a barrier metal layer 37 in contact with the source region 35 and the body region 34 is formed, and a wiring layer 38 made of aluminum alloy or the like is provided.
[0014]
[Problems to be solved by the invention]
In such a conventional MOSFET, the barrier metal layer 37 and the wiring layer 38 are continuously formed in the wiring layer forming step after the element region is formed, and then heat-treated in a hydrogen-containing gas to form an alloy, thereby stabilizing the surface. I was letting. When a metal such as aluminum (Al) is deposited on silicon (Si), a Schottky junction is ideally formed at the interface. However, in reality, since a natural oxide film exists on Si, ideal rectification characteristics are not exhibited. Therefore, in order to make the Ai / Si interface ohmic characteristics, heat treatment in a hydrogen-containing gas (hereinafter referred to as hydrogen alloy). Thus, it is necessary to alloy the Al / Si interface. However, since the Si diffusion rate in Al is high, a phenomenon called a spike occurs in which Al and Si are interdiffused, and Al diffuses into Si and breaks the pn junction. In order to avoid this, Al contains Si in advance.
[0015]
However, due to this hydrogen alloy, Si contained in Al may diffuse and grow, and precipitate as Si nodules at the contact interface with the substrate. This Si nodule closes the body contact region, which is a fine region, and causes contact failure, or the Si nodule itself has a high resistance, which may cause the contact resistance to become unstable or increase.
[0016]
For this reason, in order to prevent mutual diffusion in the hydrogen alloy process and to suppress contact failure due to Si nodules, a barrier metal layer made of a titanium-based metal is formed before Al film formation.
[0017]
Furthermore, the Si surface may exist in a state in which the Si bond is broken due to oxidation or the like in the element region forming step, and in this case, it is considered that the surface is charged with a negative charge. For this reason, since a potential is generated and the electric field is applied to the surface, the threshold voltage varies. For this reason, in the hydrogen alloy process, by bringing hydrogen to the MOSFET interface or the like, Si and hydrogen are combined to remove charges on the Si interface, thereby improving characteristics (for example, reducing dark current) Stability (for example, stable threshold voltage) is achieved.
[0018]
However, in the conventional manufacturing method, it has been found that even if hydrogen alloying is performed, it is difficult to sufficiently eliminate the charge at the interface, and V _GSOFF (threshold voltage) shifts.
[0019]
FIG. 11 shows V _GS -ID curves with and without the barrier metal layer (dotted line) and without (solid line). When a barrier metal layer is formed, V _GS shifts to a lower side (threshold voltage decreases) particularly in an N-channel MOSFET because of the occlusion characteristics of the barrier metal layer. Therefore, the impurity concentration injected into the channel layer to adjust the threshold value Therefore, there is a problem that the on-resistance increases.
[0020]
This is because the titanium-based metal that is the barrier metal layer has a hydrogen storage property, so that, for example, hydrogen is stored in the barrier metal layer before reaching the interface between the semiconductor substrate and the gate oxide film in the hydrogen alloy process. It was found that this is because less hydrogen contributes to the disappearance of the charge generated at the Si interface.
[0021]
Further, according to experiments, it is known that V _GSOFF does not shift even under a hydrogen alloy condition of about 400 ° C. without an aluminum alloy wiring layer. In this case, hydrogen reaches the substrate surface sufficiently by the hydrogen alloy. It is thought that. On the other hand, in the case where there is an aluminum alloy wiring layer, it has been found that if the temperature of the hydrogen alloy is increased, V _GSOFF becomes a predetermined value. However, as a matter of course, heat treatment exceeding the melting point of aluminum cannot be performed, and by increasing the temperature of the hydrogen alloy, the amount of Si nodules in the aluminum alloy deposited on the substrate surface increases, so stress during wire bonding Therefore, there is also a problem that element breakdown is caused by the deposited Si nodules.
[0022]
[Means for Solving the Problems]
The present invention has been made in view of such problems. First, after forming a desired element region on a silicon semiconductor substrate and forming a barrier metal layer with a metal having hydrogen storage properties, hydrogen is introduced into the substrate surface. This is achieved by including a step of forming a wiring layer on the barrier metal layer, and a step of performing a heat treatment after forming a surface protective film on the wiring layer.
[0023]
Second, a step of forming a desired element region on a silicon semiconductor substrate, a step of introducing hydrogen into the substrate surface after forming a barrier metal layer with a titanium-based metal having hydrogen storage properties, and a barrier metal layer The problem is solved by providing a step of forming a wiring layer thereon and a step of performing a heat treatment after forming a surface protective film on the wiring layer.
[0024]
In addition, after the barrier metal is formed, hydrogen is introduced into the substrate by heating at 300 to 800 ° C. in an atmosphere of hydrogen or a hydrogen-containing gas.
[0025]
In addition, after the barrier metal layer is formed, hydrogen is ion-implanted over the entire surface, and heated and diffused at 300 to 800 ° C. to introduce hydrogen into the substrate.
[0026]
The heat treatment is characterized by heating at 300 to 500 ° C. in a reduced pressure atmosphere of nitrogen, hydrogen or a hydrogen-containing gas.
[0027]
Further, the heat treatment is performed under a pressure of 0.2 to 760 Torr.
[0028]
That is, hydrogen is introduced into the substrate before the aluminum alloy film is formed, hydrogen is supplied to the silicon surface by performing a first heat treatment at a high temperature, and after the aluminum alloy is formed, the alloy heat treatment is also performed under reduced pressure and under normal pressure. By performing the second heat treatment at a temperature, it is possible to provide a method for manufacturing a semiconductor device that allows hydrogen to efficiently reach the silicon surface while suppressing the precipitation of Si nodules.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 7 by taking a trench type power MOSFET as an example.
[0030]
FIG. 1 shows the structure of a trench type power MOSFET of the present invention. A drain region 2 made of an N ⁻ type epitaxial layer is provided on an N ⁺ type silicon semiconductor substrate 1, and a P type channel layer 4 is provided on the surface thereof. A trench 7 that penetrates the channel layer 4 and reaches the drain region 2 is provided, an inner wall of the trench 7 is coated with a gate oxide film 11, and a gate electrode 13 made of polysilicon filled in the trench 7 is provided. An N ⁺ type source region 15 is formed on the surface of the channel layer 4 adjacent to the trench 7, and a P ⁺ type body contact region 14 is provided on the surface of the channel layer 4 between the source regions 15 of two adjacent cells. Further, when the gate electrode 13 is applied, a channel region (not shown) is formed from the source region 15 along the trench 7. The gate electrode 13 is covered with an interlayer insulating film 16, a barrier metal layer 17 that contacts the source region 15 and the body contact region 14 is formed, and a wiring layer 18 made of aluminum alloy or the like is provided.
[0031]
2 to 5 show a method of manufacturing the trench type power MOSFET according to the present invention. A method for manufacturing a trench power MOSFET according to the present invention includes a step of forming a desired element region on a silicon semiconductor substrate, a step of introducing hydrogen into the substrate surface after forming a barrier metal layer with a metal having hydrogen storage properties, and And a step of forming a wiring layer on the barrier metal layer and a step of performing a heat treatment after forming a surface protective film on the wiring layer.
[0032]
The first step of the present invention is to form a desired element region on a silicon semiconductor substrate as shown in FIGS.
[0033]
In FIG. 2, a drain region 2 is formed by laminating an N ⁻ type epitaxial layer on an N ⁺ type silicon semiconductor substrate 1. After the oxide film is formed on the surface, the oxide film in the portion of the planned channel layer 4 is etched. Boron is implanted at a dose of 1.0 × 10 ^{13 over the} entire surface using this oxide film as a mask, and then diffused to form a P-type channel layer 4.
[0034]
Next, a trench is formed. An NSG (Non-doped Silicate Glass) CVD oxide film is formed on the entire surface by CVD, and the resist oxide mask is removed except for the trench opening, and the CVD oxide film is partially removed by dry etching. Then, a trench opening in which the channel region 4 is exposed is formed.
[0035]
Further, using the CVD oxide film as a mask, the silicon semiconductor substrate in the trench opening is dry-etched with CF-based gas and HBr-based gas to form a trench 7 that penetrates the channel layer 4 and reaches the drain region 2.
[0036]
In FIG. 3, the gate oxide film 11 and the gate electrode 13 are formed. First, dummy oxidation is performed to form a dummy oxide film on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during dry etching. By removing the dummy oxide film and the CVD oxide film formed by this dummy oxidation simultaneously with an oxide film etchant such as hydrofluoric acid, a stable gate oxide film can be formed. In addition, the thermal oxidation at a high temperature has an effect of rounding the opening of the trench 7 to avoid electric field concentration at the opening of the trench 7. Thereafter, a gate oxide film 11 is formed. That is, the entire surface is thermally oxidized to form the gate oxide film 11 with a thickness of, for example, about 700 mm according to the threshold value.
[0037]
Further, a non-doped polysilicon layer is deposited on the entire surface, phosphorus is implanted and diffused at a high concentration to increase the conductivity, and the polysilicon layer deposited on the entire surface is dry etched without a mask and embedded in the trench 7. The left gate electrode 13 is left.
[0038]
Further, a body contact region 14 and a source region 15 for stabilizing the substrate potential are formed. First, boron is selectively ion-implanted with a mask made of a resist film to form a P ⁺ -type body contact region 14 and then the resist film is removed. Further, a new resist film is used to mask the planned source region 15 and gate electrode 13 so that arsenic is ion-implanted to form an N ⁺ type source region 15 on the surface of the channel layer 4 adjacent to the trench 7. Then, the resist film is removed. Thereafter, a BPSG (Boron Phosphorus Silicate Glass) layer is deposited on the entire surface by a CVD method to form an interlayer insulating film 16, and the interlayer insulating film 16 is left at least on the gate electrode 13 using the resist film as a mask.
[0039]
The second step of the present invention is to introduce hydrogen into the substrate surface after forming a barrier metal layer with a metal having hydrogen storage properties as shown in FIG.
[0040]
This process is a process that characterizes the present invention. First, the barrier metal layer 17 is provided. The silicon substrate is exposed at portions other than the interlayer insulating film 16, and when the aluminum alloy that becomes the wiring layer 18 is sputtered, the silicon contact (silicon nodules) contained in the aluminum alloy is a fine region of the body contact region 14. May be blocked. In order to suppress this silicon nodule and prevent mutual diffusion between a metal called a spike and a silicon substrate, a barrier metal layer 17 made of a titanium-based material (for example, Ti / TiN) is formed before the wiring layer 18 is formed. Form.
[0041]
A barrier metal layer 17 is formed by sputtering Ti / TiN or the like on the entire surface, and subsequently transferred to a furnace to perform hydrogen alloy. That is, heat treatment is performed at 300 to 800 ° C. (for example, 700 ° C.) for about 30 minutes in hydrogen gas or hydrogen-containing gas.
[0042]
Here, after the barrier metal layer 17 is formed, hydrogen ions may be implanted into the entire surface, and then heat treatment may be performed at 300 to 800 ° C. (eg, 700 ° C.).
[0043]
By this step, hydrogen is introduced into the silicon substrate surface. When hydrogen alloying is performed after sputtering an aluminum alloy as in the prior art, hydrogen cannot reach the silicon surface sufficiently, for example, with hydrogen alloy at about 400 ° C. In addition, if heat treatment is performed at a high temperature, the amount of hydrogen reaching the silicon surface increases, but naturally it cannot be heated at a temperature exceeding the melting point (about 600 ° C.) of the aluminum alloy. Further, when the temperature is increased, the amount of Si nodules deposited also increases, and there is a problem that contact failure and element destruction during wire bonding increase.
[0044]
However, according to the present invention, hydrogen alloying can be performed at a high temperature exceeding the melting point of the aluminum alloy before forming the aluminum alloy. As a result, hydrogen is sufficiently supplied to the barrier metal layer 17 and, since there is no aluminum alloy layer even at a high temperature, there is no problem of naturally depositing Si nodules contained in the aluminum layer. At this time, the barrier metal layer 17 occludes hydrogen, but when the occlusion amount is saturated, more hydrogen reaches the surface of the silicon substrate, so that charge is suppressed by the hydrogen. This is obvious from the fact that a predetermined V _GSOFF can be obtained with a hydrogen alloy of about 400 ° C. in the absence of an aluminum alloy as described above.
[0045]
As shown in FIG. 5, the third step of the present invention is to form a wiring layer on the barrier metal layer, form a surface protective film on the wiring layer, and then perform heat treatment.
[0046]
This step is also a step that characterizes the present invention. First. An aluminum alloy to be the wiring layer 18 is sputtered on the entire surface. Thereafter, although not shown, SiN or the like serving as a surface protective film is provided, and then heat treatment is performed in a reduced-pressure atmosphere of nitrogen gas, hydrogen gas, or hydrogen-containing gas. Specifically, heat treatment is performed at 300 to 500 ° C. (for example, about 400 ° C.) for about 30 minutes in a reduced pressure atmosphere of 0.01 to 760 Torr. As a result, the alloying of aluminum and the damage after the formation of the surface protective film can be removed, and further, the hydrogen occluded in the barrier metal layer 17 in the previous step is released to the silicon surface.
[0047]
Here, the hydrogen storage characteristics will be described with reference to FIG. This is a PCT curve diagram showing the relationship between the pressure P at which the barrier metal layer made of Ti / TiN is placed and the hydrogen concentration C with the temperature T as a parameter. From this figure, it can be seen that the lower the pressure P, the lower the hydrogen concentration occluded in the barrier metal. Is specifically a hydrogen concentration ¹⁰ 19 ^{cm -3} degree when the to the atmospheric pressure focusing on the case of the temperature 400 ° ^C., to about 10 -2 ^~ 10 0 Torr about to lower the pressure when ¹⁰ 15 ^{cm -3} The trend is lower and this trend does not change with decreasing temperatures. In other words, when heat treatment is performed in such a reduced pressure atmosphere, the barrier metal layer releases hydrogen, inevitably reaches the interface between the semiconductor substrate and the gate oxide film, and hydrogen increases to eliminate the charge on the silicon surface. .
[0048]
That is, in this step, heat treatment is performed in a reduced-pressure atmosphere, whereby hydrogen stored in the barrier metal layer in the previous step can be released, and the amount of hydrogen reaching the semiconductor substrate surface can be further increased.
[0049]
FIG. 7 shows V _GS -ID curves when heat treatment is performed after formation of the barrier metal layer (solid line) and when heat treatment is not performed (dotted line). According to this, it can be seen that the threshold voltage is further improved and a predetermined value is obtained by the heat treatment after the formation of the barrier metal layer. That is, silicon that reaches the silicon surface by the hydrogen alloy in the second step according to the embodiment of the present invention and hydrogen that is released from the barrier metal layer by the heat treatment under reduced pressure in the third step and reaches the silicon surface. The charge on the substrate surface can be sufficiently eliminated, and the threshold voltage can be stabilized as shown in the figure.
[0050]
【The invention's effect】
According to the manufacturing method of the present invention, it is possible to provide a method for manufacturing a semiconductor device in which the threshold voltage does not vary and the on-resistance can be further reduced.
[0051]
That is, firstly, hydrogen alloying can be performed at a high temperature after the barrier metal layer is formed and before the aluminum alloy film is formed. Therefore, the amount of hydrogen passing through the semiconductor substrate surface is increased, and the amount of hydrogen that reaches the semiconductor substrate surface and contributes to charge disappearance is increased. Can do. In a conventional manufacturing method, since there is an aluminum alloy, a predetermined threshold voltage cannot be obtained under normal (about 400 ° C.) hydrogen alloy conditions, and if heat treatment is performed at a high temperature, the amount of hydrogen reaching the substrate surface increases. A predetermined threshold voltage can be obtained, but in this case, the amount of Si nodules deposited in the aluminum alloy increases, leading to problems of contact failure and device destruction during wire bonding, and naturally heating exceeding the melting point of the aluminum alloy can be performed. There was no problem. In the manufacturing method of the present invention, it is noted that a predetermined threshold voltage can be obtained with a hydrogen alloy of about 400 ° C. before the film formation of the aluminum alloy, and the hydrogen alloy is formed at a high temperature exceeding the melting point of the aluminum alloy after the barrier metal layer is formed. As a result, the amount of hydrogen reaching the silicon surface can be increased as compared with the conventional manufacturing method.
[0052]
Second, the amount of hydrogen reaching the silicon substrate can be further increased by the heat treatment after the surface protective film is formed. In other words, under reduced pressure, the barrier metal layer, which is a hydrogen storage alloy, has the property of releasing hydrogen. Therefore, by performing heat treatment under reduced pressure, the hydrogen stored in the barrier metal layer is removed in the alloying heat treatment step of the aluminum alloy. Since the amount of hydrogen reaching the Si surface can be further reduced, the charge on the substrate surface can be sufficiently eliminated and a stable threshold voltage can be obtained.
[0053]
Third, if the threshold voltage is stable, it is not necessary to increase the concentration of impurities implanted into the channel layer more than necessary, so that an increase in on-resistance can be suppressed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention.
FIG. 6 is a characteristic diagram illustrating hydrogen storage characteristics.
FIG. 7 is a characteristic diagram illustrating a semiconductor device of the present invention.
FIG. 8 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
FIG. 9 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
FIG. 10 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.
FIG. 11 is a characteristic diagram illustrating a conventional semiconductor device.

Claims (4)

In a method for manufacturing a semiconductor device in which an aluminum-based metal layer is formed on a silicon semiconductor substrate,
Forming a desired element region on the silicon semiconductor substrate;
Forming a barrier metal layer with a titanium-based metal having hydrogen storage properties, then introducing hydrogen into the substrate surface, and performing a first heat treatment;
A step of forming the metal layer on the barrier metal layer,
After forming a surface protective layer on said metal layer, at reduced nitrogen or hydrogen or a hydrogen-containing gas atmosphere, subjected to a second heat treatment at 300 ° C. to 500 ° C. in a temperature below the melting point of the metal layer, the barrier metal layer And a step of releasing the hydrogen occluded in the semiconductor device. In the hydrogen or hydrogen-containing gas atmosphere, the first heat treatment is performed at a temperature of 800 ° C. or less that is higher than the melting point of the metal layer and does not affect the impurity concentration profile of the impurity concentration present in the silicon semiconductor substrate and the element region. The method of manufacturing a semiconductor device according to claim 1, wherein the hydrogen is introduced into the substrate. The introduction of hydrogen is performed by ion-implanting hydrogen into the entire surface after forming the barrier metal layer, and affects the impurity concentration profile of the impurity concentration present in the silicon semiconductor substrate and the element region above the melting point of the metal layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first heat treatment is performed at a temperature of 800 ° C. or less so as not to give hydrogen to diffuse the hydrogen into the substrate. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second heat treatment is performed in a reduced pressure atmosphere of 0.01 Torr to 760 Torr.

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